1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip KSZ9477 switch driver main logic 4 * 5 * Copyright (C) 2017-2018 Microchip Technology Inc. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/export.h> 10 #include <linux/gpio.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/platform_data/microchip-ksz.h> 14 #include <linux/phy.h> 15 #include <linux/etherdevice.h> 16 #include <linux/if_bridge.h> 17 #include <net/dsa.h> 18 #include <net/switchdev.h> 19 20 #include "ksz_priv.h" 21 #include "ksz_common.h" 22 #include "ksz9477_reg.h" 23 24 static const struct { 25 int index; 26 char string[ETH_GSTRING_LEN]; 27 } ksz9477_mib_names[TOTAL_SWITCH_COUNTER_NUM] = { 28 { 0x00, "rx_hi" }, 29 { 0x01, "rx_undersize" }, 30 { 0x02, "rx_fragments" }, 31 { 0x03, "rx_oversize" }, 32 { 0x04, "rx_jabbers" }, 33 { 0x05, "rx_symbol_err" }, 34 { 0x06, "rx_crc_err" }, 35 { 0x07, "rx_align_err" }, 36 { 0x08, "rx_mac_ctrl" }, 37 { 0x09, "rx_pause" }, 38 { 0x0A, "rx_bcast" }, 39 { 0x0B, "rx_mcast" }, 40 { 0x0C, "rx_ucast" }, 41 { 0x0D, "rx_64_or_less" }, 42 { 0x0E, "rx_65_127" }, 43 { 0x0F, "rx_128_255" }, 44 { 0x10, "rx_256_511" }, 45 { 0x11, "rx_512_1023" }, 46 { 0x12, "rx_1024_1522" }, 47 { 0x13, "rx_1523_2000" }, 48 { 0x14, "rx_2001" }, 49 { 0x15, "tx_hi" }, 50 { 0x16, "tx_late_col" }, 51 { 0x17, "tx_pause" }, 52 { 0x18, "tx_bcast" }, 53 { 0x19, "tx_mcast" }, 54 { 0x1A, "tx_ucast" }, 55 { 0x1B, "tx_deferred" }, 56 { 0x1C, "tx_total_col" }, 57 { 0x1D, "tx_exc_col" }, 58 { 0x1E, "tx_single_col" }, 59 { 0x1F, "tx_mult_col" }, 60 { 0x80, "rx_total" }, 61 { 0x81, "tx_total" }, 62 { 0x82, "rx_discards" }, 63 { 0x83, "tx_discards" }, 64 }; 65 66 static void ksz9477_cfg32(struct ksz_device *dev, u32 addr, u32 bits, bool set) 67 { 68 u32 data; 69 70 ksz_read32(dev, addr, &data); 71 if (set) 72 data |= bits; 73 else 74 data &= ~bits; 75 ksz_write32(dev, addr, data); 76 } 77 78 static void ksz9477_port_cfg32(struct ksz_device *dev, int port, int offset, 79 u32 bits, bool set) 80 { 81 u32 addr; 82 u32 data; 83 84 addr = PORT_CTRL_ADDR(port, offset); 85 ksz_read32(dev, addr, &data); 86 87 if (set) 88 data |= bits; 89 else 90 data &= ~bits; 91 92 ksz_write32(dev, addr, data); 93 } 94 95 static int ksz9477_wait_vlan_ctrl_ready(struct ksz_device *dev, u32 waiton, 96 int timeout) 97 { 98 u8 data; 99 100 do { 101 ksz_read8(dev, REG_SW_VLAN_CTRL, &data); 102 if (!(data & waiton)) 103 break; 104 usleep_range(1, 10); 105 } while (timeout-- > 0); 106 107 if (timeout <= 0) 108 return -ETIMEDOUT; 109 110 return 0; 111 } 112 113 static int ksz9477_get_vlan_table(struct ksz_device *dev, u16 vid, 114 u32 *vlan_table) 115 { 116 int ret; 117 118 mutex_lock(&dev->vlan_mutex); 119 120 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 121 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_READ | VLAN_START); 122 123 /* wait to be cleared */ 124 ret = ksz9477_wait_vlan_ctrl_ready(dev, VLAN_START, 1000); 125 if (ret < 0) { 126 dev_dbg(dev->dev, "Failed to read vlan table\n"); 127 goto exit; 128 } 129 130 ksz_read32(dev, REG_SW_VLAN_ENTRY__4, &vlan_table[0]); 131 ksz_read32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, &vlan_table[1]); 132 ksz_read32(dev, REG_SW_VLAN_ENTRY_PORTS__4, &vlan_table[2]); 133 134 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 135 136 exit: 137 mutex_unlock(&dev->vlan_mutex); 138 139 return ret; 140 } 141 142 static int ksz9477_set_vlan_table(struct ksz_device *dev, u16 vid, 143 u32 *vlan_table) 144 { 145 int ret; 146 147 mutex_lock(&dev->vlan_mutex); 148 149 ksz_write32(dev, REG_SW_VLAN_ENTRY__4, vlan_table[0]); 150 ksz_write32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, vlan_table[1]); 151 ksz_write32(dev, REG_SW_VLAN_ENTRY_PORTS__4, vlan_table[2]); 152 153 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 154 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_START | VLAN_WRITE); 155 156 /* wait to be cleared */ 157 ret = ksz9477_wait_vlan_ctrl_ready(dev, VLAN_START, 1000); 158 if (ret < 0) { 159 dev_dbg(dev->dev, "Failed to write vlan table\n"); 160 goto exit; 161 } 162 163 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 164 165 /* update vlan cache table */ 166 dev->vlan_cache[vid].table[0] = vlan_table[0]; 167 dev->vlan_cache[vid].table[1] = vlan_table[1]; 168 dev->vlan_cache[vid].table[2] = vlan_table[2]; 169 170 exit: 171 mutex_unlock(&dev->vlan_mutex); 172 173 return ret; 174 } 175 176 static void ksz9477_read_table(struct ksz_device *dev, u32 *table) 177 { 178 ksz_read32(dev, REG_SW_ALU_VAL_A, &table[0]); 179 ksz_read32(dev, REG_SW_ALU_VAL_B, &table[1]); 180 ksz_read32(dev, REG_SW_ALU_VAL_C, &table[2]); 181 ksz_read32(dev, REG_SW_ALU_VAL_D, &table[3]); 182 } 183 184 static void ksz9477_write_table(struct ksz_device *dev, u32 *table) 185 { 186 ksz_write32(dev, REG_SW_ALU_VAL_A, table[0]); 187 ksz_write32(dev, REG_SW_ALU_VAL_B, table[1]); 188 ksz_write32(dev, REG_SW_ALU_VAL_C, table[2]); 189 ksz_write32(dev, REG_SW_ALU_VAL_D, table[3]); 190 } 191 192 static int ksz9477_wait_alu_ready(struct ksz_device *dev, u32 waiton, 193 int timeout) 194 { 195 u32 data; 196 197 do { 198 ksz_read32(dev, REG_SW_ALU_CTRL__4, &data); 199 if (!(data & waiton)) 200 break; 201 usleep_range(1, 10); 202 } while (timeout-- > 0); 203 204 if (timeout <= 0) 205 return -ETIMEDOUT; 206 207 return 0; 208 } 209 210 static int ksz9477_wait_alu_sta_ready(struct ksz_device *dev, u32 waiton, 211 int timeout) 212 { 213 u32 data; 214 215 do { 216 ksz_read32(dev, REG_SW_ALU_STAT_CTRL__4, &data); 217 if (!(data & waiton)) 218 break; 219 usleep_range(1, 10); 220 } while (timeout-- > 0); 221 222 if (timeout <= 0) 223 return -ETIMEDOUT; 224 225 return 0; 226 } 227 228 static int ksz9477_reset_switch(struct ksz_device *dev) 229 { 230 u8 data8; 231 u16 data16; 232 u32 data32; 233 234 /* reset switch */ 235 ksz_cfg(dev, REG_SW_OPERATION, SW_RESET, true); 236 237 /* turn off SPI DO Edge select */ 238 ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8); 239 data8 &= ~SPI_AUTO_EDGE_DETECTION; 240 ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8); 241 242 /* default configuration */ 243 ksz_read8(dev, REG_SW_LUE_CTRL_1, &data8); 244 data8 = SW_AGING_ENABLE | SW_LINK_AUTO_AGING | 245 SW_SRC_ADDR_FILTER | SW_FLUSH_STP_TABLE | SW_FLUSH_MSTP_TABLE; 246 ksz_write8(dev, REG_SW_LUE_CTRL_1, data8); 247 248 /* disable interrupts */ 249 ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK); 250 ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0x7F); 251 ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32); 252 253 /* set broadcast storm protection 10% rate */ 254 ksz_read16(dev, REG_SW_MAC_CTRL_2, &data16); 255 data16 &= ~BROADCAST_STORM_RATE; 256 data16 |= (BROADCAST_STORM_VALUE * BROADCAST_STORM_PROT_RATE) / 100; 257 ksz_write16(dev, REG_SW_MAC_CTRL_2, data16); 258 259 return 0; 260 } 261 262 static enum dsa_tag_protocol ksz9477_get_tag_protocol(struct dsa_switch *ds, 263 int port) 264 { 265 return DSA_TAG_PROTO_KSZ; 266 } 267 268 static int ksz9477_phy_read16(struct dsa_switch *ds, int addr, int reg) 269 { 270 struct ksz_device *dev = ds->priv; 271 u16 val = 0xffff; 272 273 /* No real PHY after this. Simulate the PHY. 274 * A fixed PHY can be setup in the device tree, but this function is 275 * still called for that port during initialization. 276 * For RGMII PHY there is no way to access it so the fixed PHY should 277 * be used. For SGMII PHY the supporting code will be added later. 278 */ 279 if (addr >= dev->phy_port_cnt) { 280 struct ksz_port *p = &dev->ports[addr]; 281 282 switch (reg) { 283 case MII_BMCR: 284 val = 0x1140; 285 break; 286 case MII_BMSR: 287 val = 0x796d; 288 break; 289 case MII_PHYSID1: 290 val = 0x0022; 291 break; 292 case MII_PHYSID2: 293 val = 0x1631; 294 break; 295 case MII_ADVERTISE: 296 val = 0x05e1; 297 break; 298 case MII_LPA: 299 val = 0xc5e1; 300 break; 301 case MII_CTRL1000: 302 val = 0x0700; 303 break; 304 case MII_STAT1000: 305 if (p->phydev.speed == SPEED_1000) 306 val = 0x3800; 307 else 308 val = 0; 309 break; 310 } 311 } else { 312 ksz_pread16(dev, addr, 0x100 + (reg << 1), &val); 313 } 314 315 return val; 316 } 317 318 static int ksz9477_phy_write16(struct dsa_switch *ds, int addr, int reg, 319 u16 val) 320 { 321 struct ksz_device *dev = ds->priv; 322 323 /* No real PHY after this. */ 324 if (addr >= dev->phy_port_cnt) 325 return 0; 326 ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val); 327 328 return 0; 329 } 330 331 static void ksz9477_get_strings(struct dsa_switch *ds, int port, 332 u32 stringset, uint8_t *buf) 333 { 334 int i; 335 336 if (stringset != ETH_SS_STATS) 337 return; 338 339 for (i = 0; i < TOTAL_SWITCH_COUNTER_NUM; i++) { 340 memcpy(buf + i * ETH_GSTRING_LEN, ksz9477_mib_names[i].string, 341 ETH_GSTRING_LEN); 342 } 343 } 344 345 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, 346 uint64_t *buf) 347 { 348 struct ksz_device *dev = ds->priv; 349 int i; 350 u32 data; 351 int timeout; 352 353 mutex_lock(&dev->stats_mutex); 354 355 for (i = 0; i < TOTAL_SWITCH_COUNTER_NUM; i++) { 356 data = MIB_COUNTER_READ; 357 data |= ((ksz9477_mib_names[i].index & 0xFF) << 358 MIB_COUNTER_INDEX_S); 359 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, data); 360 361 timeout = 1000; 362 do { 363 ksz_pread32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 364 &data); 365 usleep_range(1, 10); 366 if (!(data & MIB_COUNTER_READ)) 367 break; 368 } while (timeout-- > 0); 369 370 /* failed to read MIB. get out of loop */ 371 if (!timeout) { 372 dev_dbg(dev->dev, "Failed to get MIB\n"); 373 break; 374 } 375 376 /* count resets upon read */ 377 ksz_pread32(dev, port, REG_PORT_MIB_DATA, &data); 378 379 dev->mib_value[i] += (uint64_t)data; 380 buf[i] = dev->mib_value[i]; 381 } 382 383 mutex_unlock(&dev->stats_mutex); 384 } 385 386 static void ksz9477_cfg_port_member(struct ksz_device *dev, int port, 387 u8 member) 388 { 389 ksz_pwrite32(dev, port, REG_PORT_VLAN_MEMBERSHIP__4, member); 390 dev->ports[port].member = member; 391 } 392 393 static void ksz9477_port_stp_state_set(struct dsa_switch *ds, int port, 394 u8 state) 395 { 396 struct ksz_device *dev = ds->priv; 397 struct ksz_port *p = &dev->ports[port]; 398 u8 data; 399 int member = -1; 400 401 ksz_pread8(dev, port, P_STP_CTRL, &data); 402 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 403 404 switch (state) { 405 case BR_STATE_DISABLED: 406 data |= PORT_LEARN_DISABLE; 407 if (port != dev->cpu_port) 408 member = 0; 409 break; 410 case BR_STATE_LISTENING: 411 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 412 if (port != dev->cpu_port && 413 p->stp_state == BR_STATE_DISABLED) 414 member = dev->host_mask | p->vid_member; 415 break; 416 case BR_STATE_LEARNING: 417 data |= PORT_RX_ENABLE; 418 break; 419 case BR_STATE_FORWARDING: 420 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 421 422 /* This function is also used internally. */ 423 if (port == dev->cpu_port) 424 break; 425 426 member = dev->host_mask | p->vid_member; 427 428 /* Port is a member of a bridge. */ 429 if (dev->br_member & (1 << port)) { 430 dev->member |= (1 << port); 431 member = dev->member; 432 } 433 break; 434 case BR_STATE_BLOCKING: 435 data |= PORT_LEARN_DISABLE; 436 if (port != dev->cpu_port && 437 p->stp_state == BR_STATE_DISABLED) 438 member = dev->host_mask | p->vid_member; 439 break; 440 default: 441 dev_err(ds->dev, "invalid STP state: %d\n", state); 442 return; 443 } 444 445 ksz_pwrite8(dev, port, P_STP_CTRL, data); 446 p->stp_state = state; 447 if (data & PORT_RX_ENABLE) 448 dev->rx_ports |= (1 << port); 449 else 450 dev->rx_ports &= ~(1 << port); 451 if (data & PORT_TX_ENABLE) 452 dev->tx_ports |= (1 << port); 453 else 454 dev->tx_ports &= ~(1 << port); 455 456 /* Port membership may share register with STP state. */ 457 if (member >= 0 && member != p->member) 458 ksz9477_cfg_port_member(dev, port, (u8)member); 459 460 /* Check if forwarding needs to be updated. */ 461 if (state != BR_STATE_FORWARDING) { 462 if (dev->br_member & (1 << port)) 463 dev->member &= ~(1 << port); 464 } 465 466 /* When topology has changed the function ksz_update_port_member 467 * should be called to modify port forwarding behavior. However 468 * as the offload_fwd_mark indication cannot be reported here 469 * the switch forwarding function is not enabled. 470 */ 471 } 472 473 static void ksz9477_flush_dyn_mac_table(struct ksz_device *dev, int port) 474 { 475 u8 data; 476 477 ksz_read8(dev, REG_SW_LUE_CTRL_2, &data); 478 data &= ~(SW_FLUSH_OPTION_M << SW_FLUSH_OPTION_S); 479 data |= (SW_FLUSH_OPTION_DYN_MAC << SW_FLUSH_OPTION_S); 480 ksz_write8(dev, REG_SW_LUE_CTRL_2, data); 481 if (port < dev->mib_port_cnt) { 482 /* flush individual port */ 483 ksz_pread8(dev, port, P_STP_CTRL, &data); 484 if (!(data & PORT_LEARN_DISABLE)) 485 ksz_pwrite8(dev, port, P_STP_CTRL, 486 data | PORT_LEARN_DISABLE); 487 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true); 488 ksz_pwrite8(dev, port, P_STP_CTRL, data); 489 } else { 490 /* flush all */ 491 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_STP_TABLE, true); 492 } 493 } 494 495 static int ksz9477_port_vlan_filtering(struct dsa_switch *ds, int port, 496 bool flag) 497 { 498 struct ksz_device *dev = ds->priv; 499 500 if (flag) { 501 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 502 PORT_VLAN_LOOKUP_VID_0, true); 503 ksz9477_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY, 504 true); 505 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, true); 506 } else { 507 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, false); 508 ksz9477_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY, 509 false); 510 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 511 PORT_VLAN_LOOKUP_VID_0, false); 512 } 513 514 return 0; 515 } 516 517 static void ksz9477_port_vlan_add(struct dsa_switch *ds, int port, 518 const struct switchdev_obj_port_vlan *vlan) 519 { 520 struct ksz_device *dev = ds->priv; 521 u32 vlan_table[3]; 522 u16 vid; 523 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 524 525 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 526 if (ksz9477_get_vlan_table(dev, vid, vlan_table)) { 527 dev_dbg(dev->dev, "Failed to get vlan table\n"); 528 return; 529 } 530 531 vlan_table[0] = VLAN_VALID | (vid & VLAN_FID_M); 532 if (untagged) 533 vlan_table[1] |= BIT(port); 534 else 535 vlan_table[1] &= ~BIT(port); 536 vlan_table[1] &= ~(BIT(dev->cpu_port)); 537 538 vlan_table[2] |= BIT(port) | BIT(dev->cpu_port); 539 540 if (ksz9477_set_vlan_table(dev, vid, vlan_table)) { 541 dev_dbg(dev->dev, "Failed to set vlan table\n"); 542 return; 543 } 544 545 /* change PVID */ 546 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) 547 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, vid); 548 } 549 } 550 551 static int ksz9477_port_vlan_del(struct dsa_switch *ds, int port, 552 const struct switchdev_obj_port_vlan *vlan) 553 { 554 struct ksz_device *dev = ds->priv; 555 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 556 u32 vlan_table[3]; 557 u16 vid; 558 u16 pvid; 559 560 ksz_pread16(dev, port, REG_PORT_DEFAULT_VID, &pvid); 561 pvid = pvid & 0xFFF; 562 563 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 564 if (ksz9477_get_vlan_table(dev, vid, vlan_table)) { 565 dev_dbg(dev->dev, "Failed to get vlan table\n"); 566 return -ETIMEDOUT; 567 } 568 569 vlan_table[2] &= ~BIT(port); 570 571 if (pvid == vid) 572 pvid = 1; 573 574 if (untagged) 575 vlan_table[1] &= ~BIT(port); 576 577 if (ksz9477_set_vlan_table(dev, vid, vlan_table)) { 578 dev_dbg(dev->dev, "Failed to set vlan table\n"); 579 return -ETIMEDOUT; 580 } 581 } 582 583 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, pvid); 584 585 return 0; 586 } 587 588 static int ksz9477_port_fdb_add(struct dsa_switch *ds, int port, 589 const unsigned char *addr, u16 vid) 590 { 591 struct ksz_device *dev = ds->priv; 592 u32 alu_table[4]; 593 u32 data; 594 int ret = 0; 595 596 mutex_lock(&dev->alu_mutex); 597 598 /* find any entry with mac & vid */ 599 data = vid << ALU_FID_INDEX_S; 600 data |= ((addr[0] << 8) | addr[1]); 601 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 602 603 data = ((addr[2] << 24) | (addr[3] << 16)); 604 data |= ((addr[4] << 8) | addr[5]); 605 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 606 607 /* start read operation */ 608 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 609 610 /* wait to be finished */ 611 ret = ksz9477_wait_alu_ready(dev, ALU_START, 1000); 612 if (ret < 0) { 613 dev_dbg(dev->dev, "Failed to read ALU\n"); 614 goto exit; 615 } 616 617 /* read ALU entry */ 618 ksz9477_read_table(dev, alu_table); 619 620 /* update ALU entry */ 621 alu_table[0] = ALU_V_STATIC_VALID; 622 alu_table[1] |= BIT(port); 623 if (vid) 624 alu_table[1] |= ALU_V_USE_FID; 625 alu_table[2] = (vid << ALU_V_FID_S); 626 alu_table[2] |= ((addr[0] << 8) | addr[1]); 627 alu_table[3] = ((addr[2] << 24) | (addr[3] << 16)); 628 alu_table[3] |= ((addr[4] << 8) | addr[5]); 629 630 ksz9477_write_table(dev, alu_table); 631 632 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 633 634 /* wait to be finished */ 635 ret = ksz9477_wait_alu_ready(dev, ALU_START, 1000); 636 if (ret < 0) 637 dev_dbg(dev->dev, "Failed to write ALU\n"); 638 639 exit: 640 mutex_unlock(&dev->alu_mutex); 641 642 return ret; 643 } 644 645 static int ksz9477_port_fdb_del(struct dsa_switch *ds, int port, 646 const unsigned char *addr, u16 vid) 647 { 648 struct ksz_device *dev = ds->priv; 649 u32 alu_table[4]; 650 u32 data; 651 int ret = 0; 652 653 mutex_lock(&dev->alu_mutex); 654 655 /* read any entry with mac & vid */ 656 data = vid << ALU_FID_INDEX_S; 657 data |= ((addr[0] << 8) | addr[1]); 658 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 659 660 data = ((addr[2] << 24) | (addr[3] << 16)); 661 data |= ((addr[4] << 8) | addr[5]); 662 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 663 664 /* start read operation */ 665 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 666 667 /* wait to be finished */ 668 ret = ksz9477_wait_alu_ready(dev, ALU_START, 1000); 669 if (ret < 0) { 670 dev_dbg(dev->dev, "Failed to read ALU\n"); 671 goto exit; 672 } 673 674 ksz_read32(dev, REG_SW_ALU_VAL_A, &alu_table[0]); 675 if (alu_table[0] & ALU_V_STATIC_VALID) { 676 ksz_read32(dev, REG_SW_ALU_VAL_B, &alu_table[1]); 677 ksz_read32(dev, REG_SW_ALU_VAL_C, &alu_table[2]); 678 ksz_read32(dev, REG_SW_ALU_VAL_D, &alu_table[3]); 679 680 /* clear forwarding port */ 681 alu_table[2] &= ~BIT(port); 682 683 /* if there is no port to forward, clear table */ 684 if ((alu_table[2] & ALU_V_PORT_MAP) == 0) { 685 alu_table[0] = 0; 686 alu_table[1] = 0; 687 alu_table[2] = 0; 688 alu_table[3] = 0; 689 } 690 } else { 691 alu_table[0] = 0; 692 alu_table[1] = 0; 693 alu_table[2] = 0; 694 alu_table[3] = 0; 695 } 696 697 ksz9477_write_table(dev, alu_table); 698 699 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 700 701 /* wait to be finished */ 702 ret = ksz9477_wait_alu_ready(dev, ALU_START, 1000); 703 if (ret < 0) 704 dev_dbg(dev->dev, "Failed to write ALU\n"); 705 706 exit: 707 mutex_unlock(&dev->alu_mutex); 708 709 return ret; 710 } 711 712 static void ksz9477_convert_alu(struct alu_struct *alu, u32 *alu_table) 713 { 714 alu->is_static = !!(alu_table[0] & ALU_V_STATIC_VALID); 715 alu->is_src_filter = !!(alu_table[0] & ALU_V_SRC_FILTER); 716 alu->is_dst_filter = !!(alu_table[0] & ALU_V_DST_FILTER); 717 alu->prio_age = (alu_table[0] >> ALU_V_PRIO_AGE_CNT_S) & 718 ALU_V_PRIO_AGE_CNT_M; 719 alu->mstp = alu_table[0] & ALU_V_MSTP_M; 720 721 alu->is_override = !!(alu_table[1] & ALU_V_OVERRIDE); 722 alu->is_use_fid = !!(alu_table[1] & ALU_V_USE_FID); 723 alu->port_forward = alu_table[1] & ALU_V_PORT_MAP; 724 725 alu->fid = (alu_table[2] >> ALU_V_FID_S) & ALU_V_FID_M; 726 727 alu->mac[0] = (alu_table[2] >> 8) & 0xFF; 728 alu->mac[1] = alu_table[2] & 0xFF; 729 alu->mac[2] = (alu_table[3] >> 24) & 0xFF; 730 alu->mac[3] = (alu_table[3] >> 16) & 0xFF; 731 alu->mac[4] = (alu_table[3] >> 8) & 0xFF; 732 alu->mac[5] = alu_table[3] & 0xFF; 733 } 734 735 static int ksz9477_port_fdb_dump(struct dsa_switch *ds, int port, 736 dsa_fdb_dump_cb_t *cb, void *data) 737 { 738 struct ksz_device *dev = ds->priv; 739 int ret = 0; 740 u32 ksz_data; 741 u32 alu_table[4]; 742 struct alu_struct alu; 743 int timeout; 744 745 mutex_lock(&dev->alu_mutex); 746 747 /* start ALU search */ 748 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_START | ALU_SEARCH); 749 750 do { 751 timeout = 1000; 752 do { 753 ksz_read32(dev, REG_SW_ALU_CTRL__4, &ksz_data); 754 if ((ksz_data & ALU_VALID) || !(ksz_data & ALU_START)) 755 break; 756 usleep_range(1, 10); 757 } while (timeout-- > 0); 758 759 if (!timeout) { 760 dev_dbg(dev->dev, "Failed to search ALU\n"); 761 ret = -ETIMEDOUT; 762 goto exit; 763 } 764 765 /* read ALU table */ 766 ksz9477_read_table(dev, alu_table); 767 768 ksz9477_convert_alu(&alu, alu_table); 769 770 if (alu.port_forward & BIT(port)) { 771 ret = cb(alu.mac, alu.fid, alu.is_static, data); 772 if (ret) 773 goto exit; 774 } 775 } while (ksz_data & ALU_START); 776 777 exit: 778 779 /* stop ALU search */ 780 ksz_write32(dev, REG_SW_ALU_CTRL__4, 0); 781 782 mutex_unlock(&dev->alu_mutex); 783 784 return ret; 785 } 786 787 static void ksz9477_port_mdb_add(struct dsa_switch *ds, int port, 788 const struct switchdev_obj_port_mdb *mdb) 789 { 790 struct ksz_device *dev = ds->priv; 791 u32 static_table[4]; 792 u32 data; 793 int index; 794 u32 mac_hi, mac_lo; 795 796 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 797 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 798 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 799 800 mutex_lock(&dev->alu_mutex); 801 802 for (index = 0; index < dev->num_statics; index++) { 803 /* find empty slot first */ 804 data = (index << ALU_STAT_INDEX_S) | 805 ALU_STAT_READ | ALU_STAT_START; 806 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 807 808 /* wait to be finished */ 809 if (ksz9477_wait_alu_sta_ready(dev, ALU_STAT_START, 1000) < 0) { 810 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 811 goto exit; 812 } 813 814 /* read ALU static table */ 815 ksz9477_read_table(dev, static_table); 816 817 if (static_table[0] & ALU_V_STATIC_VALID) { 818 /* check this has same vid & mac address */ 819 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 820 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 821 static_table[3] == mac_lo) { 822 /* found matching one */ 823 break; 824 } 825 } else { 826 /* found empty one */ 827 break; 828 } 829 } 830 831 /* no available entry */ 832 if (index == dev->num_statics) 833 goto exit; 834 835 /* add entry */ 836 static_table[0] = ALU_V_STATIC_VALID; 837 static_table[1] |= BIT(port); 838 if (mdb->vid) 839 static_table[1] |= ALU_V_USE_FID; 840 static_table[2] = (mdb->vid << ALU_V_FID_S); 841 static_table[2] |= mac_hi; 842 static_table[3] = mac_lo; 843 844 ksz9477_write_table(dev, static_table); 845 846 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START; 847 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 848 849 /* wait to be finished */ 850 if (ksz9477_wait_alu_sta_ready(dev, ALU_STAT_START, 1000) < 0) 851 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 852 853 exit: 854 mutex_unlock(&dev->alu_mutex); 855 } 856 857 static int ksz9477_port_mdb_del(struct dsa_switch *ds, int port, 858 const struct switchdev_obj_port_mdb *mdb) 859 { 860 struct ksz_device *dev = ds->priv; 861 u32 static_table[4]; 862 u32 data; 863 int index; 864 int ret = 0; 865 u32 mac_hi, mac_lo; 866 867 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 868 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 869 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 870 871 mutex_lock(&dev->alu_mutex); 872 873 for (index = 0; index < dev->num_statics; index++) { 874 /* find empty slot first */ 875 data = (index << ALU_STAT_INDEX_S) | 876 ALU_STAT_READ | ALU_STAT_START; 877 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 878 879 /* wait to be finished */ 880 ret = ksz9477_wait_alu_sta_ready(dev, ALU_STAT_START, 1000); 881 if (ret < 0) { 882 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 883 goto exit; 884 } 885 886 /* read ALU static table */ 887 ksz9477_read_table(dev, static_table); 888 889 if (static_table[0] & ALU_V_STATIC_VALID) { 890 /* check this has same vid & mac address */ 891 892 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 893 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 894 static_table[3] == mac_lo) { 895 /* found matching one */ 896 break; 897 } 898 } 899 } 900 901 /* no available entry */ 902 if (index == dev->num_statics) 903 goto exit; 904 905 /* clear port */ 906 static_table[1] &= ~BIT(port); 907 908 if ((static_table[1] & ALU_V_PORT_MAP) == 0) { 909 /* delete entry */ 910 static_table[0] = 0; 911 static_table[1] = 0; 912 static_table[2] = 0; 913 static_table[3] = 0; 914 } 915 916 ksz9477_write_table(dev, static_table); 917 918 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START; 919 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 920 921 /* wait to be finished */ 922 ret = ksz9477_wait_alu_sta_ready(dev, ALU_STAT_START, 1000); 923 if (ret < 0) 924 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 925 926 exit: 927 mutex_unlock(&dev->alu_mutex); 928 929 return ret; 930 } 931 932 static int ksz9477_port_mirror_add(struct dsa_switch *ds, int port, 933 struct dsa_mall_mirror_tc_entry *mirror, 934 bool ingress) 935 { 936 struct ksz_device *dev = ds->priv; 937 938 if (ingress) 939 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true); 940 else 941 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true); 942 943 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false); 944 945 /* configure mirror port */ 946 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 947 PORT_MIRROR_SNIFFER, true); 948 949 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false); 950 951 return 0; 952 } 953 954 static void ksz9477_port_mirror_del(struct dsa_switch *ds, int port, 955 struct dsa_mall_mirror_tc_entry *mirror) 956 { 957 struct ksz_device *dev = ds->priv; 958 u8 data; 959 960 if (mirror->ingress) 961 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false); 962 else 963 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false); 964 965 ksz_pread8(dev, port, P_MIRROR_CTRL, &data); 966 967 if (!(data & (PORT_MIRROR_RX | PORT_MIRROR_TX))) 968 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 969 PORT_MIRROR_SNIFFER, false); 970 } 971 972 static void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port) 973 { 974 u8 data8; 975 u8 member; 976 u16 data16; 977 struct ksz_port *p = &dev->ports[port]; 978 979 /* enable tag tail for host port */ 980 if (cpu_port) 981 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_TAIL_TAG_ENABLE, 982 true); 983 984 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_MAC_LOOPBACK, false); 985 986 /* set back pressure */ 987 ksz_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, true); 988 989 /* enable broadcast storm limit */ 990 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true); 991 992 /* disable DiffServ priority */ 993 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_PRIO_ENABLE, false); 994 995 /* replace priority */ 996 ksz_port_cfg(dev, port, REG_PORT_MRI_MAC_CTRL, PORT_USER_PRIO_CEILING, 997 false); 998 ksz9477_port_cfg32(dev, port, REG_PORT_MTI_QUEUE_CTRL_0__4, 999 MTI_PVID_REPLACE, false); 1000 1001 /* enable 802.1p priority */ 1002 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true); 1003 1004 if (port < dev->phy_port_cnt) { 1005 /* do not force flow control */ 1006 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, 1007 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, 1008 false); 1009 1010 } else { 1011 /* force flow control */ 1012 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, 1013 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, 1014 true); 1015 1016 /* configure MAC to 1G & RGMII mode */ 1017 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8); 1018 data8 &= ~PORT_MII_NOT_1GBIT; 1019 data8 &= ~PORT_MII_SEL_M; 1020 switch (dev->interface) { 1021 case PHY_INTERFACE_MODE_MII: 1022 data8 |= PORT_MII_NOT_1GBIT; 1023 data8 |= PORT_MII_SEL; 1024 p->phydev.speed = SPEED_100; 1025 break; 1026 case PHY_INTERFACE_MODE_RMII: 1027 data8 |= PORT_MII_NOT_1GBIT; 1028 data8 |= PORT_RMII_SEL; 1029 p->phydev.speed = SPEED_100; 1030 break; 1031 case PHY_INTERFACE_MODE_GMII: 1032 data8 |= PORT_GMII_SEL; 1033 p->phydev.speed = SPEED_1000; 1034 break; 1035 default: 1036 data8 &= ~PORT_RGMII_ID_IG_ENABLE; 1037 data8 &= ~PORT_RGMII_ID_EG_ENABLE; 1038 if (dev->interface == PHY_INTERFACE_MODE_RGMII_ID || 1039 dev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 1040 data8 |= PORT_RGMII_ID_IG_ENABLE; 1041 if (dev->interface == PHY_INTERFACE_MODE_RGMII_ID || 1042 dev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 1043 data8 |= PORT_RGMII_ID_EG_ENABLE; 1044 data8 |= PORT_RGMII_SEL; 1045 p->phydev.speed = SPEED_1000; 1046 break; 1047 } 1048 ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, data8); 1049 p->phydev.duplex = 1; 1050 } 1051 if (cpu_port) { 1052 member = dev->port_mask; 1053 dev->on_ports = dev->host_mask; 1054 dev->live_ports = dev->host_mask; 1055 } else { 1056 member = dev->host_mask | p->vid_member; 1057 dev->on_ports |= (1 << port); 1058 1059 /* Link was detected before port is enabled. */ 1060 if (p->phydev.link) 1061 dev->live_ports |= (1 << port); 1062 } 1063 ksz9477_cfg_port_member(dev, port, member); 1064 1065 /* clear pending interrupts */ 1066 if (port < dev->phy_port_cnt) 1067 ksz_pread16(dev, port, REG_PORT_PHY_INT_ENABLE, &data16); 1068 } 1069 1070 static void ksz9477_config_cpu_port(struct dsa_switch *ds) 1071 { 1072 struct ksz_device *dev = ds->priv; 1073 struct ksz_port *p; 1074 int i; 1075 1076 ds->num_ports = dev->port_cnt; 1077 1078 for (i = 0; i < dev->port_cnt; i++) { 1079 if (dsa_is_cpu_port(ds, i) && (dev->cpu_ports & (1 << i))) { 1080 dev->cpu_port = i; 1081 dev->host_mask = (1 << dev->cpu_port); 1082 dev->port_mask |= dev->host_mask; 1083 1084 /* enable cpu port */ 1085 ksz9477_port_setup(dev, i, true); 1086 p = &dev->ports[dev->cpu_port]; 1087 p->vid_member = dev->port_mask; 1088 p->on = 1; 1089 } 1090 } 1091 1092 dev->member = dev->host_mask; 1093 1094 for (i = 0; i < dev->mib_port_cnt; i++) { 1095 if (i == dev->cpu_port) 1096 continue; 1097 p = &dev->ports[i]; 1098 1099 /* Initialize to non-zero so that ksz_cfg_port_member() will 1100 * be called. 1101 */ 1102 p->vid_member = (1 << i); 1103 p->member = dev->port_mask; 1104 ksz9477_port_stp_state_set(ds, i, BR_STATE_DISABLED); 1105 p->on = 1; 1106 if (i < dev->phy_port_cnt) 1107 p->phy = 1; 1108 if (dev->chip_id == 0x00947700 && i == 6) { 1109 p->sgmii = 1; 1110 1111 /* SGMII PHY detection code is not implemented yet. */ 1112 p->phy = 0; 1113 } 1114 } 1115 } 1116 1117 static int ksz9477_setup(struct dsa_switch *ds) 1118 { 1119 struct ksz_device *dev = ds->priv; 1120 int ret = 0; 1121 1122 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 1123 dev->num_vlans, GFP_KERNEL); 1124 if (!dev->vlan_cache) 1125 return -ENOMEM; 1126 1127 ret = ksz9477_reset_switch(dev); 1128 if (ret) { 1129 dev_err(ds->dev, "failed to reset switch\n"); 1130 return ret; 1131 } 1132 1133 /* accept packet up to 2000bytes */ 1134 ksz_cfg(dev, REG_SW_MAC_CTRL_1, SW_LEGAL_PACKET_DISABLE, true); 1135 1136 ksz9477_config_cpu_port(ds); 1137 1138 ksz_cfg(dev, REG_SW_MAC_CTRL_1, MULTICAST_STORM_DISABLE, true); 1139 1140 /* queue based egress rate limit */ 1141 ksz_cfg(dev, REG_SW_MAC_CTRL_5, SW_OUT_RATE_LIMIT_QUEUE_BASED, true); 1142 1143 /* start switch */ 1144 ksz_cfg(dev, REG_SW_OPERATION, SW_START, true); 1145 1146 return 0; 1147 } 1148 1149 static const struct dsa_switch_ops ksz9477_switch_ops = { 1150 .get_tag_protocol = ksz9477_get_tag_protocol, 1151 .setup = ksz9477_setup, 1152 .phy_read = ksz9477_phy_read16, 1153 .phy_write = ksz9477_phy_write16, 1154 .port_enable = ksz_enable_port, 1155 .port_disable = ksz_disable_port, 1156 .get_strings = ksz9477_get_strings, 1157 .get_ethtool_stats = ksz_get_ethtool_stats, 1158 .get_sset_count = ksz_sset_count, 1159 .port_bridge_join = ksz_port_bridge_join, 1160 .port_bridge_leave = ksz_port_bridge_leave, 1161 .port_stp_state_set = ksz9477_port_stp_state_set, 1162 .port_fast_age = ksz_port_fast_age, 1163 .port_vlan_filtering = ksz9477_port_vlan_filtering, 1164 .port_vlan_prepare = ksz_port_vlan_prepare, 1165 .port_vlan_add = ksz9477_port_vlan_add, 1166 .port_vlan_del = ksz9477_port_vlan_del, 1167 .port_fdb_dump = ksz9477_port_fdb_dump, 1168 .port_fdb_add = ksz9477_port_fdb_add, 1169 .port_fdb_del = ksz9477_port_fdb_del, 1170 .port_mdb_prepare = ksz_port_mdb_prepare, 1171 .port_mdb_add = ksz9477_port_mdb_add, 1172 .port_mdb_del = ksz9477_port_mdb_del, 1173 .port_mirror_add = ksz9477_port_mirror_add, 1174 .port_mirror_del = ksz9477_port_mirror_del, 1175 }; 1176 1177 static u32 ksz9477_get_port_addr(int port, int offset) 1178 { 1179 return PORT_CTRL_ADDR(port, offset); 1180 } 1181 1182 static int ksz9477_switch_detect(struct ksz_device *dev) 1183 { 1184 u8 data8; 1185 u32 id32; 1186 int ret; 1187 1188 /* turn off SPI DO Edge select */ 1189 ret = ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8); 1190 if (ret) 1191 return ret; 1192 1193 data8 &= ~SPI_AUTO_EDGE_DETECTION; 1194 ret = ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8); 1195 if (ret) 1196 return ret; 1197 1198 /* read chip id */ 1199 ret = ksz_read32(dev, REG_CHIP_ID0__1, &id32); 1200 if (ret) 1201 return ret; 1202 1203 /* Number of ports can be reduced depending on chip. */ 1204 dev->mib_port_cnt = TOTAL_PORT_NUM; 1205 dev->phy_port_cnt = 5; 1206 1207 dev->chip_id = id32; 1208 1209 return 0; 1210 } 1211 1212 struct ksz_chip_data { 1213 u32 chip_id; 1214 const char *dev_name; 1215 int num_vlans; 1216 int num_alus; 1217 int num_statics; 1218 int cpu_ports; 1219 int port_cnt; 1220 }; 1221 1222 static const struct ksz_chip_data ksz9477_switch_chips[] = { 1223 { 1224 .chip_id = 0x00947700, 1225 .dev_name = "KSZ9477", 1226 .num_vlans = 4096, 1227 .num_alus = 4096, 1228 .num_statics = 16, 1229 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1230 .port_cnt = 7, /* total physical port count */ 1231 }, 1232 { 1233 .chip_id = 0x00989700, 1234 .dev_name = "KSZ9897", 1235 .num_vlans = 4096, 1236 .num_alus = 4096, 1237 .num_statics = 16, 1238 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1239 .port_cnt = 7, /* total physical port count */ 1240 }, 1241 }; 1242 1243 static int ksz9477_switch_init(struct ksz_device *dev) 1244 { 1245 int i; 1246 1247 dev->ds->ops = &ksz9477_switch_ops; 1248 1249 for (i = 0; i < ARRAY_SIZE(ksz9477_switch_chips); i++) { 1250 const struct ksz_chip_data *chip = &ksz9477_switch_chips[i]; 1251 1252 if (dev->chip_id == chip->chip_id) { 1253 dev->name = chip->dev_name; 1254 dev->num_vlans = chip->num_vlans; 1255 dev->num_alus = chip->num_alus; 1256 dev->num_statics = chip->num_statics; 1257 dev->port_cnt = chip->port_cnt; 1258 dev->cpu_ports = chip->cpu_ports; 1259 1260 break; 1261 } 1262 } 1263 1264 /* no switch found */ 1265 if (!dev->port_cnt) 1266 return -ENODEV; 1267 1268 dev->port_mask = (1 << dev->port_cnt) - 1; 1269 1270 dev->reg_mib_cnt = SWITCH_COUNTER_NUM; 1271 dev->mib_cnt = TOTAL_SWITCH_COUNTER_NUM; 1272 1273 i = dev->mib_port_cnt; 1274 dev->ports = devm_kzalloc(dev->dev, sizeof(struct ksz_port) * i, 1275 GFP_KERNEL); 1276 if (!dev->ports) 1277 return -ENOMEM; 1278 for (i = 0; i < dev->mib_port_cnt; i++) { 1279 dev->ports[i].mib.counters = 1280 devm_kzalloc(dev->dev, 1281 sizeof(u64) * 1282 (TOTAL_SWITCH_COUNTER_NUM + 1), 1283 GFP_KERNEL); 1284 if (!dev->ports[i].mib.counters) 1285 return -ENOMEM; 1286 } 1287 dev->interface = PHY_INTERFACE_MODE_RGMII_TXID; 1288 1289 return 0; 1290 } 1291 1292 static void ksz9477_switch_exit(struct ksz_device *dev) 1293 { 1294 ksz9477_reset_switch(dev); 1295 } 1296 1297 static const struct ksz_dev_ops ksz9477_dev_ops = { 1298 .get_port_addr = ksz9477_get_port_addr, 1299 .cfg_port_member = ksz9477_cfg_port_member, 1300 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 1301 .port_setup = ksz9477_port_setup, 1302 .shutdown = ksz9477_reset_switch, 1303 .detect = ksz9477_switch_detect, 1304 .init = ksz9477_switch_init, 1305 .exit = ksz9477_switch_exit, 1306 }; 1307 1308 int ksz9477_switch_register(struct ksz_device *dev) 1309 { 1310 return ksz_switch_register(dev, &ksz9477_dev_ops); 1311 } 1312 EXPORT_SYMBOL(ksz9477_switch_register); 1313 1314 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 1315 MODULE_DESCRIPTION("Microchip KSZ9477 Series Switch DSA Driver"); 1316 MODULE_LICENSE("GPL"); 1317