1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip KSZ9477 switch driver main logic 4 * 5 * Copyright (C) 2017-2018 Microchip Technology Inc. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/export.h> 10 #include <linux/gpio.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/platform_data/microchip-ksz.h> 14 #include <linux/phy.h> 15 #include <linux/etherdevice.h> 16 #include <linux/if_bridge.h> 17 #include <net/dsa.h> 18 #include <net/switchdev.h> 19 20 #include "ksz_priv.h" 21 #include "ksz_common.h" 22 #include "ksz9477_reg.h" 23 24 static const struct { 25 int index; 26 char string[ETH_GSTRING_LEN]; 27 } ksz9477_mib_names[TOTAL_SWITCH_COUNTER_NUM] = { 28 { 0x00, "rx_hi" }, 29 { 0x01, "rx_undersize" }, 30 { 0x02, "rx_fragments" }, 31 { 0x03, "rx_oversize" }, 32 { 0x04, "rx_jabbers" }, 33 { 0x05, "rx_symbol_err" }, 34 { 0x06, "rx_crc_err" }, 35 { 0x07, "rx_align_err" }, 36 { 0x08, "rx_mac_ctrl" }, 37 { 0x09, "rx_pause" }, 38 { 0x0A, "rx_bcast" }, 39 { 0x0B, "rx_mcast" }, 40 { 0x0C, "rx_ucast" }, 41 { 0x0D, "rx_64_or_less" }, 42 { 0x0E, "rx_65_127" }, 43 { 0x0F, "rx_128_255" }, 44 { 0x10, "rx_256_511" }, 45 { 0x11, "rx_512_1023" }, 46 { 0x12, "rx_1024_1522" }, 47 { 0x13, "rx_1523_2000" }, 48 { 0x14, "rx_2001" }, 49 { 0x15, "tx_hi" }, 50 { 0x16, "tx_late_col" }, 51 { 0x17, "tx_pause" }, 52 { 0x18, "tx_bcast" }, 53 { 0x19, "tx_mcast" }, 54 { 0x1A, "tx_ucast" }, 55 { 0x1B, "tx_deferred" }, 56 { 0x1C, "tx_total_col" }, 57 { 0x1D, "tx_exc_col" }, 58 { 0x1E, "tx_single_col" }, 59 { 0x1F, "tx_mult_col" }, 60 { 0x80, "rx_total" }, 61 { 0x81, "tx_total" }, 62 { 0x82, "rx_discards" }, 63 { 0x83, "tx_discards" }, 64 }; 65 66 static void ksz9477_cfg32(struct ksz_device *dev, u32 addr, u32 bits, bool set) 67 { 68 u32 data; 69 70 ksz_read32(dev, addr, &data); 71 if (set) 72 data |= bits; 73 else 74 data &= ~bits; 75 ksz_write32(dev, addr, data); 76 } 77 78 static void ksz9477_port_cfg32(struct ksz_device *dev, int port, int offset, 79 u32 bits, bool set) 80 { 81 u32 addr; 82 u32 data; 83 84 addr = PORT_CTRL_ADDR(port, offset); 85 ksz_read32(dev, addr, &data); 86 87 if (set) 88 data |= bits; 89 else 90 data &= ~bits; 91 92 ksz_write32(dev, addr, data); 93 } 94 95 static int ksz9477_wait_vlan_ctrl_ready(struct ksz_device *dev, u32 waiton, 96 int timeout) 97 { 98 u8 data; 99 100 do { 101 ksz_read8(dev, REG_SW_VLAN_CTRL, &data); 102 if (!(data & waiton)) 103 break; 104 usleep_range(1, 10); 105 } while (timeout-- > 0); 106 107 if (timeout <= 0) 108 return -ETIMEDOUT; 109 110 return 0; 111 } 112 113 static int ksz9477_get_vlan_table(struct ksz_device *dev, u16 vid, 114 u32 *vlan_table) 115 { 116 int ret; 117 118 mutex_lock(&dev->vlan_mutex); 119 120 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 121 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_READ | VLAN_START); 122 123 /* wait to be cleared */ 124 ret = ksz9477_wait_vlan_ctrl_ready(dev, VLAN_START, 1000); 125 if (ret < 0) { 126 dev_dbg(dev->dev, "Failed to read vlan table\n"); 127 goto exit; 128 } 129 130 ksz_read32(dev, REG_SW_VLAN_ENTRY__4, &vlan_table[0]); 131 ksz_read32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, &vlan_table[1]); 132 ksz_read32(dev, REG_SW_VLAN_ENTRY_PORTS__4, &vlan_table[2]); 133 134 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 135 136 exit: 137 mutex_unlock(&dev->vlan_mutex); 138 139 return ret; 140 } 141 142 static int ksz9477_set_vlan_table(struct ksz_device *dev, u16 vid, 143 u32 *vlan_table) 144 { 145 int ret; 146 147 mutex_lock(&dev->vlan_mutex); 148 149 ksz_write32(dev, REG_SW_VLAN_ENTRY__4, vlan_table[0]); 150 ksz_write32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, vlan_table[1]); 151 ksz_write32(dev, REG_SW_VLAN_ENTRY_PORTS__4, vlan_table[2]); 152 153 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 154 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_START | VLAN_WRITE); 155 156 /* wait to be cleared */ 157 ret = ksz9477_wait_vlan_ctrl_ready(dev, VLAN_START, 1000); 158 if (ret < 0) { 159 dev_dbg(dev->dev, "Failed to write vlan table\n"); 160 goto exit; 161 } 162 163 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 164 165 /* update vlan cache table */ 166 dev->vlan_cache[vid].table[0] = vlan_table[0]; 167 dev->vlan_cache[vid].table[1] = vlan_table[1]; 168 dev->vlan_cache[vid].table[2] = vlan_table[2]; 169 170 exit: 171 mutex_unlock(&dev->vlan_mutex); 172 173 return ret; 174 } 175 176 static void ksz9477_read_table(struct ksz_device *dev, u32 *table) 177 { 178 ksz_read32(dev, REG_SW_ALU_VAL_A, &table[0]); 179 ksz_read32(dev, REG_SW_ALU_VAL_B, &table[1]); 180 ksz_read32(dev, REG_SW_ALU_VAL_C, &table[2]); 181 ksz_read32(dev, REG_SW_ALU_VAL_D, &table[3]); 182 } 183 184 static void ksz9477_write_table(struct ksz_device *dev, u32 *table) 185 { 186 ksz_write32(dev, REG_SW_ALU_VAL_A, table[0]); 187 ksz_write32(dev, REG_SW_ALU_VAL_B, table[1]); 188 ksz_write32(dev, REG_SW_ALU_VAL_C, table[2]); 189 ksz_write32(dev, REG_SW_ALU_VAL_D, table[3]); 190 } 191 192 static int ksz9477_wait_alu_ready(struct ksz_device *dev, u32 waiton, 193 int timeout) 194 { 195 u32 data; 196 197 do { 198 ksz_read32(dev, REG_SW_ALU_CTRL__4, &data); 199 if (!(data & waiton)) 200 break; 201 usleep_range(1, 10); 202 } while (timeout-- > 0); 203 204 if (timeout <= 0) 205 return -ETIMEDOUT; 206 207 return 0; 208 } 209 210 static int ksz9477_wait_alu_sta_ready(struct ksz_device *dev, u32 waiton, 211 int timeout) 212 { 213 u32 data; 214 215 do { 216 ksz_read32(dev, REG_SW_ALU_STAT_CTRL__4, &data); 217 if (!(data & waiton)) 218 break; 219 usleep_range(1, 10); 220 } while (timeout-- > 0); 221 222 if (timeout <= 0) 223 return -ETIMEDOUT; 224 225 return 0; 226 } 227 228 static int ksz9477_reset_switch(struct ksz_device *dev) 229 { 230 u8 data8; 231 u16 data16; 232 u32 data32; 233 234 /* reset switch */ 235 ksz_cfg(dev, REG_SW_OPERATION, SW_RESET, true); 236 237 /* turn off SPI DO Edge select */ 238 ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8); 239 data8 &= ~SPI_AUTO_EDGE_DETECTION; 240 ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8); 241 242 /* default configuration */ 243 ksz_read8(dev, REG_SW_LUE_CTRL_1, &data8); 244 data8 = SW_AGING_ENABLE | SW_LINK_AUTO_AGING | 245 SW_SRC_ADDR_FILTER | SW_FLUSH_STP_TABLE | SW_FLUSH_MSTP_TABLE; 246 ksz_write8(dev, REG_SW_LUE_CTRL_1, data8); 247 248 /* disable interrupts */ 249 ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK); 250 ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0x7F); 251 ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32); 252 253 /* set broadcast storm protection 10% rate */ 254 ksz_read16(dev, REG_SW_MAC_CTRL_2, &data16); 255 data16 &= ~BROADCAST_STORM_RATE; 256 data16 |= (BROADCAST_STORM_VALUE * BROADCAST_STORM_PROT_RATE) / 100; 257 ksz_write16(dev, REG_SW_MAC_CTRL_2, data16); 258 259 return 0; 260 } 261 262 static enum dsa_tag_protocol ksz9477_get_tag_protocol(struct dsa_switch *ds, 263 int port) 264 { 265 return DSA_TAG_PROTO_KSZ9477; 266 } 267 268 static int ksz9477_phy_read16(struct dsa_switch *ds, int addr, int reg) 269 { 270 struct ksz_device *dev = ds->priv; 271 u16 val = 0xffff; 272 273 /* No real PHY after this. Simulate the PHY. 274 * A fixed PHY can be setup in the device tree, but this function is 275 * still called for that port during initialization. 276 * For RGMII PHY there is no way to access it so the fixed PHY should 277 * be used. For SGMII PHY the supporting code will be added later. 278 */ 279 if (addr >= dev->phy_port_cnt) { 280 struct ksz_port *p = &dev->ports[addr]; 281 282 switch (reg) { 283 case MII_BMCR: 284 val = 0x1140; 285 break; 286 case MII_BMSR: 287 val = 0x796d; 288 break; 289 case MII_PHYSID1: 290 val = 0x0022; 291 break; 292 case MII_PHYSID2: 293 val = 0x1631; 294 break; 295 case MII_ADVERTISE: 296 val = 0x05e1; 297 break; 298 case MII_LPA: 299 val = 0xc5e1; 300 break; 301 case MII_CTRL1000: 302 val = 0x0700; 303 break; 304 case MII_STAT1000: 305 if (p->phydev.speed == SPEED_1000) 306 val = 0x3800; 307 else 308 val = 0; 309 break; 310 } 311 } else { 312 ksz_pread16(dev, addr, 0x100 + (reg << 1), &val); 313 } 314 315 return val; 316 } 317 318 static int ksz9477_phy_write16(struct dsa_switch *ds, int addr, int reg, 319 u16 val) 320 { 321 struct ksz_device *dev = ds->priv; 322 323 /* No real PHY after this. */ 324 if (addr >= dev->phy_port_cnt) 325 return 0; 326 ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val); 327 328 return 0; 329 } 330 331 static void ksz9477_get_strings(struct dsa_switch *ds, int port, 332 u32 stringset, uint8_t *buf) 333 { 334 int i; 335 336 if (stringset != ETH_SS_STATS) 337 return; 338 339 for (i = 0; i < TOTAL_SWITCH_COUNTER_NUM; i++) { 340 memcpy(buf + i * ETH_GSTRING_LEN, ksz9477_mib_names[i].string, 341 ETH_GSTRING_LEN); 342 } 343 } 344 345 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, 346 uint64_t *buf) 347 { 348 struct ksz_device *dev = ds->priv; 349 int i; 350 u32 data; 351 int timeout; 352 353 mutex_lock(&dev->stats_mutex); 354 355 for (i = 0; i < TOTAL_SWITCH_COUNTER_NUM; i++) { 356 data = MIB_COUNTER_READ; 357 data |= ((ksz9477_mib_names[i].index & 0xFF) << 358 MIB_COUNTER_INDEX_S); 359 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, data); 360 361 timeout = 1000; 362 do { 363 ksz_pread32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 364 &data); 365 usleep_range(1, 10); 366 if (!(data & MIB_COUNTER_READ)) 367 break; 368 } while (timeout-- > 0); 369 370 /* failed to read MIB. get out of loop */ 371 if (!timeout) { 372 dev_dbg(dev->dev, "Failed to get MIB\n"); 373 break; 374 } 375 376 /* count resets upon read */ 377 ksz_pread32(dev, port, REG_PORT_MIB_DATA, &data); 378 379 dev->mib_value[i] += (uint64_t)data; 380 buf[i] = dev->mib_value[i]; 381 } 382 383 mutex_unlock(&dev->stats_mutex); 384 } 385 386 static void ksz9477_cfg_port_member(struct ksz_device *dev, int port, 387 u8 member) 388 { 389 ksz_pwrite32(dev, port, REG_PORT_VLAN_MEMBERSHIP__4, member); 390 dev->ports[port].member = member; 391 } 392 393 static void ksz9477_port_stp_state_set(struct dsa_switch *ds, int port, 394 u8 state) 395 { 396 struct ksz_device *dev = ds->priv; 397 struct ksz_port *p = &dev->ports[port]; 398 u8 data; 399 int member = -1; 400 int forward = dev->member; 401 402 ksz_pread8(dev, port, P_STP_CTRL, &data); 403 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 404 405 switch (state) { 406 case BR_STATE_DISABLED: 407 data |= PORT_LEARN_DISABLE; 408 if (port != dev->cpu_port) 409 member = 0; 410 break; 411 case BR_STATE_LISTENING: 412 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 413 if (port != dev->cpu_port && 414 p->stp_state == BR_STATE_DISABLED) 415 member = dev->host_mask | p->vid_member; 416 break; 417 case BR_STATE_LEARNING: 418 data |= PORT_RX_ENABLE; 419 break; 420 case BR_STATE_FORWARDING: 421 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 422 423 /* This function is also used internally. */ 424 if (port == dev->cpu_port) 425 break; 426 427 member = dev->host_mask | p->vid_member; 428 429 /* Port is a member of a bridge. */ 430 if (dev->br_member & (1 << port)) { 431 dev->member |= (1 << port); 432 member = dev->member; 433 } 434 break; 435 case BR_STATE_BLOCKING: 436 data |= PORT_LEARN_DISABLE; 437 if (port != dev->cpu_port && 438 p->stp_state == BR_STATE_DISABLED) 439 member = dev->host_mask | p->vid_member; 440 break; 441 default: 442 dev_err(ds->dev, "invalid STP state: %d\n", state); 443 return; 444 } 445 446 ksz_pwrite8(dev, port, P_STP_CTRL, data); 447 p->stp_state = state; 448 if (data & PORT_RX_ENABLE) 449 dev->rx_ports |= (1 << port); 450 else 451 dev->rx_ports &= ~(1 << port); 452 if (data & PORT_TX_ENABLE) 453 dev->tx_ports |= (1 << port); 454 else 455 dev->tx_ports &= ~(1 << port); 456 457 /* Port membership may share register with STP state. */ 458 if (member >= 0 && member != p->member) 459 ksz9477_cfg_port_member(dev, port, (u8)member); 460 461 /* Check if forwarding needs to be updated. */ 462 if (state != BR_STATE_FORWARDING) { 463 if (dev->br_member & (1 << port)) 464 dev->member &= ~(1 << port); 465 } 466 467 /* When topology has changed the function ksz_update_port_member 468 * should be called to modify port forwarding behavior. 469 */ 470 if (forward != dev->member) 471 ksz_update_port_member(dev, port); 472 } 473 474 static void ksz9477_flush_dyn_mac_table(struct ksz_device *dev, int port) 475 { 476 u8 data; 477 478 ksz_read8(dev, REG_SW_LUE_CTRL_2, &data); 479 data &= ~(SW_FLUSH_OPTION_M << SW_FLUSH_OPTION_S); 480 data |= (SW_FLUSH_OPTION_DYN_MAC << SW_FLUSH_OPTION_S); 481 ksz_write8(dev, REG_SW_LUE_CTRL_2, data); 482 if (port < dev->mib_port_cnt) { 483 /* flush individual port */ 484 ksz_pread8(dev, port, P_STP_CTRL, &data); 485 if (!(data & PORT_LEARN_DISABLE)) 486 ksz_pwrite8(dev, port, P_STP_CTRL, 487 data | PORT_LEARN_DISABLE); 488 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true); 489 ksz_pwrite8(dev, port, P_STP_CTRL, data); 490 } else { 491 /* flush all */ 492 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_STP_TABLE, true); 493 } 494 } 495 496 static int ksz9477_port_vlan_filtering(struct dsa_switch *ds, int port, 497 bool flag) 498 { 499 struct ksz_device *dev = ds->priv; 500 501 if (flag) { 502 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 503 PORT_VLAN_LOOKUP_VID_0, true); 504 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, true); 505 } else { 506 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, false); 507 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 508 PORT_VLAN_LOOKUP_VID_0, false); 509 } 510 511 return 0; 512 } 513 514 static void ksz9477_port_vlan_add(struct dsa_switch *ds, int port, 515 const struct switchdev_obj_port_vlan *vlan) 516 { 517 struct ksz_device *dev = ds->priv; 518 u32 vlan_table[3]; 519 u16 vid; 520 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 521 522 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 523 if (ksz9477_get_vlan_table(dev, vid, vlan_table)) { 524 dev_dbg(dev->dev, "Failed to get vlan table\n"); 525 return; 526 } 527 528 vlan_table[0] = VLAN_VALID | (vid & VLAN_FID_M); 529 if (untagged) 530 vlan_table[1] |= BIT(port); 531 else 532 vlan_table[1] &= ~BIT(port); 533 vlan_table[1] &= ~(BIT(dev->cpu_port)); 534 535 vlan_table[2] |= BIT(port) | BIT(dev->cpu_port); 536 537 if (ksz9477_set_vlan_table(dev, vid, vlan_table)) { 538 dev_dbg(dev->dev, "Failed to set vlan table\n"); 539 return; 540 } 541 542 /* change PVID */ 543 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) 544 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, vid); 545 } 546 } 547 548 static int ksz9477_port_vlan_del(struct dsa_switch *ds, int port, 549 const struct switchdev_obj_port_vlan *vlan) 550 { 551 struct ksz_device *dev = ds->priv; 552 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 553 u32 vlan_table[3]; 554 u16 vid; 555 u16 pvid; 556 557 ksz_pread16(dev, port, REG_PORT_DEFAULT_VID, &pvid); 558 pvid = pvid & 0xFFF; 559 560 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 561 if (ksz9477_get_vlan_table(dev, vid, vlan_table)) { 562 dev_dbg(dev->dev, "Failed to get vlan table\n"); 563 return -ETIMEDOUT; 564 } 565 566 vlan_table[2] &= ~BIT(port); 567 568 if (pvid == vid) 569 pvid = 1; 570 571 if (untagged) 572 vlan_table[1] &= ~BIT(port); 573 574 if (ksz9477_set_vlan_table(dev, vid, vlan_table)) { 575 dev_dbg(dev->dev, "Failed to set vlan table\n"); 576 return -ETIMEDOUT; 577 } 578 } 579 580 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, pvid); 581 582 return 0; 583 } 584 585 static int ksz9477_port_fdb_add(struct dsa_switch *ds, int port, 586 const unsigned char *addr, u16 vid) 587 { 588 struct ksz_device *dev = ds->priv; 589 u32 alu_table[4]; 590 u32 data; 591 int ret = 0; 592 593 mutex_lock(&dev->alu_mutex); 594 595 /* find any entry with mac & vid */ 596 data = vid << ALU_FID_INDEX_S; 597 data |= ((addr[0] << 8) | addr[1]); 598 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 599 600 data = ((addr[2] << 24) | (addr[3] << 16)); 601 data |= ((addr[4] << 8) | addr[5]); 602 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 603 604 /* start read operation */ 605 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 606 607 /* wait to be finished */ 608 ret = ksz9477_wait_alu_ready(dev, ALU_START, 1000); 609 if (ret < 0) { 610 dev_dbg(dev->dev, "Failed to read ALU\n"); 611 goto exit; 612 } 613 614 /* read ALU entry */ 615 ksz9477_read_table(dev, alu_table); 616 617 /* update ALU entry */ 618 alu_table[0] = ALU_V_STATIC_VALID; 619 alu_table[1] |= BIT(port); 620 if (vid) 621 alu_table[1] |= ALU_V_USE_FID; 622 alu_table[2] = (vid << ALU_V_FID_S); 623 alu_table[2] |= ((addr[0] << 8) | addr[1]); 624 alu_table[3] = ((addr[2] << 24) | (addr[3] << 16)); 625 alu_table[3] |= ((addr[4] << 8) | addr[5]); 626 627 ksz9477_write_table(dev, alu_table); 628 629 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 630 631 /* wait to be finished */ 632 ret = ksz9477_wait_alu_ready(dev, ALU_START, 1000); 633 if (ret < 0) 634 dev_dbg(dev->dev, "Failed to write ALU\n"); 635 636 exit: 637 mutex_unlock(&dev->alu_mutex); 638 639 return ret; 640 } 641 642 static int ksz9477_port_fdb_del(struct dsa_switch *ds, int port, 643 const unsigned char *addr, u16 vid) 644 { 645 struct ksz_device *dev = ds->priv; 646 u32 alu_table[4]; 647 u32 data; 648 int ret = 0; 649 650 mutex_lock(&dev->alu_mutex); 651 652 /* read any entry with mac & vid */ 653 data = vid << ALU_FID_INDEX_S; 654 data |= ((addr[0] << 8) | addr[1]); 655 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 656 657 data = ((addr[2] << 24) | (addr[3] << 16)); 658 data |= ((addr[4] << 8) | addr[5]); 659 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 660 661 /* start read operation */ 662 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 663 664 /* wait to be finished */ 665 ret = ksz9477_wait_alu_ready(dev, ALU_START, 1000); 666 if (ret < 0) { 667 dev_dbg(dev->dev, "Failed to read ALU\n"); 668 goto exit; 669 } 670 671 ksz_read32(dev, REG_SW_ALU_VAL_A, &alu_table[0]); 672 if (alu_table[0] & ALU_V_STATIC_VALID) { 673 ksz_read32(dev, REG_SW_ALU_VAL_B, &alu_table[1]); 674 ksz_read32(dev, REG_SW_ALU_VAL_C, &alu_table[2]); 675 ksz_read32(dev, REG_SW_ALU_VAL_D, &alu_table[3]); 676 677 /* clear forwarding port */ 678 alu_table[2] &= ~BIT(port); 679 680 /* if there is no port to forward, clear table */ 681 if ((alu_table[2] & ALU_V_PORT_MAP) == 0) { 682 alu_table[0] = 0; 683 alu_table[1] = 0; 684 alu_table[2] = 0; 685 alu_table[3] = 0; 686 } 687 } else { 688 alu_table[0] = 0; 689 alu_table[1] = 0; 690 alu_table[2] = 0; 691 alu_table[3] = 0; 692 } 693 694 ksz9477_write_table(dev, alu_table); 695 696 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 697 698 /* wait to be finished */ 699 ret = ksz9477_wait_alu_ready(dev, ALU_START, 1000); 700 if (ret < 0) 701 dev_dbg(dev->dev, "Failed to write ALU\n"); 702 703 exit: 704 mutex_unlock(&dev->alu_mutex); 705 706 return ret; 707 } 708 709 static void ksz9477_convert_alu(struct alu_struct *alu, u32 *alu_table) 710 { 711 alu->is_static = !!(alu_table[0] & ALU_V_STATIC_VALID); 712 alu->is_src_filter = !!(alu_table[0] & ALU_V_SRC_FILTER); 713 alu->is_dst_filter = !!(alu_table[0] & ALU_V_DST_FILTER); 714 alu->prio_age = (alu_table[0] >> ALU_V_PRIO_AGE_CNT_S) & 715 ALU_V_PRIO_AGE_CNT_M; 716 alu->mstp = alu_table[0] & ALU_V_MSTP_M; 717 718 alu->is_override = !!(alu_table[1] & ALU_V_OVERRIDE); 719 alu->is_use_fid = !!(alu_table[1] & ALU_V_USE_FID); 720 alu->port_forward = alu_table[1] & ALU_V_PORT_MAP; 721 722 alu->fid = (alu_table[2] >> ALU_V_FID_S) & ALU_V_FID_M; 723 724 alu->mac[0] = (alu_table[2] >> 8) & 0xFF; 725 alu->mac[1] = alu_table[2] & 0xFF; 726 alu->mac[2] = (alu_table[3] >> 24) & 0xFF; 727 alu->mac[3] = (alu_table[3] >> 16) & 0xFF; 728 alu->mac[4] = (alu_table[3] >> 8) & 0xFF; 729 alu->mac[5] = alu_table[3] & 0xFF; 730 } 731 732 static int ksz9477_port_fdb_dump(struct dsa_switch *ds, int port, 733 dsa_fdb_dump_cb_t *cb, void *data) 734 { 735 struct ksz_device *dev = ds->priv; 736 int ret = 0; 737 u32 ksz_data; 738 u32 alu_table[4]; 739 struct alu_struct alu; 740 int timeout; 741 742 mutex_lock(&dev->alu_mutex); 743 744 /* start ALU search */ 745 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_START | ALU_SEARCH); 746 747 do { 748 timeout = 1000; 749 do { 750 ksz_read32(dev, REG_SW_ALU_CTRL__4, &ksz_data); 751 if ((ksz_data & ALU_VALID) || !(ksz_data & ALU_START)) 752 break; 753 usleep_range(1, 10); 754 } while (timeout-- > 0); 755 756 if (!timeout) { 757 dev_dbg(dev->dev, "Failed to search ALU\n"); 758 ret = -ETIMEDOUT; 759 goto exit; 760 } 761 762 /* read ALU table */ 763 ksz9477_read_table(dev, alu_table); 764 765 ksz9477_convert_alu(&alu, alu_table); 766 767 if (alu.port_forward & BIT(port)) { 768 ret = cb(alu.mac, alu.fid, alu.is_static, data); 769 if (ret) 770 goto exit; 771 } 772 } while (ksz_data & ALU_START); 773 774 exit: 775 776 /* stop ALU search */ 777 ksz_write32(dev, REG_SW_ALU_CTRL__4, 0); 778 779 mutex_unlock(&dev->alu_mutex); 780 781 return ret; 782 } 783 784 static void ksz9477_port_mdb_add(struct dsa_switch *ds, int port, 785 const struct switchdev_obj_port_mdb *mdb) 786 { 787 struct ksz_device *dev = ds->priv; 788 u32 static_table[4]; 789 u32 data; 790 int index; 791 u32 mac_hi, mac_lo; 792 793 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 794 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 795 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 796 797 mutex_lock(&dev->alu_mutex); 798 799 for (index = 0; index < dev->num_statics; index++) { 800 /* find empty slot first */ 801 data = (index << ALU_STAT_INDEX_S) | 802 ALU_STAT_READ | ALU_STAT_START; 803 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 804 805 /* wait to be finished */ 806 if (ksz9477_wait_alu_sta_ready(dev, ALU_STAT_START, 1000) < 0) { 807 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 808 goto exit; 809 } 810 811 /* read ALU static table */ 812 ksz9477_read_table(dev, static_table); 813 814 if (static_table[0] & ALU_V_STATIC_VALID) { 815 /* check this has same vid & mac address */ 816 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 817 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 818 static_table[3] == mac_lo) { 819 /* found matching one */ 820 break; 821 } 822 } else { 823 /* found empty one */ 824 break; 825 } 826 } 827 828 /* no available entry */ 829 if (index == dev->num_statics) 830 goto exit; 831 832 /* add entry */ 833 static_table[0] = ALU_V_STATIC_VALID; 834 static_table[1] |= BIT(port); 835 if (mdb->vid) 836 static_table[1] |= ALU_V_USE_FID; 837 static_table[2] = (mdb->vid << ALU_V_FID_S); 838 static_table[2] |= mac_hi; 839 static_table[3] = mac_lo; 840 841 ksz9477_write_table(dev, static_table); 842 843 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START; 844 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 845 846 /* wait to be finished */ 847 if (ksz9477_wait_alu_sta_ready(dev, ALU_STAT_START, 1000) < 0) 848 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 849 850 exit: 851 mutex_unlock(&dev->alu_mutex); 852 } 853 854 static int ksz9477_port_mdb_del(struct dsa_switch *ds, int port, 855 const struct switchdev_obj_port_mdb *mdb) 856 { 857 struct ksz_device *dev = ds->priv; 858 u32 static_table[4]; 859 u32 data; 860 int index; 861 int ret = 0; 862 u32 mac_hi, mac_lo; 863 864 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 865 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 866 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 867 868 mutex_lock(&dev->alu_mutex); 869 870 for (index = 0; index < dev->num_statics; index++) { 871 /* find empty slot first */ 872 data = (index << ALU_STAT_INDEX_S) | 873 ALU_STAT_READ | ALU_STAT_START; 874 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 875 876 /* wait to be finished */ 877 ret = ksz9477_wait_alu_sta_ready(dev, ALU_STAT_START, 1000); 878 if (ret < 0) { 879 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 880 goto exit; 881 } 882 883 /* read ALU static table */ 884 ksz9477_read_table(dev, static_table); 885 886 if (static_table[0] & ALU_V_STATIC_VALID) { 887 /* check this has same vid & mac address */ 888 889 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 890 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 891 static_table[3] == mac_lo) { 892 /* found matching one */ 893 break; 894 } 895 } 896 } 897 898 /* no available entry */ 899 if (index == dev->num_statics) 900 goto exit; 901 902 /* clear port */ 903 static_table[1] &= ~BIT(port); 904 905 if ((static_table[1] & ALU_V_PORT_MAP) == 0) { 906 /* delete entry */ 907 static_table[0] = 0; 908 static_table[1] = 0; 909 static_table[2] = 0; 910 static_table[3] = 0; 911 } 912 913 ksz9477_write_table(dev, static_table); 914 915 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START; 916 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 917 918 /* wait to be finished */ 919 ret = ksz9477_wait_alu_sta_ready(dev, ALU_STAT_START, 1000); 920 if (ret < 0) 921 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 922 923 exit: 924 mutex_unlock(&dev->alu_mutex); 925 926 return ret; 927 } 928 929 static int ksz9477_port_mirror_add(struct dsa_switch *ds, int port, 930 struct dsa_mall_mirror_tc_entry *mirror, 931 bool ingress) 932 { 933 struct ksz_device *dev = ds->priv; 934 935 if (ingress) 936 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true); 937 else 938 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true); 939 940 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false); 941 942 /* configure mirror port */ 943 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 944 PORT_MIRROR_SNIFFER, true); 945 946 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false); 947 948 return 0; 949 } 950 951 static void ksz9477_port_mirror_del(struct dsa_switch *ds, int port, 952 struct dsa_mall_mirror_tc_entry *mirror) 953 { 954 struct ksz_device *dev = ds->priv; 955 u8 data; 956 957 if (mirror->ingress) 958 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false); 959 else 960 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false); 961 962 ksz_pread8(dev, port, P_MIRROR_CTRL, &data); 963 964 if (!(data & (PORT_MIRROR_RX | PORT_MIRROR_TX))) 965 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 966 PORT_MIRROR_SNIFFER, false); 967 } 968 969 static void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port) 970 { 971 u8 data8; 972 u8 member; 973 u16 data16; 974 struct ksz_port *p = &dev->ports[port]; 975 976 /* enable tag tail for host port */ 977 if (cpu_port) 978 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_TAIL_TAG_ENABLE, 979 true); 980 981 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_MAC_LOOPBACK, false); 982 983 /* set back pressure */ 984 ksz_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, true); 985 986 /* enable broadcast storm limit */ 987 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true); 988 989 /* disable DiffServ priority */ 990 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_PRIO_ENABLE, false); 991 992 /* replace priority */ 993 ksz_port_cfg(dev, port, REG_PORT_MRI_MAC_CTRL, PORT_USER_PRIO_CEILING, 994 false); 995 ksz9477_port_cfg32(dev, port, REG_PORT_MTI_QUEUE_CTRL_0__4, 996 MTI_PVID_REPLACE, false); 997 998 /* enable 802.1p priority */ 999 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true); 1000 1001 if (port < dev->phy_port_cnt) { 1002 /* do not force flow control */ 1003 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, 1004 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, 1005 false); 1006 1007 } else { 1008 /* force flow control */ 1009 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, 1010 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, 1011 true); 1012 1013 /* configure MAC to 1G & RGMII mode */ 1014 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8); 1015 data8 &= ~PORT_MII_NOT_1GBIT; 1016 data8 &= ~PORT_MII_SEL_M; 1017 switch (dev->interface) { 1018 case PHY_INTERFACE_MODE_MII: 1019 data8 |= PORT_MII_NOT_1GBIT; 1020 data8 |= PORT_MII_SEL; 1021 p->phydev.speed = SPEED_100; 1022 break; 1023 case PHY_INTERFACE_MODE_RMII: 1024 data8 |= PORT_MII_NOT_1GBIT; 1025 data8 |= PORT_RMII_SEL; 1026 p->phydev.speed = SPEED_100; 1027 break; 1028 case PHY_INTERFACE_MODE_GMII: 1029 data8 |= PORT_GMII_SEL; 1030 p->phydev.speed = SPEED_1000; 1031 break; 1032 default: 1033 data8 &= ~PORT_RGMII_ID_IG_ENABLE; 1034 data8 &= ~PORT_RGMII_ID_EG_ENABLE; 1035 if (dev->interface == PHY_INTERFACE_MODE_RGMII_ID || 1036 dev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 1037 data8 |= PORT_RGMII_ID_IG_ENABLE; 1038 if (dev->interface == PHY_INTERFACE_MODE_RGMII_ID || 1039 dev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 1040 data8 |= PORT_RGMII_ID_EG_ENABLE; 1041 data8 |= PORT_RGMII_SEL; 1042 p->phydev.speed = SPEED_1000; 1043 break; 1044 } 1045 ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, data8); 1046 p->phydev.duplex = 1; 1047 } 1048 if (cpu_port) { 1049 member = dev->port_mask; 1050 dev->on_ports = dev->host_mask; 1051 dev->live_ports = dev->host_mask; 1052 } else { 1053 member = dev->host_mask | p->vid_member; 1054 dev->on_ports |= (1 << port); 1055 1056 /* Link was detected before port is enabled. */ 1057 if (p->phydev.link) 1058 dev->live_ports |= (1 << port); 1059 } 1060 ksz9477_cfg_port_member(dev, port, member); 1061 1062 /* clear pending interrupts */ 1063 if (port < dev->phy_port_cnt) 1064 ksz_pread16(dev, port, REG_PORT_PHY_INT_ENABLE, &data16); 1065 } 1066 1067 static void ksz9477_config_cpu_port(struct dsa_switch *ds) 1068 { 1069 struct ksz_device *dev = ds->priv; 1070 struct ksz_port *p; 1071 int i; 1072 1073 ds->num_ports = dev->port_cnt; 1074 1075 for (i = 0; i < dev->port_cnt; i++) { 1076 if (dsa_is_cpu_port(ds, i) && (dev->cpu_ports & (1 << i))) { 1077 dev->cpu_port = i; 1078 dev->host_mask = (1 << dev->cpu_port); 1079 dev->port_mask |= dev->host_mask; 1080 1081 /* enable cpu port */ 1082 ksz9477_port_setup(dev, i, true); 1083 p = &dev->ports[dev->cpu_port]; 1084 p->vid_member = dev->port_mask; 1085 p->on = 1; 1086 } 1087 } 1088 1089 dev->member = dev->host_mask; 1090 1091 for (i = 0; i < dev->mib_port_cnt; i++) { 1092 if (i == dev->cpu_port) 1093 continue; 1094 p = &dev->ports[i]; 1095 1096 /* Initialize to non-zero so that ksz_cfg_port_member() will 1097 * be called. 1098 */ 1099 p->vid_member = (1 << i); 1100 p->member = dev->port_mask; 1101 ksz9477_port_stp_state_set(ds, i, BR_STATE_DISABLED); 1102 p->on = 1; 1103 if (i < dev->phy_port_cnt) 1104 p->phy = 1; 1105 if (dev->chip_id == 0x00947700 && i == 6) { 1106 p->sgmii = 1; 1107 1108 /* SGMII PHY detection code is not implemented yet. */ 1109 p->phy = 0; 1110 } 1111 } 1112 } 1113 1114 static int ksz9477_setup(struct dsa_switch *ds) 1115 { 1116 struct ksz_device *dev = ds->priv; 1117 int ret = 0; 1118 1119 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 1120 dev->num_vlans, GFP_KERNEL); 1121 if (!dev->vlan_cache) 1122 return -ENOMEM; 1123 1124 ret = ksz9477_reset_switch(dev); 1125 if (ret) { 1126 dev_err(ds->dev, "failed to reset switch\n"); 1127 return ret; 1128 } 1129 1130 /* Required for port partitioning. */ 1131 ksz9477_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY, 1132 true); 1133 1134 /* accept packet up to 2000bytes */ 1135 ksz_cfg(dev, REG_SW_MAC_CTRL_1, SW_LEGAL_PACKET_DISABLE, true); 1136 1137 ksz9477_config_cpu_port(ds); 1138 1139 ksz_cfg(dev, REG_SW_MAC_CTRL_1, MULTICAST_STORM_DISABLE, true); 1140 1141 /* queue based egress rate limit */ 1142 ksz_cfg(dev, REG_SW_MAC_CTRL_5, SW_OUT_RATE_LIMIT_QUEUE_BASED, true); 1143 1144 /* start switch */ 1145 ksz_cfg(dev, REG_SW_OPERATION, SW_START, true); 1146 1147 return 0; 1148 } 1149 1150 static const struct dsa_switch_ops ksz9477_switch_ops = { 1151 .get_tag_protocol = ksz9477_get_tag_protocol, 1152 .setup = ksz9477_setup, 1153 .phy_read = ksz9477_phy_read16, 1154 .phy_write = ksz9477_phy_write16, 1155 .port_enable = ksz_enable_port, 1156 .port_disable = ksz_disable_port, 1157 .get_strings = ksz9477_get_strings, 1158 .get_ethtool_stats = ksz_get_ethtool_stats, 1159 .get_sset_count = ksz_sset_count, 1160 .port_bridge_join = ksz_port_bridge_join, 1161 .port_bridge_leave = ksz_port_bridge_leave, 1162 .port_stp_state_set = ksz9477_port_stp_state_set, 1163 .port_fast_age = ksz_port_fast_age, 1164 .port_vlan_filtering = ksz9477_port_vlan_filtering, 1165 .port_vlan_prepare = ksz_port_vlan_prepare, 1166 .port_vlan_add = ksz9477_port_vlan_add, 1167 .port_vlan_del = ksz9477_port_vlan_del, 1168 .port_fdb_dump = ksz9477_port_fdb_dump, 1169 .port_fdb_add = ksz9477_port_fdb_add, 1170 .port_fdb_del = ksz9477_port_fdb_del, 1171 .port_mdb_prepare = ksz_port_mdb_prepare, 1172 .port_mdb_add = ksz9477_port_mdb_add, 1173 .port_mdb_del = ksz9477_port_mdb_del, 1174 .port_mirror_add = ksz9477_port_mirror_add, 1175 .port_mirror_del = ksz9477_port_mirror_del, 1176 }; 1177 1178 static u32 ksz9477_get_port_addr(int port, int offset) 1179 { 1180 return PORT_CTRL_ADDR(port, offset); 1181 } 1182 1183 static int ksz9477_switch_detect(struct ksz_device *dev) 1184 { 1185 u8 data8; 1186 u32 id32; 1187 int ret; 1188 1189 /* turn off SPI DO Edge select */ 1190 ret = ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8); 1191 if (ret) 1192 return ret; 1193 1194 data8 &= ~SPI_AUTO_EDGE_DETECTION; 1195 ret = ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8); 1196 if (ret) 1197 return ret; 1198 1199 /* read chip id */ 1200 ret = ksz_read32(dev, REG_CHIP_ID0__1, &id32); 1201 if (ret) 1202 return ret; 1203 1204 /* Number of ports can be reduced depending on chip. */ 1205 dev->mib_port_cnt = TOTAL_PORT_NUM; 1206 dev->phy_port_cnt = 5; 1207 1208 dev->chip_id = id32; 1209 1210 return 0; 1211 } 1212 1213 struct ksz_chip_data { 1214 u32 chip_id; 1215 const char *dev_name; 1216 int num_vlans; 1217 int num_alus; 1218 int num_statics; 1219 int cpu_ports; 1220 int port_cnt; 1221 }; 1222 1223 static const struct ksz_chip_data ksz9477_switch_chips[] = { 1224 { 1225 .chip_id = 0x00947700, 1226 .dev_name = "KSZ9477", 1227 .num_vlans = 4096, 1228 .num_alus = 4096, 1229 .num_statics = 16, 1230 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1231 .port_cnt = 7, /* total physical port count */ 1232 }, 1233 { 1234 .chip_id = 0x00989700, 1235 .dev_name = "KSZ9897", 1236 .num_vlans = 4096, 1237 .num_alus = 4096, 1238 .num_statics = 16, 1239 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1240 .port_cnt = 7, /* total physical port count */ 1241 }, 1242 }; 1243 1244 static int ksz9477_switch_init(struct ksz_device *dev) 1245 { 1246 int i; 1247 1248 dev->ds->ops = &ksz9477_switch_ops; 1249 1250 for (i = 0; i < ARRAY_SIZE(ksz9477_switch_chips); i++) { 1251 const struct ksz_chip_data *chip = &ksz9477_switch_chips[i]; 1252 1253 if (dev->chip_id == chip->chip_id) { 1254 dev->name = chip->dev_name; 1255 dev->num_vlans = chip->num_vlans; 1256 dev->num_alus = chip->num_alus; 1257 dev->num_statics = chip->num_statics; 1258 dev->port_cnt = chip->port_cnt; 1259 dev->cpu_ports = chip->cpu_ports; 1260 1261 break; 1262 } 1263 } 1264 1265 /* no switch found */ 1266 if (!dev->port_cnt) 1267 return -ENODEV; 1268 1269 dev->port_mask = (1 << dev->port_cnt) - 1; 1270 1271 dev->reg_mib_cnt = SWITCH_COUNTER_NUM; 1272 dev->mib_cnt = TOTAL_SWITCH_COUNTER_NUM; 1273 1274 i = dev->mib_port_cnt; 1275 dev->ports = devm_kzalloc(dev->dev, sizeof(struct ksz_port) * i, 1276 GFP_KERNEL); 1277 if (!dev->ports) 1278 return -ENOMEM; 1279 for (i = 0; i < dev->mib_port_cnt; i++) { 1280 dev->ports[i].mib.counters = 1281 devm_kzalloc(dev->dev, 1282 sizeof(u64) * 1283 (TOTAL_SWITCH_COUNTER_NUM + 1), 1284 GFP_KERNEL); 1285 if (!dev->ports[i].mib.counters) 1286 return -ENOMEM; 1287 } 1288 dev->interface = PHY_INTERFACE_MODE_RGMII_TXID; 1289 1290 return 0; 1291 } 1292 1293 static void ksz9477_switch_exit(struct ksz_device *dev) 1294 { 1295 ksz9477_reset_switch(dev); 1296 } 1297 1298 static const struct ksz_dev_ops ksz9477_dev_ops = { 1299 .get_port_addr = ksz9477_get_port_addr, 1300 .cfg_port_member = ksz9477_cfg_port_member, 1301 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 1302 .port_setup = ksz9477_port_setup, 1303 .shutdown = ksz9477_reset_switch, 1304 .detect = ksz9477_switch_detect, 1305 .init = ksz9477_switch_init, 1306 .exit = ksz9477_switch_exit, 1307 }; 1308 1309 int ksz9477_switch_register(struct ksz_device *dev) 1310 { 1311 return ksz_switch_register(dev, &ksz9477_dev_ops); 1312 } 1313 EXPORT_SYMBOL(ksz9477_switch_register); 1314 1315 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 1316 MODULE_DESCRIPTION("Microchip KSZ9477 Series Switch DSA Driver"); 1317 MODULE_LICENSE("GPL"); 1318