1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip KSZ9477 switch driver main logic 4 * 5 * Copyright (C) 2017-2025 Microchip Technology Inc. 6 */ 7 8 #include <linux/dsa/ksz_common.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/iopoll.h> 12 #include <linux/platform_data/microchip-ksz.h> 13 #include <linux/phy.h> 14 #include <linux/if_bridge.h> 15 #include <linux/if_hsr.h> 16 #include <linux/if_vlan.h> 17 #include <net/dsa.h> 18 #include <net/ieee8021q.h> 19 #include <net/switchdev.h> 20 21 #include "ksz9477_reg.h" 22 #include "ksz_common.h" 23 #include "ksz_dcb.h" 24 #include "ksz9477.h" 25 26 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) 27 { 28 regmap_update_bits(ksz_regmap_8(dev), addr, bits, set ? bits : 0); 29 } 30 31 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits, 32 bool set) 33 { 34 regmap_update_bits(ksz_regmap_8(dev), PORT_CTRL_ADDR(port, offset), 35 bits, set ? bits : 0); 36 } 37 38 static void ksz9477_cfg32(struct ksz_device *dev, u32 addr, u32 bits, bool set) 39 { 40 regmap_update_bits(ksz_regmap_32(dev), addr, bits, set ? bits : 0); 41 } 42 43 static void ksz9477_port_cfg32(struct ksz_device *dev, int port, int offset, 44 u32 bits, bool set) 45 { 46 regmap_update_bits(ksz_regmap_32(dev), PORT_CTRL_ADDR(port, offset), 47 bits, set ? bits : 0); 48 } 49 50 static int ksz9477_change_mtu(struct dsa_switch *ds, int port, int mtu) 51 { 52 struct ksz_device *dev = ds->priv; 53 u16 frame_size; 54 55 if (!dsa_is_cpu_port(dev->ds, port)) 56 return 0; 57 58 frame_size = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 59 60 return regmap_update_bits(ksz_regmap_16(dev), REG_SW_MTU__2, 61 REG_SW_MTU_MASK, frame_size); 62 } 63 64 int ksz9477_max_mtu(struct dsa_switch *ds, int port) 65 { 66 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 67 } 68 69 static int ksz9477_wait_vlan_ctrl_ready(struct ksz_device *dev) 70 { 71 unsigned int val; 72 73 return regmap_read_poll_timeout(ksz_regmap_8(dev), REG_SW_VLAN_CTRL, 74 val, !(val & VLAN_START), 10, 1000); 75 } 76 77 static int ksz9477_get_vlan_table(struct ksz_device *dev, u16 vid, 78 u32 *vlan_table) 79 { 80 int ret; 81 82 mutex_lock(&dev->vlan_mutex); 83 84 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 85 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_READ | VLAN_START); 86 87 /* wait to be cleared */ 88 ret = ksz9477_wait_vlan_ctrl_ready(dev); 89 if (ret) { 90 dev_dbg(dev->dev, "Failed to read vlan table\n"); 91 goto exit; 92 } 93 94 ksz_read32(dev, REG_SW_VLAN_ENTRY__4, &vlan_table[0]); 95 ksz_read32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, &vlan_table[1]); 96 ksz_read32(dev, REG_SW_VLAN_ENTRY_PORTS__4, &vlan_table[2]); 97 98 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 99 100 exit: 101 mutex_unlock(&dev->vlan_mutex); 102 103 return ret; 104 } 105 106 static int ksz9477_set_vlan_table(struct ksz_device *dev, u16 vid, 107 u32 *vlan_table) 108 { 109 int ret; 110 111 mutex_lock(&dev->vlan_mutex); 112 113 ksz_write32(dev, REG_SW_VLAN_ENTRY__4, vlan_table[0]); 114 ksz_write32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, vlan_table[1]); 115 ksz_write32(dev, REG_SW_VLAN_ENTRY_PORTS__4, vlan_table[2]); 116 117 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 118 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_START | VLAN_WRITE); 119 120 /* wait to be cleared */ 121 ret = ksz9477_wait_vlan_ctrl_ready(dev); 122 if (ret) { 123 dev_dbg(dev->dev, "Failed to write vlan table\n"); 124 goto exit; 125 } 126 127 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 128 129 /* update vlan cache table */ 130 dev->vlan_cache[vid].table[0] = vlan_table[0]; 131 dev->vlan_cache[vid].table[1] = vlan_table[1]; 132 dev->vlan_cache[vid].table[2] = vlan_table[2]; 133 134 exit: 135 mutex_unlock(&dev->vlan_mutex); 136 137 return ret; 138 } 139 140 static void ksz9477_read_table(struct ksz_device *dev, u32 *table) 141 { 142 ksz_read32(dev, REG_SW_ALU_VAL_A, &table[0]); 143 ksz_read32(dev, REG_SW_ALU_VAL_B, &table[1]); 144 ksz_read32(dev, REG_SW_ALU_VAL_C, &table[2]); 145 ksz_read32(dev, REG_SW_ALU_VAL_D, &table[3]); 146 } 147 148 static void ksz9477_write_table(struct ksz_device *dev, u32 *table) 149 { 150 ksz_write32(dev, REG_SW_ALU_VAL_A, table[0]); 151 ksz_write32(dev, REG_SW_ALU_VAL_B, table[1]); 152 ksz_write32(dev, REG_SW_ALU_VAL_C, table[2]); 153 ksz_write32(dev, REG_SW_ALU_VAL_D, table[3]); 154 } 155 156 static int ksz9477_wait_alu_ready(struct ksz_device *dev) 157 { 158 unsigned int val; 159 160 return regmap_read_poll_timeout(ksz_regmap_32(dev), REG_SW_ALU_CTRL__4, 161 val, !(val & ALU_START), 10, 1000); 162 } 163 164 static int ksz9477_wait_alu_sta_ready(struct ksz_device *dev) 165 { 166 unsigned int val; 167 168 return regmap_read_poll_timeout(ksz_regmap_32(dev), 169 REG_SW_ALU_STAT_CTRL__4, 170 val, !(val & ALU_STAT_START), 171 10, 1000); 172 } 173 174 static void port_sgmii_s(struct ksz_device *dev, uint port, u16 devid, u16 reg) 175 { 176 u32 data; 177 178 data = (devid & MII_MMD_CTRL_DEVAD_MASK) << 16; 179 data |= reg; 180 ksz_pwrite32(dev, port, REG_PORT_SGMII_ADDR__4, data); 181 } 182 183 static void port_sgmii_r(struct ksz_device *dev, uint port, u16 devid, u16 reg, 184 u16 *buf) 185 { 186 port_sgmii_s(dev, port, devid, reg); 187 ksz_pread16(dev, port, REG_PORT_SGMII_DATA__4 + 2, buf); 188 } 189 190 static void port_sgmii_w(struct ksz_device *dev, uint port, u16 devid, u16 reg, 191 u16 buf) 192 { 193 port_sgmii_s(dev, port, devid, reg); 194 ksz_pwrite32(dev, port, REG_PORT_SGMII_DATA__4, buf); 195 } 196 197 static int ksz9477_pcs_read(struct mii_bus *bus, int phy, int mmd, int reg) 198 { 199 struct ksz_device *dev = bus->priv; 200 int port = ksz_get_sgmii_port(dev); 201 u16 val; 202 203 port_sgmii_r(dev, port, mmd, reg, &val); 204 205 /* Simulate a value to activate special code in the XPCS driver if 206 * supported. 207 */ 208 if (mmd == MDIO_MMD_PMAPMD) { 209 if (reg == MDIO_DEVID1) 210 val = 0x9477; 211 else if (reg == MDIO_DEVID2) 212 val = 0x22 << 10; 213 } else if (mmd == MDIO_MMD_VEND2) { 214 struct ksz_port *p = &dev->ports[port]; 215 216 /* Need to update MII_BMCR register with the exact speed and 217 * duplex mode when running in SGMII mode and this register is 218 * used to detect connected speed in that mode. 219 */ 220 if (reg == MMD_SR_MII_AUTO_NEG_STATUS) { 221 int duplex, speed; 222 223 if (val & SR_MII_STAT_LINK_UP) { 224 speed = (val >> SR_MII_STAT_S) & SR_MII_STAT_M; 225 if (speed == SR_MII_STAT_1000_MBPS) 226 speed = SPEED_1000; 227 else if (speed == SR_MII_STAT_100_MBPS) 228 speed = SPEED_100; 229 else 230 speed = SPEED_10; 231 232 if (val & SR_MII_STAT_FULL_DUPLEX) 233 duplex = DUPLEX_FULL; 234 else 235 duplex = DUPLEX_HALF; 236 237 if (!p->link || p->speed != speed || 238 p->duplex != duplex) { 239 u16 ctrl; 240 241 p->link = true; 242 p->speed = speed; 243 p->duplex = duplex; 244 port_sgmii_r(dev, port, mmd, MII_BMCR, 245 &ctrl); 246 ctrl &= BMCR_ANENABLE; 247 ctrl |= mii_bmcr_encode_fixed(speed, 248 duplex); 249 port_sgmii_w(dev, port, mmd, MII_BMCR, 250 ctrl); 251 } 252 } else { 253 p->link = false; 254 } 255 } else if (reg == MII_BMSR) { 256 p->link = !!(val & BMSR_LSTATUS); 257 } 258 } 259 260 return val; 261 } 262 263 static int ksz9477_pcs_write(struct mii_bus *bus, int phy, int mmd, int reg, 264 u16 val) 265 { 266 struct ksz_device *dev = bus->priv; 267 int port = ksz_get_sgmii_port(dev); 268 269 if (mmd == MDIO_MMD_VEND2) { 270 struct ksz_port *p = &dev->ports[port]; 271 272 if (reg == MMD_SR_MII_AUTO_NEG_CTRL) { 273 u16 sgmii_mode = SR_MII_PCS_SGMII << SR_MII_PCS_MODE_S; 274 275 /* Need these bits for 1000BASE-X mode to work with 276 * AN on. 277 */ 278 if (!(val & sgmii_mode)) 279 val |= SR_MII_SGMII_LINK_UP | 280 SR_MII_TX_CFG_PHY_MASTER; 281 282 /* SGMII interrupt in the port cannot be masked, so 283 * make sure interrupt is not enabled as it is not 284 * handled. 285 */ 286 val &= ~SR_MII_AUTO_NEG_COMPLETE_INTR; 287 } else if (reg == MII_BMCR) { 288 /* The MII_ADVERTISE register needs to write once 289 * before doing auto-negotiation for the correct 290 * config_word to be sent out after reset. 291 */ 292 if ((val & BMCR_ANENABLE) && !p->sgmii_adv_write) { 293 u16 adv; 294 295 /* The SGMII port cannot disable flow control 296 * so it is better to just advertise symmetric 297 * pause. 298 */ 299 port_sgmii_r(dev, port, mmd, MII_ADVERTISE, 300 &adv); 301 adv |= ADVERTISE_1000XPAUSE; 302 adv &= ~ADVERTISE_1000XPSE_ASYM; 303 port_sgmii_w(dev, port, mmd, MII_ADVERTISE, 304 adv); 305 p->sgmii_adv_write = 1; 306 } else if (val & BMCR_RESET) { 307 p->sgmii_adv_write = 0; 308 } 309 } else if (reg == MII_ADVERTISE) { 310 /* XPCS driver writes to this register so there is no 311 * need to update it for the errata. 312 */ 313 p->sgmii_adv_write = 1; 314 } 315 } 316 port_sgmii_w(dev, port, mmd, reg, val); 317 318 return 0; 319 } 320 321 static int ksz9477_pcs_create(struct ksz_device *dev) 322 { 323 int port = ksz_get_sgmii_port(dev); 324 struct ksz_port *p = &dev->ports[port]; 325 struct phylink_pcs *pcs; 326 struct mii_bus *bus; 327 int ret; 328 329 bus = devm_mdiobus_alloc(dev->dev); 330 if (!bus) 331 return -ENOMEM; 332 333 bus->name = "ksz_pcs_mdio_bus"; 334 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-pcs", 335 dev_name(dev->dev)); 336 bus->read_c45 = &ksz9477_pcs_read; 337 bus->write_c45 = &ksz9477_pcs_write; 338 bus->parent = dev->dev; 339 bus->phy_mask = ~0; 340 bus->priv = dev; 341 342 ret = devm_mdiobus_register(dev->dev, bus); 343 if (ret) 344 return ret; 345 346 pcs = xpcs_create_pcs_mdiodev(bus, 0); 347 if (IS_ERR(pcs)) 348 return PTR_ERR(pcs); 349 p->pcs = pcs; 350 351 return 0; 352 } 353 354 static int ksz9477_reset_switch(struct ksz_device *dev) 355 { 356 u8 data8; 357 u32 data32; 358 359 /* reset switch */ 360 ksz_cfg(dev, REG_SW_OPERATION, SW_RESET, true); 361 362 /* turn off SPI DO Edge select */ 363 regmap_update_bits(ksz_regmap_8(dev), REG_SW_GLOBAL_SERIAL_CTRL_0, 364 SPI_AUTO_EDGE_DETECTION, 0); 365 366 /* default configuration */ 367 ksz_write8(dev, REG_SW_LUE_CTRL_1, 368 SW_AGING_ENABLE | SW_LINK_AUTO_AGING | SW_SRC_ADDR_FILTER); 369 370 /* disable interrupts */ 371 ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK); 372 ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0x7F); 373 ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32); 374 375 /* KSZ9893 compatible chips do not support refclk configuration */ 376 if (dev->chip_id == KSZ9893_CHIP_ID || 377 dev->chip_id == KSZ8563_CHIP_ID || 378 dev->chip_id == KSZ9563_CHIP_ID) 379 return 0; 380 381 data8 = SW_ENABLE_REFCLKO; 382 if (dev->synclko_disable) 383 data8 = 0; 384 else if (dev->synclko_125) 385 data8 = SW_ENABLE_REFCLKO | SW_REFCLKO_IS_125MHZ; 386 ksz_write8(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1, data8); 387 388 return 0; 389 } 390 391 void ksz9477_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, u64 *cnt) 392 { 393 struct ksz_port *p = &dev->ports[port]; 394 unsigned int val; 395 u32 data; 396 int ret; 397 398 /* retain the flush/freeze bit */ 399 data = p->freeze ? MIB_COUNTER_FLUSH_FREEZE : 0; 400 data |= MIB_COUNTER_READ; 401 data |= (addr << MIB_COUNTER_INDEX_S); 402 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, data); 403 404 ret = regmap_read_poll_timeout(ksz_regmap_32(dev), 405 PORT_CTRL_ADDR(port, REG_PORT_MIB_CTRL_STAT__4), 406 val, !(val & MIB_COUNTER_READ), 10, 1000); 407 /* failed to read MIB. get out of loop */ 408 if (ret) { 409 dev_dbg(dev->dev, "Failed to get MIB\n"); 410 return; 411 } 412 413 /* count resets upon read */ 414 ksz_pread32(dev, port, REG_PORT_MIB_DATA, &data); 415 *cnt += data; 416 } 417 418 void ksz9477_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 419 u64 *dropped, u64 *cnt) 420 { 421 addr = dev->info->mib_names[addr].index; 422 ksz9477_r_mib_cnt(dev, port, addr, cnt); 423 } 424 425 void ksz9477_freeze_mib(struct ksz_device *dev, int port, bool freeze) 426 { 427 u32 val = freeze ? MIB_COUNTER_FLUSH_FREEZE : 0; 428 struct ksz_port *p = &dev->ports[port]; 429 430 /* enable/disable the port for flush/freeze function */ 431 mutex_lock(&p->mib.cnt_mutex); 432 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, val); 433 434 /* used by MIB counter reading code to know freeze is enabled */ 435 p->freeze = freeze; 436 mutex_unlock(&p->mib.cnt_mutex); 437 } 438 439 static int ksz9477_half_duplex_monitor(struct ksz_device *dev, int port, 440 u64 tx_late_col) 441 { 442 u8 lue_ctrl; 443 u32 pmavbc; 444 u16 pqm; 445 int ret; 446 447 /* Errata DS80000754 recommends monitoring potential faults in 448 * half-duplex mode. The switch might not be able to communicate anymore 449 * in these states. If you see this message, please read the 450 * errata-sheet for more information: 451 * https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/Errata/KSZ9477S-Errata-DS80000754.pdf 452 * To workaround this issue, half-duplex mode should be avoided. 453 * A software reset could be implemented to recover from this state. 454 */ 455 dev_warn_once(dev->dev, 456 "Half-duplex detected on port %d, transmission halt may occur\n", 457 port); 458 if (tx_late_col != 0) { 459 /* Transmission halt with late collisions */ 460 dev_crit_once(dev->dev, 461 "TX late collisions detected, transmission may be halted on port %d\n", 462 port); 463 } 464 ret = ksz_read8(dev, REG_SW_LUE_CTRL_0, &lue_ctrl); 465 if (ret) 466 return ret; 467 if (lue_ctrl & SW_VLAN_ENABLE) { 468 ret = ksz_pread16(dev, port, REG_PORT_QM_TX_CNT_0__4, &pqm); 469 if (ret) 470 return ret; 471 472 ret = ksz_read32(dev, REG_PMAVBC, &pmavbc); 473 if (ret) 474 return ret; 475 476 if ((FIELD_GET(PMAVBC_MASK, pmavbc) <= PMAVBC_MIN) || 477 (FIELD_GET(PORT_QM_TX_CNT_M, pqm) >= PORT_QM_TX_CNT_MAX)) { 478 /* Transmission halt with Half-Duplex and VLAN */ 479 dev_crit_once(dev->dev, 480 "resources out of limits, transmission may be halted\n"); 481 } 482 } 483 484 return ret; 485 } 486 487 static int ksz9477_errata_monitor(struct ksz_device *dev, int port, 488 u64 tx_late_col) 489 { 490 u8 status; 491 int ret; 492 493 ret = ksz_pread8(dev, port, REG_PORT_STATUS_0, &status); 494 if (ret) 495 return ret; 496 497 if (!(FIELD_GET(PORT_INTF_SPEED_MASK, status) 498 == PORT_INTF_SPEED_NONE) && 499 !(status & PORT_INTF_FULL_DUPLEX)) { 500 ret = ksz9477_half_duplex_monitor(dev, port, tx_late_col); 501 } 502 503 return ret; 504 } 505 506 static void ksz9477_r_mib_stats64(struct ksz_device *dev, int port) 507 { 508 struct ksz_stats_raw *raw; 509 struct ksz_port_mib *mib; 510 int ret; 511 512 ksz_r_mib_stats64(dev, port); 513 514 if (dev->info->phy_errata_9477 && !ksz_is_sgmii_port(dev, port)) { 515 mib = &dev->ports[port].mib; 516 raw = (struct ksz_stats_raw *)mib->counters; 517 518 ret = ksz9477_errata_monitor(dev, port, raw->tx_late_col); 519 if (ret) 520 dev_err(dev->dev, "Failed to monitor transmission halt\n"); 521 } 522 }; 523 524 void ksz9477_port_init_cnt(struct ksz_device *dev, int port) 525 { 526 struct ksz_port_mib *mib = &dev->ports[port].mib; 527 528 /* flush all enabled port MIB counters */ 529 mutex_lock(&mib->cnt_mutex); 530 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 531 MIB_COUNTER_FLUSH_FREEZE); 532 ksz_write8(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FLUSH); 533 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 0); 534 mutex_unlock(&mib->cnt_mutex); 535 } 536 537 static void ksz9477_r_phy_quirks(struct ksz_device *dev, u16 addr, u16 reg, 538 u16 *data) 539 { 540 /* KSZ8563R do not have extended registers but BMSR_ESTATEN and 541 * BMSR_ERCAP bits are set. 542 */ 543 if (dev->chip_id == KSZ8563_CHIP_ID && reg == MII_BMSR) 544 *data &= ~(BMSR_ESTATEN | BMSR_ERCAP); 545 } 546 547 static int ksz9477_r_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 *data) 548 { 549 u16 val = 0xffff; 550 int ret; 551 552 /* No real PHY after this. Simulate the PHY. 553 * A fixed PHY can be setup in the device tree, but this function is 554 * still called for that port during initialization. 555 * For RGMII PHY there is no way to access it so the fixed PHY should 556 * be used. 557 */ 558 if (!dev->info->internal_phy[addr]) { 559 struct ksz_port *p = &dev->ports[addr]; 560 561 switch (reg) { 562 case MII_BMCR: 563 val = 0x1140; 564 break; 565 case MII_BMSR: 566 val = 0x796d; 567 break; 568 case MII_PHYSID1: 569 val = 0x0022; 570 break; 571 case MII_PHYSID2: 572 val = 0x1631; 573 break; 574 case MII_ADVERTISE: 575 val = 0x05e1; 576 break; 577 case MII_LPA: 578 val = 0xc5e1; 579 break; 580 case MII_CTRL1000: 581 val = 0x0700; 582 break; 583 case MII_STAT1000: 584 if (p->speed == SPEED_1000) 585 val = 0x3800; 586 else 587 val = 0; 588 break; 589 } 590 } else { 591 ret = ksz_pread16(dev, addr, 0x100 + (reg << 1), &val); 592 if (ret) 593 return ret; 594 595 ksz9477_r_phy_quirks(dev, addr, reg, &val); 596 } 597 598 *data = val; 599 600 return 0; 601 } 602 603 static int ksz9477_phy_read16(struct dsa_switch *ds, int addr, int reg) 604 { 605 struct ksz_device *dev = ds->priv; 606 u16 val = 0xffff; 607 int ret; 608 609 ret = ksz9477_r_phy(dev, addr, reg, &val); 610 if (ret) 611 return ret; 612 613 return val; 614 } 615 616 static int ksz9477_w_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 val) 617 { 618 u32 mask, val32; 619 620 /* No real PHY after this. */ 621 if (!dev->info->internal_phy[addr]) 622 return 0; 623 624 if (reg < 0x10) 625 return ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val); 626 627 /* Errata: When using SPI, I2C, or in-band register access, 628 * writes to certain PHY registers should be performed as 629 * 32-bit writes instead of 16-bit writes. 630 */ 631 val32 = val; 632 mask = 0xffff; 633 if ((reg & 1) == 0) { 634 val32 <<= 16; 635 mask <<= 16; 636 } 637 reg &= ~1; 638 return ksz_prmw32(dev, addr, 0x100 + (reg << 1), mask, val32); 639 } 640 641 static int ksz9477_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 642 { 643 struct ksz_device *dev = ds->priv; 644 int ret; 645 646 ret = ksz9477_w_phy(dev, addr, reg, val); 647 if (ret) 648 return ret; 649 650 return 0; 651 } 652 653 void ksz9477_cfg_port_member(struct ksz_device *dev, int port, u8 member) 654 { 655 ksz_pwrite32(dev, port, REG_PORT_VLAN_MEMBERSHIP__4, member); 656 } 657 658 void ksz9477_flush_dyn_mac_table(struct dsa_switch *ds, int port) 659 { 660 struct ksz_device *dev = ds->priv; 661 const u16 *regs = dev->info->regs; 662 u8 data; 663 664 regmap_update_bits(ksz_regmap_8(dev), REG_SW_LUE_CTRL_2, 665 SW_FLUSH_OPTION_M << SW_FLUSH_OPTION_S, 666 SW_FLUSH_OPTION_DYN_MAC << SW_FLUSH_OPTION_S); 667 668 if (port < dev->info->port_cnt) { 669 /* flush individual port */ 670 ksz_pread8(dev, port, regs[P_STP_CTRL], &data); 671 if (!(data & PORT_LEARN_DISABLE)) 672 ksz_pwrite8(dev, port, regs[P_STP_CTRL], 673 data | PORT_LEARN_DISABLE); 674 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true); 675 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data); 676 } else { 677 /* flush all */ 678 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_STP_TABLE, true); 679 } 680 } 681 682 int ksz9477_port_vlan_filtering(struct dsa_switch *ds, int port, 683 bool flag, struct netlink_ext_ack *extack) 684 { 685 struct ksz_device *dev = ds->priv; 686 687 if (flag) { 688 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 689 PORT_VLAN_LOOKUP_VID_0, true); 690 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, true); 691 } else { 692 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, false); 693 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 694 PORT_VLAN_LOOKUP_VID_0, false); 695 } 696 697 return 0; 698 } 699 700 int ksz9477_port_vlan_add(struct dsa_switch *ds, int port, 701 const struct switchdev_obj_port_vlan *vlan, 702 struct netlink_ext_ack *extack) 703 { 704 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 705 struct ksz_device *dev = ds->priv; 706 u32 vlan_table[3]; 707 int err; 708 709 err = ksz9477_get_vlan_table(dev, vlan->vid, vlan_table); 710 if (err) { 711 NL_SET_ERR_MSG_MOD(extack, "Failed to get vlan table"); 712 return err; 713 } 714 715 vlan_table[0] = VLAN_VALID | (vlan->vid & VLAN_FID_M); 716 if (untagged) 717 vlan_table[1] |= BIT(port); 718 else 719 vlan_table[1] &= ~BIT(port); 720 vlan_table[1] &= ~(BIT(dev->cpu_port)); 721 722 vlan_table[2] |= BIT(port) | BIT(dev->cpu_port); 723 724 err = ksz9477_set_vlan_table(dev, vlan->vid, vlan_table); 725 if (err) { 726 NL_SET_ERR_MSG_MOD(extack, "Failed to set vlan table"); 727 return err; 728 } 729 730 /* change PVID */ 731 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) 732 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, vlan->vid); 733 734 return 0; 735 } 736 737 int ksz9477_port_vlan_del(struct dsa_switch *ds, int port, 738 const struct switchdev_obj_port_vlan *vlan) 739 { 740 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 741 struct ksz_device *dev = ds->priv; 742 u32 vlan_table[3]; 743 u16 pvid; 744 745 ksz_pread16(dev, port, REG_PORT_DEFAULT_VID, &pvid); 746 pvid = pvid & 0xFFF; 747 748 if (ksz9477_get_vlan_table(dev, vlan->vid, vlan_table)) { 749 dev_dbg(dev->dev, "Failed to get vlan table\n"); 750 return -ETIMEDOUT; 751 } 752 753 vlan_table[2] &= ~BIT(port); 754 755 if (pvid == vlan->vid) 756 pvid = 1; 757 758 if (untagged) 759 vlan_table[1] &= ~BIT(port); 760 761 if (ksz9477_set_vlan_table(dev, vlan->vid, vlan_table)) { 762 dev_dbg(dev->dev, "Failed to set vlan table\n"); 763 return -ETIMEDOUT; 764 } 765 766 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, pvid); 767 768 return 0; 769 } 770 771 int ksz9477_fdb_add(struct dsa_switch *ds, int port, 772 const unsigned char *addr, u16 vid, struct dsa_db db) 773 { 774 struct ksz_device *dev = ds->priv; 775 u32 alu_table[4]; 776 u32 data; 777 int ret = 0; 778 779 mutex_lock(&dev->alu_mutex); 780 781 /* find any entry with mac & vid */ 782 data = vid << ALU_FID_INDEX_S; 783 data |= ((addr[0] << 8) | addr[1]); 784 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 785 786 data = ((addr[2] << 24) | (addr[3] << 16)); 787 data |= ((addr[4] << 8) | addr[5]); 788 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 789 790 /* start read operation */ 791 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 792 793 /* wait to be finished */ 794 ret = ksz9477_wait_alu_ready(dev); 795 if (ret) { 796 dev_dbg(dev->dev, "Failed to read ALU\n"); 797 goto exit; 798 } 799 800 /* read ALU entry */ 801 ksz9477_read_table(dev, alu_table); 802 803 /* update ALU entry */ 804 alu_table[0] = ALU_V_STATIC_VALID; 805 alu_table[1] |= BIT(port); 806 if (vid) 807 alu_table[1] |= ALU_V_USE_FID; 808 alu_table[2] = (vid << ALU_V_FID_S); 809 alu_table[2] |= ((addr[0] << 8) | addr[1]); 810 alu_table[3] = ((addr[2] << 24) | (addr[3] << 16)); 811 alu_table[3] |= ((addr[4] << 8) | addr[5]); 812 813 ksz9477_write_table(dev, alu_table); 814 815 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 816 817 /* wait to be finished */ 818 ret = ksz9477_wait_alu_ready(dev); 819 if (ret) 820 dev_dbg(dev->dev, "Failed to write ALU\n"); 821 822 exit: 823 mutex_unlock(&dev->alu_mutex); 824 825 return ret; 826 } 827 828 int ksz9477_fdb_del(struct dsa_switch *ds, int port, 829 const unsigned char *addr, u16 vid, struct dsa_db db) 830 { 831 struct ksz_device *dev = ds->priv; 832 u32 alu_table[4]; 833 u32 data; 834 int ret = 0; 835 836 mutex_lock(&dev->alu_mutex); 837 838 /* read any entry with mac & vid */ 839 data = vid << ALU_FID_INDEX_S; 840 data |= ((addr[0] << 8) | addr[1]); 841 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 842 843 data = ((addr[2] << 24) | (addr[3] << 16)); 844 data |= ((addr[4] << 8) | addr[5]); 845 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 846 847 /* start read operation */ 848 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 849 850 /* wait to be finished */ 851 ret = ksz9477_wait_alu_ready(dev); 852 if (ret) { 853 dev_dbg(dev->dev, "Failed to read ALU\n"); 854 goto exit; 855 } 856 857 ksz_read32(dev, REG_SW_ALU_VAL_A, &alu_table[0]); 858 if (alu_table[0] & ALU_V_STATIC_VALID) { 859 ksz_read32(dev, REG_SW_ALU_VAL_B, &alu_table[1]); 860 ksz_read32(dev, REG_SW_ALU_VAL_C, &alu_table[2]); 861 ksz_read32(dev, REG_SW_ALU_VAL_D, &alu_table[3]); 862 863 /* clear forwarding port */ 864 alu_table[1] &= ~BIT(port); 865 866 /* if there is no port to forward, clear table */ 867 if ((alu_table[1] & ALU_V_PORT_MAP) == 0) { 868 alu_table[0] = 0; 869 alu_table[1] = 0; 870 alu_table[2] = 0; 871 alu_table[3] = 0; 872 } 873 } else { 874 alu_table[0] = 0; 875 alu_table[1] = 0; 876 alu_table[2] = 0; 877 alu_table[3] = 0; 878 } 879 880 ksz9477_write_table(dev, alu_table); 881 882 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 883 884 /* wait to be finished */ 885 ret = ksz9477_wait_alu_ready(dev); 886 if (ret) 887 dev_dbg(dev->dev, "Failed to write ALU\n"); 888 889 exit: 890 mutex_unlock(&dev->alu_mutex); 891 892 return ret; 893 } 894 895 static void ksz9477_convert_alu(struct alu_struct *alu, u32 *alu_table) 896 { 897 alu->is_static = !!(alu_table[0] & ALU_V_STATIC_VALID); 898 alu->is_src_filter = !!(alu_table[0] & ALU_V_SRC_FILTER); 899 alu->is_dst_filter = !!(alu_table[0] & ALU_V_DST_FILTER); 900 alu->prio_age = (alu_table[0] >> ALU_V_PRIO_AGE_CNT_S) & 901 ALU_V_PRIO_AGE_CNT_M; 902 alu->mstp = alu_table[0] & ALU_V_MSTP_M; 903 904 alu->is_override = !!(alu_table[1] & ALU_V_OVERRIDE); 905 alu->is_use_fid = !!(alu_table[1] & ALU_V_USE_FID); 906 alu->port_forward = alu_table[1] & ALU_V_PORT_MAP; 907 908 alu->fid = (alu_table[2] >> ALU_V_FID_S) & ALU_V_FID_M; 909 910 alu->mac[0] = (alu_table[2] >> 8) & 0xFF; 911 alu->mac[1] = alu_table[2] & 0xFF; 912 alu->mac[2] = (alu_table[3] >> 24) & 0xFF; 913 alu->mac[3] = (alu_table[3] >> 16) & 0xFF; 914 alu->mac[4] = (alu_table[3] >> 8) & 0xFF; 915 alu->mac[5] = alu_table[3] & 0xFF; 916 } 917 918 int ksz9477_fdb_dump(struct dsa_switch *ds, int port, 919 dsa_fdb_dump_cb_t *cb, void *data) 920 { 921 struct ksz_device *dev = ds->priv; 922 struct alu_struct alu; 923 u32 alu_table[4]; 924 u32 ksz_data; 925 int ret = 0; 926 int timeout; 927 928 mutex_lock(&dev->alu_mutex); 929 930 /* start ALU search */ 931 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_START | ALU_SEARCH); 932 933 do { 934 timeout = 1000; 935 do { 936 ksz_read32(dev, REG_SW_ALU_CTRL__4, &ksz_data); 937 if ((ksz_data & ALU_VALID) || !(ksz_data & ALU_START)) 938 break; 939 usleep_range(1, 10); 940 } while (timeout-- > 0); 941 942 if (!timeout) { 943 dev_dbg(dev->dev, "Failed to search ALU\n"); 944 ret = -ETIMEDOUT; 945 goto exit; 946 } 947 948 if (!(ksz_data & ALU_VALID)) 949 continue; 950 951 /* read ALU table */ 952 ksz9477_read_table(dev, alu_table); 953 954 ksz9477_convert_alu(&alu, alu_table); 955 956 if (alu.port_forward & BIT(port)) { 957 ret = cb(alu.mac, alu.fid, alu.is_static, data); 958 if (ret) 959 goto exit; 960 } 961 } while (ksz_data & ALU_START); 962 963 exit: 964 965 /* stop ALU search */ 966 ksz_write32(dev, REG_SW_ALU_CTRL__4, 0); 967 968 mutex_unlock(&dev->alu_mutex); 969 970 return ret; 971 } 972 973 int ksz9477_mdb_add(struct dsa_switch *ds, int port, 974 const struct switchdev_obj_port_mdb *mdb, struct dsa_db db) 975 { 976 struct ksz_device *dev = ds->priv; 977 u32 static_table[4]; 978 const u8 *shifts; 979 const u32 *masks; 980 u32 data; 981 int index; 982 u32 mac_hi, mac_lo; 983 int err = 0; 984 985 shifts = dev->info->shifts; 986 masks = dev->info->masks; 987 988 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 989 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 990 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 991 992 mutex_lock(&dev->alu_mutex); 993 994 for (index = 0; index < dev->info->num_statics; index++) { 995 /* find empty slot first */ 996 data = (index << shifts[ALU_STAT_INDEX]) | 997 masks[ALU_STAT_READ] | ALU_STAT_START; 998 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 999 1000 /* wait to be finished */ 1001 err = ksz9477_wait_alu_sta_ready(dev); 1002 if (err) { 1003 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 1004 goto exit; 1005 } 1006 1007 /* read ALU static table */ 1008 ksz9477_read_table(dev, static_table); 1009 1010 if (static_table[0] & ALU_V_STATIC_VALID) { 1011 /* check this has same vid & mac address */ 1012 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 1013 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 1014 static_table[3] == mac_lo) { 1015 /* found matching one */ 1016 break; 1017 } 1018 } else { 1019 /* found empty one */ 1020 break; 1021 } 1022 } 1023 1024 /* no available entry */ 1025 if (index == dev->info->num_statics) { 1026 err = -ENOSPC; 1027 goto exit; 1028 } 1029 1030 /* add entry */ 1031 static_table[0] = ALU_V_STATIC_VALID; 1032 static_table[1] |= BIT(port); 1033 if (mdb->vid) 1034 static_table[1] |= ALU_V_USE_FID; 1035 static_table[2] = (mdb->vid << ALU_V_FID_S); 1036 static_table[2] |= mac_hi; 1037 static_table[3] = mac_lo; 1038 1039 ksz9477_write_table(dev, static_table); 1040 1041 data = (index << shifts[ALU_STAT_INDEX]) | ALU_STAT_START; 1042 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 1043 1044 /* wait to be finished */ 1045 if (ksz9477_wait_alu_sta_ready(dev)) 1046 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 1047 1048 exit: 1049 mutex_unlock(&dev->alu_mutex); 1050 return err; 1051 } 1052 1053 int ksz9477_mdb_del(struct dsa_switch *ds, int port, 1054 const struct switchdev_obj_port_mdb *mdb, struct dsa_db db) 1055 { 1056 struct ksz_device *dev = ds->priv; 1057 u32 static_table[4]; 1058 u32 mac_hi, mac_lo; 1059 const u8 *shifts; 1060 const u32 *masks; 1061 int ret = 0; 1062 int index; 1063 u32 data; 1064 1065 shifts = dev->info->shifts; 1066 masks = dev->info->masks; 1067 1068 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 1069 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 1070 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 1071 1072 mutex_lock(&dev->alu_mutex); 1073 1074 for (index = 0; index < dev->info->num_statics; index++) { 1075 /* find empty slot first */ 1076 data = (index << shifts[ALU_STAT_INDEX]) | 1077 masks[ALU_STAT_READ] | ALU_STAT_START; 1078 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 1079 1080 /* wait to be finished */ 1081 ret = ksz9477_wait_alu_sta_ready(dev); 1082 if (ret) { 1083 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 1084 goto exit; 1085 } 1086 1087 /* read ALU static table */ 1088 ksz9477_read_table(dev, static_table); 1089 1090 if (static_table[0] & ALU_V_STATIC_VALID) { 1091 /* check this has same vid & mac address */ 1092 1093 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 1094 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 1095 static_table[3] == mac_lo) { 1096 /* found matching one */ 1097 break; 1098 } 1099 } 1100 } 1101 1102 /* no available entry */ 1103 if (index == dev->info->num_statics) 1104 goto exit; 1105 1106 /* clear port */ 1107 static_table[1] &= ~BIT(port); 1108 1109 if ((static_table[1] & ALU_V_PORT_MAP) == 0) { 1110 /* delete entry */ 1111 static_table[0] = 0; 1112 static_table[1] = 0; 1113 static_table[2] = 0; 1114 static_table[3] = 0; 1115 } 1116 1117 ksz9477_write_table(dev, static_table); 1118 1119 data = (index << shifts[ALU_STAT_INDEX]) | ALU_STAT_START; 1120 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 1121 1122 /* wait to be finished */ 1123 ret = ksz9477_wait_alu_sta_ready(dev); 1124 if (ret) 1125 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 1126 1127 exit: 1128 mutex_unlock(&dev->alu_mutex); 1129 1130 return ret; 1131 } 1132 1133 int ksz9477_port_mirror_add(struct dsa_switch *ds, int port, 1134 struct dsa_mall_mirror_tc_entry *mirror, 1135 bool ingress, struct netlink_ext_ack *extack) 1136 { 1137 struct ksz_device *dev = ds->priv; 1138 u8 data; 1139 int p; 1140 1141 /* Limit to one sniffer port 1142 * Check if any of the port is already set for sniffing 1143 * If yes, instruct the user to remove the previous entry & exit 1144 */ 1145 for (p = 0; p < dev->info->port_cnt; p++) { 1146 /* Skip the current sniffing port */ 1147 if (p == mirror->to_local_port) 1148 continue; 1149 1150 ksz_pread8(dev, p, P_MIRROR_CTRL, &data); 1151 1152 if (data & PORT_MIRROR_SNIFFER) { 1153 NL_SET_ERR_MSG_MOD(extack, 1154 "Sniffer port is already configured, delete existing rules & retry"); 1155 return -EBUSY; 1156 } 1157 } 1158 1159 if (ingress) 1160 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true); 1161 else 1162 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true); 1163 1164 /* configure mirror port */ 1165 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 1166 PORT_MIRROR_SNIFFER, true); 1167 1168 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false); 1169 1170 return 0; 1171 } 1172 1173 void ksz9477_port_mirror_del(struct dsa_switch *ds, int port, 1174 struct dsa_mall_mirror_tc_entry *mirror) 1175 { 1176 struct ksz_device *dev = ds->priv; 1177 bool in_use = false; 1178 u8 data; 1179 int p; 1180 1181 if (mirror->ingress) 1182 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false); 1183 else 1184 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false); 1185 1186 1187 /* Check if any of the port is still referring to sniffer port */ 1188 for (p = 0; p < dev->info->port_cnt; p++) { 1189 ksz_pread8(dev, p, P_MIRROR_CTRL, &data); 1190 1191 if ((data & (PORT_MIRROR_RX | PORT_MIRROR_TX))) { 1192 in_use = true; 1193 break; 1194 } 1195 } 1196 1197 /* delete sniffing if there are no other mirroring rules */ 1198 if (!in_use) 1199 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 1200 PORT_MIRROR_SNIFFER, false); 1201 } 1202 1203 static bool ksz9477_get_gbit(struct ksz_device *dev, int port) 1204 { 1205 const u8 *bitval = dev->info->xmii_ctrl1; 1206 const u16 *regs = dev->info->regs; 1207 bool gbit = false; 1208 u8 data8; 1209 bool val; 1210 1211 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 1212 1213 val = FIELD_GET(P_GMII_1GBIT_M, data8); 1214 1215 if (val == bitval[P_GMII_1GBIT]) 1216 gbit = true; 1217 1218 return gbit; 1219 } 1220 1221 static phy_interface_t ksz9477_get_xmii(struct ksz_device *dev, int port, 1222 bool gbit) 1223 { 1224 const u8 *bitval = dev->info->xmii_ctrl1; 1225 const u16 *regs = dev->info->regs; 1226 phy_interface_t interface; 1227 u8 data8; 1228 u8 val; 1229 1230 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 1231 1232 val = FIELD_GET(P_MII_SEL_M, data8); 1233 1234 if (val == bitval[P_MII_SEL]) { 1235 if (gbit) 1236 interface = PHY_INTERFACE_MODE_GMII; 1237 else 1238 interface = PHY_INTERFACE_MODE_MII; 1239 } else if (val == bitval[P_RMII_SEL]) { 1240 interface = PHY_INTERFACE_MODE_RMII; 1241 } else { 1242 interface = PHY_INTERFACE_MODE_RGMII; 1243 if (data8 & P_RGMII_ID_EG_ENABLE) 1244 interface = PHY_INTERFACE_MODE_RGMII_TXID; 1245 if (data8 & P_RGMII_ID_IG_ENABLE) { 1246 interface = PHY_INTERFACE_MODE_RGMII_RXID; 1247 if (data8 & P_RGMII_ID_EG_ENABLE) 1248 interface = PHY_INTERFACE_MODE_RGMII_ID; 1249 } 1250 } 1251 1252 return interface; 1253 } 1254 1255 static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port) 1256 { 1257 phy_interface_t interface; 1258 bool gbit; 1259 1260 if (dev->info->internal_phy[port]) 1261 return PHY_INTERFACE_MODE_NA; 1262 1263 gbit = ksz9477_get_gbit(dev, port); 1264 1265 interface = ksz9477_get_xmii(dev, port, gbit); 1266 1267 return interface; 1268 } 1269 1270 static void ksz9477_phylink_get_caps(struct dsa_switch *ds, int port, 1271 struct phylink_config *config) 1272 { 1273 struct ksz_device *dev = ds->priv; 1274 1275 config->mac_capabilities = MAC_10 | MAC_100 | MAC_ASYM_PAUSE | 1276 MAC_SYM_PAUSE; 1277 1278 if (dev->info->gbit_capable[port]) 1279 config->mac_capabilities |= MAC_1000FD; 1280 1281 if (ksz_is_sgmii_port(dev, port)) { 1282 struct ksz_port *p = &dev->ports[port]; 1283 1284 phy_interface_or(config->supported_interfaces, 1285 config->supported_interfaces, 1286 p->pcs->supported_interfaces); 1287 } 1288 1289 ksz_phylink_get_caps(ds, port, config); 1290 } 1291 1292 static int ksz9477_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 1293 { 1294 struct ksz_device *dev = ds->priv; 1295 u32 secs = msecs / 1000; 1296 u8 data, mult, value; 1297 u32 max_val; 1298 int ret; 1299 1300 #define MAX_TIMER_VAL ((1 << 8) - 1) 1301 1302 /* The aging timer comprises a 3-bit multiplier and an 8-bit second 1303 * value. Either of them cannot be zero. The maximum timer is then 1304 * 7 * 255 = 1785 seconds. 1305 */ 1306 if (!secs) 1307 secs = 1; 1308 1309 /* Return error if too large. */ 1310 else if (secs > 7 * MAX_TIMER_VAL) 1311 return -EINVAL; 1312 1313 ret = ksz_read8(dev, REG_SW_LUE_CTRL_0, &value); 1314 if (ret < 0) 1315 return ret; 1316 1317 /* Check whether there is need to update the multiplier. */ 1318 mult = FIELD_GET(SW_AGE_CNT_M, value); 1319 max_val = MAX_TIMER_VAL; 1320 if (mult > 0) { 1321 /* Try to use the same multiplier already in the register as 1322 * the hardware default uses multiplier 4 and 75 seconds for 1323 * 300 seconds. 1324 */ 1325 max_val = DIV_ROUND_UP(secs, mult); 1326 if (max_val > MAX_TIMER_VAL || max_val * mult != secs) 1327 max_val = MAX_TIMER_VAL; 1328 } 1329 1330 data = DIV_ROUND_UP(secs, max_val); 1331 if (mult != data) { 1332 value &= ~SW_AGE_CNT_M; 1333 value |= FIELD_PREP(SW_AGE_CNT_M, data); 1334 ret = ksz_write8(dev, REG_SW_LUE_CTRL_0, value); 1335 if (ret < 0) 1336 return ret; 1337 } 1338 1339 value = DIV_ROUND_UP(secs, data); 1340 return ksz_write8(dev, REG_SW_LUE_CTRL_3, value); 1341 } 1342 1343 void ksz9477_port_queue_split(struct ksz_device *dev, int port) 1344 { 1345 u8 data; 1346 1347 if (dev->info->num_tx_queues == 8) 1348 data = PORT_EIGHT_QUEUE; 1349 else if (dev->info->num_tx_queues == 4) 1350 data = PORT_FOUR_QUEUE; 1351 else if (dev->info->num_tx_queues == 2) 1352 data = PORT_TWO_QUEUE; 1353 else 1354 data = PORT_SINGLE_QUEUE; 1355 1356 ksz_prmw8(dev, port, REG_PORT_CTRL_0, PORT_QUEUE_SPLIT_MASK, data); 1357 } 1358 1359 static void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port) 1360 { 1361 const u16 *regs = dev->info->regs; 1362 struct dsa_switch *ds = dev->ds; 1363 u16 data16; 1364 u8 member; 1365 1366 /* enable tag tail for host port */ 1367 if (cpu_port) 1368 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_TAIL_TAG_ENABLE, 1369 true); 1370 1371 ksz9477_port_queue_split(dev, port); 1372 1373 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_MAC_LOOPBACK, false); 1374 1375 /* set back pressure */ 1376 ksz_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, true); 1377 1378 /* enable broadcast storm limit */ 1379 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true); 1380 1381 /* replace priority */ 1382 ksz_port_cfg(dev, port, REG_PORT_MRI_MAC_CTRL, PORT_USER_PRIO_CEILING, 1383 false); 1384 ksz9477_port_cfg32(dev, port, REG_PORT_MTI_QUEUE_CTRL_0__4, 1385 MTI_PVID_REPLACE, false); 1386 1387 /* force flow control for non-PHY ports only */ 1388 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, 1389 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, 1390 !dev->info->internal_phy[port]); 1391 1392 if (cpu_port) 1393 member = dsa_user_ports(ds); 1394 else 1395 member = BIT(dsa_upstream_port(ds, port)); 1396 1397 ksz9477_cfg_port_member(dev, port, member); 1398 1399 /* clear pending interrupts */ 1400 if (dev->info->internal_phy[port]) 1401 ksz_pread16(dev, port, REG_PORT_PHY_INT_ENABLE, &data16); 1402 1403 ksz9477_port_acl_init(dev, port); 1404 1405 /* clear pending wake flags */ 1406 ksz_handle_wake_reason(dev, port); 1407 1408 /* Disable all WoL options by default. Otherwise 1409 * ksz_switch_macaddr_get/put logic will not work properly. 1410 */ 1411 ksz_pwrite8(dev, port, regs[REG_PORT_PME_CTRL], 0); 1412 } 1413 1414 int ksz9477_set_default_prio_queue_mapping(struct ksz_device *dev, int port) 1415 { 1416 u32 queue_map = 0; 1417 int ipm; 1418 1419 for (ipm = 0; ipm < dev->info->num_ipms; ipm++) { 1420 int queue; 1421 1422 /* Traffic Type (TT) is corresponding to the Internal Priority 1423 * Map (IPM) in the switch. Traffic Class (TC) is 1424 * corresponding to the queue in the switch. 1425 */ 1426 queue = ieee8021q_tt_to_tc(ipm, dev->info->num_tx_queues); 1427 if (queue < 0) 1428 return queue; 1429 1430 queue_map |= queue << (ipm * KSZ9477_PORT_TC_MAP_S); 1431 } 1432 1433 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map); 1434 } 1435 1436 static int ksz9477_dsa_port_setup(struct dsa_switch *ds, int port) 1437 { 1438 struct ksz_device *dev = ds->priv; 1439 int ret; 1440 1441 if (!dsa_is_user_port(ds, port)) 1442 return 0; 1443 1444 ksz9477_port_setup(dev, port, false); 1445 1446 ret = ksz9477_set_default_prio_queue_mapping(dev, port); 1447 if (ret) 1448 return ret; 1449 1450 return ksz_dcb_init_port(dev, port); 1451 } 1452 1453 static void ksz9477_config_cpu_port(struct dsa_switch *ds) 1454 { 1455 struct ksz_device *dev = ds->priv; 1456 struct ksz_port *p; 1457 int i; 1458 1459 for (i = 0; i < dev->info->port_cnt; i++) { 1460 if (dsa_is_cpu_port(ds, i) && 1461 (dev->info->cpu_ports & (1 << i))) { 1462 phy_interface_t interface; 1463 const char *prev_msg; 1464 const char *prev_mode; 1465 1466 dev->cpu_port = i; 1467 p = &dev->ports[i]; 1468 1469 /* Read from XMII register to determine host port 1470 * interface. If set specifically in device tree 1471 * note the difference to help debugging. 1472 */ 1473 interface = ksz9477_get_interface(dev, i); 1474 if (!p->interface) { 1475 if (dev->compat_interface) { 1476 dev_warn(dev->dev, 1477 "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. " 1478 "Please update your device tree.\n", 1479 i); 1480 p->interface = dev->compat_interface; 1481 } else { 1482 p->interface = interface; 1483 } 1484 } 1485 if (interface && interface != p->interface) { 1486 prev_msg = " instead of "; 1487 prev_mode = phy_modes(interface); 1488 } else { 1489 prev_msg = ""; 1490 prev_mode = ""; 1491 } 1492 dev_info(dev->dev, 1493 "Port%d: using phy mode %s%s%s\n", 1494 i, 1495 phy_modes(p->interface), 1496 prev_msg, 1497 prev_mode); 1498 1499 /* enable cpu port */ 1500 ksz9477_port_setup(dev, i, true); 1501 } 1502 } 1503 1504 for (i = 0; i < dev->info->port_cnt; i++) { 1505 if (i == dev->cpu_port) 1506 continue; 1507 ksz_port_stp_state_set(ds, i, BR_STATE_DISABLED); 1508 1509 /* Power down the internal PHY if port is unused. */ 1510 if (dsa_is_unused_port(ds, i) && dev->info->internal_phy[i]) 1511 ksz_pwrite16(dev, i, 0x100, BMCR_PDOWN); 1512 } 1513 } 1514 1515 #define RESV_MCAST_CNT 8 1516 1517 static u8 reserved_mcast_map[RESV_MCAST_CNT] = { 0, 1, 3, 16, 32, 33, 2, 17 }; 1518 1519 int ksz9477_enable_stp_addr(struct ksz_device *dev) 1520 { 1521 u8 i, ports, update; 1522 const u32 *masks; 1523 bool override; 1524 u32 data; 1525 int ret; 1526 1527 masks = dev->info->masks; 1528 1529 /* Enable Reserved multicast table */ 1530 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_RESV_MCAST_ENABLE, true); 1531 1532 /* The reserved multicast address table has 8 entries. Each entry has 1533 * a default value of which port to forward. It is assumed the host 1534 * port is the last port in most of the switches, but that is not the 1535 * case for KSZ9477 or maybe KSZ9897. For LAN937X family the default 1536 * port is port 5, the first RGMII port. It is okay for LAN9370, a 1537 * 5-port switch, but may not be correct for the other 8-port 1538 * versions. It is necessary to update the whole table to forward to 1539 * the right ports. 1540 * Furthermore PTP messages can use a reserved multicast address and 1541 * the host will not receive them if this table is not correct. 1542 */ 1543 for (i = 0; i < RESV_MCAST_CNT; i++) { 1544 data = reserved_mcast_map[i] << 1545 dev->info->shifts[ALU_STAT_INDEX]; 1546 data |= ALU_STAT_START | 1547 masks[ALU_STAT_DIRECT] | 1548 masks[ALU_RESV_MCAST_ADDR] | 1549 masks[ALU_STAT_READ]; 1550 ret = ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 1551 if (ret < 0) 1552 return ret; 1553 1554 /* wait to be finished */ 1555 ret = ksz9477_wait_alu_sta_ready(dev); 1556 if (ret < 0) 1557 return ret; 1558 1559 ret = ksz_read32(dev, REG_SW_ALU_VAL_B, &data); 1560 if (ret < 0) 1561 return ret; 1562 1563 override = false; 1564 ports = data & dev->port_mask; 1565 switch (i) { 1566 case 0: 1567 case 6: 1568 /* Change the host port. */ 1569 update = BIT(dev->cpu_port); 1570 override = true; 1571 break; 1572 case 2: 1573 /* Change the host port. */ 1574 update = BIT(dev->cpu_port); 1575 break; 1576 case 4: 1577 case 5: 1578 case 7: 1579 /* Skip the host port. */ 1580 update = dev->port_mask & ~BIT(dev->cpu_port); 1581 break; 1582 default: 1583 update = ports; 1584 break; 1585 } 1586 if (update != ports || override) { 1587 data &= ~dev->port_mask; 1588 data |= update; 1589 /* Set Override bit to receive frame even when port is 1590 * closed. 1591 */ 1592 if (override) 1593 data |= ALU_V_OVERRIDE; 1594 ret = ksz_write32(dev, REG_SW_ALU_VAL_B, data); 1595 if (ret < 0) 1596 return ret; 1597 1598 data = reserved_mcast_map[i] << 1599 dev->info->shifts[ALU_STAT_INDEX]; 1600 data |= ALU_STAT_START | 1601 masks[ALU_STAT_DIRECT] | 1602 masks[ALU_RESV_MCAST_ADDR] | 1603 masks[ALU_STAT_WRITE]; 1604 ret = ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 1605 if (ret < 0) 1606 return ret; 1607 1608 /* wait to be finished */ 1609 ret = ksz9477_wait_alu_sta_ready(dev); 1610 if (ret < 0) 1611 return ret; 1612 } 1613 } 1614 1615 return 0; 1616 } 1617 1618 /** 1619 * ksz9477_parse_drive_strength() - Extract and apply drive strength 1620 * configurations from device tree properties. 1621 * @dev: ksz device 1622 * 1623 * This function reads the specified drive strength properties from the 1624 * device tree, validates against the supported chip variants, and sets 1625 * them accordingly. An error should be critical here, as the drive strength 1626 * settings are crucial for EMI compliance. 1627 * 1628 * Return: 0 on success, error code otherwise 1629 */ 1630 static int ksz9477_parse_drive_strength(struct ksz_device *dev) 1631 { 1632 struct ksz_driver_strength_prop of_props[] = { 1633 [KSZ_DRIVER_STRENGTH_HI] = { 1634 .name = "microchip,hi-drive-strength-microamp", 1635 .offset = SW_HI_SPEED_DRIVE_STRENGTH_S, 1636 .value = -1, 1637 }, 1638 [KSZ_DRIVER_STRENGTH_LO] = { 1639 .name = "microchip,lo-drive-strength-microamp", 1640 .offset = SW_LO_SPEED_DRIVE_STRENGTH_S, 1641 .value = -1, 1642 }, 1643 [KSZ_DRIVER_STRENGTH_IO] = { 1644 .name = "microchip,io-drive-strength-microamp", 1645 .offset = 0, /* don't care */ 1646 .value = -1, 1647 }, 1648 }; 1649 struct device_node *np = dev->dev->of_node; 1650 bool have_any_prop = false; 1651 int i, ret; 1652 1653 for (i = 0; i < ARRAY_SIZE(of_props); i++) { 1654 ret = of_property_read_u32(np, of_props[i].name, 1655 &of_props[i].value); 1656 if (ret && ret != -EINVAL) 1657 dev_warn(dev->dev, "Failed to read %s\n", 1658 of_props[i].name); 1659 if (ret) 1660 continue; 1661 1662 have_any_prop = true; 1663 } 1664 1665 if (!have_any_prop) 1666 return 0; 1667 1668 return ksz_drive_strength_write(dev, of_props, ARRAY_SIZE(of_props)); 1669 } 1670 static int ksz9477_setup(struct dsa_switch *ds) 1671 { 1672 struct ksz_device *dev = ds->priv; 1673 u16 storm_mask, storm_rate; 1674 struct dsa_port *dp; 1675 struct ksz_port *p; 1676 const u16 *regs; 1677 int ret; 1678 1679 regs = dev->info->regs; 1680 1681 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 1682 dev->info->num_vlans, GFP_KERNEL); 1683 if (!dev->vlan_cache) 1684 return -ENOMEM; 1685 1686 ret = ksz9477_reset_switch(dev); 1687 if (ret) { 1688 dev_err(ds->dev, "failed to reset switch\n"); 1689 return ret; 1690 } 1691 1692 ret = ksz9477_parse_drive_strength(dev); 1693 if (ret) 1694 return ret; 1695 1696 if (ksz_has_sgmii_port(dev)) { 1697 ret = ksz9477_pcs_create(dev); 1698 if (ret) 1699 return ret; 1700 } 1701 1702 /* set broadcast storm protection 10% rate */ 1703 storm_mask = BROADCAST_STORM_RATE; 1704 storm_rate = (BROADCAST_STORM_VALUE * BROADCAST_STORM_PROT_RATE) / 100; 1705 regmap_update_bits(ksz_regmap_16(dev), regs[S_BROADCAST_CTRL], 1706 storm_mask, storm_rate); 1707 1708 ksz9477_config_cpu_port(ds); 1709 1710 ksz9477_enable_stp_addr(dev); 1711 1712 ds->num_tx_queues = dev->info->num_tx_queues; 1713 1714 regmap_update_bits(ksz_regmap_8(dev), regs[S_MULTICAST_CTRL], 1715 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE); 1716 1717 ksz_init_mib_timer(dev); 1718 1719 ds->configure_vlan_while_not_filtering = false; 1720 ds->dscp_prio_mapping_is_global = true; 1721 ds->mtu_enforcement_ingress = true; 1722 1723 /* Required for port partitioning. */ 1724 ksz9477_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY, 1725 true); 1726 1727 /* Do not work correctly with tail tagging. */ 1728 ksz_cfg(dev, REG_SW_MAC_CTRL_0, SW_CHECK_LENGTH, false); 1729 1730 /* Enable REG_SW_MTU__2 reg by setting SW_JUMBO_PACKET */ 1731 ksz_cfg(dev, REG_SW_MAC_CTRL_1, SW_JUMBO_PACKET, true); 1732 1733 /* Use collision based back pressure mode. */ 1734 ksz_cfg(dev, REG_SW_MAC_CTRL_1, SW_BACK_PRESSURE, 1735 SW_BACK_PRESSURE_COLLISION); 1736 1737 /* Now we can configure default MTU value */ 1738 ret = regmap_update_bits(ksz_regmap_16(dev), REG_SW_MTU__2, REG_SW_MTU_MASK, 1739 VLAN_ETH_FRAME_LEN + ETH_FCS_LEN); 1740 if (ret) 1741 return ret; 1742 1743 /* queue based egress rate limit */ 1744 ksz_cfg(dev, REG_SW_MAC_CTRL_5, SW_OUT_RATE_LIMIT_QUEUE_BASED, true); 1745 1746 /* enable global MIB counter freeze function */ 1747 ksz_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true); 1748 1749 /* Make sure PME (WoL) is not enabled. If requested, it will 1750 * be enabled by ksz_wol_pre_shutdown(). Otherwise, some PMICs 1751 * do not like PME events changes before shutdown. 1752 */ 1753 ret = ksz_write8(dev, regs[REG_SW_PME_CTRL], 0); 1754 if (ret < 0) 1755 return ret; 1756 1757 /* Start with learning disabled on standalone user ports, and enabled 1758 * on the CPU port. In lack of other finer mechanisms, learning on the 1759 * CPU port will avoid flooding bridge local addresses on the network 1760 * in some cases. 1761 */ 1762 p = &dev->ports[dev->cpu_port]; 1763 p->learning = true; 1764 1765 if (dev->irq > 0) { 1766 ret = ksz_girq_setup(dev); 1767 if (ret) 1768 return ret; 1769 1770 dsa_switch_for_each_user_port(dp, dev->ds) { 1771 ret = ksz_pirq_setup(dev, dp->index); 1772 if (ret) 1773 goto port_release; 1774 1775 if (dev->info->ptp_capable) { 1776 ret = ksz_ptp_irq_setup(ds, dp->index); 1777 if (ret) 1778 goto pirq_release; 1779 } 1780 } 1781 } 1782 1783 if (dev->info->ptp_capable) { 1784 ret = ksz_ptp_clock_register(ds); 1785 if (ret) { 1786 dev_err(dev->dev, "Failed to register PTP clock: %d\n", 1787 ret); 1788 goto port_release; 1789 } 1790 } 1791 1792 ret = ksz_mdio_register(dev); 1793 if (ret < 0) { 1794 dev_err(dev->dev, "failed to register the mdio"); 1795 goto out_ptp_clock_unregister; 1796 } 1797 1798 ret = ksz_dcb_init(dev); 1799 if (ret) 1800 goto out_ptp_clock_unregister; 1801 1802 /* start switch */ 1803 regmap_update_bits(ksz_regmap_8(dev), regs[S_START_CTRL], 1804 SW_START, SW_START); 1805 1806 return 0; 1807 1808 out_ptp_clock_unregister: 1809 if (dev->info->ptp_capable) 1810 ksz_ptp_clock_unregister(ds); 1811 port_release: 1812 if (dev->irq > 0) { 1813 dsa_switch_for_each_user_port_continue_reverse(dp, dev->ds) { 1814 if (dev->info->ptp_capable) 1815 ksz_ptp_irq_free(ds, dp->index); 1816 pirq_release: 1817 ksz_irq_free(&dev->ports[dp->index].pirq); 1818 } 1819 ksz_irq_free(&dev->girq); 1820 } 1821 1822 return ret; 1823 } 1824 1825 u32 ksz9477_get_port_addr(int port, int offset) 1826 { 1827 return PORT_CTRL_ADDR(port, offset); 1828 } 1829 1830 static int ksz9477_tc_cbs_set_cinc(struct ksz_device *dev, int port, u32 val) 1831 { 1832 val = val >> 8; 1833 1834 return ksz_pwrite16(dev, port, REG_PORT_MTI_CREDIT_INCREMENT, val); 1835 } 1836 1837 /* The KSZ9477 provides following HW features to accelerate 1838 * HSR frames handling: 1839 * 1840 * 1. TX PACKET DUPLICATION FROM HOST TO SWITCH 1841 * 2. RX PACKET DUPLICATION DISCARDING 1842 * 3. PREVENTING PACKET LOOP IN THE RING BY SELF-ADDRESS FILTERING 1843 * 1844 * Only one from point 1. has the NETIF_F* flag available. 1845 * 1846 * Ones from point 2 and 3 are "best effort" - i.e. those will 1847 * work correctly most of the time, but it may happen that some 1848 * frames will not be caught - to be more specific; there is a race 1849 * condition in hardware such that, when duplicate packets are received 1850 * on member ports very close in time to each other, the hardware fails 1851 * to detect that they are duplicates. 1852 * 1853 * Hence, the SW needs to handle those special cases. However, the speed 1854 * up gain is considerable when above features are used. 1855 * 1856 * Moreover, the NETIF_F_HW_HSR_FWD feature is also enabled, as HSR frames 1857 * can be forwarded in the switch fabric between HSR ports. 1858 */ 1859 #define KSZ9477_SUPPORTED_HSR_FEATURES (NETIF_F_HW_HSR_DUP | NETIF_F_HW_HSR_FWD) 1860 1861 static int ksz9477_hsr_join(struct dsa_switch *ds, int port, 1862 struct net_device *hsr, 1863 struct netlink_ext_ack *extack) 1864 { 1865 struct ksz_device *dev = ds->priv; 1866 struct net_device *user; 1867 struct dsa_port *hsr_dp; 1868 u8 data, hsr_ports = 0; 1869 enum hsr_version ver; 1870 int ret; 1871 1872 ret = hsr_get_version(hsr, &ver); 1873 if (ret) 1874 return ret; 1875 1876 if (dev->chip_id != KSZ9477_CHIP_ID) { 1877 NL_SET_ERR_MSG_MOD(extack, "Chip does not support HSR offload"); 1878 return -EOPNOTSUPP; 1879 } 1880 1881 /* KSZ9477 can support HW offloading of only 1 HSR device */ 1882 if (dev->hsr_dev && hsr != dev->hsr_dev) { 1883 NL_SET_ERR_MSG_MOD(extack, 1884 "Offload supported for a single HSR"); 1885 return -EOPNOTSUPP; 1886 } 1887 1888 /* KSZ9477 only supports HSR v0 and v1 */ 1889 if (!(ver == HSR_V0 || ver == HSR_V1)) { 1890 NL_SET_ERR_MSG_MOD(extack, "Only HSR v0 and v1 supported"); 1891 return -EOPNOTSUPP; 1892 } 1893 1894 /* KSZ9477 can only perform HSR offloading for up to two ports */ 1895 if (hweight8(dev->hsr_ports) >= 2) { 1896 NL_SET_ERR_MSG_MOD(extack, 1897 "Cannot offload more than two ports - using software HSR"); 1898 return -EOPNOTSUPP; 1899 } 1900 1901 /* Self MAC address filtering, to avoid frames traversing 1902 * the HSR ring more than once. 1903 */ 1904 ret = ksz_switch_macaddr_get(ds, port, extack); 1905 if (ret) 1906 return ret; 1907 1908 /* Program which port(s) shall support HSR */ 1909 ksz_rmw32(dev, REG_HSR_PORT_MAP__4, BIT(port), BIT(port)); 1910 1911 /* Forward frames between HSR ports (i.e. bridge together HSR ports) */ 1912 if (dev->hsr_ports) { 1913 dsa_hsr_foreach_port(hsr_dp, ds, hsr) 1914 hsr_ports |= BIT(hsr_dp->index); 1915 1916 hsr_ports |= BIT(dsa_upstream_port(ds, port)); 1917 dsa_hsr_foreach_port(hsr_dp, ds, hsr) 1918 ksz9477_cfg_port_member(dev, hsr_dp->index, hsr_ports); 1919 } 1920 1921 if (!dev->hsr_ports) { 1922 /* Enable discarding of received HSR frames */ 1923 ksz_read8(dev, REG_HSR_ALU_CTRL_0__1, &data); 1924 data |= HSR_DUPLICATE_DISCARD; 1925 data &= ~HSR_NODE_UNICAST; 1926 ksz_write8(dev, REG_HSR_ALU_CTRL_0__1, data); 1927 } 1928 1929 /* Enable per port self-address filtering. 1930 * The global self-address filtering has already been enabled in the 1931 * ksz9477_reset_switch() function. 1932 */ 1933 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, PORT_SRC_ADDR_FILTER, true); 1934 1935 /* Setup HW supported features for lan HSR ports */ 1936 user = dsa_to_port(ds, port)->user; 1937 user->features |= KSZ9477_SUPPORTED_HSR_FEATURES; 1938 1939 dev->hsr_dev = hsr; 1940 dev->hsr_ports |= BIT(port); 1941 1942 return 0; 1943 } 1944 1945 static int ksz9477_hsr_leave(struct dsa_switch *ds, int port, 1946 struct net_device *hsr) 1947 { 1948 struct ksz_device *dev = ds->priv; 1949 1950 WARN_ON(dev->chip_id != KSZ9477_CHIP_ID); 1951 1952 /* Clear port HSR support */ 1953 ksz_rmw32(dev, REG_HSR_PORT_MAP__4, BIT(port), 0); 1954 1955 /* Disable forwarding frames between HSR ports */ 1956 ksz9477_cfg_port_member(dev, port, BIT(dsa_upstream_port(ds, port))); 1957 1958 /* Disable per port self-address filtering */ 1959 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, PORT_SRC_ADDR_FILTER, false); 1960 1961 dev->hsr_ports &= ~BIT(port); 1962 if (!dev->hsr_ports) 1963 dev->hsr_dev = NULL; 1964 1965 ksz_switch_macaddr_put(ds); 1966 1967 return 0; 1968 } 1969 1970 static int ksz9477_switch_init(struct ksz_device *dev) 1971 { 1972 u8 data8; 1973 int ret; 1974 1975 dev->port_mask = (1 << dev->info->port_cnt) - 1; 1976 1977 /* turn off SPI DO Edge select */ 1978 ret = ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8); 1979 if (ret) 1980 return ret; 1981 1982 data8 &= ~SPI_AUTO_EDGE_DETECTION; 1983 ret = ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8); 1984 if (ret) 1985 return ret; 1986 1987 return 0; 1988 } 1989 1990 static enum dsa_tag_protocol ksz9477_get_tag_protocol(struct dsa_switch *ds, 1991 int port, 1992 enum dsa_tag_protocol mp) 1993 { 1994 struct ksz_device *dev = ds->priv; 1995 1996 if (dev->chip_id == KSZ8563_CHIP_ID || 1997 dev->chip_id == KSZ9893_CHIP_ID || 1998 dev->chip_id == KSZ9563_CHIP_ID) 1999 return DSA_TAG_PROTO_KSZ9893; 2000 2001 return DSA_TAG_PROTO_KSZ9477; 2002 } 2003 2004 static int ksz9477_connect_tag_protocol(struct dsa_switch *ds, 2005 enum dsa_tag_protocol proto) 2006 { 2007 struct ksz_tagger_data *tagger_data; 2008 2009 if (proto != DSA_TAG_PROTO_KSZ9893 && proto != DSA_TAG_PROTO_KSZ9477) 2010 return -EPROTONOSUPPORT; 2011 2012 tagger_data = ksz_tagger_data(ds); 2013 tagger_data->xmit_work_fn = ksz_port_deferred_xmit; 2014 2015 return 0; 2016 } 2017 2018 static void ksz9477_set_gbit(struct ksz_device *dev, int port, bool gbit) 2019 { 2020 const u8 *bitval = dev->info->xmii_ctrl1; 2021 const u16 *regs = dev->info->regs; 2022 u8 data8; 2023 2024 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2025 2026 data8 &= ~P_GMII_1GBIT_M; 2027 2028 if (gbit) 2029 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]); 2030 else 2031 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]); 2032 2033 /* Write the updated value */ 2034 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 2035 } 2036 2037 static void ksz9477_set_100_10mbit(struct ksz_device *dev, int port, int speed) 2038 { 2039 const u8 *bitval = dev->info->xmii_ctrl0; 2040 const u16 *regs = dev->info->regs; 2041 u8 data8; 2042 2043 ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8); 2044 2045 data8 &= ~P_MII_100MBIT_M; 2046 2047 if (speed == SPEED_100) 2048 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]); 2049 else 2050 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]); 2051 2052 /* Write the updated value */ 2053 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8); 2054 } 2055 2056 static void ksz9477_port_set_xmii_speed(struct ksz_device *dev, int port, 2057 int speed) 2058 { 2059 if (speed == SPEED_1000) 2060 ksz9477_set_gbit(dev, port, true); 2061 else 2062 ksz9477_set_gbit(dev, port, false); 2063 2064 if (speed == SPEED_100 || speed == SPEED_10) 2065 ksz9477_set_100_10mbit(dev, port, speed); 2066 } 2067 2068 static void ksz9477_duplex_flowctrl(struct ksz_device *dev, int port, int duplex, 2069 bool tx_pause, bool rx_pause) 2070 { 2071 const u8 *bitval = dev->info->xmii_ctrl0; 2072 const u32 *masks = dev->info->masks; 2073 const u16 *regs = dev->info->regs; 2074 u8 mask; 2075 u8 val; 2076 2077 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] | 2078 masks[P_MII_RX_FLOW_CTRL]; 2079 2080 if (duplex == DUPLEX_FULL) 2081 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]); 2082 else 2083 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]); 2084 2085 if (tx_pause) 2086 val |= masks[P_MII_TX_FLOW_CTRL]; 2087 2088 if (rx_pause) 2089 val |= masks[P_MII_RX_FLOW_CTRL]; 2090 2091 ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val); 2092 } 2093 2094 static void ksz9477_port_teardown(struct dsa_switch *ds, int port) 2095 { 2096 struct ksz_device *dev = ds->priv; 2097 2098 if (dsa_is_user_port(ds, port)) 2099 ksz9477_port_acl_free(dev, port); 2100 } 2101 2102 void ksz9477_phylink_mac_link_up(struct phylink_config *config, 2103 struct phy_device *phydev, 2104 unsigned int mode, 2105 phy_interface_t interface, 2106 int speed, int duplex, bool tx_pause, 2107 bool rx_pause) 2108 { 2109 struct dsa_port *dp = dsa_phylink_to_port(config); 2110 struct ksz_device *dev = dp->ds->priv; 2111 int port = dp->index; 2112 struct ksz_port *p; 2113 2114 p = &dev->ports[port]; 2115 2116 /* Internal PHYs */ 2117 if (dev->info->internal_phy[port]) 2118 return; 2119 2120 p->speed = speed; 2121 2122 ksz9477_port_set_xmii_speed(dev, port, speed); 2123 2124 ksz9477_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause); 2125 } 2126 2127 /** 2128 * ksz9477_support_eee - Determine Energy Efficient Ethernet (EEE) support for a 2129 * port 2130 * @ds: Pointer to the DSA switch structure 2131 * @port: Port number to check 2132 * 2133 * This function also documents devices where EEE was initially advertised but 2134 * later withdrawn due to reliability issues, as described in official errata 2135 * documents. These devices are explicitly listed to record known limitations, 2136 * even if there is no technical necessity for runtime checks. 2137 * 2138 * Returns: true if the internal PHY on the given port supports fully 2139 * operational EEE, false otherwise. 2140 */ 2141 static bool ksz9477_support_eee(struct dsa_switch *ds, int port) 2142 { 2143 struct ksz_device *dev = ds->priv; 2144 2145 if (!dev->info->internal_phy[port]) 2146 return false; 2147 2148 switch (dev->chip_id) { 2149 case KSZ8563_CHIP_ID: 2150 case KSZ9563_CHIP_ID: 2151 case KSZ9893_CHIP_ID: 2152 return true; 2153 default: 2154 /* KSZ8567R Errata DS80000752C Module 4 */ 2155 /* KSZ9477S Errata DS80000754A Module 4 */ 2156 /* KSZ9567S Errata DS80000756A Module 4 */ 2157 /* KSZ9896C Errata DS80000757A Module 3 */ 2158 /* KSZ9897R Errata DS80000758C Module 4 */ 2159 /* Energy Efficient Ethernet (EEE) feature select must be 2160 * manually disabled 2161 * The EEE feature is enabled by default, but it is not fully 2162 * operational. It must be manually disabled through register 2163 * controls. If not disabled, the PHY ports can auto-negotiate 2164 * to enable EEE, and this feature can cause link drops when 2165 * linked to another device supporting EEE. 2166 * 2167 * The same item appears in the errata for all switches above. 2168 */ 2169 break; 2170 } 2171 2172 return false; 2173 } 2174 2175 static struct phylink_pcs * 2176 ksz9477_phylink_mac_select_pcs(struct phylink_config *config, 2177 phy_interface_t interface) 2178 { 2179 struct dsa_port *dp = dsa_phylink_to_port(config); 2180 struct ksz_device *dev = dp->ds->priv; 2181 struct ksz_port *p = &dev->ports[dp->index]; 2182 2183 if (ksz_is_sgmii_port(dev, dp->index) && 2184 (interface == PHY_INTERFACE_MODE_SGMII || 2185 interface == PHY_INTERFACE_MODE_1000BASEX)) 2186 return p->pcs; 2187 2188 return NULL; 2189 } 2190 2191 const struct phylink_mac_ops ksz9477_phylink_mac_ops = { 2192 .mac_config = ksz_phylink_mac_config, 2193 .mac_link_down = ksz_phylink_mac_link_down, 2194 .mac_link_up = ksz9477_phylink_mac_link_up, 2195 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi, 2196 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi, 2197 .mac_select_pcs = ksz9477_phylink_mac_select_pcs, 2198 }; 2199 2200 const struct ksz_dev_ops ksz9477_dev_ops = { 2201 .get_port_addr = ksz9477_get_port_addr, 2202 .cfg_port_member = ksz9477_cfg_port_member, 2203 .r_mib_cnt = ksz9477_r_mib_cnt, 2204 .r_mib_pkt = ksz9477_r_mib_pkt, 2205 .r_mib_stat64 = ksz9477_r_mib_stats64, 2206 .freeze_mib = ksz9477_freeze_mib, 2207 .port_init_cnt = ksz9477_port_init_cnt, 2208 .pme_write8 = ksz_write8, 2209 .pme_pread8 = ksz_pread8, 2210 .pme_pwrite8 = ksz_pwrite8, 2211 .tc_cbs_set_cinc = ksz9477_tc_cbs_set_cinc, 2212 .init = ksz9477_switch_init, 2213 }; 2214 2215 const struct dsa_switch_ops ksz9477_switch_ops = { 2216 .get_tag_protocol = ksz9477_get_tag_protocol, 2217 .connect_tag_protocol = ksz9477_connect_tag_protocol, 2218 .setup = ksz9477_setup, 2219 .teardown = ksz_teardown, 2220 .phy_read = ksz9477_phy_read16, 2221 .phy_write = ksz9477_phy_write16, 2222 .phylink_get_caps = ksz9477_phylink_get_caps, 2223 .port_setup = ksz9477_dsa_port_setup, 2224 .set_ageing_time = ksz9477_set_ageing_time, 2225 .get_strings = ksz_get_strings, 2226 .get_ethtool_stats = ksz_get_ethtool_stats, 2227 .get_sset_count = ksz_sset_count, 2228 .port_bridge_join = ksz_port_bridge_join, 2229 .port_bridge_leave = ksz_port_bridge_leave, 2230 .port_hsr_join = ksz9477_hsr_join, 2231 .port_hsr_leave = ksz9477_hsr_leave, 2232 .port_set_mac_address = ksz_port_set_mac_address, 2233 .port_stp_state_set = ksz_port_stp_state_set, 2234 .port_teardown = ksz9477_port_teardown, 2235 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 2236 .port_bridge_flags = ksz_port_bridge_flags, 2237 .port_fast_age = ksz9477_flush_dyn_mac_table, 2238 .port_vlan_filtering = ksz9477_port_vlan_filtering, 2239 .port_vlan_add = ksz9477_port_vlan_add, 2240 .port_vlan_del = ksz9477_port_vlan_del, 2241 .port_fdb_dump = ksz9477_fdb_dump, 2242 .port_fdb_add = ksz9477_fdb_add, 2243 .port_fdb_del = ksz9477_fdb_del, 2244 .port_mdb_add = ksz9477_mdb_add, 2245 .port_mdb_del = ksz9477_mdb_del, 2246 .port_mirror_add = ksz9477_port_mirror_add, 2247 .port_mirror_del = ksz9477_port_mirror_del, 2248 .get_stats64 = ksz_get_stats64, 2249 .get_pause_stats = ksz_get_pause_stats, 2250 .port_change_mtu = ksz9477_change_mtu, 2251 .port_max_mtu = ksz9477_max_mtu, 2252 .get_wol = ksz_get_wol, 2253 .set_wol = ksz_set_wol, 2254 .suspend = ksz_suspend, 2255 .resume = ksz_resume, 2256 .get_ts_info = ksz_get_ts_info, 2257 .port_hwtstamp_get = ksz_hwtstamp_get, 2258 .port_hwtstamp_set = ksz_hwtstamp_set, 2259 .port_txtstamp = ksz_port_txtstamp, 2260 .port_rxtstamp = ksz_port_rxtstamp, 2261 .cls_flower_add = ksz9477_cls_flower_add, 2262 .cls_flower_del = ksz9477_cls_flower_del, 2263 .port_setup_tc = ksz_setup_tc, 2264 .support_eee = ksz9477_support_eee, 2265 .set_mac_eee = ksz_set_mac_eee, 2266 .port_get_default_prio = ksz_port_get_default_prio, 2267 .port_set_default_prio = ksz_port_set_default_prio, 2268 .port_get_dscp_prio = ksz_port_get_dscp_prio, 2269 .port_add_dscp_prio = ksz_port_add_dscp_prio, 2270 .port_del_dscp_prio = ksz_port_del_dscp_prio, 2271 .port_get_apptrust = ksz_port_get_apptrust, 2272 .port_set_apptrust = ksz_port_set_apptrust, 2273 }; 2274 2275 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 2276 MODULE_DESCRIPTION("Microchip KSZ9477 Series Switch DSA Driver"); 2277 MODULE_LICENSE("GPL"); 2278