1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip KSZ9477 switch driver main logic 4 * 5 * Copyright (C) 2017-2019 Microchip Technology Inc. 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/iopoll.h> 11 #include <linux/platform_data/microchip-ksz.h> 12 #include <linux/phy.h> 13 #include <linux/if_bridge.h> 14 #include <linux/if_vlan.h> 15 #include <net/dsa.h> 16 #include <net/switchdev.h> 17 18 #include "ksz9477_reg.h" 19 #include "ksz_common.h" 20 21 /* Used with variable features to indicate capabilities. */ 22 #define GBIT_SUPPORT BIT(0) 23 #define NEW_XMII BIT(1) 24 #define IS_9893 BIT(2) 25 26 static const struct { 27 int index; 28 char string[ETH_GSTRING_LEN]; 29 } ksz9477_mib_names[TOTAL_SWITCH_COUNTER_NUM] = { 30 { 0x00, "rx_hi" }, 31 { 0x01, "rx_undersize" }, 32 { 0x02, "rx_fragments" }, 33 { 0x03, "rx_oversize" }, 34 { 0x04, "rx_jabbers" }, 35 { 0x05, "rx_symbol_err" }, 36 { 0x06, "rx_crc_err" }, 37 { 0x07, "rx_align_err" }, 38 { 0x08, "rx_mac_ctrl" }, 39 { 0x09, "rx_pause" }, 40 { 0x0A, "rx_bcast" }, 41 { 0x0B, "rx_mcast" }, 42 { 0x0C, "rx_ucast" }, 43 { 0x0D, "rx_64_or_less" }, 44 { 0x0E, "rx_65_127" }, 45 { 0x0F, "rx_128_255" }, 46 { 0x10, "rx_256_511" }, 47 { 0x11, "rx_512_1023" }, 48 { 0x12, "rx_1024_1522" }, 49 { 0x13, "rx_1523_2000" }, 50 { 0x14, "rx_2001" }, 51 { 0x15, "tx_hi" }, 52 { 0x16, "tx_late_col" }, 53 { 0x17, "tx_pause" }, 54 { 0x18, "tx_bcast" }, 55 { 0x19, "tx_mcast" }, 56 { 0x1A, "tx_ucast" }, 57 { 0x1B, "tx_deferred" }, 58 { 0x1C, "tx_total_col" }, 59 { 0x1D, "tx_exc_col" }, 60 { 0x1E, "tx_single_col" }, 61 { 0x1F, "tx_mult_col" }, 62 { 0x80, "rx_total" }, 63 { 0x81, "tx_total" }, 64 { 0x82, "rx_discards" }, 65 { 0x83, "tx_discards" }, 66 }; 67 68 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) 69 { 70 regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0); 71 } 72 73 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits, 74 bool set) 75 { 76 regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset), 77 bits, set ? bits : 0); 78 } 79 80 static void ksz9477_cfg32(struct ksz_device *dev, u32 addr, u32 bits, bool set) 81 { 82 regmap_update_bits(dev->regmap[2], addr, bits, set ? bits : 0); 83 } 84 85 static void ksz9477_port_cfg32(struct ksz_device *dev, int port, int offset, 86 u32 bits, bool set) 87 { 88 regmap_update_bits(dev->regmap[2], PORT_CTRL_ADDR(port, offset), 89 bits, set ? bits : 0); 90 } 91 92 static int ksz9477_change_mtu(struct dsa_switch *ds, int port, int mtu) 93 { 94 struct ksz_device *dev = ds->priv; 95 u16 frame_size, max_frame = 0; 96 int i; 97 98 frame_size = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 99 100 /* Cache the per-port MTU setting */ 101 dev->ports[port].max_frame = frame_size; 102 103 for (i = 0; i < dev->port_cnt; i++) 104 max_frame = max(max_frame, dev->ports[i].max_frame); 105 106 return regmap_update_bits(dev->regmap[1], REG_SW_MTU__2, 107 REG_SW_MTU_MASK, max_frame); 108 } 109 110 static int ksz9477_max_mtu(struct dsa_switch *ds, int port) 111 { 112 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 113 } 114 115 static int ksz9477_wait_vlan_ctrl_ready(struct ksz_device *dev) 116 { 117 unsigned int val; 118 119 return regmap_read_poll_timeout(dev->regmap[0], REG_SW_VLAN_CTRL, 120 val, !(val & VLAN_START), 10, 1000); 121 } 122 123 static int ksz9477_get_vlan_table(struct ksz_device *dev, u16 vid, 124 u32 *vlan_table) 125 { 126 int ret; 127 128 mutex_lock(&dev->vlan_mutex); 129 130 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 131 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_READ | VLAN_START); 132 133 /* wait to be cleared */ 134 ret = ksz9477_wait_vlan_ctrl_ready(dev); 135 if (ret) { 136 dev_dbg(dev->dev, "Failed to read vlan table\n"); 137 goto exit; 138 } 139 140 ksz_read32(dev, REG_SW_VLAN_ENTRY__4, &vlan_table[0]); 141 ksz_read32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, &vlan_table[1]); 142 ksz_read32(dev, REG_SW_VLAN_ENTRY_PORTS__4, &vlan_table[2]); 143 144 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 145 146 exit: 147 mutex_unlock(&dev->vlan_mutex); 148 149 return ret; 150 } 151 152 static int ksz9477_set_vlan_table(struct ksz_device *dev, u16 vid, 153 u32 *vlan_table) 154 { 155 int ret; 156 157 mutex_lock(&dev->vlan_mutex); 158 159 ksz_write32(dev, REG_SW_VLAN_ENTRY__4, vlan_table[0]); 160 ksz_write32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, vlan_table[1]); 161 ksz_write32(dev, REG_SW_VLAN_ENTRY_PORTS__4, vlan_table[2]); 162 163 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 164 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_START | VLAN_WRITE); 165 166 /* wait to be cleared */ 167 ret = ksz9477_wait_vlan_ctrl_ready(dev); 168 if (ret) { 169 dev_dbg(dev->dev, "Failed to write vlan table\n"); 170 goto exit; 171 } 172 173 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 174 175 /* update vlan cache table */ 176 dev->vlan_cache[vid].table[0] = vlan_table[0]; 177 dev->vlan_cache[vid].table[1] = vlan_table[1]; 178 dev->vlan_cache[vid].table[2] = vlan_table[2]; 179 180 exit: 181 mutex_unlock(&dev->vlan_mutex); 182 183 return ret; 184 } 185 186 static void ksz9477_read_table(struct ksz_device *dev, u32 *table) 187 { 188 ksz_read32(dev, REG_SW_ALU_VAL_A, &table[0]); 189 ksz_read32(dev, REG_SW_ALU_VAL_B, &table[1]); 190 ksz_read32(dev, REG_SW_ALU_VAL_C, &table[2]); 191 ksz_read32(dev, REG_SW_ALU_VAL_D, &table[3]); 192 } 193 194 static void ksz9477_write_table(struct ksz_device *dev, u32 *table) 195 { 196 ksz_write32(dev, REG_SW_ALU_VAL_A, table[0]); 197 ksz_write32(dev, REG_SW_ALU_VAL_B, table[1]); 198 ksz_write32(dev, REG_SW_ALU_VAL_C, table[2]); 199 ksz_write32(dev, REG_SW_ALU_VAL_D, table[3]); 200 } 201 202 static int ksz9477_wait_alu_ready(struct ksz_device *dev) 203 { 204 unsigned int val; 205 206 return regmap_read_poll_timeout(dev->regmap[2], REG_SW_ALU_CTRL__4, 207 val, !(val & ALU_START), 10, 1000); 208 } 209 210 static int ksz9477_wait_alu_sta_ready(struct ksz_device *dev) 211 { 212 unsigned int val; 213 214 return regmap_read_poll_timeout(dev->regmap[2], 215 REG_SW_ALU_STAT_CTRL__4, 216 val, !(val & ALU_STAT_START), 217 10, 1000); 218 } 219 220 static int ksz9477_reset_switch(struct ksz_device *dev) 221 { 222 u8 data8; 223 u32 data32; 224 225 /* reset switch */ 226 ksz_cfg(dev, REG_SW_OPERATION, SW_RESET, true); 227 228 /* turn off SPI DO Edge select */ 229 regmap_update_bits(dev->regmap[0], REG_SW_GLOBAL_SERIAL_CTRL_0, 230 SPI_AUTO_EDGE_DETECTION, 0); 231 232 /* default configuration */ 233 ksz_read8(dev, REG_SW_LUE_CTRL_1, &data8); 234 data8 = SW_AGING_ENABLE | SW_LINK_AUTO_AGING | 235 SW_SRC_ADDR_FILTER | SW_FLUSH_STP_TABLE | SW_FLUSH_MSTP_TABLE; 236 ksz_write8(dev, REG_SW_LUE_CTRL_1, data8); 237 238 /* disable interrupts */ 239 ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK); 240 ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0x7F); 241 ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32); 242 243 /* set broadcast storm protection 10% rate */ 244 regmap_update_bits(dev->regmap[1], REG_SW_MAC_CTRL_2, 245 BROADCAST_STORM_RATE, 246 (BROADCAST_STORM_VALUE * 247 BROADCAST_STORM_PROT_RATE) / 100); 248 249 data8 = SW_ENABLE_REFCLKO; 250 if (dev->synclko_disable) 251 data8 = 0; 252 else if (dev->synclko_125) 253 data8 = SW_ENABLE_REFCLKO | SW_REFCLKO_IS_125MHZ; 254 ksz_write8(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1, data8); 255 256 return 0; 257 } 258 259 static void ksz9477_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, 260 u64 *cnt) 261 { 262 struct ksz_port *p = &dev->ports[port]; 263 unsigned int val; 264 u32 data; 265 int ret; 266 267 /* retain the flush/freeze bit */ 268 data = p->freeze ? MIB_COUNTER_FLUSH_FREEZE : 0; 269 data |= MIB_COUNTER_READ; 270 data |= (addr << MIB_COUNTER_INDEX_S); 271 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, data); 272 273 ret = regmap_read_poll_timeout(dev->regmap[2], 274 PORT_CTRL_ADDR(port, REG_PORT_MIB_CTRL_STAT__4), 275 val, !(val & MIB_COUNTER_READ), 10, 1000); 276 /* failed to read MIB. get out of loop */ 277 if (ret) { 278 dev_dbg(dev->dev, "Failed to get MIB\n"); 279 return; 280 } 281 282 /* count resets upon read */ 283 ksz_pread32(dev, port, REG_PORT_MIB_DATA, &data); 284 *cnt += data; 285 } 286 287 static void ksz9477_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 288 u64 *dropped, u64 *cnt) 289 { 290 addr = ksz9477_mib_names[addr].index; 291 ksz9477_r_mib_cnt(dev, port, addr, cnt); 292 } 293 294 static void ksz9477_freeze_mib(struct ksz_device *dev, int port, bool freeze) 295 { 296 u32 val = freeze ? MIB_COUNTER_FLUSH_FREEZE : 0; 297 struct ksz_port *p = &dev->ports[port]; 298 299 /* enable/disable the port for flush/freeze function */ 300 mutex_lock(&p->mib.cnt_mutex); 301 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, val); 302 303 /* used by MIB counter reading code to know freeze is enabled */ 304 p->freeze = freeze; 305 mutex_unlock(&p->mib.cnt_mutex); 306 } 307 308 static void ksz9477_port_init_cnt(struct ksz_device *dev, int port) 309 { 310 struct ksz_port_mib *mib = &dev->ports[port].mib; 311 312 /* flush all enabled port MIB counters */ 313 mutex_lock(&mib->cnt_mutex); 314 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 315 MIB_COUNTER_FLUSH_FREEZE); 316 ksz_write8(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FLUSH); 317 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 0); 318 mutex_unlock(&mib->cnt_mutex); 319 320 mib->cnt_ptr = 0; 321 memset(mib->counters, 0, dev->mib_cnt * sizeof(u64)); 322 } 323 324 static enum dsa_tag_protocol ksz9477_get_tag_protocol(struct dsa_switch *ds, 325 int port, 326 enum dsa_tag_protocol mp) 327 { 328 enum dsa_tag_protocol proto = DSA_TAG_PROTO_KSZ9477; 329 struct ksz_device *dev = ds->priv; 330 331 if (dev->features & IS_9893) 332 proto = DSA_TAG_PROTO_KSZ9893; 333 return proto; 334 } 335 336 static int ksz9477_phy_read16(struct dsa_switch *ds, int addr, int reg) 337 { 338 struct ksz_device *dev = ds->priv; 339 u16 val = 0xffff; 340 341 /* No real PHY after this. Simulate the PHY. 342 * A fixed PHY can be setup in the device tree, but this function is 343 * still called for that port during initialization. 344 * For RGMII PHY there is no way to access it so the fixed PHY should 345 * be used. For SGMII PHY the supporting code will be added later. 346 */ 347 if (addr >= dev->phy_port_cnt) { 348 struct ksz_port *p = &dev->ports[addr]; 349 350 switch (reg) { 351 case MII_BMCR: 352 val = 0x1140; 353 break; 354 case MII_BMSR: 355 val = 0x796d; 356 break; 357 case MII_PHYSID1: 358 val = 0x0022; 359 break; 360 case MII_PHYSID2: 361 val = 0x1631; 362 break; 363 case MII_ADVERTISE: 364 val = 0x05e1; 365 break; 366 case MII_LPA: 367 val = 0xc5e1; 368 break; 369 case MII_CTRL1000: 370 val = 0x0700; 371 break; 372 case MII_STAT1000: 373 if (p->phydev.speed == SPEED_1000) 374 val = 0x3800; 375 else 376 val = 0; 377 break; 378 } 379 } else { 380 ksz_pread16(dev, addr, 0x100 + (reg << 1), &val); 381 } 382 383 return val; 384 } 385 386 static int ksz9477_phy_write16(struct dsa_switch *ds, int addr, int reg, 387 u16 val) 388 { 389 struct ksz_device *dev = ds->priv; 390 391 /* No real PHY after this. */ 392 if (addr >= dev->phy_port_cnt) 393 return 0; 394 395 /* No gigabit support. Do not write to this register. */ 396 if (!(dev->features & GBIT_SUPPORT) && reg == MII_CTRL1000) 397 return 0; 398 ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val); 399 400 return 0; 401 } 402 403 static void ksz9477_get_strings(struct dsa_switch *ds, int port, 404 u32 stringset, uint8_t *buf) 405 { 406 int i; 407 408 if (stringset != ETH_SS_STATS) 409 return; 410 411 for (i = 0; i < TOTAL_SWITCH_COUNTER_NUM; i++) { 412 memcpy(buf + i * ETH_GSTRING_LEN, ksz9477_mib_names[i].string, 413 ETH_GSTRING_LEN); 414 } 415 } 416 417 static void ksz9477_cfg_port_member(struct ksz_device *dev, int port, 418 u8 member) 419 { 420 ksz_pwrite32(dev, port, REG_PORT_VLAN_MEMBERSHIP__4, member); 421 } 422 423 static void ksz9477_port_stp_state_set(struct dsa_switch *ds, int port, 424 u8 state) 425 { 426 ksz_port_stp_state_set(ds, port, state, P_STP_CTRL); 427 } 428 429 static void ksz9477_flush_dyn_mac_table(struct ksz_device *dev, int port) 430 { 431 u8 data; 432 433 regmap_update_bits(dev->regmap[0], REG_SW_LUE_CTRL_2, 434 SW_FLUSH_OPTION_M << SW_FLUSH_OPTION_S, 435 SW_FLUSH_OPTION_DYN_MAC << SW_FLUSH_OPTION_S); 436 437 if (port < dev->port_cnt) { 438 /* flush individual port */ 439 ksz_pread8(dev, port, P_STP_CTRL, &data); 440 if (!(data & PORT_LEARN_DISABLE)) 441 ksz_pwrite8(dev, port, P_STP_CTRL, 442 data | PORT_LEARN_DISABLE); 443 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true); 444 ksz_pwrite8(dev, port, P_STP_CTRL, data); 445 } else { 446 /* flush all */ 447 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_STP_TABLE, true); 448 } 449 } 450 451 static int ksz9477_port_vlan_filtering(struct dsa_switch *ds, int port, 452 bool flag, 453 struct netlink_ext_ack *extack) 454 { 455 struct ksz_device *dev = ds->priv; 456 457 if (flag) { 458 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 459 PORT_VLAN_LOOKUP_VID_0, true); 460 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, true); 461 } else { 462 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, false); 463 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 464 PORT_VLAN_LOOKUP_VID_0, false); 465 } 466 467 return 0; 468 } 469 470 static int ksz9477_port_vlan_add(struct dsa_switch *ds, int port, 471 const struct switchdev_obj_port_vlan *vlan, 472 struct netlink_ext_ack *extack) 473 { 474 struct ksz_device *dev = ds->priv; 475 u32 vlan_table[3]; 476 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 477 int err; 478 479 err = ksz9477_get_vlan_table(dev, vlan->vid, vlan_table); 480 if (err) { 481 NL_SET_ERR_MSG_MOD(extack, "Failed to get vlan table"); 482 return err; 483 } 484 485 vlan_table[0] = VLAN_VALID | (vlan->vid & VLAN_FID_M); 486 if (untagged) 487 vlan_table[1] |= BIT(port); 488 else 489 vlan_table[1] &= ~BIT(port); 490 vlan_table[1] &= ~(BIT(dev->cpu_port)); 491 492 vlan_table[2] |= BIT(port) | BIT(dev->cpu_port); 493 494 err = ksz9477_set_vlan_table(dev, vlan->vid, vlan_table); 495 if (err) { 496 NL_SET_ERR_MSG_MOD(extack, "Failed to set vlan table"); 497 return err; 498 } 499 500 /* change PVID */ 501 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) 502 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, vlan->vid); 503 504 return 0; 505 } 506 507 static int ksz9477_port_vlan_del(struct dsa_switch *ds, int port, 508 const struct switchdev_obj_port_vlan *vlan) 509 { 510 struct ksz_device *dev = ds->priv; 511 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 512 u32 vlan_table[3]; 513 u16 pvid; 514 515 ksz_pread16(dev, port, REG_PORT_DEFAULT_VID, &pvid); 516 pvid = pvid & 0xFFF; 517 518 if (ksz9477_get_vlan_table(dev, vlan->vid, vlan_table)) { 519 dev_dbg(dev->dev, "Failed to get vlan table\n"); 520 return -ETIMEDOUT; 521 } 522 523 vlan_table[2] &= ~BIT(port); 524 525 if (pvid == vlan->vid) 526 pvid = 1; 527 528 if (untagged) 529 vlan_table[1] &= ~BIT(port); 530 531 if (ksz9477_set_vlan_table(dev, vlan->vid, vlan_table)) { 532 dev_dbg(dev->dev, "Failed to set vlan table\n"); 533 return -ETIMEDOUT; 534 } 535 536 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, pvid); 537 538 return 0; 539 } 540 541 static int ksz9477_port_fdb_add(struct dsa_switch *ds, int port, 542 const unsigned char *addr, u16 vid, 543 struct dsa_db db) 544 { 545 struct ksz_device *dev = ds->priv; 546 u32 alu_table[4]; 547 u32 data; 548 int ret = 0; 549 550 mutex_lock(&dev->alu_mutex); 551 552 /* find any entry with mac & vid */ 553 data = vid << ALU_FID_INDEX_S; 554 data |= ((addr[0] << 8) | addr[1]); 555 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 556 557 data = ((addr[2] << 24) | (addr[3] << 16)); 558 data |= ((addr[4] << 8) | addr[5]); 559 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 560 561 /* start read operation */ 562 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 563 564 /* wait to be finished */ 565 ret = ksz9477_wait_alu_ready(dev); 566 if (ret) { 567 dev_dbg(dev->dev, "Failed to read ALU\n"); 568 goto exit; 569 } 570 571 /* read ALU entry */ 572 ksz9477_read_table(dev, alu_table); 573 574 /* update ALU entry */ 575 alu_table[0] = ALU_V_STATIC_VALID; 576 alu_table[1] |= BIT(port); 577 if (vid) 578 alu_table[1] |= ALU_V_USE_FID; 579 alu_table[2] = (vid << ALU_V_FID_S); 580 alu_table[2] |= ((addr[0] << 8) | addr[1]); 581 alu_table[3] = ((addr[2] << 24) | (addr[3] << 16)); 582 alu_table[3] |= ((addr[4] << 8) | addr[5]); 583 584 ksz9477_write_table(dev, alu_table); 585 586 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 587 588 /* wait to be finished */ 589 ret = ksz9477_wait_alu_ready(dev); 590 if (ret) 591 dev_dbg(dev->dev, "Failed to write ALU\n"); 592 593 exit: 594 mutex_unlock(&dev->alu_mutex); 595 596 return ret; 597 } 598 599 static int ksz9477_port_fdb_del(struct dsa_switch *ds, int port, 600 const unsigned char *addr, u16 vid, 601 struct dsa_db db) 602 { 603 struct ksz_device *dev = ds->priv; 604 u32 alu_table[4]; 605 u32 data; 606 int ret = 0; 607 608 mutex_lock(&dev->alu_mutex); 609 610 /* read any entry with mac & vid */ 611 data = vid << ALU_FID_INDEX_S; 612 data |= ((addr[0] << 8) | addr[1]); 613 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 614 615 data = ((addr[2] << 24) | (addr[3] << 16)); 616 data |= ((addr[4] << 8) | addr[5]); 617 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 618 619 /* start read operation */ 620 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 621 622 /* wait to be finished */ 623 ret = ksz9477_wait_alu_ready(dev); 624 if (ret) { 625 dev_dbg(dev->dev, "Failed to read ALU\n"); 626 goto exit; 627 } 628 629 ksz_read32(dev, REG_SW_ALU_VAL_A, &alu_table[0]); 630 if (alu_table[0] & ALU_V_STATIC_VALID) { 631 ksz_read32(dev, REG_SW_ALU_VAL_B, &alu_table[1]); 632 ksz_read32(dev, REG_SW_ALU_VAL_C, &alu_table[2]); 633 ksz_read32(dev, REG_SW_ALU_VAL_D, &alu_table[3]); 634 635 /* clear forwarding port */ 636 alu_table[2] &= ~BIT(port); 637 638 /* if there is no port to forward, clear table */ 639 if ((alu_table[2] & ALU_V_PORT_MAP) == 0) { 640 alu_table[0] = 0; 641 alu_table[1] = 0; 642 alu_table[2] = 0; 643 alu_table[3] = 0; 644 } 645 } else { 646 alu_table[0] = 0; 647 alu_table[1] = 0; 648 alu_table[2] = 0; 649 alu_table[3] = 0; 650 } 651 652 ksz9477_write_table(dev, alu_table); 653 654 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 655 656 /* wait to be finished */ 657 ret = ksz9477_wait_alu_ready(dev); 658 if (ret) 659 dev_dbg(dev->dev, "Failed to write ALU\n"); 660 661 exit: 662 mutex_unlock(&dev->alu_mutex); 663 664 return ret; 665 } 666 667 static void ksz9477_convert_alu(struct alu_struct *alu, u32 *alu_table) 668 { 669 alu->is_static = !!(alu_table[0] & ALU_V_STATIC_VALID); 670 alu->is_src_filter = !!(alu_table[0] & ALU_V_SRC_FILTER); 671 alu->is_dst_filter = !!(alu_table[0] & ALU_V_DST_FILTER); 672 alu->prio_age = (alu_table[0] >> ALU_V_PRIO_AGE_CNT_S) & 673 ALU_V_PRIO_AGE_CNT_M; 674 alu->mstp = alu_table[0] & ALU_V_MSTP_M; 675 676 alu->is_override = !!(alu_table[1] & ALU_V_OVERRIDE); 677 alu->is_use_fid = !!(alu_table[1] & ALU_V_USE_FID); 678 alu->port_forward = alu_table[1] & ALU_V_PORT_MAP; 679 680 alu->fid = (alu_table[2] >> ALU_V_FID_S) & ALU_V_FID_M; 681 682 alu->mac[0] = (alu_table[2] >> 8) & 0xFF; 683 alu->mac[1] = alu_table[2] & 0xFF; 684 alu->mac[2] = (alu_table[3] >> 24) & 0xFF; 685 alu->mac[3] = (alu_table[3] >> 16) & 0xFF; 686 alu->mac[4] = (alu_table[3] >> 8) & 0xFF; 687 alu->mac[5] = alu_table[3] & 0xFF; 688 } 689 690 static int ksz9477_port_fdb_dump(struct dsa_switch *ds, int port, 691 dsa_fdb_dump_cb_t *cb, void *data) 692 { 693 struct ksz_device *dev = ds->priv; 694 int ret = 0; 695 u32 ksz_data; 696 u32 alu_table[4]; 697 struct alu_struct alu; 698 int timeout; 699 700 mutex_lock(&dev->alu_mutex); 701 702 /* start ALU search */ 703 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_START | ALU_SEARCH); 704 705 do { 706 timeout = 1000; 707 do { 708 ksz_read32(dev, REG_SW_ALU_CTRL__4, &ksz_data); 709 if ((ksz_data & ALU_VALID) || !(ksz_data & ALU_START)) 710 break; 711 usleep_range(1, 10); 712 } while (timeout-- > 0); 713 714 if (!timeout) { 715 dev_dbg(dev->dev, "Failed to search ALU\n"); 716 ret = -ETIMEDOUT; 717 goto exit; 718 } 719 720 /* read ALU table */ 721 ksz9477_read_table(dev, alu_table); 722 723 ksz9477_convert_alu(&alu, alu_table); 724 725 if (alu.port_forward & BIT(port)) { 726 ret = cb(alu.mac, alu.fid, alu.is_static, data); 727 if (ret) 728 goto exit; 729 } 730 } while (ksz_data & ALU_START); 731 732 exit: 733 734 /* stop ALU search */ 735 ksz_write32(dev, REG_SW_ALU_CTRL__4, 0); 736 737 mutex_unlock(&dev->alu_mutex); 738 739 return ret; 740 } 741 742 static int ksz9477_port_mdb_add(struct dsa_switch *ds, int port, 743 const struct switchdev_obj_port_mdb *mdb, 744 struct dsa_db db) 745 { 746 struct ksz_device *dev = ds->priv; 747 u32 static_table[4]; 748 u32 data; 749 int index; 750 u32 mac_hi, mac_lo; 751 int err = 0; 752 753 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 754 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 755 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 756 757 mutex_lock(&dev->alu_mutex); 758 759 for (index = 0; index < dev->num_statics; index++) { 760 /* find empty slot first */ 761 data = (index << ALU_STAT_INDEX_S) | 762 ALU_STAT_READ | ALU_STAT_START; 763 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 764 765 /* wait to be finished */ 766 err = ksz9477_wait_alu_sta_ready(dev); 767 if (err) { 768 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 769 goto exit; 770 } 771 772 /* read ALU static table */ 773 ksz9477_read_table(dev, static_table); 774 775 if (static_table[0] & ALU_V_STATIC_VALID) { 776 /* check this has same vid & mac address */ 777 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 778 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 779 static_table[3] == mac_lo) { 780 /* found matching one */ 781 break; 782 } 783 } else { 784 /* found empty one */ 785 break; 786 } 787 } 788 789 /* no available entry */ 790 if (index == dev->num_statics) { 791 err = -ENOSPC; 792 goto exit; 793 } 794 795 /* add entry */ 796 static_table[0] = ALU_V_STATIC_VALID; 797 static_table[1] |= BIT(port); 798 if (mdb->vid) 799 static_table[1] |= ALU_V_USE_FID; 800 static_table[2] = (mdb->vid << ALU_V_FID_S); 801 static_table[2] |= mac_hi; 802 static_table[3] = mac_lo; 803 804 ksz9477_write_table(dev, static_table); 805 806 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START; 807 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 808 809 /* wait to be finished */ 810 if (ksz9477_wait_alu_sta_ready(dev)) 811 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 812 813 exit: 814 mutex_unlock(&dev->alu_mutex); 815 return err; 816 } 817 818 static int ksz9477_port_mdb_del(struct dsa_switch *ds, int port, 819 const struct switchdev_obj_port_mdb *mdb, 820 struct dsa_db db) 821 { 822 struct ksz_device *dev = ds->priv; 823 u32 static_table[4]; 824 u32 data; 825 int index; 826 int ret = 0; 827 u32 mac_hi, mac_lo; 828 829 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 830 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 831 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 832 833 mutex_lock(&dev->alu_mutex); 834 835 for (index = 0; index < dev->num_statics; index++) { 836 /* find empty slot first */ 837 data = (index << ALU_STAT_INDEX_S) | 838 ALU_STAT_READ | ALU_STAT_START; 839 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 840 841 /* wait to be finished */ 842 ret = ksz9477_wait_alu_sta_ready(dev); 843 if (ret) { 844 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 845 goto exit; 846 } 847 848 /* read ALU static table */ 849 ksz9477_read_table(dev, static_table); 850 851 if (static_table[0] & ALU_V_STATIC_VALID) { 852 /* check this has same vid & mac address */ 853 854 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 855 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 856 static_table[3] == mac_lo) { 857 /* found matching one */ 858 break; 859 } 860 } 861 } 862 863 /* no available entry */ 864 if (index == dev->num_statics) 865 goto exit; 866 867 /* clear port */ 868 static_table[1] &= ~BIT(port); 869 870 if ((static_table[1] & ALU_V_PORT_MAP) == 0) { 871 /* delete entry */ 872 static_table[0] = 0; 873 static_table[1] = 0; 874 static_table[2] = 0; 875 static_table[3] = 0; 876 } 877 878 ksz9477_write_table(dev, static_table); 879 880 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START; 881 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 882 883 /* wait to be finished */ 884 ret = ksz9477_wait_alu_sta_ready(dev); 885 if (ret) 886 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 887 888 exit: 889 mutex_unlock(&dev->alu_mutex); 890 891 return ret; 892 } 893 894 static int ksz9477_port_mirror_add(struct dsa_switch *ds, int port, 895 struct dsa_mall_mirror_tc_entry *mirror, 896 bool ingress, struct netlink_ext_ack *extack) 897 { 898 struct ksz_device *dev = ds->priv; 899 u8 data; 900 int p; 901 902 /* Limit to one sniffer port 903 * Check if any of the port is already set for sniffing 904 * If yes, instruct the user to remove the previous entry & exit 905 */ 906 for (p = 0; p < dev->port_cnt; p++) { 907 /* Skip the current sniffing port */ 908 if (p == mirror->to_local_port) 909 continue; 910 911 ksz_pread8(dev, p, P_MIRROR_CTRL, &data); 912 913 if (data & PORT_MIRROR_SNIFFER) { 914 NL_SET_ERR_MSG_MOD(extack, 915 "Sniffer port is already configured, delete existing rules & retry"); 916 return -EBUSY; 917 } 918 } 919 920 if (ingress) 921 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true); 922 else 923 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true); 924 925 /* configure mirror port */ 926 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 927 PORT_MIRROR_SNIFFER, true); 928 929 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false); 930 931 return 0; 932 } 933 934 static void ksz9477_port_mirror_del(struct dsa_switch *ds, int port, 935 struct dsa_mall_mirror_tc_entry *mirror) 936 { 937 struct ksz_device *dev = ds->priv; 938 bool in_use = false; 939 u8 data; 940 int p; 941 942 if (mirror->ingress) 943 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false); 944 else 945 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false); 946 947 948 /* Check if any of the port is still referring to sniffer port */ 949 for (p = 0; p < dev->port_cnt; p++) { 950 ksz_pread8(dev, p, P_MIRROR_CTRL, &data); 951 952 if ((data & (PORT_MIRROR_RX | PORT_MIRROR_TX))) { 953 in_use = true; 954 break; 955 } 956 } 957 958 /* delete sniffing if there are no other mirroring rules */ 959 if (!in_use) 960 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 961 PORT_MIRROR_SNIFFER, false); 962 } 963 964 static bool ksz9477_get_gbit(struct ksz_device *dev, u8 data) 965 { 966 bool gbit; 967 968 if (dev->features & NEW_XMII) 969 gbit = !(data & PORT_MII_NOT_1GBIT); 970 else 971 gbit = !!(data & PORT_MII_1000MBIT_S1); 972 return gbit; 973 } 974 975 static void ksz9477_set_gbit(struct ksz_device *dev, bool gbit, u8 *data) 976 { 977 if (dev->features & NEW_XMII) { 978 if (gbit) 979 *data &= ~PORT_MII_NOT_1GBIT; 980 else 981 *data |= PORT_MII_NOT_1GBIT; 982 } else { 983 if (gbit) 984 *data |= PORT_MII_1000MBIT_S1; 985 else 986 *data &= ~PORT_MII_1000MBIT_S1; 987 } 988 } 989 990 static int ksz9477_get_xmii(struct ksz_device *dev, u8 data) 991 { 992 int mode; 993 994 if (dev->features & NEW_XMII) { 995 switch (data & PORT_MII_SEL_M) { 996 case PORT_MII_SEL: 997 mode = 0; 998 break; 999 case PORT_RMII_SEL: 1000 mode = 1; 1001 break; 1002 case PORT_GMII_SEL: 1003 mode = 2; 1004 break; 1005 default: 1006 mode = 3; 1007 } 1008 } else { 1009 switch (data & PORT_MII_SEL_M) { 1010 case PORT_MII_SEL_S1: 1011 mode = 0; 1012 break; 1013 case PORT_RMII_SEL_S1: 1014 mode = 1; 1015 break; 1016 case PORT_GMII_SEL_S1: 1017 mode = 2; 1018 break; 1019 default: 1020 mode = 3; 1021 } 1022 } 1023 return mode; 1024 } 1025 1026 static void ksz9477_set_xmii(struct ksz_device *dev, int mode, u8 *data) 1027 { 1028 u8 xmii; 1029 1030 if (dev->features & NEW_XMII) { 1031 switch (mode) { 1032 case 0: 1033 xmii = PORT_MII_SEL; 1034 break; 1035 case 1: 1036 xmii = PORT_RMII_SEL; 1037 break; 1038 case 2: 1039 xmii = PORT_GMII_SEL; 1040 break; 1041 default: 1042 xmii = PORT_RGMII_SEL; 1043 break; 1044 } 1045 } else { 1046 switch (mode) { 1047 case 0: 1048 xmii = PORT_MII_SEL_S1; 1049 break; 1050 case 1: 1051 xmii = PORT_RMII_SEL_S1; 1052 break; 1053 case 2: 1054 xmii = PORT_GMII_SEL_S1; 1055 break; 1056 default: 1057 xmii = PORT_RGMII_SEL_S1; 1058 break; 1059 } 1060 } 1061 *data &= ~PORT_MII_SEL_M; 1062 *data |= xmii; 1063 } 1064 1065 static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port) 1066 { 1067 phy_interface_t interface; 1068 bool gbit; 1069 int mode; 1070 u8 data8; 1071 1072 if (port < dev->phy_port_cnt) 1073 return PHY_INTERFACE_MODE_NA; 1074 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8); 1075 gbit = ksz9477_get_gbit(dev, data8); 1076 mode = ksz9477_get_xmii(dev, data8); 1077 switch (mode) { 1078 case 2: 1079 interface = PHY_INTERFACE_MODE_GMII; 1080 if (gbit) 1081 break; 1082 fallthrough; 1083 case 0: 1084 interface = PHY_INTERFACE_MODE_MII; 1085 break; 1086 case 1: 1087 interface = PHY_INTERFACE_MODE_RMII; 1088 break; 1089 default: 1090 interface = PHY_INTERFACE_MODE_RGMII; 1091 if (data8 & PORT_RGMII_ID_EG_ENABLE) 1092 interface = PHY_INTERFACE_MODE_RGMII_TXID; 1093 if (data8 & PORT_RGMII_ID_IG_ENABLE) { 1094 interface = PHY_INTERFACE_MODE_RGMII_RXID; 1095 if (data8 & PORT_RGMII_ID_EG_ENABLE) 1096 interface = PHY_INTERFACE_MODE_RGMII_ID; 1097 } 1098 break; 1099 } 1100 return interface; 1101 } 1102 1103 static void ksz9477_port_mmd_write(struct ksz_device *dev, int port, 1104 u8 dev_addr, u16 reg_addr, u16 val) 1105 { 1106 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, 1107 MMD_SETUP(PORT_MMD_OP_INDEX, dev_addr)); 1108 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, reg_addr); 1109 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, 1110 MMD_SETUP(PORT_MMD_OP_DATA_NO_INCR, dev_addr)); 1111 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, val); 1112 } 1113 1114 static void ksz9477_phy_errata_setup(struct ksz_device *dev, int port) 1115 { 1116 /* Apply PHY settings to address errata listed in 1117 * KSZ9477, KSZ9897, KSZ9896, KSZ9567, KSZ8565 1118 * Silicon Errata and Data Sheet Clarification documents: 1119 * 1120 * Register settings are needed to improve PHY receive performance 1121 */ 1122 ksz9477_port_mmd_write(dev, port, 0x01, 0x6f, 0xdd0b); 1123 ksz9477_port_mmd_write(dev, port, 0x01, 0x8f, 0x6032); 1124 ksz9477_port_mmd_write(dev, port, 0x01, 0x9d, 0x248c); 1125 ksz9477_port_mmd_write(dev, port, 0x01, 0x75, 0x0060); 1126 ksz9477_port_mmd_write(dev, port, 0x01, 0xd3, 0x7777); 1127 ksz9477_port_mmd_write(dev, port, 0x1c, 0x06, 0x3008); 1128 ksz9477_port_mmd_write(dev, port, 0x1c, 0x08, 0x2001); 1129 1130 /* Transmit waveform amplitude can be improved 1131 * (1000BASE-T, 100BASE-TX, 10BASE-Te) 1132 */ 1133 ksz9477_port_mmd_write(dev, port, 0x1c, 0x04, 0x00d0); 1134 1135 /* Energy Efficient Ethernet (EEE) feature select must 1136 * be manually disabled (except on KSZ8565 which is 100Mbit) 1137 */ 1138 if (dev->features & GBIT_SUPPORT) 1139 ksz9477_port_mmd_write(dev, port, 0x07, 0x3c, 0x0000); 1140 1141 /* Register settings are required to meet data sheet 1142 * supply current specifications 1143 */ 1144 ksz9477_port_mmd_write(dev, port, 0x1c, 0x13, 0x6eff); 1145 ksz9477_port_mmd_write(dev, port, 0x1c, 0x14, 0xe6ff); 1146 ksz9477_port_mmd_write(dev, port, 0x1c, 0x15, 0x6eff); 1147 ksz9477_port_mmd_write(dev, port, 0x1c, 0x16, 0xe6ff); 1148 ksz9477_port_mmd_write(dev, port, 0x1c, 0x17, 0x00ff); 1149 ksz9477_port_mmd_write(dev, port, 0x1c, 0x18, 0x43ff); 1150 ksz9477_port_mmd_write(dev, port, 0x1c, 0x19, 0xc3ff); 1151 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1a, 0x6fff); 1152 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1b, 0x07ff); 1153 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1c, 0x0fff); 1154 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1d, 0xe7ff); 1155 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1e, 0xefff); 1156 ksz9477_port_mmd_write(dev, port, 0x1c, 0x20, 0xeeee); 1157 } 1158 1159 static void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port) 1160 { 1161 struct ksz_port *p = &dev->ports[port]; 1162 struct dsa_switch *ds = dev->ds; 1163 u8 data8, member; 1164 u16 data16; 1165 1166 /* enable tag tail for host port */ 1167 if (cpu_port) 1168 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_TAIL_TAG_ENABLE, 1169 true); 1170 1171 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_MAC_LOOPBACK, false); 1172 1173 /* set back pressure */ 1174 ksz_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, true); 1175 1176 /* enable broadcast storm limit */ 1177 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true); 1178 1179 /* disable DiffServ priority */ 1180 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_PRIO_ENABLE, false); 1181 1182 /* replace priority */ 1183 ksz_port_cfg(dev, port, REG_PORT_MRI_MAC_CTRL, PORT_USER_PRIO_CEILING, 1184 false); 1185 ksz9477_port_cfg32(dev, port, REG_PORT_MTI_QUEUE_CTRL_0__4, 1186 MTI_PVID_REPLACE, false); 1187 1188 /* enable 802.1p priority */ 1189 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true); 1190 1191 if (port < dev->phy_port_cnt) { 1192 /* do not force flow control */ 1193 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, 1194 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, 1195 false); 1196 1197 if (dev->phy_errata_9477) 1198 ksz9477_phy_errata_setup(dev, port); 1199 } else { 1200 /* force flow control */ 1201 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, 1202 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, 1203 true); 1204 1205 /* configure MAC to 1G & RGMII mode */ 1206 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8); 1207 switch (p->interface) { 1208 case PHY_INTERFACE_MODE_MII: 1209 ksz9477_set_xmii(dev, 0, &data8); 1210 ksz9477_set_gbit(dev, false, &data8); 1211 p->phydev.speed = SPEED_100; 1212 break; 1213 case PHY_INTERFACE_MODE_RMII: 1214 ksz9477_set_xmii(dev, 1, &data8); 1215 ksz9477_set_gbit(dev, false, &data8); 1216 p->phydev.speed = SPEED_100; 1217 break; 1218 case PHY_INTERFACE_MODE_GMII: 1219 ksz9477_set_xmii(dev, 2, &data8); 1220 ksz9477_set_gbit(dev, true, &data8); 1221 p->phydev.speed = SPEED_1000; 1222 break; 1223 default: 1224 ksz9477_set_xmii(dev, 3, &data8); 1225 ksz9477_set_gbit(dev, true, &data8); 1226 data8 &= ~PORT_RGMII_ID_IG_ENABLE; 1227 data8 &= ~PORT_RGMII_ID_EG_ENABLE; 1228 if (p->interface == PHY_INTERFACE_MODE_RGMII_ID || 1229 p->interface == PHY_INTERFACE_MODE_RGMII_RXID) 1230 data8 |= PORT_RGMII_ID_IG_ENABLE; 1231 if (p->interface == PHY_INTERFACE_MODE_RGMII_ID || 1232 p->interface == PHY_INTERFACE_MODE_RGMII_TXID) 1233 data8 |= PORT_RGMII_ID_EG_ENABLE; 1234 /* On KSZ9893, disable RGMII in-band status support */ 1235 if (dev->features & IS_9893) 1236 data8 &= ~PORT_MII_MAC_MODE; 1237 p->phydev.speed = SPEED_1000; 1238 break; 1239 } 1240 ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, data8); 1241 p->phydev.duplex = 1; 1242 } 1243 1244 if (cpu_port) 1245 member = dsa_user_ports(ds); 1246 else 1247 member = BIT(dsa_upstream_port(ds, port)); 1248 1249 ksz9477_cfg_port_member(dev, port, member); 1250 1251 /* clear pending interrupts */ 1252 if (port < dev->phy_port_cnt) 1253 ksz_pread16(dev, port, REG_PORT_PHY_INT_ENABLE, &data16); 1254 } 1255 1256 static void ksz9477_config_cpu_port(struct dsa_switch *ds) 1257 { 1258 struct ksz_device *dev = ds->priv; 1259 struct ksz_port *p; 1260 int i; 1261 1262 for (i = 0; i < dev->port_cnt; i++) { 1263 if (dsa_is_cpu_port(ds, i) && (dev->cpu_ports & (1 << i))) { 1264 phy_interface_t interface; 1265 const char *prev_msg; 1266 const char *prev_mode; 1267 1268 dev->cpu_port = i; 1269 p = &dev->ports[i]; 1270 1271 /* Read from XMII register to determine host port 1272 * interface. If set specifically in device tree 1273 * note the difference to help debugging. 1274 */ 1275 interface = ksz9477_get_interface(dev, i); 1276 if (!p->interface) { 1277 if (dev->compat_interface) { 1278 dev_warn(dev->dev, 1279 "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. " 1280 "Please update your device tree.\n", 1281 i); 1282 p->interface = dev->compat_interface; 1283 } else { 1284 p->interface = interface; 1285 } 1286 } 1287 if (interface && interface != p->interface) { 1288 prev_msg = " instead of "; 1289 prev_mode = phy_modes(interface); 1290 } else { 1291 prev_msg = ""; 1292 prev_mode = ""; 1293 } 1294 dev_info(dev->dev, 1295 "Port%d: using phy mode %s%s%s\n", 1296 i, 1297 phy_modes(p->interface), 1298 prev_msg, 1299 prev_mode); 1300 1301 /* enable cpu port */ 1302 ksz9477_port_setup(dev, i, true); 1303 p->on = 1; 1304 } 1305 } 1306 1307 for (i = 0; i < dev->port_cnt; i++) { 1308 if (i == dev->cpu_port) 1309 continue; 1310 p = &dev->ports[i]; 1311 1312 ksz9477_port_stp_state_set(ds, i, BR_STATE_DISABLED); 1313 p->on = 1; 1314 if (i < dev->phy_port_cnt) 1315 p->phy = 1; 1316 if (dev->chip_id == 0x00947700 && i == 6) { 1317 p->sgmii = 1; 1318 1319 /* SGMII PHY detection code is not implemented yet. */ 1320 p->phy = 0; 1321 } 1322 } 1323 } 1324 1325 static int ksz9477_setup(struct dsa_switch *ds) 1326 { 1327 struct ksz_device *dev = ds->priv; 1328 int ret = 0; 1329 1330 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 1331 dev->num_vlans, GFP_KERNEL); 1332 if (!dev->vlan_cache) 1333 return -ENOMEM; 1334 1335 ret = ksz9477_reset_switch(dev); 1336 if (ret) { 1337 dev_err(ds->dev, "failed to reset switch\n"); 1338 return ret; 1339 } 1340 1341 /* Required for port partitioning. */ 1342 ksz9477_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY, 1343 true); 1344 1345 /* Do not work correctly with tail tagging. */ 1346 ksz_cfg(dev, REG_SW_MAC_CTRL_0, SW_CHECK_LENGTH, false); 1347 1348 /* Enable REG_SW_MTU__2 reg by setting SW_JUMBO_PACKET */ 1349 ksz_cfg(dev, REG_SW_MAC_CTRL_1, SW_JUMBO_PACKET, true); 1350 1351 /* Now we can configure default MTU value */ 1352 ret = regmap_update_bits(dev->regmap[1], REG_SW_MTU__2, REG_SW_MTU_MASK, 1353 VLAN_ETH_FRAME_LEN + ETH_FCS_LEN); 1354 if (ret) 1355 return ret; 1356 1357 ksz9477_config_cpu_port(ds); 1358 1359 ksz_cfg(dev, REG_SW_MAC_CTRL_1, MULTICAST_STORM_DISABLE, true); 1360 1361 /* queue based egress rate limit */ 1362 ksz_cfg(dev, REG_SW_MAC_CTRL_5, SW_OUT_RATE_LIMIT_QUEUE_BASED, true); 1363 1364 /* enable global MIB counter freeze function */ 1365 ksz_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true); 1366 1367 /* start switch */ 1368 ksz_cfg(dev, REG_SW_OPERATION, SW_START, true); 1369 1370 ksz_init_mib_timer(dev); 1371 1372 ds->configure_vlan_while_not_filtering = false; 1373 1374 return 0; 1375 } 1376 1377 static const struct dsa_switch_ops ksz9477_switch_ops = { 1378 .get_tag_protocol = ksz9477_get_tag_protocol, 1379 .setup = ksz9477_setup, 1380 .phy_read = ksz9477_phy_read16, 1381 .phy_write = ksz9477_phy_write16, 1382 .phylink_mac_link_down = ksz_mac_link_down, 1383 .port_enable = ksz_enable_port, 1384 .get_strings = ksz9477_get_strings, 1385 .get_ethtool_stats = ksz_get_ethtool_stats, 1386 .get_sset_count = ksz_sset_count, 1387 .port_bridge_join = ksz_port_bridge_join, 1388 .port_bridge_leave = ksz_port_bridge_leave, 1389 .port_stp_state_set = ksz9477_port_stp_state_set, 1390 .port_fast_age = ksz_port_fast_age, 1391 .port_vlan_filtering = ksz9477_port_vlan_filtering, 1392 .port_vlan_add = ksz9477_port_vlan_add, 1393 .port_vlan_del = ksz9477_port_vlan_del, 1394 .port_fdb_dump = ksz9477_port_fdb_dump, 1395 .port_fdb_add = ksz9477_port_fdb_add, 1396 .port_fdb_del = ksz9477_port_fdb_del, 1397 .port_mdb_add = ksz9477_port_mdb_add, 1398 .port_mdb_del = ksz9477_port_mdb_del, 1399 .port_mirror_add = ksz9477_port_mirror_add, 1400 .port_mirror_del = ksz9477_port_mirror_del, 1401 .get_stats64 = ksz_get_stats64, 1402 .port_change_mtu = ksz9477_change_mtu, 1403 .port_max_mtu = ksz9477_max_mtu, 1404 }; 1405 1406 static u32 ksz9477_get_port_addr(int port, int offset) 1407 { 1408 return PORT_CTRL_ADDR(port, offset); 1409 } 1410 1411 static int ksz9477_switch_detect(struct ksz_device *dev) 1412 { 1413 u8 data8; 1414 u8 id_hi; 1415 u8 id_lo; 1416 u32 id32; 1417 int ret; 1418 1419 /* turn off SPI DO Edge select */ 1420 ret = ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8); 1421 if (ret) 1422 return ret; 1423 1424 data8 &= ~SPI_AUTO_EDGE_DETECTION; 1425 ret = ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8); 1426 if (ret) 1427 return ret; 1428 1429 /* read chip id */ 1430 ret = ksz_read32(dev, REG_CHIP_ID0__1, &id32); 1431 if (ret) 1432 return ret; 1433 ret = ksz_read8(dev, REG_GLOBAL_OPTIONS, &data8); 1434 if (ret) 1435 return ret; 1436 1437 /* Number of ports can be reduced depending on chip. */ 1438 dev->phy_port_cnt = 5; 1439 1440 /* Default capability is gigabit capable. */ 1441 dev->features = GBIT_SUPPORT; 1442 1443 dev_dbg(dev->dev, "Switch detect: ID=%08x%02x\n", id32, data8); 1444 id_hi = (u8)(id32 >> 16); 1445 id_lo = (u8)(id32 >> 8); 1446 if ((id_lo & 0xf) == 3) { 1447 /* Chip is from KSZ9893 design. */ 1448 dev_info(dev->dev, "Found KSZ9893\n"); 1449 dev->features |= IS_9893; 1450 1451 /* Chip does not support gigabit. */ 1452 if (data8 & SW_QW_ABLE) 1453 dev->features &= ~GBIT_SUPPORT; 1454 dev->phy_port_cnt = 2; 1455 } else { 1456 dev_info(dev->dev, "Found KSZ9477 or compatible\n"); 1457 /* Chip uses new XMII register definitions. */ 1458 dev->features |= NEW_XMII; 1459 1460 /* Chip does not support gigabit. */ 1461 if (!(data8 & SW_GIGABIT_ABLE)) 1462 dev->features &= ~GBIT_SUPPORT; 1463 } 1464 1465 /* Change chip id to known ones so it can be matched against them. */ 1466 id32 = (id_hi << 16) | (id_lo << 8); 1467 1468 dev->chip_id = id32; 1469 1470 return 0; 1471 } 1472 1473 struct ksz_chip_data { 1474 u32 chip_id; 1475 const char *dev_name; 1476 int num_vlans; 1477 int num_alus; 1478 int num_statics; 1479 int cpu_ports; 1480 int port_cnt; 1481 bool phy_errata_9477; 1482 }; 1483 1484 static const struct ksz_chip_data ksz9477_switch_chips[] = { 1485 { 1486 .chip_id = 0x00947700, 1487 .dev_name = "KSZ9477", 1488 .num_vlans = 4096, 1489 .num_alus = 4096, 1490 .num_statics = 16, 1491 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1492 .port_cnt = 7, /* total physical port count */ 1493 .phy_errata_9477 = true, 1494 }, 1495 { 1496 .chip_id = 0x00989700, 1497 .dev_name = "KSZ9897", 1498 .num_vlans = 4096, 1499 .num_alus = 4096, 1500 .num_statics = 16, 1501 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1502 .port_cnt = 7, /* total physical port count */ 1503 .phy_errata_9477 = true, 1504 }, 1505 { 1506 .chip_id = 0x00989300, 1507 .dev_name = "KSZ9893", 1508 .num_vlans = 4096, 1509 .num_alus = 4096, 1510 .num_statics = 16, 1511 .cpu_ports = 0x07, /* can be configured as cpu port */ 1512 .port_cnt = 3, /* total port count */ 1513 }, 1514 { 1515 .chip_id = 0x00956700, 1516 .dev_name = "KSZ9567", 1517 .num_vlans = 4096, 1518 .num_alus = 4096, 1519 .num_statics = 16, 1520 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1521 .port_cnt = 7, /* total physical port count */ 1522 .phy_errata_9477 = true, 1523 }, 1524 }; 1525 1526 static int ksz9477_switch_init(struct ksz_device *dev) 1527 { 1528 int i; 1529 1530 dev->ds->ops = &ksz9477_switch_ops; 1531 1532 for (i = 0; i < ARRAY_SIZE(ksz9477_switch_chips); i++) { 1533 const struct ksz_chip_data *chip = &ksz9477_switch_chips[i]; 1534 1535 if (dev->chip_id == chip->chip_id) { 1536 dev->name = chip->dev_name; 1537 dev->num_vlans = chip->num_vlans; 1538 dev->num_alus = chip->num_alus; 1539 dev->num_statics = chip->num_statics; 1540 dev->port_cnt = chip->port_cnt; 1541 dev->cpu_ports = chip->cpu_ports; 1542 dev->phy_errata_9477 = chip->phy_errata_9477; 1543 1544 break; 1545 } 1546 } 1547 1548 /* no switch found */ 1549 if (!dev->port_cnt) 1550 return -ENODEV; 1551 1552 dev->port_mask = (1 << dev->port_cnt) - 1; 1553 1554 dev->reg_mib_cnt = SWITCH_COUNTER_NUM; 1555 dev->mib_cnt = TOTAL_SWITCH_COUNTER_NUM; 1556 1557 dev->ports = devm_kzalloc(dev->dev, 1558 dev->port_cnt * sizeof(struct ksz_port), 1559 GFP_KERNEL); 1560 if (!dev->ports) 1561 return -ENOMEM; 1562 for (i = 0; i < dev->port_cnt; i++) { 1563 spin_lock_init(&dev->ports[i].mib.stats64_lock); 1564 mutex_init(&dev->ports[i].mib.cnt_mutex); 1565 dev->ports[i].mib.counters = 1566 devm_kzalloc(dev->dev, 1567 sizeof(u64) * 1568 (TOTAL_SWITCH_COUNTER_NUM + 1), 1569 GFP_KERNEL); 1570 if (!dev->ports[i].mib.counters) 1571 return -ENOMEM; 1572 } 1573 1574 /* set the real number of ports */ 1575 dev->ds->num_ports = dev->port_cnt; 1576 1577 return 0; 1578 } 1579 1580 static void ksz9477_switch_exit(struct ksz_device *dev) 1581 { 1582 ksz9477_reset_switch(dev); 1583 } 1584 1585 static const struct ksz_dev_ops ksz9477_dev_ops = { 1586 .get_port_addr = ksz9477_get_port_addr, 1587 .cfg_port_member = ksz9477_cfg_port_member, 1588 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 1589 .port_setup = ksz9477_port_setup, 1590 .r_mib_cnt = ksz9477_r_mib_cnt, 1591 .r_mib_pkt = ksz9477_r_mib_pkt, 1592 .r_mib_stat64 = ksz_r_mib_stats64, 1593 .freeze_mib = ksz9477_freeze_mib, 1594 .port_init_cnt = ksz9477_port_init_cnt, 1595 .shutdown = ksz9477_reset_switch, 1596 .detect = ksz9477_switch_detect, 1597 .init = ksz9477_switch_init, 1598 .exit = ksz9477_switch_exit, 1599 }; 1600 1601 int ksz9477_switch_register(struct ksz_device *dev) 1602 { 1603 int ret, i; 1604 struct phy_device *phydev; 1605 1606 ret = ksz_switch_register(dev, &ksz9477_dev_ops); 1607 if (ret) 1608 return ret; 1609 1610 for (i = 0; i < dev->phy_port_cnt; ++i) { 1611 if (!dsa_is_user_port(dev->ds, i)) 1612 continue; 1613 1614 phydev = dsa_to_port(dev->ds, i)->slave->phydev; 1615 1616 /* The MAC actually cannot run in 1000 half-duplex mode. */ 1617 phy_remove_link_mode(phydev, 1618 ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1619 1620 /* PHY does not support gigabit. */ 1621 if (!(dev->features & GBIT_SUPPORT)) 1622 phy_remove_link_mode(phydev, 1623 ETHTOOL_LINK_MODE_1000baseT_Full_BIT); 1624 } 1625 return ret; 1626 } 1627 EXPORT_SYMBOL(ksz9477_switch_register); 1628 1629 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 1630 MODULE_DESCRIPTION("Microchip KSZ9477 Series Switch DSA Driver"); 1631 MODULE_LICENSE("GPL"); 1632