1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip KSZ9477 switch driver main logic 4 * 5 * Copyright (C) 2017-2019 Microchip Technology Inc. 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/iopoll.h> 11 #include <linux/platform_data/microchip-ksz.h> 12 #include <linux/phy.h> 13 #include <linux/if_bridge.h> 14 #include <linux/if_vlan.h> 15 #include <net/dsa.h> 16 #include <net/switchdev.h> 17 18 #include "ksz9477_reg.h" 19 #include "ksz_common.h" 20 #include "ksz9477.h" 21 22 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) 23 { 24 regmap_update_bits(ksz_regmap_8(dev), addr, bits, set ? bits : 0); 25 } 26 27 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits, 28 bool set) 29 { 30 regmap_update_bits(ksz_regmap_8(dev), PORT_CTRL_ADDR(port, offset), 31 bits, set ? bits : 0); 32 } 33 34 static void ksz9477_cfg32(struct ksz_device *dev, u32 addr, u32 bits, bool set) 35 { 36 regmap_update_bits(ksz_regmap_32(dev), addr, bits, set ? bits : 0); 37 } 38 39 static void ksz9477_port_cfg32(struct ksz_device *dev, int port, int offset, 40 u32 bits, bool set) 41 { 42 regmap_update_bits(ksz_regmap_32(dev), PORT_CTRL_ADDR(port, offset), 43 bits, set ? bits : 0); 44 } 45 46 int ksz9477_change_mtu(struct ksz_device *dev, int port, int mtu) 47 { 48 u16 frame_size; 49 50 if (!dsa_is_cpu_port(dev->ds, port)) 51 return 0; 52 53 frame_size = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 54 55 return regmap_update_bits(ksz_regmap_16(dev), REG_SW_MTU__2, 56 REG_SW_MTU_MASK, frame_size); 57 } 58 59 /** 60 * ksz9477_handle_wake_reason - Handle wake reason on a specified port. 61 * @dev: The device structure. 62 * @port: The port number. 63 * 64 * This function reads the PME (Power Management Event) status register of a 65 * specified port to determine the wake reason. If there is no wake event, it 66 * returns early. Otherwise, it logs the wake reason which could be due to a 67 * "Magic Packet", "Link Up", or "Energy Detect" event. The PME status register 68 * is then cleared to acknowledge the handling of the wake event. 69 * 70 * Return: 0 on success, or an error code on failure. 71 */ 72 static int ksz9477_handle_wake_reason(struct ksz_device *dev, int port) 73 { 74 u8 pme_status; 75 int ret; 76 77 ret = ksz_pread8(dev, port, REG_PORT_PME_STATUS, &pme_status); 78 if (ret) 79 return ret; 80 81 if (!pme_status) 82 return 0; 83 84 dev_dbg(dev->dev, "Wake event on port %d due to:%s%s%s\n", port, 85 pme_status & PME_WOL_MAGICPKT ? " \"Magic Packet\"" : "", 86 pme_status & PME_WOL_LINKUP ? " \"Link Up\"" : "", 87 pme_status & PME_WOL_ENERGY ? " \"Energy detect\"" : ""); 88 89 return ksz_pwrite8(dev, port, REG_PORT_PME_STATUS, pme_status); 90 } 91 92 /** 93 * ksz9477_get_wol - Get Wake-on-LAN settings for a specified port. 94 * @dev: The device structure. 95 * @port: The port number. 96 * @wol: Pointer to ethtool Wake-on-LAN settings structure. 97 * 98 * This function checks the PME Pin Control Register to see if PME Pin Output 99 * Enable is set, indicating PME is enabled. If enabled, it sets the supported 100 * and active WoL flags. 101 */ 102 void ksz9477_get_wol(struct ksz_device *dev, int port, 103 struct ethtool_wolinfo *wol) 104 { 105 u8 pme_ctrl; 106 int ret; 107 108 if (!dev->wakeup_source) 109 return; 110 111 wol->supported = WAKE_PHY; 112 113 /* Check if the current MAC address on this port can be set 114 * as global for WAKE_MAGIC support. The result may vary 115 * dynamically based on other ports configurations. 116 */ 117 if (ksz_is_port_mac_global_usable(dev->ds, port)) 118 wol->supported |= WAKE_MAGIC; 119 120 ret = ksz_pread8(dev, port, REG_PORT_PME_CTRL, &pme_ctrl); 121 if (ret) 122 return; 123 124 if (pme_ctrl & PME_WOL_MAGICPKT) 125 wol->wolopts |= WAKE_MAGIC; 126 if (pme_ctrl & (PME_WOL_LINKUP | PME_WOL_ENERGY)) 127 wol->wolopts |= WAKE_PHY; 128 } 129 130 /** 131 * ksz9477_set_wol - Set Wake-on-LAN settings for a specified port. 132 * @dev: The device structure. 133 * @port: The port number. 134 * @wol: Pointer to ethtool Wake-on-LAN settings structure. 135 * 136 * This function configures Wake-on-LAN (WoL) settings for a specified port. 137 * It validates the provided WoL options, checks if PME is enabled via the 138 * switch's PME Pin Control Register, clears any previous wake reasons, 139 * and sets the Magic Packet flag in the port's PME control register if 140 * specified. 141 * 142 * Return: 0 on success, or other error codes on failure. 143 */ 144 int ksz9477_set_wol(struct ksz_device *dev, int port, 145 struct ethtool_wolinfo *wol) 146 { 147 u8 pme_ctrl = 0, pme_ctrl_old = 0; 148 bool magic_switched_off; 149 bool magic_switched_on; 150 int ret; 151 152 if (wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC)) 153 return -EINVAL; 154 155 if (!dev->wakeup_source) 156 return -EOPNOTSUPP; 157 158 ret = ksz9477_handle_wake_reason(dev, port); 159 if (ret) 160 return ret; 161 162 if (wol->wolopts & WAKE_MAGIC) 163 pme_ctrl |= PME_WOL_MAGICPKT; 164 if (wol->wolopts & WAKE_PHY) 165 pme_ctrl |= PME_WOL_LINKUP | PME_WOL_ENERGY; 166 167 ret = ksz_pread8(dev, port, REG_PORT_PME_CTRL, &pme_ctrl_old); 168 if (ret) 169 return ret; 170 171 if (pme_ctrl_old == pme_ctrl) 172 return 0; 173 174 magic_switched_off = (pme_ctrl_old & PME_WOL_MAGICPKT) && 175 !(pme_ctrl & PME_WOL_MAGICPKT); 176 magic_switched_on = !(pme_ctrl_old & PME_WOL_MAGICPKT) && 177 (pme_ctrl & PME_WOL_MAGICPKT); 178 179 /* To keep reference count of MAC address, we should do this 180 * operation only on change of WOL settings. 181 */ 182 if (magic_switched_on) { 183 ret = ksz_switch_macaddr_get(dev->ds, port, NULL); 184 if (ret) 185 return ret; 186 } else if (magic_switched_off) { 187 ksz_switch_macaddr_put(dev->ds); 188 } 189 190 ret = ksz_pwrite8(dev, port, REG_PORT_PME_CTRL, pme_ctrl); 191 if (ret) { 192 if (magic_switched_on) 193 ksz_switch_macaddr_put(dev->ds); 194 return ret; 195 } 196 197 return 0; 198 } 199 200 /** 201 * ksz9477_wol_pre_shutdown - Prepares the switch device for shutdown while 202 * considering Wake-on-LAN (WoL) settings. 203 * @dev: The switch device structure. 204 * @wol_enabled: Pointer to a boolean which will be set to true if WoL is 205 * enabled on any port. 206 * 207 * This function prepares the switch device for a safe shutdown while taking 208 * into account the Wake-on-LAN (WoL) settings on the user ports. It updates 209 * the wol_enabled flag accordingly to reflect whether WoL is active on any 210 * port. 211 */ 212 void ksz9477_wol_pre_shutdown(struct ksz_device *dev, bool *wol_enabled) 213 { 214 struct dsa_port *dp; 215 int ret; 216 217 *wol_enabled = false; 218 219 if (!dev->wakeup_source) 220 return; 221 222 dsa_switch_for_each_user_port(dp, dev->ds) { 223 u8 pme_ctrl = 0; 224 225 ret = ksz_pread8(dev, dp->index, REG_PORT_PME_CTRL, &pme_ctrl); 226 if (!ret && pme_ctrl) 227 *wol_enabled = true; 228 229 /* make sure there are no pending wake events which would 230 * prevent the device from going to sleep/shutdown. 231 */ 232 ksz9477_handle_wake_reason(dev, dp->index); 233 } 234 235 /* Now we are save to enable PME pin. */ 236 if (*wol_enabled) 237 ksz_write8(dev, REG_SW_PME_CTRL, PME_ENABLE); 238 } 239 240 static int ksz9477_wait_vlan_ctrl_ready(struct ksz_device *dev) 241 { 242 unsigned int val; 243 244 return regmap_read_poll_timeout(ksz_regmap_8(dev), REG_SW_VLAN_CTRL, 245 val, !(val & VLAN_START), 10, 1000); 246 } 247 248 static int ksz9477_get_vlan_table(struct ksz_device *dev, u16 vid, 249 u32 *vlan_table) 250 { 251 int ret; 252 253 mutex_lock(&dev->vlan_mutex); 254 255 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 256 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_READ | VLAN_START); 257 258 /* wait to be cleared */ 259 ret = ksz9477_wait_vlan_ctrl_ready(dev); 260 if (ret) { 261 dev_dbg(dev->dev, "Failed to read vlan table\n"); 262 goto exit; 263 } 264 265 ksz_read32(dev, REG_SW_VLAN_ENTRY__4, &vlan_table[0]); 266 ksz_read32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, &vlan_table[1]); 267 ksz_read32(dev, REG_SW_VLAN_ENTRY_PORTS__4, &vlan_table[2]); 268 269 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 270 271 exit: 272 mutex_unlock(&dev->vlan_mutex); 273 274 return ret; 275 } 276 277 static int ksz9477_set_vlan_table(struct ksz_device *dev, u16 vid, 278 u32 *vlan_table) 279 { 280 int ret; 281 282 mutex_lock(&dev->vlan_mutex); 283 284 ksz_write32(dev, REG_SW_VLAN_ENTRY__4, vlan_table[0]); 285 ksz_write32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, vlan_table[1]); 286 ksz_write32(dev, REG_SW_VLAN_ENTRY_PORTS__4, vlan_table[2]); 287 288 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 289 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_START | VLAN_WRITE); 290 291 /* wait to be cleared */ 292 ret = ksz9477_wait_vlan_ctrl_ready(dev); 293 if (ret) { 294 dev_dbg(dev->dev, "Failed to write vlan table\n"); 295 goto exit; 296 } 297 298 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 299 300 /* update vlan cache table */ 301 dev->vlan_cache[vid].table[0] = vlan_table[0]; 302 dev->vlan_cache[vid].table[1] = vlan_table[1]; 303 dev->vlan_cache[vid].table[2] = vlan_table[2]; 304 305 exit: 306 mutex_unlock(&dev->vlan_mutex); 307 308 return ret; 309 } 310 311 static void ksz9477_read_table(struct ksz_device *dev, u32 *table) 312 { 313 ksz_read32(dev, REG_SW_ALU_VAL_A, &table[0]); 314 ksz_read32(dev, REG_SW_ALU_VAL_B, &table[1]); 315 ksz_read32(dev, REG_SW_ALU_VAL_C, &table[2]); 316 ksz_read32(dev, REG_SW_ALU_VAL_D, &table[3]); 317 } 318 319 static void ksz9477_write_table(struct ksz_device *dev, u32 *table) 320 { 321 ksz_write32(dev, REG_SW_ALU_VAL_A, table[0]); 322 ksz_write32(dev, REG_SW_ALU_VAL_B, table[1]); 323 ksz_write32(dev, REG_SW_ALU_VAL_C, table[2]); 324 ksz_write32(dev, REG_SW_ALU_VAL_D, table[3]); 325 } 326 327 static int ksz9477_wait_alu_ready(struct ksz_device *dev) 328 { 329 unsigned int val; 330 331 return regmap_read_poll_timeout(ksz_regmap_32(dev), REG_SW_ALU_CTRL__4, 332 val, !(val & ALU_START), 10, 1000); 333 } 334 335 static int ksz9477_wait_alu_sta_ready(struct ksz_device *dev) 336 { 337 unsigned int val; 338 339 return regmap_read_poll_timeout(ksz_regmap_32(dev), 340 REG_SW_ALU_STAT_CTRL__4, 341 val, !(val & ALU_STAT_START), 342 10, 1000); 343 } 344 345 int ksz9477_reset_switch(struct ksz_device *dev) 346 { 347 u8 data8; 348 u32 data32; 349 350 /* reset switch */ 351 ksz_cfg(dev, REG_SW_OPERATION, SW_RESET, true); 352 353 /* turn off SPI DO Edge select */ 354 regmap_update_bits(ksz_regmap_8(dev), REG_SW_GLOBAL_SERIAL_CTRL_0, 355 SPI_AUTO_EDGE_DETECTION, 0); 356 357 /* default configuration */ 358 ksz_write8(dev, REG_SW_LUE_CTRL_1, 359 SW_AGING_ENABLE | SW_LINK_AUTO_AGING | SW_SRC_ADDR_FILTER); 360 361 /* disable interrupts */ 362 ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK); 363 ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0x7F); 364 ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32); 365 366 /* KSZ9893 compatible chips do not support refclk configuration */ 367 if (dev->chip_id == KSZ9893_CHIP_ID || 368 dev->chip_id == KSZ8563_CHIP_ID || 369 dev->chip_id == KSZ9563_CHIP_ID) 370 return 0; 371 372 data8 = SW_ENABLE_REFCLKO; 373 if (dev->synclko_disable) 374 data8 = 0; 375 else if (dev->synclko_125) 376 data8 = SW_ENABLE_REFCLKO | SW_REFCLKO_IS_125MHZ; 377 ksz_write8(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1, data8); 378 379 return 0; 380 } 381 382 void ksz9477_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, u64 *cnt) 383 { 384 struct ksz_port *p = &dev->ports[port]; 385 unsigned int val; 386 u32 data; 387 int ret; 388 389 /* retain the flush/freeze bit */ 390 data = p->freeze ? MIB_COUNTER_FLUSH_FREEZE : 0; 391 data |= MIB_COUNTER_READ; 392 data |= (addr << MIB_COUNTER_INDEX_S); 393 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, data); 394 395 ret = regmap_read_poll_timeout(ksz_regmap_32(dev), 396 PORT_CTRL_ADDR(port, REG_PORT_MIB_CTRL_STAT__4), 397 val, !(val & MIB_COUNTER_READ), 10, 1000); 398 /* failed to read MIB. get out of loop */ 399 if (ret) { 400 dev_dbg(dev->dev, "Failed to get MIB\n"); 401 return; 402 } 403 404 /* count resets upon read */ 405 ksz_pread32(dev, port, REG_PORT_MIB_DATA, &data); 406 *cnt += data; 407 } 408 409 void ksz9477_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 410 u64 *dropped, u64 *cnt) 411 { 412 addr = dev->info->mib_names[addr].index; 413 ksz9477_r_mib_cnt(dev, port, addr, cnt); 414 } 415 416 void ksz9477_freeze_mib(struct ksz_device *dev, int port, bool freeze) 417 { 418 u32 val = freeze ? MIB_COUNTER_FLUSH_FREEZE : 0; 419 struct ksz_port *p = &dev->ports[port]; 420 421 /* enable/disable the port for flush/freeze function */ 422 mutex_lock(&p->mib.cnt_mutex); 423 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, val); 424 425 /* used by MIB counter reading code to know freeze is enabled */ 426 p->freeze = freeze; 427 mutex_unlock(&p->mib.cnt_mutex); 428 } 429 430 static int ksz9477_half_duplex_monitor(struct ksz_device *dev, int port, 431 u64 tx_late_col) 432 { 433 u8 lue_ctrl; 434 u32 pmavbc; 435 u16 pqm; 436 int ret; 437 438 /* Errata DS80000754 recommends monitoring potential faults in 439 * half-duplex mode. The switch might not be able to communicate anymore 440 * in these states. If you see this message, please read the 441 * errata-sheet for more information: 442 * https://ww1.microchip.com/downloads/aemDocuments/documents 443 * /UNG/ProductDocuments/Errata/KSZ9477S-Errata-DS80000754.pdf 444 * To workaround this issue, half-duplex mode should be avoided. 445 * A software reset could be implemented to recover from this state. 446 */ 447 dev_warn_once(dev->dev, 448 "Half-duplex detected on port %d, transmission halt may occur\n", 449 port); 450 if (tx_late_col != 0) { 451 /* Transmission halt with late collisions */ 452 dev_crit_once(dev->dev, 453 "TX late collisions detected, transmission may be halted on port %d\n", 454 port); 455 } 456 ret = ksz_read8(dev, REG_SW_LUE_CTRL_0, &lue_ctrl); 457 if (ret) 458 return ret; 459 if (lue_ctrl & SW_VLAN_ENABLE) { 460 ret = ksz_pread16(dev, port, REG_PORT_QM_TX_CNT_0__4, &pqm); 461 if (ret) 462 return ret; 463 464 ret = ksz_read32(dev, REG_PMAVBC, &pmavbc); 465 if (ret) 466 return ret; 467 468 if ((FIELD_GET(PMAVBC_MASK, pmavbc) <= PMAVBC_MIN) || 469 (FIELD_GET(PORT_QM_TX_CNT_M, pqm) >= PORT_QM_TX_CNT_MAX)) { 470 /* Transmission halt with Half-Duplex and VLAN */ 471 dev_crit_once(dev->dev, 472 "resources out of limits, transmission may be halted\n"); 473 } 474 } 475 476 return ret; 477 } 478 479 int ksz9477_errata_monitor(struct ksz_device *dev, int port, 480 u64 tx_late_col) 481 { 482 u8 status; 483 int ret; 484 485 ret = ksz_pread8(dev, port, REG_PORT_STATUS_0, &status); 486 if (ret) 487 return ret; 488 489 if (!(FIELD_GET(PORT_INTF_SPEED_MASK, status) 490 == PORT_INTF_SPEED_NONE) && 491 !(status & PORT_INTF_FULL_DUPLEX)) { 492 ret = ksz9477_half_duplex_monitor(dev, port, tx_late_col); 493 } 494 495 return ret; 496 } 497 498 void ksz9477_port_init_cnt(struct ksz_device *dev, int port) 499 { 500 struct ksz_port_mib *mib = &dev->ports[port].mib; 501 502 /* flush all enabled port MIB counters */ 503 mutex_lock(&mib->cnt_mutex); 504 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 505 MIB_COUNTER_FLUSH_FREEZE); 506 ksz_write8(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FLUSH); 507 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 0); 508 mutex_unlock(&mib->cnt_mutex); 509 } 510 511 static void ksz9477_r_phy_quirks(struct ksz_device *dev, u16 addr, u16 reg, 512 u16 *data) 513 { 514 /* KSZ8563R do not have extended registers but BMSR_ESTATEN and 515 * BMSR_ERCAP bits are set. 516 */ 517 if (dev->chip_id == KSZ8563_CHIP_ID && reg == MII_BMSR) 518 *data &= ~(BMSR_ESTATEN | BMSR_ERCAP); 519 } 520 521 int ksz9477_r_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 *data) 522 { 523 u16 val = 0xffff; 524 int ret; 525 526 /* No real PHY after this. Simulate the PHY. 527 * A fixed PHY can be setup in the device tree, but this function is 528 * still called for that port during initialization. 529 * For RGMII PHY there is no way to access it so the fixed PHY should 530 * be used. For SGMII PHY the supporting code will be added later. 531 */ 532 if (!dev->info->internal_phy[addr]) { 533 struct ksz_port *p = &dev->ports[addr]; 534 535 switch (reg) { 536 case MII_BMCR: 537 val = 0x1140; 538 break; 539 case MII_BMSR: 540 val = 0x796d; 541 break; 542 case MII_PHYSID1: 543 val = 0x0022; 544 break; 545 case MII_PHYSID2: 546 val = 0x1631; 547 break; 548 case MII_ADVERTISE: 549 val = 0x05e1; 550 break; 551 case MII_LPA: 552 val = 0xc5e1; 553 break; 554 case MII_CTRL1000: 555 val = 0x0700; 556 break; 557 case MII_STAT1000: 558 if (p->phydev.speed == SPEED_1000) 559 val = 0x3800; 560 else 561 val = 0; 562 break; 563 } 564 } else { 565 ret = ksz_pread16(dev, addr, 0x100 + (reg << 1), &val); 566 if (ret) 567 return ret; 568 569 ksz9477_r_phy_quirks(dev, addr, reg, &val); 570 } 571 572 *data = val; 573 574 return 0; 575 } 576 577 int ksz9477_w_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 val) 578 { 579 u32 mask, val32; 580 581 /* No real PHY after this. */ 582 if (!dev->info->internal_phy[addr]) 583 return 0; 584 585 if (reg < 0x10) 586 return ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val); 587 588 /* Errata: When using SPI, I2C, or in-band register access, 589 * writes to certain PHY registers should be performed as 590 * 32-bit writes instead of 16-bit writes. 591 */ 592 val32 = val; 593 mask = 0xffff; 594 if ((reg & 1) == 0) { 595 val32 <<= 16; 596 mask <<= 16; 597 } 598 reg &= ~1; 599 return ksz_prmw32(dev, addr, 0x100 + (reg << 1), mask, val32); 600 } 601 602 void ksz9477_cfg_port_member(struct ksz_device *dev, int port, u8 member) 603 { 604 ksz_pwrite32(dev, port, REG_PORT_VLAN_MEMBERSHIP__4, member); 605 } 606 607 void ksz9477_flush_dyn_mac_table(struct ksz_device *dev, int port) 608 { 609 const u16 *regs = dev->info->regs; 610 u8 data; 611 612 regmap_update_bits(ksz_regmap_8(dev), REG_SW_LUE_CTRL_2, 613 SW_FLUSH_OPTION_M << SW_FLUSH_OPTION_S, 614 SW_FLUSH_OPTION_DYN_MAC << SW_FLUSH_OPTION_S); 615 616 if (port < dev->info->port_cnt) { 617 /* flush individual port */ 618 ksz_pread8(dev, port, regs[P_STP_CTRL], &data); 619 if (!(data & PORT_LEARN_DISABLE)) 620 ksz_pwrite8(dev, port, regs[P_STP_CTRL], 621 data | PORT_LEARN_DISABLE); 622 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true); 623 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data); 624 } else { 625 /* flush all */ 626 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_STP_TABLE, true); 627 } 628 } 629 630 int ksz9477_port_vlan_filtering(struct ksz_device *dev, int port, 631 bool flag, struct netlink_ext_ack *extack) 632 { 633 if (flag) { 634 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 635 PORT_VLAN_LOOKUP_VID_0, true); 636 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, true); 637 } else { 638 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, false); 639 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 640 PORT_VLAN_LOOKUP_VID_0, false); 641 } 642 643 return 0; 644 } 645 646 int ksz9477_port_vlan_add(struct ksz_device *dev, int port, 647 const struct switchdev_obj_port_vlan *vlan, 648 struct netlink_ext_ack *extack) 649 { 650 u32 vlan_table[3]; 651 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 652 int err; 653 654 err = ksz9477_get_vlan_table(dev, vlan->vid, vlan_table); 655 if (err) { 656 NL_SET_ERR_MSG_MOD(extack, "Failed to get vlan table"); 657 return err; 658 } 659 660 vlan_table[0] = VLAN_VALID | (vlan->vid & VLAN_FID_M); 661 if (untagged) 662 vlan_table[1] |= BIT(port); 663 else 664 vlan_table[1] &= ~BIT(port); 665 vlan_table[1] &= ~(BIT(dev->cpu_port)); 666 667 vlan_table[2] |= BIT(port) | BIT(dev->cpu_port); 668 669 err = ksz9477_set_vlan_table(dev, vlan->vid, vlan_table); 670 if (err) { 671 NL_SET_ERR_MSG_MOD(extack, "Failed to set vlan table"); 672 return err; 673 } 674 675 /* change PVID */ 676 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) 677 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, vlan->vid); 678 679 return 0; 680 } 681 682 int ksz9477_port_vlan_del(struct ksz_device *dev, int port, 683 const struct switchdev_obj_port_vlan *vlan) 684 { 685 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 686 u32 vlan_table[3]; 687 u16 pvid; 688 689 ksz_pread16(dev, port, REG_PORT_DEFAULT_VID, &pvid); 690 pvid = pvid & 0xFFF; 691 692 if (ksz9477_get_vlan_table(dev, vlan->vid, vlan_table)) { 693 dev_dbg(dev->dev, "Failed to get vlan table\n"); 694 return -ETIMEDOUT; 695 } 696 697 vlan_table[2] &= ~BIT(port); 698 699 if (pvid == vlan->vid) 700 pvid = 1; 701 702 if (untagged) 703 vlan_table[1] &= ~BIT(port); 704 705 if (ksz9477_set_vlan_table(dev, vlan->vid, vlan_table)) { 706 dev_dbg(dev->dev, "Failed to set vlan table\n"); 707 return -ETIMEDOUT; 708 } 709 710 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, pvid); 711 712 return 0; 713 } 714 715 int ksz9477_fdb_add(struct ksz_device *dev, int port, 716 const unsigned char *addr, u16 vid, struct dsa_db db) 717 { 718 u32 alu_table[4]; 719 u32 data; 720 int ret = 0; 721 722 mutex_lock(&dev->alu_mutex); 723 724 /* find any entry with mac & vid */ 725 data = vid << ALU_FID_INDEX_S; 726 data |= ((addr[0] << 8) | addr[1]); 727 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 728 729 data = ((addr[2] << 24) | (addr[3] << 16)); 730 data |= ((addr[4] << 8) | addr[5]); 731 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 732 733 /* start read operation */ 734 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 735 736 /* wait to be finished */ 737 ret = ksz9477_wait_alu_ready(dev); 738 if (ret) { 739 dev_dbg(dev->dev, "Failed to read ALU\n"); 740 goto exit; 741 } 742 743 /* read ALU entry */ 744 ksz9477_read_table(dev, alu_table); 745 746 /* update ALU entry */ 747 alu_table[0] = ALU_V_STATIC_VALID; 748 alu_table[1] |= BIT(port); 749 if (vid) 750 alu_table[1] |= ALU_V_USE_FID; 751 alu_table[2] = (vid << ALU_V_FID_S); 752 alu_table[2] |= ((addr[0] << 8) | addr[1]); 753 alu_table[3] = ((addr[2] << 24) | (addr[3] << 16)); 754 alu_table[3] |= ((addr[4] << 8) | addr[5]); 755 756 ksz9477_write_table(dev, alu_table); 757 758 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 759 760 /* wait to be finished */ 761 ret = ksz9477_wait_alu_ready(dev); 762 if (ret) 763 dev_dbg(dev->dev, "Failed to write ALU\n"); 764 765 exit: 766 mutex_unlock(&dev->alu_mutex); 767 768 return ret; 769 } 770 771 int ksz9477_fdb_del(struct ksz_device *dev, int port, 772 const unsigned char *addr, u16 vid, struct dsa_db db) 773 { 774 u32 alu_table[4]; 775 u32 data; 776 int ret = 0; 777 778 mutex_lock(&dev->alu_mutex); 779 780 /* read any entry with mac & vid */ 781 data = vid << ALU_FID_INDEX_S; 782 data |= ((addr[0] << 8) | addr[1]); 783 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 784 785 data = ((addr[2] << 24) | (addr[3] << 16)); 786 data |= ((addr[4] << 8) | addr[5]); 787 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 788 789 /* start read operation */ 790 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 791 792 /* wait to be finished */ 793 ret = ksz9477_wait_alu_ready(dev); 794 if (ret) { 795 dev_dbg(dev->dev, "Failed to read ALU\n"); 796 goto exit; 797 } 798 799 ksz_read32(dev, REG_SW_ALU_VAL_A, &alu_table[0]); 800 if (alu_table[0] & ALU_V_STATIC_VALID) { 801 ksz_read32(dev, REG_SW_ALU_VAL_B, &alu_table[1]); 802 ksz_read32(dev, REG_SW_ALU_VAL_C, &alu_table[2]); 803 ksz_read32(dev, REG_SW_ALU_VAL_D, &alu_table[3]); 804 805 /* clear forwarding port */ 806 alu_table[1] &= ~BIT(port); 807 808 /* if there is no port to forward, clear table */ 809 if ((alu_table[1] & ALU_V_PORT_MAP) == 0) { 810 alu_table[0] = 0; 811 alu_table[1] = 0; 812 alu_table[2] = 0; 813 alu_table[3] = 0; 814 } 815 } else { 816 alu_table[0] = 0; 817 alu_table[1] = 0; 818 alu_table[2] = 0; 819 alu_table[3] = 0; 820 } 821 822 ksz9477_write_table(dev, alu_table); 823 824 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 825 826 /* wait to be finished */ 827 ret = ksz9477_wait_alu_ready(dev); 828 if (ret) 829 dev_dbg(dev->dev, "Failed to write ALU\n"); 830 831 exit: 832 mutex_unlock(&dev->alu_mutex); 833 834 return ret; 835 } 836 837 static void ksz9477_convert_alu(struct alu_struct *alu, u32 *alu_table) 838 { 839 alu->is_static = !!(alu_table[0] & ALU_V_STATIC_VALID); 840 alu->is_src_filter = !!(alu_table[0] & ALU_V_SRC_FILTER); 841 alu->is_dst_filter = !!(alu_table[0] & ALU_V_DST_FILTER); 842 alu->prio_age = (alu_table[0] >> ALU_V_PRIO_AGE_CNT_S) & 843 ALU_V_PRIO_AGE_CNT_M; 844 alu->mstp = alu_table[0] & ALU_V_MSTP_M; 845 846 alu->is_override = !!(alu_table[1] & ALU_V_OVERRIDE); 847 alu->is_use_fid = !!(alu_table[1] & ALU_V_USE_FID); 848 alu->port_forward = alu_table[1] & ALU_V_PORT_MAP; 849 850 alu->fid = (alu_table[2] >> ALU_V_FID_S) & ALU_V_FID_M; 851 852 alu->mac[0] = (alu_table[2] >> 8) & 0xFF; 853 alu->mac[1] = alu_table[2] & 0xFF; 854 alu->mac[2] = (alu_table[3] >> 24) & 0xFF; 855 alu->mac[3] = (alu_table[3] >> 16) & 0xFF; 856 alu->mac[4] = (alu_table[3] >> 8) & 0xFF; 857 alu->mac[5] = alu_table[3] & 0xFF; 858 } 859 860 int ksz9477_fdb_dump(struct ksz_device *dev, int port, 861 dsa_fdb_dump_cb_t *cb, void *data) 862 { 863 int ret = 0; 864 u32 ksz_data; 865 u32 alu_table[4]; 866 struct alu_struct alu; 867 int timeout; 868 869 mutex_lock(&dev->alu_mutex); 870 871 /* start ALU search */ 872 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_START | ALU_SEARCH); 873 874 do { 875 timeout = 1000; 876 do { 877 ksz_read32(dev, REG_SW_ALU_CTRL__4, &ksz_data); 878 if ((ksz_data & ALU_VALID) || !(ksz_data & ALU_START)) 879 break; 880 usleep_range(1, 10); 881 } while (timeout-- > 0); 882 883 if (!timeout) { 884 dev_dbg(dev->dev, "Failed to search ALU\n"); 885 ret = -ETIMEDOUT; 886 goto exit; 887 } 888 889 if (!(ksz_data & ALU_VALID)) 890 continue; 891 892 /* read ALU table */ 893 ksz9477_read_table(dev, alu_table); 894 895 ksz9477_convert_alu(&alu, alu_table); 896 897 if (alu.port_forward & BIT(port)) { 898 ret = cb(alu.mac, alu.fid, alu.is_static, data); 899 if (ret) 900 goto exit; 901 } 902 } while (ksz_data & ALU_START); 903 904 exit: 905 906 /* stop ALU search */ 907 ksz_write32(dev, REG_SW_ALU_CTRL__4, 0); 908 909 mutex_unlock(&dev->alu_mutex); 910 911 return ret; 912 } 913 914 int ksz9477_mdb_add(struct ksz_device *dev, int port, 915 const struct switchdev_obj_port_mdb *mdb, struct dsa_db db) 916 { 917 u32 static_table[4]; 918 const u8 *shifts; 919 const u32 *masks; 920 u32 data; 921 int index; 922 u32 mac_hi, mac_lo; 923 int err = 0; 924 925 shifts = dev->info->shifts; 926 masks = dev->info->masks; 927 928 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 929 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 930 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 931 932 mutex_lock(&dev->alu_mutex); 933 934 for (index = 0; index < dev->info->num_statics; index++) { 935 /* find empty slot first */ 936 data = (index << shifts[ALU_STAT_INDEX]) | 937 masks[ALU_STAT_READ] | ALU_STAT_START; 938 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 939 940 /* wait to be finished */ 941 err = ksz9477_wait_alu_sta_ready(dev); 942 if (err) { 943 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 944 goto exit; 945 } 946 947 /* read ALU static table */ 948 ksz9477_read_table(dev, static_table); 949 950 if (static_table[0] & ALU_V_STATIC_VALID) { 951 /* check this has same vid & mac address */ 952 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 953 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 954 static_table[3] == mac_lo) { 955 /* found matching one */ 956 break; 957 } 958 } else { 959 /* found empty one */ 960 break; 961 } 962 } 963 964 /* no available entry */ 965 if (index == dev->info->num_statics) { 966 err = -ENOSPC; 967 goto exit; 968 } 969 970 /* add entry */ 971 static_table[0] = ALU_V_STATIC_VALID; 972 static_table[1] |= BIT(port); 973 if (mdb->vid) 974 static_table[1] |= ALU_V_USE_FID; 975 static_table[2] = (mdb->vid << ALU_V_FID_S); 976 static_table[2] |= mac_hi; 977 static_table[3] = mac_lo; 978 979 ksz9477_write_table(dev, static_table); 980 981 data = (index << shifts[ALU_STAT_INDEX]) | ALU_STAT_START; 982 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 983 984 /* wait to be finished */ 985 if (ksz9477_wait_alu_sta_ready(dev)) 986 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 987 988 exit: 989 mutex_unlock(&dev->alu_mutex); 990 return err; 991 } 992 993 int ksz9477_mdb_del(struct ksz_device *dev, int port, 994 const struct switchdev_obj_port_mdb *mdb, struct dsa_db db) 995 { 996 u32 static_table[4]; 997 const u8 *shifts; 998 const u32 *masks; 999 u32 data; 1000 int index; 1001 int ret = 0; 1002 u32 mac_hi, mac_lo; 1003 1004 shifts = dev->info->shifts; 1005 masks = dev->info->masks; 1006 1007 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 1008 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 1009 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 1010 1011 mutex_lock(&dev->alu_mutex); 1012 1013 for (index = 0; index < dev->info->num_statics; index++) { 1014 /* find empty slot first */ 1015 data = (index << shifts[ALU_STAT_INDEX]) | 1016 masks[ALU_STAT_READ] | ALU_STAT_START; 1017 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 1018 1019 /* wait to be finished */ 1020 ret = ksz9477_wait_alu_sta_ready(dev); 1021 if (ret) { 1022 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 1023 goto exit; 1024 } 1025 1026 /* read ALU static table */ 1027 ksz9477_read_table(dev, static_table); 1028 1029 if (static_table[0] & ALU_V_STATIC_VALID) { 1030 /* check this has same vid & mac address */ 1031 1032 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 1033 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 1034 static_table[3] == mac_lo) { 1035 /* found matching one */ 1036 break; 1037 } 1038 } 1039 } 1040 1041 /* no available entry */ 1042 if (index == dev->info->num_statics) 1043 goto exit; 1044 1045 /* clear port */ 1046 static_table[1] &= ~BIT(port); 1047 1048 if ((static_table[1] & ALU_V_PORT_MAP) == 0) { 1049 /* delete entry */ 1050 static_table[0] = 0; 1051 static_table[1] = 0; 1052 static_table[2] = 0; 1053 static_table[3] = 0; 1054 } 1055 1056 ksz9477_write_table(dev, static_table); 1057 1058 data = (index << shifts[ALU_STAT_INDEX]) | ALU_STAT_START; 1059 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 1060 1061 /* wait to be finished */ 1062 ret = ksz9477_wait_alu_sta_ready(dev); 1063 if (ret) 1064 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 1065 1066 exit: 1067 mutex_unlock(&dev->alu_mutex); 1068 1069 return ret; 1070 } 1071 1072 int ksz9477_port_mirror_add(struct ksz_device *dev, int port, 1073 struct dsa_mall_mirror_tc_entry *mirror, 1074 bool ingress, struct netlink_ext_ack *extack) 1075 { 1076 u8 data; 1077 int p; 1078 1079 /* Limit to one sniffer port 1080 * Check if any of the port is already set for sniffing 1081 * If yes, instruct the user to remove the previous entry & exit 1082 */ 1083 for (p = 0; p < dev->info->port_cnt; p++) { 1084 /* Skip the current sniffing port */ 1085 if (p == mirror->to_local_port) 1086 continue; 1087 1088 ksz_pread8(dev, p, P_MIRROR_CTRL, &data); 1089 1090 if (data & PORT_MIRROR_SNIFFER) { 1091 NL_SET_ERR_MSG_MOD(extack, 1092 "Sniffer port is already configured, delete existing rules & retry"); 1093 return -EBUSY; 1094 } 1095 } 1096 1097 if (ingress) 1098 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true); 1099 else 1100 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true); 1101 1102 /* configure mirror port */ 1103 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 1104 PORT_MIRROR_SNIFFER, true); 1105 1106 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false); 1107 1108 return 0; 1109 } 1110 1111 void ksz9477_port_mirror_del(struct ksz_device *dev, int port, 1112 struct dsa_mall_mirror_tc_entry *mirror) 1113 { 1114 bool in_use = false; 1115 u8 data; 1116 int p; 1117 1118 if (mirror->ingress) 1119 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false); 1120 else 1121 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false); 1122 1123 1124 /* Check if any of the port is still referring to sniffer port */ 1125 for (p = 0; p < dev->info->port_cnt; p++) { 1126 ksz_pread8(dev, p, P_MIRROR_CTRL, &data); 1127 1128 if ((data & (PORT_MIRROR_RX | PORT_MIRROR_TX))) { 1129 in_use = true; 1130 break; 1131 } 1132 } 1133 1134 /* delete sniffing if there are no other mirroring rules */ 1135 if (!in_use) 1136 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 1137 PORT_MIRROR_SNIFFER, false); 1138 } 1139 1140 static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port) 1141 { 1142 phy_interface_t interface; 1143 bool gbit; 1144 1145 if (dev->info->internal_phy[port]) 1146 return PHY_INTERFACE_MODE_NA; 1147 1148 gbit = ksz_get_gbit(dev, port); 1149 1150 interface = ksz_get_xmii(dev, port, gbit); 1151 1152 return interface; 1153 } 1154 1155 void ksz9477_get_caps(struct ksz_device *dev, int port, 1156 struct phylink_config *config) 1157 { 1158 config->mac_capabilities = MAC_10 | MAC_100 | MAC_ASYM_PAUSE | 1159 MAC_SYM_PAUSE; 1160 1161 if (dev->info->gbit_capable[port]) 1162 config->mac_capabilities |= MAC_1000FD; 1163 } 1164 1165 int ksz9477_set_ageing_time(struct ksz_device *dev, unsigned int msecs) 1166 { 1167 u32 secs = msecs / 1000; 1168 u8 value; 1169 u8 data; 1170 int ret; 1171 1172 value = FIELD_GET(SW_AGE_PERIOD_7_0_M, secs); 1173 1174 ret = ksz_write8(dev, REG_SW_LUE_CTRL_3, value); 1175 if (ret < 0) 1176 return ret; 1177 1178 data = FIELD_GET(SW_AGE_PERIOD_10_8_M, secs); 1179 1180 ret = ksz_read8(dev, REG_SW_LUE_CTRL_0, &value); 1181 if (ret < 0) 1182 return ret; 1183 1184 value &= ~SW_AGE_CNT_M; 1185 value |= FIELD_PREP(SW_AGE_CNT_M, data); 1186 1187 return ksz_write8(dev, REG_SW_LUE_CTRL_0, value); 1188 } 1189 1190 void ksz9477_port_queue_split(struct ksz_device *dev, int port) 1191 { 1192 u8 data; 1193 1194 if (dev->info->num_tx_queues == 8) 1195 data = PORT_EIGHT_QUEUE; 1196 else if (dev->info->num_tx_queues == 4) 1197 data = PORT_FOUR_QUEUE; 1198 else if (dev->info->num_tx_queues == 2) 1199 data = PORT_TWO_QUEUE; 1200 else 1201 data = PORT_SINGLE_QUEUE; 1202 1203 ksz_prmw8(dev, port, REG_PORT_CTRL_0, PORT_QUEUE_SPLIT_MASK, data); 1204 } 1205 1206 void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port) 1207 { 1208 struct dsa_switch *ds = dev->ds; 1209 u16 data16; 1210 u8 member; 1211 1212 /* enable tag tail for host port */ 1213 if (cpu_port) 1214 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_TAIL_TAG_ENABLE, 1215 true); 1216 1217 ksz9477_port_queue_split(dev, port); 1218 1219 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_MAC_LOOPBACK, false); 1220 1221 /* set back pressure */ 1222 ksz_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, true); 1223 1224 /* enable broadcast storm limit */ 1225 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true); 1226 1227 /* replace priority */ 1228 ksz_port_cfg(dev, port, REG_PORT_MRI_MAC_CTRL, PORT_USER_PRIO_CEILING, 1229 false); 1230 ksz9477_port_cfg32(dev, port, REG_PORT_MTI_QUEUE_CTRL_0__4, 1231 MTI_PVID_REPLACE, false); 1232 1233 /* force flow control for non-PHY ports only */ 1234 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, 1235 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, 1236 !dev->info->internal_phy[port]); 1237 1238 if (cpu_port) 1239 member = dsa_user_ports(ds); 1240 else 1241 member = BIT(dsa_upstream_port(ds, port)); 1242 1243 ksz9477_cfg_port_member(dev, port, member); 1244 1245 /* clear pending interrupts */ 1246 if (dev->info->internal_phy[port]) 1247 ksz_pread16(dev, port, REG_PORT_PHY_INT_ENABLE, &data16); 1248 1249 ksz9477_port_acl_init(dev, port); 1250 1251 /* clear pending wake flags */ 1252 ksz9477_handle_wake_reason(dev, port); 1253 1254 /* Disable all WoL options by default. Otherwise 1255 * ksz_switch_macaddr_get/put logic will not work properly. 1256 */ 1257 ksz_pwrite8(dev, port, REG_PORT_PME_CTRL, 0); 1258 } 1259 1260 void ksz9477_config_cpu_port(struct dsa_switch *ds) 1261 { 1262 struct ksz_device *dev = ds->priv; 1263 struct ksz_port *p; 1264 int i; 1265 1266 for (i = 0; i < dev->info->port_cnt; i++) { 1267 if (dsa_is_cpu_port(ds, i) && 1268 (dev->info->cpu_ports & (1 << i))) { 1269 phy_interface_t interface; 1270 const char *prev_msg; 1271 const char *prev_mode; 1272 1273 dev->cpu_port = i; 1274 p = &dev->ports[i]; 1275 1276 /* Read from XMII register to determine host port 1277 * interface. If set specifically in device tree 1278 * note the difference to help debugging. 1279 */ 1280 interface = ksz9477_get_interface(dev, i); 1281 if (!p->interface) { 1282 if (dev->compat_interface) { 1283 dev_warn(dev->dev, 1284 "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. " 1285 "Please update your device tree.\n", 1286 i); 1287 p->interface = dev->compat_interface; 1288 } else { 1289 p->interface = interface; 1290 } 1291 } 1292 if (interface && interface != p->interface) { 1293 prev_msg = " instead of "; 1294 prev_mode = phy_modes(interface); 1295 } else { 1296 prev_msg = ""; 1297 prev_mode = ""; 1298 } 1299 dev_info(dev->dev, 1300 "Port%d: using phy mode %s%s%s\n", 1301 i, 1302 phy_modes(p->interface), 1303 prev_msg, 1304 prev_mode); 1305 1306 /* enable cpu port */ 1307 ksz9477_port_setup(dev, i, true); 1308 } 1309 } 1310 1311 for (i = 0; i < dev->info->port_cnt; i++) { 1312 if (i == dev->cpu_port) 1313 continue; 1314 ksz_port_stp_state_set(ds, i, BR_STATE_DISABLED); 1315 } 1316 } 1317 1318 int ksz9477_enable_stp_addr(struct ksz_device *dev) 1319 { 1320 const u32 *masks; 1321 u32 data; 1322 int ret; 1323 1324 masks = dev->info->masks; 1325 1326 /* Enable Reserved multicast table */ 1327 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_RESV_MCAST_ENABLE, true); 1328 1329 /* Set the Override bit for forwarding BPDU packet to CPU */ 1330 ret = ksz_write32(dev, REG_SW_ALU_VAL_B, 1331 ALU_V_OVERRIDE | BIT(dev->cpu_port)); 1332 if (ret < 0) 1333 return ret; 1334 1335 data = ALU_STAT_START | ALU_RESV_MCAST_ADDR | masks[ALU_STAT_WRITE]; 1336 1337 ret = ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 1338 if (ret < 0) 1339 return ret; 1340 1341 /* wait to be finished */ 1342 ret = ksz9477_wait_alu_sta_ready(dev); 1343 if (ret < 0) { 1344 dev_err(dev->dev, "Failed to update Reserved Multicast table\n"); 1345 return ret; 1346 } 1347 1348 return 0; 1349 } 1350 1351 int ksz9477_setup(struct dsa_switch *ds) 1352 { 1353 struct ksz_device *dev = ds->priv; 1354 int ret = 0; 1355 1356 ds->mtu_enforcement_ingress = true; 1357 1358 /* Required for port partitioning. */ 1359 ksz9477_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY, 1360 true); 1361 1362 /* Do not work correctly with tail tagging. */ 1363 ksz_cfg(dev, REG_SW_MAC_CTRL_0, SW_CHECK_LENGTH, false); 1364 1365 /* Enable REG_SW_MTU__2 reg by setting SW_JUMBO_PACKET */ 1366 ksz_cfg(dev, REG_SW_MAC_CTRL_1, SW_JUMBO_PACKET, true); 1367 1368 /* Use collision based back pressure mode. */ 1369 ksz_cfg(dev, REG_SW_MAC_CTRL_1, SW_BACK_PRESSURE, 1370 SW_BACK_PRESSURE_COLLISION); 1371 1372 /* Now we can configure default MTU value */ 1373 ret = regmap_update_bits(ksz_regmap_16(dev), REG_SW_MTU__2, REG_SW_MTU_MASK, 1374 VLAN_ETH_FRAME_LEN + ETH_FCS_LEN); 1375 if (ret) 1376 return ret; 1377 1378 /* queue based egress rate limit */ 1379 ksz_cfg(dev, REG_SW_MAC_CTRL_5, SW_OUT_RATE_LIMIT_QUEUE_BASED, true); 1380 1381 /* enable global MIB counter freeze function */ 1382 ksz_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true); 1383 1384 /* Make sure PME (WoL) is not enabled. If requested, it will be 1385 * enabled by ksz9477_wol_pre_shutdown(). Otherwise, some PMICs do not 1386 * like PME events changes before shutdown. 1387 */ 1388 ksz_write8(dev, REG_SW_PME_CTRL, 0); 1389 1390 return 0; 1391 } 1392 1393 u32 ksz9477_get_port_addr(int port, int offset) 1394 { 1395 return PORT_CTRL_ADDR(port, offset); 1396 } 1397 1398 int ksz9477_tc_cbs_set_cinc(struct ksz_device *dev, int port, u32 val) 1399 { 1400 val = val >> 8; 1401 1402 return ksz_pwrite16(dev, port, REG_PORT_MTI_CREDIT_INCREMENT, val); 1403 } 1404 1405 /* The KSZ9477 provides following HW features to accelerate 1406 * HSR frames handling: 1407 * 1408 * 1. TX PACKET DUPLICATION FROM HOST TO SWITCH 1409 * 2. RX PACKET DUPLICATION DISCARDING 1410 * 3. PREVENTING PACKET LOOP IN THE RING BY SELF-ADDRESS FILTERING 1411 * 1412 * Only one from point 1. has the NETIF_F* flag available. 1413 * 1414 * Ones from point 2 and 3 are "best effort" - i.e. those will 1415 * work correctly most of the time, but it may happen that some 1416 * frames will not be caught - to be more specific; there is a race 1417 * condition in hardware such that, when duplicate packets are received 1418 * on member ports very close in time to each other, the hardware fails 1419 * to detect that they are duplicates. 1420 * 1421 * Hence, the SW needs to handle those special cases. However, the speed 1422 * up gain is considerable when above features are used. 1423 * 1424 * Moreover, the NETIF_F_HW_HSR_FWD feature is also enabled, as HSR frames 1425 * can be forwarded in the switch fabric between HSR ports. 1426 */ 1427 #define KSZ9477_SUPPORTED_HSR_FEATURES (NETIF_F_HW_HSR_DUP | NETIF_F_HW_HSR_FWD) 1428 1429 void ksz9477_hsr_join(struct dsa_switch *ds, int port, struct net_device *hsr) 1430 { 1431 struct ksz_device *dev = ds->priv; 1432 struct net_device *user; 1433 struct dsa_port *hsr_dp; 1434 u8 data, hsr_ports = 0; 1435 1436 /* Program which port(s) shall support HSR */ 1437 ksz_rmw32(dev, REG_HSR_PORT_MAP__4, BIT(port), BIT(port)); 1438 1439 /* Forward frames between HSR ports (i.e. bridge together HSR ports) */ 1440 if (dev->hsr_ports) { 1441 dsa_hsr_foreach_port(hsr_dp, ds, hsr) 1442 hsr_ports |= BIT(hsr_dp->index); 1443 1444 hsr_ports |= BIT(dsa_upstream_port(ds, port)); 1445 dsa_hsr_foreach_port(hsr_dp, ds, hsr) 1446 ksz9477_cfg_port_member(dev, hsr_dp->index, hsr_ports); 1447 } 1448 1449 if (!dev->hsr_ports) { 1450 /* Enable discarding of received HSR frames */ 1451 ksz_read8(dev, REG_HSR_ALU_CTRL_0__1, &data); 1452 data |= HSR_DUPLICATE_DISCARD; 1453 data &= ~HSR_NODE_UNICAST; 1454 ksz_write8(dev, REG_HSR_ALU_CTRL_0__1, data); 1455 } 1456 1457 /* Enable per port self-address filtering. 1458 * The global self-address filtering has already been enabled in the 1459 * ksz9477_reset_switch() function. 1460 */ 1461 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, PORT_SRC_ADDR_FILTER, true); 1462 1463 /* Setup HW supported features for lan HSR ports */ 1464 user = dsa_to_port(ds, port)->user; 1465 user->features |= KSZ9477_SUPPORTED_HSR_FEATURES; 1466 } 1467 1468 void ksz9477_hsr_leave(struct dsa_switch *ds, int port, struct net_device *hsr) 1469 { 1470 struct ksz_device *dev = ds->priv; 1471 1472 /* Clear port HSR support */ 1473 ksz_rmw32(dev, REG_HSR_PORT_MAP__4, BIT(port), 0); 1474 1475 /* Disable forwarding frames between HSR ports */ 1476 ksz9477_cfg_port_member(dev, port, BIT(dsa_upstream_port(ds, port))); 1477 1478 /* Disable per port self-address filtering */ 1479 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, PORT_SRC_ADDR_FILTER, false); 1480 } 1481 1482 int ksz9477_switch_init(struct ksz_device *dev) 1483 { 1484 u8 data8; 1485 int ret; 1486 1487 dev->port_mask = (1 << dev->info->port_cnt) - 1; 1488 1489 /* turn off SPI DO Edge select */ 1490 ret = ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8); 1491 if (ret) 1492 return ret; 1493 1494 data8 &= ~SPI_AUTO_EDGE_DETECTION; 1495 ret = ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8); 1496 if (ret) 1497 return ret; 1498 1499 return 0; 1500 } 1501 1502 void ksz9477_switch_exit(struct ksz_device *dev) 1503 { 1504 ksz9477_reset_switch(dev); 1505 } 1506 1507 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 1508 MODULE_DESCRIPTION("Microchip KSZ9477 Series Switch DSA Driver"); 1509 MODULE_LICENSE("GPL"); 1510