1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip KSZ9477 switch driver main logic 4 * 5 * Copyright (C) 2017-2019 Microchip Technology Inc. 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/iopoll.h> 11 #include <linux/platform_data/microchip-ksz.h> 12 #include <linux/phy.h> 13 #include <linux/if_bridge.h> 14 #include <linux/if_vlan.h> 15 #include <net/dsa.h> 16 #include <net/switchdev.h> 17 18 #include "ksz9477_reg.h" 19 #include "ksz_common.h" 20 #include "ksz9477.h" 21 22 /* Used with variable features to indicate capabilities. */ 23 #define GBIT_SUPPORT BIT(0) 24 #define NEW_XMII BIT(1) 25 #define IS_9893 BIT(2) 26 27 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) 28 { 29 regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0); 30 } 31 32 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits, 33 bool set) 34 { 35 regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset), 36 bits, set ? bits : 0); 37 } 38 39 static void ksz9477_cfg32(struct ksz_device *dev, u32 addr, u32 bits, bool set) 40 { 41 regmap_update_bits(dev->regmap[2], addr, bits, set ? bits : 0); 42 } 43 44 static void ksz9477_port_cfg32(struct ksz_device *dev, int port, int offset, 45 u32 bits, bool set) 46 { 47 regmap_update_bits(dev->regmap[2], PORT_CTRL_ADDR(port, offset), 48 bits, set ? bits : 0); 49 } 50 51 int ksz9477_change_mtu(struct ksz_device *dev, int port, int mtu) 52 { 53 u16 frame_size, max_frame = 0; 54 int i; 55 56 frame_size = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 57 58 /* Cache the per-port MTU setting */ 59 dev->ports[port].max_frame = frame_size; 60 61 for (i = 0; i < dev->info->port_cnt; i++) 62 max_frame = max(max_frame, dev->ports[i].max_frame); 63 64 return regmap_update_bits(dev->regmap[1], REG_SW_MTU__2, 65 REG_SW_MTU_MASK, max_frame); 66 } 67 68 int ksz9477_max_mtu(struct ksz_device *dev, int port) 69 { 70 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 71 } 72 73 static int ksz9477_wait_vlan_ctrl_ready(struct ksz_device *dev) 74 { 75 unsigned int val; 76 77 return regmap_read_poll_timeout(dev->regmap[0], REG_SW_VLAN_CTRL, 78 val, !(val & VLAN_START), 10, 1000); 79 } 80 81 static int ksz9477_get_vlan_table(struct ksz_device *dev, u16 vid, 82 u32 *vlan_table) 83 { 84 int ret; 85 86 mutex_lock(&dev->vlan_mutex); 87 88 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 89 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_READ | VLAN_START); 90 91 /* wait to be cleared */ 92 ret = ksz9477_wait_vlan_ctrl_ready(dev); 93 if (ret) { 94 dev_dbg(dev->dev, "Failed to read vlan table\n"); 95 goto exit; 96 } 97 98 ksz_read32(dev, REG_SW_VLAN_ENTRY__4, &vlan_table[0]); 99 ksz_read32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, &vlan_table[1]); 100 ksz_read32(dev, REG_SW_VLAN_ENTRY_PORTS__4, &vlan_table[2]); 101 102 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 103 104 exit: 105 mutex_unlock(&dev->vlan_mutex); 106 107 return ret; 108 } 109 110 static int ksz9477_set_vlan_table(struct ksz_device *dev, u16 vid, 111 u32 *vlan_table) 112 { 113 int ret; 114 115 mutex_lock(&dev->vlan_mutex); 116 117 ksz_write32(dev, REG_SW_VLAN_ENTRY__4, vlan_table[0]); 118 ksz_write32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, vlan_table[1]); 119 ksz_write32(dev, REG_SW_VLAN_ENTRY_PORTS__4, vlan_table[2]); 120 121 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 122 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_START | VLAN_WRITE); 123 124 /* wait to be cleared */ 125 ret = ksz9477_wait_vlan_ctrl_ready(dev); 126 if (ret) { 127 dev_dbg(dev->dev, "Failed to write vlan table\n"); 128 goto exit; 129 } 130 131 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 132 133 /* update vlan cache table */ 134 dev->vlan_cache[vid].table[0] = vlan_table[0]; 135 dev->vlan_cache[vid].table[1] = vlan_table[1]; 136 dev->vlan_cache[vid].table[2] = vlan_table[2]; 137 138 exit: 139 mutex_unlock(&dev->vlan_mutex); 140 141 return ret; 142 } 143 144 static void ksz9477_read_table(struct ksz_device *dev, u32 *table) 145 { 146 ksz_read32(dev, REG_SW_ALU_VAL_A, &table[0]); 147 ksz_read32(dev, REG_SW_ALU_VAL_B, &table[1]); 148 ksz_read32(dev, REG_SW_ALU_VAL_C, &table[2]); 149 ksz_read32(dev, REG_SW_ALU_VAL_D, &table[3]); 150 } 151 152 static void ksz9477_write_table(struct ksz_device *dev, u32 *table) 153 { 154 ksz_write32(dev, REG_SW_ALU_VAL_A, table[0]); 155 ksz_write32(dev, REG_SW_ALU_VAL_B, table[1]); 156 ksz_write32(dev, REG_SW_ALU_VAL_C, table[2]); 157 ksz_write32(dev, REG_SW_ALU_VAL_D, table[3]); 158 } 159 160 static int ksz9477_wait_alu_ready(struct ksz_device *dev) 161 { 162 unsigned int val; 163 164 return regmap_read_poll_timeout(dev->regmap[2], REG_SW_ALU_CTRL__4, 165 val, !(val & ALU_START), 10, 1000); 166 } 167 168 static int ksz9477_wait_alu_sta_ready(struct ksz_device *dev) 169 { 170 unsigned int val; 171 172 return regmap_read_poll_timeout(dev->regmap[2], 173 REG_SW_ALU_STAT_CTRL__4, 174 val, !(val & ALU_STAT_START), 175 10, 1000); 176 } 177 178 int ksz9477_reset_switch(struct ksz_device *dev) 179 { 180 u8 data8; 181 u32 data32; 182 183 /* reset switch */ 184 ksz_cfg(dev, REG_SW_OPERATION, SW_RESET, true); 185 186 /* turn off SPI DO Edge select */ 187 regmap_update_bits(dev->regmap[0], REG_SW_GLOBAL_SERIAL_CTRL_0, 188 SPI_AUTO_EDGE_DETECTION, 0); 189 190 /* default configuration */ 191 ksz_read8(dev, REG_SW_LUE_CTRL_1, &data8); 192 data8 = SW_AGING_ENABLE | SW_LINK_AUTO_AGING | 193 SW_SRC_ADDR_FILTER | SW_FLUSH_STP_TABLE | SW_FLUSH_MSTP_TABLE; 194 ksz_write8(dev, REG_SW_LUE_CTRL_1, data8); 195 196 /* disable interrupts */ 197 ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK); 198 ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0x7F); 199 ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32); 200 201 data8 = SW_ENABLE_REFCLKO; 202 if (dev->synclko_disable) 203 data8 = 0; 204 else if (dev->synclko_125) 205 data8 = SW_ENABLE_REFCLKO | SW_REFCLKO_IS_125MHZ; 206 ksz_write8(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1, data8); 207 208 return 0; 209 } 210 211 void ksz9477_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, u64 *cnt) 212 { 213 struct ksz_port *p = &dev->ports[port]; 214 unsigned int val; 215 u32 data; 216 int ret; 217 218 /* retain the flush/freeze bit */ 219 data = p->freeze ? MIB_COUNTER_FLUSH_FREEZE : 0; 220 data |= MIB_COUNTER_READ; 221 data |= (addr << MIB_COUNTER_INDEX_S); 222 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, data); 223 224 ret = regmap_read_poll_timeout(dev->regmap[2], 225 PORT_CTRL_ADDR(port, REG_PORT_MIB_CTRL_STAT__4), 226 val, !(val & MIB_COUNTER_READ), 10, 1000); 227 /* failed to read MIB. get out of loop */ 228 if (ret) { 229 dev_dbg(dev->dev, "Failed to get MIB\n"); 230 return; 231 } 232 233 /* count resets upon read */ 234 ksz_pread32(dev, port, REG_PORT_MIB_DATA, &data); 235 *cnt += data; 236 } 237 238 void ksz9477_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 239 u64 *dropped, u64 *cnt) 240 { 241 addr = dev->info->mib_names[addr].index; 242 ksz9477_r_mib_cnt(dev, port, addr, cnt); 243 } 244 245 void ksz9477_freeze_mib(struct ksz_device *dev, int port, bool freeze) 246 { 247 u32 val = freeze ? MIB_COUNTER_FLUSH_FREEZE : 0; 248 struct ksz_port *p = &dev->ports[port]; 249 250 /* enable/disable the port for flush/freeze function */ 251 mutex_lock(&p->mib.cnt_mutex); 252 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, val); 253 254 /* used by MIB counter reading code to know freeze is enabled */ 255 p->freeze = freeze; 256 mutex_unlock(&p->mib.cnt_mutex); 257 } 258 259 void ksz9477_port_init_cnt(struct ksz_device *dev, int port) 260 { 261 struct ksz_port_mib *mib = &dev->ports[port].mib; 262 263 /* flush all enabled port MIB counters */ 264 mutex_lock(&mib->cnt_mutex); 265 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 266 MIB_COUNTER_FLUSH_FREEZE); 267 ksz_write8(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FLUSH); 268 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 0); 269 mutex_unlock(&mib->cnt_mutex); 270 } 271 272 void ksz9477_r_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 *data) 273 { 274 u16 val = 0xffff; 275 276 /* No real PHY after this. Simulate the PHY. 277 * A fixed PHY can be setup in the device tree, but this function is 278 * still called for that port during initialization. 279 * For RGMII PHY there is no way to access it so the fixed PHY should 280 * be used. For SGMII PHY the supporting code will be added later. 281 */ 282 if (addr >= dev->phy_port_cnt) { 283 struct ksz_port *p = &dev->ports[addr]; 284 285 switch (reg) { 286 case MII_BMCR: 287 val = 0x1140; 288 break; 289 case MII_BMSR: 290 val = 0x796d; 291 break; 292 case MII_PHYSID1: 293 val = 0x0022; 294 break; 295 case MII_PHYSID2: 296 val = 0x1631; 297 break; 298 case MII_ADVERTISE: 299 val = 0x05e1; 300 break; 301 case MII_LPA: 302 val = 0xc5e1; 303 break; 304 case MII_CTRL1000: 305 val = 0x0700; 306 break; 307 case MII_STAT1000: 308 if (p->phydev.speed == SPEED_1000) 309 val = 0x3800; 310 else 311 val = 0; 312 break; 313 } 314 } else { 315 ksz_pread16(dev, addr, 0x100 + (reg << 1), &val); 316 } 317 318 *data = val; 319 } 320 321 void ksz9477_w_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 val) 322 { 323 /* No real PHY after this. */ 324 if (addr >= dev->phy_port_cnt) 325 return; 326 327 /* No gigabit support. Do not write to this register. */ 328 if (!(dev->features & GBIT_SUPPORT) && reg == MII_CTRL1000) 329 return; 330 331 ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val); 332 } 333 334 void ksz9477_cfg_port_member(struct ksz_device *dev, int port, u8 member) 335 { 336 ksz_pwrite32(dev, port, REG_PORT_VLAN_MEMBERSHIP__4, member); 337 } 338 339 void ksz9477_flush_dyn_mac_table(struct ksz_device *dev, int port) 340 { 341 u8 data; 342 343 regmap_update_bits(dev->regmap[0], REG_SW_LUE_CTRL_2, 344 SW_FLUSH_OPTION_M << SW_FLUSH_OPTION_S, 345 SW_FLUSH_OPTION_DYN_MAC << SW_FLUSH_OPTION_S); 346 347 if (port < dev->info->port_cnt) { 348 /* flush individual port */ 349 ksz_pread8(dev, port, P_STP_CTRL, &data); 350 if (!(data & PORT_LEARN_DISABLE)) 351 ksz_pwrite8(dev, port, P_STP_CTRL, 352 data | PORT_LEARN_DISABLE); 353 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true); 354 ksz_pwrite8(dev, port, P_STP_CTRL, data); 355 } else { 356 /* flush all */ 357 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_STP_TABLE, true); 358 } 359 } 360 361 int ksz9477_port_vlan_filtering(struct ksz_device *dev, int port, 362 bool flag, struct netlink_ext_ack *extack) 363 { 364 if (flag) { 365 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 366 PORT_VLAN_LOOKUP_VID_0, true); 367 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, true); 368 } else { 369 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, false); 370 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 371 PORT_VLAN_LOOKUP_VID_0, false); 372 } 373 374 return 0; 375 } 376 377 int ksz9477_port_vlan_add(struct ksz_device *dev, int port, 378 const struct switchdev_obj_port_vlan *vlan, 379 struct netlink_ext_ack *extack) 380 { 381 u32 vlan_table[3]; 382 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 383 int err; 384 385 err = ksz9477_get_vlan_table(dev, vlan->vid, vlan_table); 386 if (err) { 387 NL_SET_ERR_MSG_MOD(extack, "Failed to get vlan table"); 388 return err; 389 } 390 391 vlan_table[0] = VLAN_VALID | (vlan->vid & VLAN_FID_M); 392 if (untagged) 393 vlan_table[1] |= BIT(port); 394 else 395 vlan_table[1] &= ~BIT(port); 396 vlan_table[1] &= ~(BIT(dev->cpu_port)); 397 398 vlan_table[2] |= BIT(port) | BIT(dev->cpu_port); 399 400 err = ksz9477_set_vlan_table(dev, vlan->vid, vlan_table); 401 if (err) { 402 NL_SET_ERR_MSG_MOD(extack, "Failed to set vlan table"); 403 return err; 404 } 405 406 /* change PVID */ 407 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) 408 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, vlan->vid); 409 410 return 0; 411 } 412 413 int ksz9477_port_vlan_del(struct ksz_device *dev, int port, 414 const struct switchdev_obj_port_vlan *vlan) 415 { 416 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 417 u32 vlan_table[3]; 418 u16 pvid; 419 420 ksz_pread16(dev, port, REG_PORT_DEFAULT_VID, &pvid); 421 pvid = pvid & 0xFFF; 422 423 if (ksz9477_get_vlan_table(dev, vlan->vid, vlan_table)) { 424 dev_dbg(dev->dev, "Failed to get vlan table\n"); 425 return -ETIMEDOUT; 426 } 427 428 vlan_table[2] &= ~BIT(port); 429 430 if (pvid == vlan->vid) 431 pvid = 1; 432 433 if (untagged) 434 vlan_table[1] &= ~BIT(port); 435 436 if (ksz9477_set_vlan_table(dev, vlan->vid, vlan_table)) { 437 dev_dbg(dev->dev, "Failed to set vlan table\n"); 438 return -ETIMEDOUT; 439 } 440 441 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, pvid); 442 443 return 0; 444 } 445 446 int ksz9477_fdb_add(struct ksz_device *dev, int port, 447 const unsigned char *addr, u16 vid, struct dsa_db db) 448 { 449 u32 alu_table[4]; 450 u32 data; 451 int ret = 0; 452 453 mutex_lock(&dev->alu_mutex); 454 455 /* find any entry with mac & vid */ 456 data = vid << ALU_FID_INDEX_S; 457 data |= ((addr[0] << 8) | addr[1]); 458 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 459 460 data = ((addr[2] << 24) | (addr[3] << 16)); 461 data |= ((addr[4] << 8) | addr[5]); 462 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 463 464 /* start read operation */ 465 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 466 467 /* wait to be finished */ 468 ret = ksz9477_wait_alu_ready(dev); 469 if (ret) { 470 dev_dbg(dev->dev, "Failed to read ALU\n"); 471 goto exit; 472 } 473 474 /* read ALU entry */ 475 ksz9477_read_table(dev, alu_table); 476 477 /* update ALU entry */ 478 alu_table[0] = ALU_V_STATIC_VALID; 479 alu_table[1] |= BIT(port); 480 if (vid) 481 alu_table[1] |= ALU_V_USE_FID; 482 alu_table[2] = (vid << ALU_V_FID_S); 483 alu_table[2] |= ((addr[0] << 8) | addr[1]); 484 alu_table[3] = ((addr[2] << 24) | (addr[3] << 16)); 485 alu_table[3] |= ((addr[4] << 8) | addr[5]); 486 487 ksz9477_write_table(dev, alu_table); 488 489 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 490 491 /* wait to be finished */ 492 ret = ksz9477_wait_alu_ready(dev); 493 if (ret) 494 dev_dbg(dev->dev, "Failed to write ALU\n"); 495 496 exit: 497 mutex_unlock(&dev->alu_mutex); 498 499 return ret; 500 } 501 502 int ksz9477_fdb_del(struct ksz_device *dev, int port, 503 const unsigned char *addr, u16 vid, struct dsa_db db) 504 { 505 u32 alu_table[4]; 506 u32 data; 507 int ret = 0; 508 509 mutex_lock(&dev->alu_mutex); 510 511 /* read any entry with mac & vid */ 512 data = vid << ALU_FID_INDEX_S; 513 data |= ((addr[0] << 8) | addr[1]); 514 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 515 516 data = ((addr[2] << 24) | (addr[3] << 16)); 517 data |= ((addr[4] << 8) | addr[5]); 518 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 519 520 /* start read operation */ 521 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 522 523 /* wait to be finished */ 524 ret = ksz9477_wait_alu_ready(dev); 525 if (ret) { 526 dev_dbg(dev->dev, "Failed to read ALU\n"); 527 goto exit; 528 } 529 530 ksz_read32(dev, REG_SW_ALU_VAL_A, &alu_table[0]); 531 if (alu_table[0] & ALU_V_STATIC_VALID) { 532 ksz_read32(dev, REG_SW_ALU_VAL_B, &alu_table[1]); 533 ksz_read32(dev, REG_SW_ALU_VAL_C, &alu_table[2]); 534 ksz_read32(dev, REG_SW_ALU_VAL_D, &alu_table[3]); 535 536 /* clear forwarding port */ 537 alu_table[2] &= ~BIT(port); 538 539 /* if there is no port to forward, clear table */ 540 if ((alu_table[2] & ALU_V_PORT_MAP) == 0) { 541 alu_table[0] = 0; 542 alu_table[1] = 0; 543 alu_table[2] = 0; 544 alu_table[3] = 0; 545 } 546 } else { 547 alu_table[0] = 0; 548 alu_table[1] = 0; 549 alu_table[2] = 0; 550 alu_table[3] = 0; 551 } 552 553 ksz9477_write_table(dev, alu_table); 554 555 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 556 557 /* wait to be finished */ 558 ret = ksz9477_wait_alu_ready(dev); 559 if (ret) 560 dev_dbg(dev->dev, "Failed to write ALU\n"); 561 562 exit: 563 mutex_unlock(&dev->alu_mutex); 564 565 return ret; 566 } 567 568 static void ksz9477_convert_alu(struct alu_struct *alu, u32 *alu_table) 569 { 570 alu->is_static = !!(alu_table[0] & ALU_V_STATIC_VALID); 571 alu->is_src_filter = !!(alu_table[0] & ALU_V_SRC_FILTER); 572 alu->is_dst_filter = !!(alu_table[0] & ALU_V_DST_FILTER); 573 alu->prio_age = (alu_table[0] >> ALU_V_PRIO_AGE_CNT_S) & 574 ALU_V_PRIO_AGE_CNT_M; 575 alu->mstp = alu_table[0] & ALU_V_MSTP_M; 576 577 alu->is_override = !!(alu_table[1] & ALU_V_OVERRIDE); 578 alu->is_use_fid = !!(alu_table[1] & ALU_V_USE_FID); 579 alu->port_forward = alu_table[1] & ALU_V_PORT_MAP; 580 581 alu->fid = (alu_table[2] >> ALU_V_FID_S) & ALU_V_FID_M; 582 583 alu->mac[0] = (alu_table[2] >> 8) & 0xFF; 584 alu->mac[1] = alu_table[2] & 0xFF; 585 alu->mac[2] = (alu_table[3] >> 24) & 0xFF; 586 alu->mac[3] = (alu_table[3] >> 16) & 0xFF; 587 alu->mac[4] = (alu_table[3] >> 8) & 0xFF; 588 alu->mac[5] = alu_table[3] & 0xFF; 589 } 590 591 int ksz9477_fdb_dump(struct ksz_device *dev, int port, 592 dsa_fdb_dump_cb_t *cb, void *data) 593 { 594 int ret = 0; 595 u32 ksz_data; 596 u32 alu_table[4]; 597 struct alu_struct alu; 598 int timeout; 599 600 mutex_lock(&dev->alu_mutex); 601 602 /* start ALU search */ 603 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_START | ALU_SEARCH); 604 605 do { 606 timeout = 1000; 607 do { 608 ksz_read32(dev, REG_SW_ALU_CTRL__4, &ksz_data); 609 if ((ksz_data & ALU_VALID) || !(ksz_data & ALU_START)) 610 break; 611 usleep_range(1, 10); 612 } while (timeout-- > 0); 613 614 if (!timeout) { 615 dev_dbg(dev->dev, "Failed to search ALU\n"); 616 ret = -ETIMEDOUT; 617 goto exit; 618 } 619 620 /* read ALU table */ 621 ksz9477_read_table(dev, alu_table); 622 623 ksz9477_convert_alu(&alu, alu_table); 624 625 if (alu.port_forward & BIT(port)) { 626 ret = cb(alu.mac, alu.fid, alu.is_static, data); 627 if (ret) 628 goto exit; 629 } 630 } while (ksz_data & ALU_START); 631 632 exit: 633 634 /* stop ALU search */ 635 ksz_write32(dev, REG_SW_ALU_CTRL__4, 0); 636 637 mutex_unlock(&dev->alu_mutex); 638 639 return ret; 640 } 641 642 int ksz9477_mdb_add(struct ksz_device *dev, int port, 643 const struct switchdev_obj_port_mdb *mdb, struct dsa_db db) 644 { 645 u32 static_table[4]; 646 u32 data; 647 int index; 648 u32 mac_hi, mac_lo; 649 int err = 0; 650 651 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 652 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 653 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 654 655 mutex_lock(&dev->alu_mutex); 656 657 for (index = 0; index < dev->info->num_statics; index++) { 658 /* find empty slot first */ 659 data = (index << ALU_STAT_INDEX_S) | 660 ALU_STAT_READ | ALU_STAT_START; 661 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 662 663 /* wait to be finished */ 664 err = ksz9477_wait_alu_sta_ready(dev); 665 if (err) { 666 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 667 goto exit; 668 } 669 670 /* read ALU static table */ 671 ksz9477_read_table(dev, static_table); 672 673 if (static_table[0] & ALU_V_STATIC_VALID) { 674 /* check this has same vid & mac address */ 675 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 676 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 677 static_table[3] == mac_lo) { 678 /* found matching one */ 679 break; 680 } 681 } else { 682 /* found empty one */ 683 break; 684 } 685 } 686 687 /* no available entry */ 688 if (index == dev->info->num_statics) { 689 err = -ENOSPC; 690 goto exit; 691 } 692 693 /* add entry */ 694 static_table[0] = ALU_V_STATIC_VALID; 695 static_table[1] |= BIT(port); 696 if (mdb->vid) 697 static_table[1] |= ALU_V_USE_FID; 698 static_table[2] = (mdb->vid << ALU_V_FID_S); 699 static_table[2] |= mac_hi; 700 static_table[3] = mac_lo; 701 702 ksz9477_write_table(dev, static_table); 703 704 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START; 705 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 706 707 /* wait to be finished */ 708 if (ksz9477_wait_alu_sta_ready(dev)) 709 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 710 711 exit: 712 mutex_unlock(&dev->alu_mutex); 713 return err; 714 } 715 716 int ksz9477_mdb_del(struct ksz_device *dev, int port, 717 const struct switchdev_obj_port_mdb *mdb, struct dsa_db db) 718 { 719 u32 static_table[4]; 720 u32 data; 721 int index; 722 int ret = 0; 723 u32 mac_hi, mac_lo; 724 725 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 726 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 727 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 728 729 mutex_lock(&dev->alu_mutex); 730 731 for (index = 0; index < dev->info->num_statics; index++) { 732 /* find empty slot first */ 733 data = (index << ALU_STAT_INDEX_S) | 734 ALU_STAT_READ | ALU_STAT_START; 735 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 736 737 /* wait to be finished */ 738 ret = ksz9477_wait_alu_sta_ready(dev); 739 if (ret) { 740 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 741 goto exit; 742 } 743 744 /* read ALU static table */ 745 ksz9477_read_table(dev, static_table); 746 747 if (static_table[0] & ALU_V_STATIC_VALID) { 748 /* check this has same vid & mac address */ 749 750 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 751 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 752 static_table[3] == mac_lo) { 753 /* found matching one */ 754 break; 755 } 756 } 757 } 758 759 /* no available entry */ 760 if (index == dev->info->num_statics) 761 goto exit; 762 763 /* clear port */ 764 static_table[1] &= ~BIT(port); 765 766 if ((static_table[1] & ALU_V_PORT_MAP) == 0) { 767 /* delete entry */ 768 static_table[0] = 0; 769 static_table[1] = 0; 770 static_table[2] = 0; 771 static_table[3] = 0; 772 } 773 774 ksz9477_write_table(dev, static_table); 775 776 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START; 777 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 778 779 /* wait to be finished */ 780 ret = ksz9477_wait_alu_sta_ready(dev); 781 if (ret) 782 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 783 784 exit: 785 mutex_unlock(&dev->alu_mutex); 786 787 return ret; 788 } 789 790 int ksz9477_port_mirror_add(struct ksz_device *dev, int port, 791 struct dsa_mall_mirror_tc_entry *mirror, 792 bool ingress, struct netlink_ext_ack *extack) 793 { 794 u8 data; 795 int p; 796 797 /* Limit to one sniffer port 798 * Check if any of the port is already set for sniffing 799 * If yes, instruct the user to remove the previous entry & exit 800 */ 801 for (p = 0; p < dev->info->port_cnt; p++) { 802 /* Skip the current sniffing port */ 803 if (p == mirror->to_local_port) 804 continue; 805 806 ksz_pread8(dev, p, P_MIRROR_CTRL, &data); 807 808 if (data & PORT_MIRROR_SNIFFER) { 809 NL_SET_ERR_MSG_MOD(extack, 810 "Sniffer port is already configured, delete existing rules & retry"); 811 return -EBUSY; 812 } 813 } 814 815 if (ingress) 816 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true); 817 else 818 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true); 819 820 /* configure mirror port */ 821 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 822 PORT_MIRROR_SNIFFER, true); 823 824 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false); 825 826 return 0; 827 } 828 829 void ksz9477_port_mirror_del(struct ksz_device *dev, int port, 830 struct dsa_mall_mirror_tc_entry *mirror) 831 { 832 bool in_use = false; 833 u8 data; 834 int p; 835 836 if (mirror->ingress) 837 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false); 838 else 839 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false); 840 841 842 /* Check if any of the port is still referring to sniffer port */ 843 for (p = 0; p < dev->info->port_cnt; p++) { 844 ksz_pread8(dev, p, P_MIRROR_CTRL, &data); 845 846 if ((data & (PORT_MIRROR_RX | PORT_MIRROR_TX))) { 847 in_use = true; 848 break; 849 } 850 } 851 852 /* delete sniffing if there are no other mirroring rules */ 853 if (!in_use) 854 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 855 PORT_MIRROR_SNIFFER, false); 856 } 857 858 static bool ksz9477_get_gbit(struct ksz_device *dev, u8 data) 859 { 860 bool gbit; 861 862 if (dev->features & NEW_XMII) 863 gbit = !(data & PORT_MII_NOT_1GBIT); 864 else 865 gbit = !!(data & PORT_MII_1000MBIT_S1); 866 return gbit; 867 } 868 869 static void ksz9477_set_gbit(struct ksz_device *dev, bool gbit, u8 *data) 870 { 871 if (dev->features & NEW_XMII) { 872 if (gbit) 873 *data &= ~PORT_MII_NOT_1GBIT; 874 else 875 *data |= PORT_MII_NOT_1GBIT; 876 } else { 877 if (gbit) 878 *data |= PORT_MII_1000MBIT_S1; 879 else 880 *data &= ~PORT_MII_1000MBIT_S1; 881 } 882 } 883 884 static int ksz9477_get_xmii(struct ksz_device *dev, u8 data) 885 { 886 int mode; 887 888 if (dev->features & NEW_XMII) { 889 switch (data & PORT_MII_SEL_M) { 890 case PORT_MII_SEL: 891 mode = 0; 892 break; 893 case PORT_RMII_SEL: 894 mode = 1; 895 break; 896 case PORT_GMII_SEL: 897 mode = 2; 898 break; 899 default: 900 mode = 3; 901 } 902 } else { 903 switch (data & PORT_MII_SEL_M) { 904 case PORT_MII_SEL_S1: 905 mode = 0; 906 break; 907 case PORT_RMII_SEL_S1: 908 mode = 1; 909 break; 910 case PORT_GMII_SEL_S1: 911 mode = 2; 912 break; 913 default: 914 mode = 3; 915 } 916 } 917 return mode; 918 } 919 920 static void ksz9477_set_xmii(struct ksz_device *dev, int mode, u8 *data) 921 { 922 u8 xmii; 923 924 if (dev->features & NEW_XMII) { 925 switch (mode) { 926 case 0: 927 xmii = PORT_MII_SEL; 928 break; 929 case 1: 930 xmii = PORT_RMII_SEL; 931 break; 932 case 2: 933 xmii = PORT_GMII_SEL; 934 break; 935 default: 936 xmii = PORT_RGMII_SEL; 937 break; 938 } 939 } else { 940 switch (mode) { 941 case 0: 942 xmii = PORT_MII_SEL_S1; 943 break; 944 case 1: 945 xmii = PORT_RMII_SEL_S1; 946 break; 947 case 2: 948 xmii = PORT_GMII_SEL_S1; 949 break; 950 default: 951 xmii = PORT_RGMII_SEL_S1; 952 break; 953 } 954 } 955 *data &= ~PORT_MII_SEL_M; 956 *data |= xmii; 957 } 958 959 static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port) 960 { 961 phy_interface_t interface; 962 bool gbit; 963 int mode; 964 u8 data8; 965 966 if (port < dev->phy_port_cnt) 967 return PHY_INTERFACE_MODE_NA; 968 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8); 969 gbit = ksz9477_get_gbit(dev, data8); 970 mode = ksz9477_get_xmii(dev, data8); 971 switch (mode) { 972 case 2: 973 interface = PHY_INTERFACE_MODE_GMII; 974 if (gbit) 975 break; 976 fallthrough; 977 case 0: 978 interface = PHY_INTERFACE_MODE_MII; 979 break; 980 case 1: 981 interface = PHY_INTERFACE_MODE_RMII; 982 break; 983 default: 984 interface = PHY_INTERFACE_MODE_RGMII; 985 if (data8 & PORT_RGMII_ID_EG_ENABLE) 986 interface = PHY_INTERFACE_MODE_RGMII_TXID; 987 if (data8 & PORT_RGMII_ID_IG_ENABLE) { 988 interface = PHY_INTERFACE_MODE_RGMII_RXID; 989 if (data8 & PORT_RGMII_ID_EG_ENABLE) 990 interface = PHY_INTERFACE_MODE_RGMII_ID; 991 } 992 break; 993 } 994 return interface; 995 } 996 997 static void ksz9477_port_mmd_write(struct ksz_device *dev, int port, 998 u8 dev_addr, u16 reg_addr, u16 val) 999 { 1000 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, 1001 MMD_SETUP(PORT_MMD_OP_INDEX, dev_addr)); 1002 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, reg_addr); 1003 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, 1004 MMD_SETUP(PORT_MMD_OP_DATA_NO_INCR, dev_addr)); 1005 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, val); 1006 } 1007 1008 static void ksz9477_phy_errata_setup(struct ksz_device *dev, int port) 1009 { 1010 /* Apply PHY settings to address errata listed in 1011 * KSZ9477, KSZ9897, KSZ9896, KSZ9567, KSZ8565 1012 * Silicon Errata and Data Sheet Clarification documents: 1013 * 1014 * Register settings are needed to improve PHY receive performance 1015 */ 1016 ksz9477_port_mmd_write(dev, port, 0x01, 0x6f, 0xdd0b); 1017 ksz9477_port_mmd_write(dev, port, 0x01, 0x8f, 0x6032); 1018 ksz9477_port_mmd_write(dev, port, 0x01, 0x9d, 0x248c); 1019 ksz9477_port_mmd_write(dev, port, 0x01, 0x75, 0x0060); 1020 ksz9477_port_mmd_write(dev, port, 0x01, 0xd3, 0x7777); 1021 ksz9477_port_mmd_write(dev, port, 0x1c, 0x06, 0x3008); 1022 ksz9477_port_mmd_write(dev, port, 0x1c, 0x08, 0x2001); 1023 1024 /* Transmit waveform amplitude can be improved 1025 * (1000BASE-T, 100BASE-TX, 10BASE-Te) 1026 */ 1027 ksz9477_port_mmd_write(dev, port, 0x1c, 0x04, 0x00d0); 1028 1029 /* Energy Efficient Ethernet (EEE) feature select must 1030 * be manually disabled (except on KSZ8565 which is 100Mbit) 1031 */ 1032 if (dev->features & GBIT_SUPPORT) 1033 ksz9477_port_mmd_write(dev, port, 0x07, 0x3c, 0x0000); 1034 1035 /* Register settings are required to meet data sheet 1036 * supply current specifications 1037 */ 1038 ksz9477_port_mmd_write(dev, port, 0x1c, 0x13, 0x6eff); 1039 ksz9477_port_mmd_write(dev, port, 0x1c, 0x14, 0xe6ff); 1040 ksz9477_port_mmd_write(dev, port, 0x1c, 0x15, 0x6eff); 1041 ksz9477_port_mmd_write(dev, port, 0x1c, 0x16, 0xe6ff); 1042 ksz9477_port_mmd_write(dev, port, 0x1c, 0x17, 0x00ff); 1043 ksz9477_port_mmd_write(dev, port, 0x1c, 0x18, 0x43ff); 1044 ksz9477_port_mmd_write(dev, port, 0x1c, 0x19, 0xc3ff); 1045 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1a, 0x6fff); 1046 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1b, 0x07ff); 1047 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1c, 0x0fff); 1048 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1d, 0xe7ff); 1049 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1e, 0xefff); 1050 ksz9477_port_mmd_write(dev, port, 0x1c, 0x20, 0xeeee); 1051 } 1052 1053 void ksz9477_get_caps(struct ksz_device *dev, int port, 1054 struct phylink_config *config) 1055 { 1056 config->mac_capabilities = MAC_10 | MAC_100 | MAC_ASYM_PAUSE | 1057 MAC_SYM_PAUSE; 1058 1059 if (dev->features & GBIT_SUPPORT) 1060 config->mac_capabilities |= MAC_1000FD; 1061 } 1062 1063 void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port) 1064 { 1065 struct ksz_port *p = &dev->ports[port]; 1066 struct dsa_switch *ds = dev->ds; 1067 u8 data8, member; 1068 u16 data16; 1069 1070 /* enable tag tail for host port */ 1071 if (cpu_port) 1072 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_TAIL_TAG_ENABLE, 1073 true); 1074 1075 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_MAC_LOOPBACK, false); 1076 1077 /* set back pressure */ 1078 ksz_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, true); 1079 1080 /* enable broadcast storm limit */ 1081 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true); 1082 1083 /* disable DiffServ priority */ 1084 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_PRIO_ENABLE, false); 1085 1086 /* replace priority */ 1087 ksz_port_cfg(dev, port, REG_PORT_MRI_MAC_CTRL, PORT_USER_PRIO_CEILING, 1088 false); 1089 ksz9477_port_cfg32(dev, port, REG_PORT_MTI_QUEUE_CTRL_0__4, 1090 MTI_PVID_REPLACE, false); 1091 1092 /* enable 802.1p priority */ 1093 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true); 1094 1095 if (port < dev->phy_port_cnt) { 1096 /* do not force flow control */ 1097 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, 1098 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, 1099 false); 1100 1101 if (dev->info->phy_errata_9477) 1102 ksz9477_phy_errata_setup(dev, port); 1103 } else { 1104 /* force flow control */ 1105 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, 1106 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, 1107 true); 1108 1109 /* configure MAC to 1G & RGMII mode */ 1110 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8); 1111 switch (p->interface) { 1112 case PHY_INTERFACE_MODE_MII: 1113 ksz9477_set_xmii(dev, 0, &data8); 1114 ksz9477_set_gbit(dev, false, &data8); 1115 p->phydev.speed = SPEED_100; 1116 break; 1117 case PHY_INTERFACE_MODE_RMII: 1118 ksz9477_set_xmii(dev, 1, &data8); 1119 ksz9477_set_gbit(dev, false, &data8); 1120 p->phydev.speed = SPEED_100; 1121 break; 1122 case PHY_INTERFACE_MODE_GMII: 1123 ksz9477_set_xmii(dev, 2, &data8); 1124 ksz9477_set_gbit(dev, true, &data8); 1125 p->phydev.speed = SPEED_1000; 1126 break; 1127 default: 1128 ksz9477_set_xmii(dev, 3, &data8); 1129 ksz9477_set_gbit(dev, true, &data8); 1130 data8 &= ~PORT_RGMII_ID_IG_ENABLE; 1131 data8 &= ~PORT_RGMII_ID_EG_ENABLE; 1132 if (p->interface == PHY_INTERFACE_MODE_RGMII_ID || 1133 p->interface == PHY_INTERFACE_MODE_RGMII_RXID) 1134 data8 |= PORT_RGMII_ID_IG_ENABLE; 1135 if (p->interface == PHY_INTERFACE_MODE_RGMII_ID || 1136 p->interface == PHY_INTERFACE_MODE_RGMII_TXID) 1137 data8 |= PORT_RGMII_ID_EG_ENABLE; 1138 /* On KSZ9893, disable RGMII in-band status support */ 1139 if (dev->features & IS_9893) 1140 data8 &= ~PORT_MII_MAC_MODE; 1141 p->phydev.speed = SPEED_1000; 1142 break; 1143 } 1144 ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, data8); 1145 p->phydev.duplex = 1; 1146 } 1147 1148 if (cpu_port) 1149 member = dsa_user_ports(ds); 1150 else 1151 member = BIT(dsa_upstream_port(ds, port)); 1152 1153 ksz9477_cfg_port_member(dev, port, member); 1154 1155 /* clear pending interrupts */ 1156 if (port < dev->phy_port_cnt) 1157 ksz_pread16(dev, port, REG_PORT_PHY_INT_ENABLE, &data16); 1158 } 1159 1160 void ksz9477_config_cpu_port(struct dsa_switch *ds) 1161 { 1162 struct ksz_device *dev = ds->priv; 1163 struct ksz_port *p; 1164 int i; 1165 1166 for (i = 0; i < dev->info->port_cnt; i++) { 1167 if (dsa_is_cpu_port(ds, i) && 1168 (dev->info->cpu_ports & (1 << i))) { 1169 phy_interface_t interface; 1170 const char *prev_msg; 1171 const char *prev_mode; 1172 1173 dev->cpu_port = i; 1174 p = &dev->ports[i]; 1175 1176 /* Read from XMII register to determine host port 1177 * interface. If set specifically in device tree 1178 * note the difference to help debugging. 1179 */ 1180 interface = ksz9477_get_interface(dev, i); 1181 if (!p->interface) { 1182 if (dev->compat_interface) { 1183 dev_warn(dev->dev, 1184 "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. " 1185 "Please update your device tree.\n", 1186 i); 1187 p->interface = dev->compat_interface; 1188 } else { 1189 p->interface = interface; 1190 } 1191 } 1192 if (interface && interface != p->interface) { 1193 prev_msg = " instead of "; 1194 prev_mode = phy_modes(interface); 1195 } else { 1196 prev_msg = ""; 1197 prev_mode = ""; 1198 } 1199 dev_info(dev->dev, 1200 "Port%d: using phy mode %s%s%s\n", 1201 i, 1202 phy_modes(p->interface), 1203 prev_msg, 1204 prev_mode); 1205 1206 /* enable cpu port */ 1207 ksz9477_port_setup(dev, i, true); 1208 p->on = 1; 1209 } 1210 } 1211 1212 for (i = 0; i < dev->info->port_cnt; i++) { 1213 if (i == dev->cpu_port) 1214 continue; 1215 p = &dev->ports[i]; 1216 1217 ksz_port_stp_state_set(ds, i, BR_STATE_DISABLED); 1218 p->on = 1; 1219 if (i < dev->phy_port_cnt) 1220 p->phy = 1; 1221 if (dev->chip_id == 0x00947700 && i == 6) { 1222 p->sgmii = 1; 1223 1224 /* SGMII PHY detection code is not implemented yet. */ 1225 p->phy = 0; 1226 } 1227 } 1228 } 1229 1230 int ksz9477_enable_stp_addr(struct ksz_device *dev) 1231 { 1232 u32 data; 1233 int ret; 1234 1235 /* Enable Reserved multicast table */ 1236 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_RESV_MCAST_ENABLE, true); 1237 1238 /* Set the Override bit for forwarding BPDU packet to CPU */ 1239 ret = ksz_write32(dev, REG_SW_ALU_VAL_B, 1240 ALU_V_OVERRIDE | BIT(dev->cpu_port)); 1241 if (ret < 0) 1242 return ret; 1243 1244 data = ALU_STAT_START | ALU_RESV_MCAST_ADDR; 1245 1246 ret = ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 1247 if (ret < 0) 1248 return ret; 1249 1250 /* wait to be finished */ 1251 ret = ksz9477_wait_alu_sta_ready(dev); 1252 if (ret < 0) { 1253 dev_err(dev->dev, "Failed to update Reserved Multicast table\n"); 1254 return ret; 1255 } 1256 1257 return 0; 1258 } 1259 1260 int ksz9477_setup(struct dsa_switch *ds) 1261 { 1262 struct ksz_device *dev = ds->priv; 1263 int ret = 0; 1264 1265 /* Required for port partitioning. */ 1266 ksz9477_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY, 1267 true); 1268 1269 /* Do not work correctly with tail tagging. */ 1270 ksz_cfg(dev, REG_SW_MAC_CTRL_0, SW_CHECK_LENGTH, false); 1271 1272 /* Enable REG_SW_MTU__2 reg by setting SW_JUMBO_PACKET */ 1273 ksz_cfg(dev, REG_SW_MAC_CTRL_1, SW_JUMBO_PACKET, true); 1274 1275 /* Now we can configure default MTU value */ 1276 ret = regmap_update_bits(dev->regmap[1], REG_SW_MTU__2, REG_SW_MTU_MASK, 1277 VLAN_ETH_FRAME_LEN + ETH_FCS_LEN); 1278 if (ret) 1279 return ret; 1280 1281 /* queue based egress rate limit */ 1282 ksz_cfg(dev, REG_SW_MAC_CTRL_5, SW_OUT_RATE_LIMIT_QUEUE_BASED, true); 1283 1284 /* enable global MIB counter freeze function */ 1285 ksz_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true); 1286 1287 return 0; 1288 } 1289 1290 u32 ksz9477_get_port_addr(int port, int offset) 1291 { 1292 return PORT_CTRL_ADDR(port, offset); 1293 } 1294 1295 int ksz9477_switch_init(struct ksz_device *dev) 1296 { 1297 u8 data8; 1298 int ret; 1299 1300 dev->port_mask = (1 << dev->info->port_cnt) - 1; 1301 1302 /* turn off SPI DO Edge select */ 1303 ret = ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8); 1304 if (ret) 1305 return ret; 1306 1307 data8 &= ~SPI_AUTO_EDGE_DETECTION; 1308 ret = ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8); 1309 if (ret) 1310 return ret; 1311 1312 ret = ksz_read8(dev, REG_GLOBAL_OPTIONS, &data8); 1313 if (ret) 1314 return ret; 1315 1316 /* Number of ports can be reduced depending on chip. */ 1317 dev->phy_port_cnt = 5; 1318 1319 /* Default capability is gigabit capable. */ 1320 dev->features = GBIT_SUPPORT; 1321 1322 if (dev->chip_id == KSZ9893_CHIP_ID) { 1323 dev->features |= IS_9893; 1324 1325 /* Chip does not support gigabit. */ 1326 if (data8 & SW_QW_ABLE) 1327 dev->features &= ~GBIT_SUPPORT; 1328 dev->phy_port_cnt = 2; 1329 } else { 1330 /* Chip uses new XMII register definitions. */ 1331 dev->features |= NEW_XMII; 1332 1333 /* Chip does not support gigabit. */ 1334 if (!(data8 & SW_GIGABIT_ABLE)) 1335 dev->features &= ~GBIT_SUPPORT; 1336 } 1337 1338 return 0; 1339 } 1340 1341 void ksz9477_switch_exit(struct ksz_device *dev) 1342 { 1343 ksz9477_reset_switch(dev); 1344 } 1345 1346 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 1347 MODULE_DESCRIPTION("Microchip KSZ9477 Series Switch DSA Driver"); 1348 MODULE_LICENSE("GPL"); 1349