1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip KSZ9477 switch driver main logic 4 * 5 * Copyright (C) 2017-2019 Microchip Technology Inc. 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/iopoll.h> 11 #include <linux/platform_data/microchip-ksz.h> 12 #include <linux/phy.h> 13 #include <linux/if_bridge.h> 14 #include <net/dsa.h> 15 #include <net/switchdev.h> 16 17 #include "ksz9477_reg.h" 18 #include "ksz_common.h" 19 20 /* Used with variable features to indicate capabilities. */ 21 #define GBIT_SUPPORT BIT(0) 22 #define NEW_XMII BIT(1) 23 #define IS_9893 BIT(2) 24 25 static const struct { 26 int index; 27 char string[ETH_GSTRING_LEN]; 28 } ksz9477_mib_names[TOTAL_SWITCH_COUNTER_NUM] = { 29 { 0x00, "rx_hi" }, 30 { 0x01, "rx_undersize" }, 31 { 0x02, "rx_fragments" }, 32 { 0x03, "rx_oversize" }, 33 { 0x04, "rx_jabbers" }, 34 { 0x05, "rx_symbol_err" }, 35 { 0x06, "rx_crc_err" }, 36 { 0x07, "rx_align_err" }, 37 { 0x08, "rx_mac_ctrl" }, 38 { 0x09, "rx_pause" }, 39 { 0x0A, "rx_bcast" }, 40 { 0x0B, "rx_mcast" }, 41 { 0x0C, "rx_ucast" }, 42 { 0x0D, "rx_64_or_less" }, 43 { 0x0E, "rx_65_127" }, 44 { 0x0F, "rx_128_255" }, 45 { 0x10, "rx_256_511" }, 46 { 0x11, "rx_512_1023" }, 47 { 0x12, "rx_1024_1522" }, 48 { 0x13, "rx_1523_2000" }, 49 { 0x14, "rx_2001" }, 50 { 0x15, "tx_hi" }, 51 { 0x16, "tx_late_col" }, 52 { 0x17, "tx_pause" }, 53 { 0x18, "tx_bcast" }, 54 { 0x19, "tx_mcast" }, 55 { 0x1A, "tx_ucast" }, 56 { 0x1B, "tx_deferred" }, 57 { 0x1C, "tx_total_col" }, 58 { 0x1D, "tx_exc_col" }, 59 { 0x1E, "tx_single_col" }, 60 { 0x1F, "tx_mult_col" }, 61 { 0x80, "rx_total" }, 62 { 0x81, "tx_total" }, 63 { 0x82, "rx_discards" }, 64 { 0x83, "tx_discards" }, 65 }; 66 67 struct ksz9477_stats_raw { 68 u64 rx_hi; 69 u64 rx_undersize; 70 u64 rx_fragments; 71 u64 rx_oversize; 72 u64 rx_jabbers; 73 u64 rx_symbol_err; 74 u64 rx_crc_err; 75 u64 rx_align_err; 76 u64 rx_mac_ctrl; 77 u64 rx_pause; 78 u64 rx_bcast; 79 u64 rx_mcast; 80 u64 rx_ucast; 81 u64 rx_64_or_less; 82 u64 rx_65_127; 83 u64 rx_128_255; 84 u64 rx_256_511; 85 u64 rx_512_1023; 86 u64 rx_1024_1522; 87 u64 rx_1523_2000; 88 u64 rx_2001; 89 u64 tx_hi; 90 u64 tx_late_col; 91 u64 tx_pause; 92 u64 tx_bcast; 93 u64 tx_mcast; 94 u64 tx_ucast; 95 u64 tx_deferred; 96 u64 tx_total_col; 97 u64 tx_exc_col; 98 u64 tx_single_col; 99 u64 tx_mult_col; 100 u64 rx_total; 101 u64 tx_total; 102 u64 rx_discards; 103 u64 tx_discards; 104 }; 105 106 static void ksz9477_r_mib_stats64(struct ksz_device *dev, int port) 107 { 108 struct rtnl_link_stats64 *stats; 109 struct ksz9477_stats_raw *raw; 110 struct ksz_port_mib *mib; 111 112 mib = &dev->ports[port].mib; 113 stats = &mib->stats64; 114 raw = (struct ksz9477_stats_raw *)mib->counters; 115 116 spin_lock(&mib->stats64_lock); 117 118 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast; 119 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast; 120 121 /* HW counters are counting bytes + FCS which is not acceptable 122 * for rtnl_link_stats64 interface 123 */ 124 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN; 125 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN; 126 127 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 128 raw->rx_oversize; 129 130 stats->rx_crc_errors = raw->rx_crc_err; 131 stats->rx_frame_errors = raw->rx_align_err; 132 stats->rx_dropped = raw->rx_discards; 133 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 134 stats->rx_frame_errors + stats->rx_dropped; 135 136 stats->tx_window_errors = raw->tx_late_col; 137 stats->tx_fifo_errors = raw->tx_discards; 138 stats->tx_aborted_errors = raw->tx_exc_col; 139 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 140 stats->tx_aborted_errors; 141 142 stats->multicast = raw->rx_mcast; 143 stats->collisions = raw->tx_total_col; 144 145 spin_unlock(&mib->stats64_lock); 146 } 147 148 static void ksz9477_get_stats64(struct dsa_switch *ds, int port, 149 struct rtnl_link_stats64 *s) 150 { 151 struct ksz_device *dev = ds->priv; 152 struct ksz_port_mib *mib; 153 154 mib = &dev->ports[port].mib; 155 156 spin_lock(&mib->stats64_lock); 157 memcpy(s, &mib->stats64, sizeof(*s)); 158 spin_unlock(&mib->stats64_lock); 159 } 160 161 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) 162 { 163 regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0); 164 } 165 166 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits, 167 bool set) 168 { 169 regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset), 170 bits, set ? bits : 0); 171 } 172 173 static void ksz9477_cfg32(struct ksz_device *dev, u32 addr, u32 bits, bool set) 174 { 175 regmap_update_bits(dev->regmap[2], addr, bits, set ? bits : 0); 176 } 177 178 static void ksz9477_port_cfg32(struct ksz_device *dev, int port, int offset, 179 u32 bits, bool set) 180 { 181 regmap_update_bits(dev->regmap[2], PORT_CTRL_ADDR(port, offset), 182 bits, set ? bits : 0); 183 } 184 185 static int ksz9477_wait_vlan_ctrl_ready(struct ksz_device *dev) 186 { 187 unsigned int val; 188 189 return regmap_read_poll_timeout(dev->regmap[0], REG_SW_VLAN_CTRL, 190 val, !(val & VLAN_START), 10, 1000); 191 } 192 193 static int ksz9477_get_vlan_table(struct ksz_device *dev, u16 vid, 194 u32 *vlan_table) 195 { 196 int ret; 197 198 mutex_lock(&dev->vlan_mutex); 199 200 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 201 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_READ | VLAN_START); 202 203 /* wait to be cleared */ 204 ret = ksz9477_wait_vlan_ctrl_ready(dev); 205 if (ret) { 206 dev_dbg(dev->dev, "Failed to read vlan table\n"); 207 goto exit; 208 } 209 210 ksz_read32(dev, REG_SW_VLAN_ENTRY__4, &vlan_table[0]); 211 ksz_read32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, &vlan_table[1]); 212 ksz_read32(dev, REG_SW_VLAN_ENTRY_PORTS__4, &vlan_table[2]); 213 214 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 215 216 exit: 217 mutex_unlock(&dev->vlan_mutex); 218 219 return ret; 220 } 221 222 static int ksz9477_set_vlan_table(struct ksz_device *dev, u16 vid, 223 u32 *vlan_table) 224 { 225 int ret; 226 227 mutex_lock(&dev->vlan_mutex); 228 229 ksz_write32(dev, REG_SW_VLAN_ENTRY__4, vlan_table[0]); 230 ksz_write32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, vlan_table[1]); 231 ksz_write32(dev, REG_SW_VLAN_ENTRY_PORTS__4, vlan_table[2]); 232 233 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 234 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_START | VLAN_WRITE); 235 236 /* wait to be cleared */ 237 ret = ksz9477_wait_vlan_ctrl_ready(dev); 238 if (ret) { 239 dev_dbg(dev->dev, "Failed to write vlan table\n"); 240 goto exit; 241 } 242 243 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 244 245 /* update vlan cache table */ 246 dev->vlan_cache[vid].table[0] = vlan_table[0]; 247 dev->vlan_cache[vid].table[1] = vlan_table[1]; 248 dev->vlan_cache[vid].table[2] = vlan_table[2]; 249 250 exit: 251 mutex_unlock(&dev->vlan_mutex); 252 253 return ret; 254 } 255 256 static void ksz9477_read_table(struct ksz_device *dev, u32 *table) 257 { 258 ksz_read32(dev, REG_SW_ALU_VAL_A, &table[0]); 259 ksz_read32(dev, REG_SW_ALU_VAL_B, &table[1]); 260 ksz_read32(dev, REG_SW_ALU_VAL_C, &table[2]); 261 ksz_read32(dev, REG_SW_ALU_VAL_D, &table[3]); 262 } 263 264 static void ksz9477_write_table(struct ksz_device *dev, u32 *table) 265 { 266 ksz_write32(dev, REG_SW_ALU_VAL_A, table[0]); 267 ksz_write32(dev, REG_SW_ALU_VAL_B, table[1]); 268 ksz_write32(dev, REG_SW_ALU_VAL_C, table[2]); 269 ksz_write32(dev, REG_SW_ALU_VAL_D, table[3]); 270 } 271 272 static int ksz9477_wait_alu_ready(struct ksz_device *dev) 273 { 274 unsigned int val; 275 276 return regmap_read_poll_timeout(dev->regmap[2], REG_SW_ALU_CTRL__4, 277 val, !(val & ALU_START), 10, 1000); 278 } 279 280 static int ksz9477_wait_alu_sta_ready(struct ksz_device *dev) 281 { 282 unsigned int val; 283 284 return regmap_read_poll_timeout(dev->regmap[2], 285 REG_SW_ALU_STAT_CTRL__4, 286 val, !(val & ALU_STAT_START), 287 10, 1000); 288 } 289 290 static int ksz9477_reset_switch(struct ksz_device *dev) 291 { 292 u8 data8; 293 u32 data32; 294 295 /* reset switch */ 296 ksz_cfg(dev, REG_SW_OPERATION, SW_RESET, true); 297 298 /* turn off SPI DO Edge select */ 299 regmap_update_bits(dev->regmap[0], REG_SW_GLOBAL_SERIAL_CTRL_0, 300 SPI_AUTO_EDGE_DETECTION, 0); 301 302 /* default configuration */ 303 ksz_read8(dev, REG_SW_LUE_CTRL_1, &data8); 304 data8 = SW_AGING_ENABLE | SW_LINK_AUTO_AGING | 305 SW_SRC_ADDR_FILTER | SW_FLUSH_STP_TABLE | SW_FLUSH_MSTP_TABLE; 306 ksz_write8(dev, REG_SW_LUE_CTRL_1, data8); 307 308 /* disable interrupts */ 309 ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK); 310 ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0x7F); 311 ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32); 312 313 /* set broadcast storm protection 10% rate */ 314 regmap_update_bits(dev->regmap[1], REG_SW_MAC_CTRL_2, 315 BROADCAST_STORM_RATE, 316 (BROADCAST_STORM_VALUE * 317 BROADCAST_STORM_PROT_RATE) / 100); 318 319 data8 = SW_ENABLE_REFCLKO; 320 if (dev->synclko_disable) 321 data8 = 0; 322 else if (dev->synclko_125) 323 data8 = SW_ENABLE_REFCLKO | SW_REFCLKO_IS_125MHZ; 324 ksz_write8(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1, data8); 325 326 return 0; 327 } 328 329 static void ksz9477_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, 330 u64 *cnt) 331 { 332 struct ksz_port *p = &dev->ports[port]; 333 unsigned int val; 334 u32 data; 335 int ret; 336 337 /* retain the flush/freeze bit */ 338 data = p->freeze ? MIB_COUNTER_FLUSH_FREEZE : 0; 339 data |= MIB_COUNTER_READ; 340 data |= (addr << MIB_COUNTER_INDEX_S); 341 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, data); 342 343 ret = regmap_read_poll_timeout(dev->regmap[2], 344 PORT_CTRL_ADDR(port, REG_PORT_MIB_CTRL_STAT__4), 345 val, !(val & MIB_COUNTER_READ), 10, 1000); 346 /* failed to read MIB. get out of loop */ 347 if (ret) { 348 dev_dbg(dev->dev, "Failed to get MIB\n"); 349 return; 350 } 351 352 /* count resets upon read */ 353 ksz_pread32(dev, port, REG_PORT_MIB_DATA, &data); 354 *cnt += data; 355 } 356 357 static void ksz9477_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 358 u64 *dropped, u64 *cnt) 359 { 360 addr = ksz9477_mib_names[addr].index; 361 ksz9477_r_mib_cnt(dev, port, addr, cnt); 362 } 363 364 static void ksz9477_freeze_mib(struct ksz_device *dev, int port, bool freeze) 365 { 366 u32 val = freeze ? MIB_COUNTER_FLUSH_FREEZE : 0; 367 struct ksz_port *p = &dev->ports[port]; 368 369 /* enable/disable the port for flush/freeze function */ 370 mutex_lock(&p->mib.cnt_mutex); 371 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, val); 372 373 /* used by MIB counter reading code to know freeze is enabled */ 374 p->freeze = freeze; 375 mutex_unlock(&p->mib.cnt_mutex); 376 } 377 378 static void ksz9477_port_init_cnt(struct ksz_device *dev, int port) 379 { 380 struct ksz_port_mib *mib = &dev->ports[port].mib; 381 382 /* flush all enabled port MIB counters */ 383 mutex_lock(&mib->cnt_mutex); 384 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 385 MIB_COUNTER_FLUSH_FREEZE); 386 ksz_write8(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FLUSH); 387 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 0); 388 mutex_unlock(&mib->cnt_mutex); 389 390 mib->cnt_ptr = 0; 391 memset(mib->counters, 0, dev->mib_cnt * sizeof(u64)); 392 } 393 394 static enum dsa_tag_protocol ksz9477_get_tag_protocol(struct dsa_switch *ds, 395 int port, 396 enum dsa_tag_protocol mp) 397 { 398 enum dsa_tag_protocol proto = DSA_TAG_PROTO_KSZ9477; 399 struct ksz_device *dev = ds->priv; 400 401 if (dev->features & IS_9893) 402 proto = DSA_TAG_PROTO_KSZ9893; 403 return proto; 404 } 405 406 static int ksz9477_phy_read16(struct dsa_switch *ds, int addr, int reg) 407 { 408 struct ksz_device *dev = ds->priv; 409 u16 val = 0xffff; 410 411 /* No real PHY after this. Simulate the PHY. 412 * A fixed PHY can be setup in the device tree, but this function is 413 * still called for that port during initialization. 414 * For RGMII PHY there is no way to access it so the fixed PHY should 415 * be used. For SGMII PHY the supporting code will be added later. 416 */ 417 if (addr >= dev->phy_port_cnt) { 418 struct ksz_port *p = &dev->ports[addr]; 419 420 switch (reg) { 421 case MII_BMCR: 422 val = 0x1140; 423 break; 424 case MII_BMSR: 425 val = 0x796d; 426 break; 427 case MII_PHYSID1: 428 val = 0x0022; 429 break; 430 case MII_PHYSID2: 431 val = 0x1631; 432 break; 433 case MII_ADVERTISE: 434 val = 0x05e1; 435 break; 436 case MII_LPA: 437 val = 0xc5e1; 438 break; 439 case MII_CTRL1000: 440 val = 0x0700; 441 break; 442 case MII_STAT1000: 443 if (p->phydev.speed == SPEED_1000) 444 val = 0x3800; 445 else 446 val = 0; 447 break; 448 } 449 } else { 450 ksz_pread16(dev, addr, 0x100 + (reg << 1), &val); 451 } 452 453 return val; 454 } 455 456 static int ksz9477_phy_write16(struct dsa_switch *ds, int addr, int reg, 457 u16 val) 458 { 459 struct ksz_device *dev = ds->priv; 460 461 /* No real PHY after this. */ 462 if (addr >= dev->phy_port_cnt) 463 return 0; 464 465 /* No gigabit support. Do not write to this register. */ 466 if (!(dev->features & GBIT_SUPPORT) && reg == MII_CTRL1000) 467 return 0; 468 ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val); 469 470 return 0; 471 } 472 473 static void ksz9477_get_strings(struct dsa_switch *ds, int port, 474 u32 stringset, uint8_t *buf) 475 { 476 int i; 477 478 if (stringset != ETH_SS_STATS) 479 return; 480 481 for (i = 0; i < TOTAL_SWITCH_COUNTER_NUM; i++) { 482 memcpy(buf + i * ETH_GSTRING_LEN, ksz9477_mib_names[i].string, 483 ETH_GSTRING_LEN); 484 } 485 } 486 487 static void ksz9477_cfg_port_member(struct ksz_device *dev, int port, 488 u8 member) 489 { 490 ksz_pwrite32(dev, port, REG_PORT_VLAN_MEMBERSHIP__4, member); 491 } 492 493 static void ksz9477_port_stp_state_set(struct dsa_switch *ds, int port, 494 u8 state) 495 { 496 struct ksz_device *dev = ds->priv; 497 struct ksz_port *p = &dev->ports[port]; 498 u8 data; 499 500 ksz_pread8(dev, port, P_STP_CTRL, &data); 501 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 502 503 switch (state) { 504 case BR_STATE_DISABLED: 505 data |= PORT_LEARN_DISABLE; 506 break; 507 case BR_STATE_LISTENING: 508 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 509 break; 510 case BR_STATE_LEARNING: 511 data |= PORT_RX_ENABLE; 512 break; 513 case BR_STATE_FORWARDING: 514 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 515 break; 516 case BR_STATE_BLOCKING: 517 data |= PORT_LEARN_DISABLE; 518 break; 519 default: 520 dev_err(ds->dev, "invalid STP state: %d\n", state); 521 return; 522 } 523 524 ksz_pwrite8(dev, port, P_STP_CTRL, data); 525 p->stp_state = state; 526 527 ksz_update_port_member(dev, port); 528 } 529 530 static void ksz9477_flush_dyn_mac_table(struct ksz_device *dev, int port) 531 { 532 u8 data; 533 534 regmap_update_bits(dev->regmap[0], REG_SW_LUE_CTRL_2, 535 SW_FLUSH_OPTION_M << SW_FLUSH_OPTION_S, 536 SW_FLUSH_OPTION_DYN_MAC << SW_FLUSH_OPTION_S); 537 538 if (port < dev->port_cnt) { 539 /* flush individual port */ 540 ksz_pread8(dev, port, P_STP_CTRL, &data); 541 if (!(data & PORT_LEARN_DISABLE)) 542 ksz_pwrite8(dev, port, P_STP_CTRL, 543 data | PORT_LEARN_DISABLE); 544 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true); 545 ksz_pwrite8(dev, port, P_STP_CTRL, data); 546 } else { 547 /* flush all */ 548 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_STP_TABLE, true); 549 } 550 } 551 552 static int ksz9477_port_vlan_filtering(struct dsa_switch *ds, int port, 553 bool flag, 554 struct netlink_ext_ack *extack) 555 { 556 struct ksz_device *dev = ds->priv; 557 558 if (flag) { 559 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 560 PORT_VLAN_LOOKUP_VID_0, true); 561 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, true); 562 } else { 563 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, false); 564 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 565 PORT_VLAN_LOOKUP_VID_0, false); 566 } 567 568 return 0; 569 } 570 571 static int ksz9477_port_vlan_add(struct dsa_switch *ds, int port, 572 const struct switchdev_obj_port_vlan *vlan, 573 struct netlink_ext_ack *extack) 574 { 575 struct ksz_device *dev = ds->priv; 576 u32 vlan_table[3]; 577 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 578 int err; 579 580 err = ksz9477_get_vlan_table(dev, vlan->vid, vlan_table); 581 if (err) { 582 NL_SET_ERR_MSG_MOD(extack, "Failed to get vlan table"); 583 return err; 584 } 585 586 vlan_table[0] = VLAN_VALID | (vlan->vid & VLAN_FID_M); 587 if (untagged) 588 vlan_table[1] |= BIT(port); 589 else 590 vlan_table[1] &= ~BIT(port); 591 vlan_table[1] &= ~(BIT(dev->cpu_port)); 592 593 vlan_table[2] |= BIT(port) | BIT(dev->cpu_port); 594 595 err = ksz9477_set_vlan_table(dev, vlan->vid, vlan_table); 596 if (err) { 597 NL_SET_ERR_MSG_MOD(extack, "Failed to set vlan table"); 598 return err; 599 } 600 601 /* change PVID */ 602 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) 603 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, vlan->vid); 604 605 return 0; 606 } 607 608 static int ksz9477_port_vlan_del(struct dsa_switch *ds, int port, 609 const struct switchdev_obj_port_vlan *vlan) 610 { 611 struct ksz_device *dev = ds->priv; 612 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 613 u32 vlan_table[3]; 614 u16 pvid; 615 616 ksz_pread16(dev, port, REG_PORT_DEFAULT_VID, &pvid); 617 pvid = pvid & 0xFFF; 618 619 if (ksz9477_get_vlan_table(dev, vlan->vid, vlan_table)) { 620 dev_dbg(dev->dev, "Failed to get vlan table\n"); 621 return -ETIMEDOUT; 622 } 623 624 vlan_table[2] &= ~BIT(port); 625 626 if (pvid == vlan->vid) 627 pvid = 1; 628 629 if (untagged) 630 vlan_table[1] &= ~BIT(port); 631 632 if (ksz9477_set_vlan_table(dev, vlan->vid, vlan_table)) { 633 dev_dbg(dev->dev, "Failed to set vlan table\n"); 634 return -ETIMEDOUT; 635 } 636 637 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, pvid); 638 639 return 0; 640 } 641 642 static int ksz9477_port_fdb_add(struct dsa_switch *ds, int port, 643 const unsigned char *addr, u16 vid, 644 struct dsa_db db) 645 { 646 struct ksz_device *dev = ds->priv; 647 u32 alu_table[4]; 648 u32 data; 649 int ret = 0; 650 651 mutex_lock(&dev->alu_mutex); 652 653 /* find any entry with mac & vid */ 654 data = vid << ALU_FID_INDEX_S; 655 data |= ((addr[0] << 8) | addr[1]); 656 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 657 658 data = ((addr[2] << 24) | (addr[3] << 16)); 659 data |= ((addr[4] << 8) | addr[5]); 660 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 661 662 /* start read operation */ 663 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 664 665 /* wait to be finished */ 666 ret = ksz9477_wait_alu_ready(dev); 667 if (ret) { 668 dev_dbg(dev->dev, "Failed to read ALU\n"); 669 goto exit; 670 } 671 672 /* read ALU entry */ 673 ksz9477_read_table(dev, alu_table); 674 675 /* update ALU entry */ 676 alu_table[0] = ALU_V_STATIC_VALID; 677 alu_table[1] |= BIT(port); 678 if (vid) 679 alu_table[1] |= ALU_V_USE_FID; 680 alu_table[2] = (vid << ALU_V_FID_S); 681 alu_table[2] |= ((addr[0] << 8) | addr[1]); 682 alu_table[3] = ((addr[2] << 24) | (addr[3] << 16)); 683 alu_table[3] |= ((addr[4] << 8) | addr[5]); 684 685 ksz9477_write_table(dev, alu_table); 686 687 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 688 689 /* wait to be finished */ 690 ret = ksz9477_wait_alu_ready(dev); 691 if (ret) 692 dev_dbg(dev->dev, "Failed to write ALU\n"); 693 694 exit: 695 mutex_unlock(&dev->alu_mutex); 696 697 return ret; 698 } 699 700 static int ksz9477_port_fdb_del(struct dsa_switch *ds, int port, 701 const unsigned char *addr, u16 vid, 702 struct dsa_db db) 703 { 704 struct ksz_device *dev = ds->priv; 705 u32 alu_table[4]; 706 u32 data; 707 int ret = 0; 708 709 mutex_lock(&dev->alu_mutex); 710 711 /* read any entry with mac & vid */ 712 data = vid << ALU_FID_INDEX_S; 713 data |= ((addr[0] << 8) | addr[1]); 714 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 715 716 data = ((addr[2] << 24) | (addr[3] << 16)); 717 data |= ((addr[4] << 8) | addr[5]); 718 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 719 720 /* start read operation */ 721 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 722 723 /* wait to be finished */ 724 ret = ksz9477_wait_alu_ready(dev); 725 if (ret) { 726 dev_dbg(dev->dev, "Failed to read ALU\n"); 727 goto exit; 728 } 729 730 ksz_read32(dev, REG_SW_ALU_VAL_A, &alu_table[0]); 731 if (alu_table[0] & ALU_V_STATIC_VALID) { 732 ksz_read32(dev, REG_SW_ALU_VAL_B, &alu_table[1]); 733 ksz_read32(dev, REG_SW_ALU_VAL_C, &alu_table[2]); 734 ksz_read32(dev, REG_SW_ALU_VAL_D, &alu_table[3]); 735 736 /* clear forwarding port */ 737 alu_table[2] &= ~BIT(port); 738 739 /* if there is no port to forward, clear table */ 740 if ((alu_table[2] & ALU_V_PORT_MAP) == 0) { 741 alu_table[0] = 0; 742 alu_table[1] = 0; 743 alu_table[2] = 0; 744 alu_table[3] = 0; 745 } 746 } else { 747 alu_table[0] = 0; 748 alu_table[1] = 0; 749 alu_table[2] = 0; 750 alu_table[3] = 0; 751 } 752 753 ksz9477_write_table(dev, alu_table); 754 755 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 756 757 /* wait to be finished */ 758 ret = ksz9477_wait_alu_ready(dev); 759 if (ret) 760 dev_dbg(dev->dev, "Failed to write ALU\n"); 761 762 exit: 763 mutex_unlock(&dev->alu_mutex); 764 765 return ret; 766 } 767 768 static void ksz9477_convert_alu(struct alu_struct *alu, u32 *alu_table) 769 { 770 alu->is_static = !!(alu_table[0] & ALU_V_STATIC_VALID); 771 alu->is_src_filter = !!(alu_table[0] & ALU_V_SRC_FILTER); 772 alu->is_dst_filter = !!(alu_table[0] & ALU_V_DST_FILTER); 773 alu->prio_age = (alu_table[0] >> ALU_V_PRIO_AGE_CNT_S) & 774 ALU_V_PRIO_AGE_CNT_M; 775 alu->mstp = alu_table[0] & ALU_V_MSTP_M; 776 777 alu->is_override = !!(alu_table[1] & ALU_V_OVERRIDE); 778 alu->is_use_fid = !!(alu_table[1] & ALU_V_USE_FID); 779 alu->port_forward = alu_table[1] & ALU_V_PORT_MAP; 780 781 alu->fid = (alu_table[2] >> ALU_V_FID_S) & ALU_V_FID_M; 782 783 alu->mac[0] = (alu_table[2] >> 8) & 0xFF; 784 alu->mac[1] = alu_table[2] & 0xFF; 785 alu->mac[2] = (alu_table[3] >> 24) & 0xFF; 786 alu->mac[3] = (alu_table[3] >> 16) & 0xFF; 787 alu->mac[4] = (alu_table[3] >> 8) & 0xFF; 788 alu->mac[5] = alu_table[3] & 0xFF; 789 } 790 791 static int ksz9477_port_fdb_dump(struct dsa_switch *ds, int port, 792 dsa_fdb_dump_cb_t *cb, void *data) 793 { 794 struct ksz_device *dev = ds->priv; 795 int ret = 0; 796 u32 ksz_data; 797 u32 alu_table[4]; 798 struct alu_struct alu; 799 int timeout; 800 801 mutex_lock(&dev->alu_mutex); 802 803 /* start ALU search */ 804 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_START | ALU_SEARCH); 805 806 do { 807 timeout = 1000; 808 do { 809 ksz_read32(dev, REG_SW_ALU_CTRL__4, &ksz_data); 810 if ((ksz_data & ALU_VALID) || !(ksz_data & ALU_START)) 811 break; 812 usleep_range(1, 10); 813 } while (timeout-- > 0); 814 815 if (!timeout) { 816 dev_dbg(dev->dev, "Failed to search ALU\n"); 817 ret = -ETIMEDOUT; 818 goto exit; 819 } 820 821 /* read ALU table */ 822 ksz9477_read_table(dev, alu_table); 823 824 ksz9477_convert_alu(&alu, alu_table); 825 826 if (alu.port_forward & BIT(port)) { 827 ret = cb(alu.mac, alu.fid, alu.is_static, data); 828 if (ret) 829 goto exit; 830 } 831 } while (ksz_data & ALU_START); 832 833 exit: 834 835 /* stop ALU search */ 836 ksz_write32(dev, REG_SW_ALU_CTRL__4, 0); 837 838 mutex_unlock(&dev->alu_mutex); 839 840 return ret; 841 } 842 843 static int ksz9477_port_mdb_add(struct dsa_switch *ds, int port, 844 const struct switchdev_obj_port_mdb *mdb, 845 struct dsa_db db) 846 { 847 struct ksz_device *dev = ds->priv; 848 u32 static_table[4]; 849 u32 data; 850 int index; 851 u32 mac_hi, mac_lo; 852 int err = 0; 853 854 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 855 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 856 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 857 858 mutex_lock(&dev->alu_mutex); 859 860 for (index = 0; index < dev->num_statics; index++) { 861 /* find empty slot first */ 862 data = (index << ALU_STAT_INDEX_S) | 863 ALU_STAT_READ | ALU_STAT_START; 864 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 865 866 /* wait to be finished */ 867 err = ksz9477_wait_alu_sta_ready(dev); 868 if (err) { 869 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 870 goto exit; 871 } 872 873 /* read ALU static table */ 874 ksz9477_read_table(dev, static_table); 875 876 if (static_table[0] & ALU_V_STATIC_VALID) { 877 /* check this has same vid & mac address */ 878 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 879 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 880 static_table[3] == mac_lo) { 881 /* found matching one */ 882 break; 883 } 884 } else { 885 /* found empty one */ 886 break; 887 } 888 } 889 890 /* no available entry */ 891 if (index == dev->num_statics) { 892 err = -ENOSPC; 893 goto exit; 894 } 895 896 /* add entry */ 897 static_table[0] = ALU_V_STATIC_VALID; 898 static_table[1] |= BIT(port); 899 if (mdb->vid) 900 static_table[1] |= ALU_V_USE_FID; 901 static_table[2] = (mdb->vid << ALU_V_FID_S); 902 static_table[2] |= mac_hi; 903 static_table[3] = mac_lo; 904 905 ksz9477_write_table(dev, static_table); 906 907 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START; 908 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 909 910 /* wait to be finished */ 911 if (ksz9477_wait_alu_sta_ready(dev)) 912 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 913 914 exit: 915 mutex_unlock(&dev->alu_mutex); 916 return err; 917 } 918 919 static int ksz9477_port_mdb_del(struct dsa_switch *ds, int port, 920 const struct switchdev_obj_port_mdb *mdb, 921 struct dsa_db db) 922 { 923 struct ksz_device *dev = ds->priv; 924 u32 static_table[4]; 925 u32 data; 926 int index; 927 int ret = 0; 928 u32 mac_hi, mac_lo; 929 930 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 931 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 932 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 933 934 mutex_lock(&dev->alu_mutex); 935 936 for (index = 0; index < dev->num_statics; index++) { 937 /* find empty slot first */ 938 data = (index << ALU_STAT_INDEX_S) | 939 ALU_STAT_READ | ALU_STAT_START; 940 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 941 942 /* wait to be finished */ 943 ret = ksz9477_wait_alu_sta_ready(dev); 944 if (ret) { 945 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 946 goto exit; 947 } 948 949 /* read ALU static table */ 950 ksz9477_read_table(dev, static_table); 951 952 if (static_table[0] & ALU_V_STATIC_VALID) { 953 /* check this has same vid & mac address */ 954 955 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 956 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 957 static_table[3] == mac_lo) { 958 /* found matching one */ 959 break; 960 } 961 } 962 } 963 964 /* no available entry */ 965 if (index == dev->num_statics) 966 goto exit; 967 968 /* clear port */ 969 static_table[1] &= ~BIT(port); 970 971 if ((static_table[1] & ALU_V_PORT_MAP) == 0) { 972 /* delete entry */ 973 static_table[0] = 0; 974 static_table[1] = 0; 975 static_table[2] = 0; 976 static_table[3] = 0; 977 } 978 979 ksz9477_write_table(dev, static_table); 980 981 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START; 982 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 983 984 /* wait to be finished */ 985 ret = ksz9477_wait_alu_sta_ready(dev); 986 if (ret) 987 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 988 989 exit: 990 mutex_unlock(&dev->alu_mutex); 991 992 return ret; 993 } 994 995 static int ksz9477_port_mirror_add(struct dsa_switch *ds, int port, 996 struct dsa_mall_mirror_tc_entry *mirror, 997 bool ingress) 998 { 999 struct ksz_device *dev = ds->priv; 1000 1001 if (ingress) 1002 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true); 1003 else 1004 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true); 1005 1006 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false); 1007 1008 /* configure mirror port */ 1009 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 1010 PORT_MIRROR_SNIFFER, true); 1011 1012 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false); 1013 1014 return 0; 1015 } 1016 1017 static void ksz9477_port_mirror_del(struct dsa_switch *ds, int port, 1018 struct dsa_mall_mirror_tc_entry *mirror) 1019 { 1020 struct ksz_device *dev = ds->priv; 1021 u8 data; 1022 1023 if (mirror->ingress) 1024 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false); 1025 else 1026 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false); 1027 1028 ksz_pread8(dev, port, P_MIRROR_CTRL, &data); 1029 1030 if (!(data & (PORT_MIRROR_RX | PORT_MIRROR_TX))) 1031 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 1032 PORT_MIRROR_SNIFFER, false); 1033 } 1034 1035 static bool ksz9477_get_gbit(struct ksz_device *dev, u8 data) 1036 { 1037 bool gbit; 1038 1039 if (dev->features & NEW_XMII) 1040 gbit = !(data & PORT_MII_NOT_1GBIT); 1041 else 1042 gbit = !!(data & PORT_MII_1000MBIT_S1); 1043 return gbit; 1044 } 1045 1046 static void ksz9477_set_gbit(struct ksz_device *dev, bool gbit, u8 *data) 1047 { 1048 if (dev->features & NEW_XMII) { 1049 if (gbit) 1050 *data &= ~PORT_MII_NOT_1GBIT; 1051 else 1052 *data |= PORT_MII_NOT_1GBIT; 1053 } else { 1054 if (gbit) 1055 *data |= PORT_MII_1000MBIT_S1; 1056 else 1057 *data &= ~PORT_MII_1000MBIT_S1; 1058 } 1059 } 1060 1061 static int ksz9477_get_xmii(struct ksz_device *dev, u8 data) 1062 { 1063 int mode; 1064 1065 if (dev->features & NEW_XMII) { 1066 switch (data & PORT_MII_SEL_M) { 1067 case PORT_MII_SEL: 1068 mode = 0; 1069 break; 1070 case PORT_RMII_SEL: 1071 mode = 1; 1072 break; 1073 case PORT_GMII_SEL: 1074 mode = 2; 1075 break; 1076 default: 1077 mode = 3; 1078 } 1079 } else { 1080 switch (data & PORT_MII_SEL_M) { 1081 case PORT_MII_SEL_S1: 1082 mode = 0; 1083 break; 1084 case PORT_RMII_SEL_S1: 1085 mode = 1; 1086 break; 1087 case PORT_GMII_SEL_S1: 1088 mode = 2; 1089 break; 1090 default: 1091 mode = 3; 1092 } 1093 } 1094 return mode; 1095 } 1096 1097 static void ksz9477_set_xmii(struct ksz_device *dev, int mode, u8 *data) 1098 { 1099 u8 xmii; 1100 1101 if (dev->features & NEW_XMII) { 1102 switch (mode) { 1103 case 0: 1104 xmii = PORT_MII_SEL; 1105 break; 1106 case 1: 1107 xmii = PORT_RMII_SEL; 1108 break; 1109 case 2: 1110 xmii = PORT_GMII_SEL; 1111 break; 1112 default: 1113 xmii = PORT_RGMII_SEL; 1114 break; 1115 } 1116 } else { 1117 switch (mode) { 1118 case 0: 1119 xmii = PORT_MII_SEL_S1; 1120 break; 1121 case 1: 1122 xmii = PORT_RMII_SEL_S1; 1123 break; 1124 case 2: 1125 xmii = PORT_GMII_SEL_S1; 1126 break; 1127 default: 1128 xmii = PORT_RGMII_SEL_S1; 1129 break; 1130 } 1131 } 1132 *data &= ~PORT_MII_SEL_M; 1133 *data |= xmii; 1134 } 1135 1136 static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port) 1137 { 1138 phy_interface_t interface; 1139 bool gbit; 1140 int mode; 1141 u8 data8; 1142 1143 if (port < dev->phy_port_cnt) 1144 return PHY_INTERFACE_MODE_NA; 1145 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8); 1146 gbit = ksz9477_get_gbit(dev, data8); 1147 mode = ksz9477_get_xmii(dev, data8); 1148 switch (mode) { 1149 case 2: 1150 interface = PHY_INTERFACE_MODE_GMII; 1151 if (gbit) 1152 break; 1153 fallthrough; 1154 case 0: 1155 interface = PHY_INTERFACE_MODE_MII; 1156 break; 1157 case 1: 1158 interface = PHY_INTERFACE_MODE_RMII; 1159 break; 1160 default: 1161 interface = PHY_INTERFACE_MODE_RGMII; 1162 if (data8 & PORT_RGMII_ID_EG_ENABLE) 1163 interface = PHY_INTERFACE_MODE_RGMII_TXID; 1164 if (data8 & PORT_RGMII_ID_IG_ENABLE) { 1165 interface = PHY_INTERFACE_MODE_RGMII_RXID; 1166 if (data8 & PORT_RGMII_ID_EG_ENABLE) 1167 interface = PHY_INTERFACE_MODE_RGMII_ID; 1168 } 1169 break; 1170 } 1171 return interface; 1172 } 1173 1174 static void ksz9477_port_mmd_write(struct ksz_device *dev, int port, 1175 u8 dev_addr, u16 reg_addr, u16 val) 1176 { 1177 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, 1178 MMD_SETUP(PORT_MMD_OP_INDEX, dev_addr)); 1179 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, reg_addr); 1180 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, 1181 MMD_SETUP(PORT_MMD_OP_DATA_NO_INCR, dev_addr)); 1182 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, val); 1183 } 1184 1185 static void ksz9477_phy_errata_setup(struct ksz_device *dev, int port) 1186 { 1187 /* Apply PHY settings to address errata listed in 1188 * KSZ9477, KSZ9897, KSZ9896, KSZ9567, KSZ8565 1189 * Silicon Errata and Data Sheet Clarification documents: 1190 * 1191 * Register settings are needed to improve PHY receive performance 1192 */ 1193 ksz9477_port_mmd_write(dev, port, 0x01, 0x6f, 0xdd0b); 1194 ksz9477_port_mmd_write(dev, port, 0x01, 0x8f, 0x6032); 1195 ksz9477_port_mmd_write(dev, port, 0x01, 0x9d, 0x248c); 1196 ksz9477_port_mmd_write(dev, port, 0x01, 0x75, 0x0060); 1197 ksz9477_port_mmd_write(dev, port, 0x01, 0xd3, 0x7777); 1198 ksz9477_port_mmd_write(dev, port, 0x1c, 0x06, 0x3008); 1199 ksz9477_port_mmd_write(dev, port, 0x1c, 0x08, 0x2001); 1200 1201 /* Transmit waveform amplitude can be improved 1202 * (1000BASE-T, 100BASE-TX, 10BASE-Te) 1203 */ 1204 ksz9477_port_mmd_write(dev, port, 0x1c, 0x04, 0x00d0); 1205 1206 /* Energy Efficient Ethernet (EEE) feature select must 1207 * be manually disabled (except on KSZ8565 which is 100Mbit) 1208 */ 1209 if (dev->features & GBIT_SUPPORT) 1210 ksz9477_port_mmd_write(dev, port, 0x07, 0x3c, 0x0000); 1211 1212 /* Register settings are required to meet data sheet 1213 * supply current specifications 1214 */ 1215 ksz9477_port_mmd_write(dev, port, 0x1c, 0x13, 0x6eff); 1216 ksz9477_port_mmd_write(dev, port, 0x1c, 0x14, 0xe6ff); 1217 ksz9477_port_mmd_write(dev, port, 0x1c, 0x15, 0x6eff); 1218 ksz9477_port_mmd_write(dev, port, 0x1c, 0x16, 0xe6ff); 1219 ksz9477_port_mmd_write(dev, port, 0x1c, 0x17, 0x00ff); 1220 ksz9477_port_mmd_write(dev, port, 0x1c, 0x18, 0x43ff); 1221 ksz9477_port_mmd_write(dev, port, 0x1c, 0x19, 0xc3ff); 1222 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1a, 0x6fff); 1223 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1b, 0x07ff); 1224 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1c, 0x0fff); 1225 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1d, 0xe7ff); 1226 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1e, 0xefff); 1227 ksz9477_port_mmd_write(dev, port, 0x1c, 0x20, 0xeeee); 1228 } 1229 1230 static void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port) 1231 { 1232 struct ksz_port *p = &dev->ports[port]; 1233 struct dsa_switch *ds = dev->ds; 1234 u8 data8, member; 1235 u16 data16; 1236 1237 /* enable tag tail for host port */ 1238 if (cpu_port) 1239 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_TAIL_TAG_ENABLE, 1240 true); 1241 1242 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_MAC_LOOPBACK, false); 1243 1244 /* set back pressure */ 1245 ksz_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, true); 1246 1247 /* enable broadcast storm limit */ 1248 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true); 1249 1250 /* disable DiffServ priority */ 1251 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_PRIO_ENABLE, false); 1252 1253 /* replace priority */ 1254 ksz_port_cfg(dev, port, REG_PORT_MRI_MAC_CTRL, PORT_USER_PRIO_CEILING, 1255 false); 1256 ksz9477_port_cfg32(dev, port, REG_PORT_MTI_QUEUE_CTRL_0__4, 1257 MTI_PVID_REPLACE, false); 1258 1259 /* enable 802.1p priority */ 1260 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true); 1261 1262 if (port < dev->phy_port_cnt) { 1263 /* do not force flow control */ 1264 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, 1265 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, 1266 false); 1267 1268 if (dev->phy_errata_9477) 1269 ksz9477_phy_errata_setup(dev, port); 1270 } else { 1271 /* force flow control */ 1272 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, 1273 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, 1274 true); 1275 1276 /* configure MAC to 1G & RGMII mode */ 1277 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8); 1278 switch (p->interface) { 1279 case PHY_INTERFACE_MODE_MII: 1280 ksz9477_set_xmii(dev, 0, &data8); 1281 ksz9477_set_gbit(dev, false, &data8); 1282 p->phydev.speed = SPEED_100; 1283 break; 1284 case PHY_INTERFACE_MODE_RMII: 1285 ksz9477_set_xmii(dev, 1, &data8); 1286 ksz9477_set_gbit(dev, false, &data8); 1287 p->phydev.speed = SPEED_100; 1288 break; 1289 case PHY_INTERFACE_MODE_GMII: 1290 ksz9477_set_xmii(dev, 2, &data8); 1291 ksz9477_set_gbit(dev, true, &data8); 1292 p->phydev.speed = SPEED_1000; 1293 break; 1294 default: 1295 ksz9477_set_xmii(dev, 3, &data8); 1296 ksz9477_set_gbit(dev, true, &data8); 1297 data8 &= ~PORT_RGMII_ID_IG_ENABLE; 1298 data8 &= ~PORT_RGMII_ID_EG_ENABLE; 1299 if (p->interface == PHY_INTERFACE_MODE_RGMII_ID || 1300 p->interface == PHY_INTERFACE_MODE_RGMII_RXID) 1301 data8 |= PORT_RGMII_ID_IG_ENABLE; 1302 if (p->interface == PHY_INTERFACE_MODE_RGMII_ID || 1303 p->interface == PHY_INTERFACE_MODE_RGMII_TXID) 1304 data8 |= PORT_RGMII_ID_EG_ENABLE; 1305 /* On KSZ9893, disable RGMII in-band status support */ 1306 if (dev->features & IS_9893) 1307 data8 &= ~PORT_MII_MAC_MODE; 1308 p->phydev.speed = SPEED_1000; 1309 break; 1310 } 1311 ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, data8); 1312 p->phydev.duplex = 1; 1313 } 1314 1315 if (cpu_port) 1316 member = dsa_user_ports(ds); 1317 else 1318 member = BIT(dsa_upstream_port(ds, port)); 1319 1320 ksz9477_cfg_port_member(dev, port, member); 1321 1322 /* clear pending interrupts */ 1323 if (port < dev->phy_port_cnt) 1324 ksz_pread16(dev, port, REG_PORT_PHY_INT_ENABLE, &data16); 1325 } 1326 1327 static void ksz9477_config_cpu_port(struct dsa_switch *ds) 1328 { 1329 struct ksz_device *dev = ds->priv; 1330 struct ksz_port *p; 1331 int i; 1332 1333 for (i = 0; i < dev->port_cnt; i++) { 1334 if (dsa_is_cpu_port(ds, i) && (dev->cpu_ports & (1 << i))) { 1335 phy_interface_t interface; 1336 const char *prev_msg; 1337 const char *prev_mode; 1338 1339 dev->cpu_port = i; 1340 p = &dev->ports[i]; 1341 1342 /* Read from XMII register to determine host port 1343 * interface. If set specifically in device tree 1344 * note the difference to help debugging. 1345 */ 1346 interface = ksz9477_get_interface(dev, i); 1347 if (!p->interface) { 1348 if (dev->compat_interface) { 1349 dev_warn(dev->dev, 1350 "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. " 1351 "Please update your device tree.\n", 1352 i); 1353 p->interface = dev->compat_interface; 1354 } else { 1355 p->interface = interface; 1356 } 1357 } 1358 if (interface && interface != p->interface) { 1359 prev_msg = " instead of "; 1360 prev_mode = phy_modes(interface); 1361 } else { 1362 prev_msg = ""; 1363 prev_mode = ""; 1364 } 1365 dev_info(dev->dev, 1366 "Port%d: using phy mode %s%s%s\n", 1367 i, 1368 phy_modes(p->interface), 1369 prev_msg, 1370 prev_mode); 1371 1372 /* enable cpu port */ 1373 ksz9477_port_setup(dev, i, true); 1374 p->on = 1; 1375 } 1376 } 1377 1378 for (i = 0; i < dev->port_cnt; i++) { 1379 if (i == dev->cpu_port) 1380 continue; 1381 p = &dev->ports[i]; 1382 1383 ksz9477_port_stp_state_set(ds, i, BR_STATE_DISABLED); 1384 p->on = 1; 1385 if (i < dev->phy_port_cnt) 1386 p->phy = 1; 1387 if (dev->chip_id == 0x00947700 && i == 6) { 1388 p->sgmii = 1; 1389 1390 /* SGMII PHY detection code is not implemented yet. */ 1391 p->phy = 0; 1392 } 1393 } 1394 } 1395 1396 static int ksz9477_setup(struct dsa_switch *ds) 1397 { 1398 struct ksz_device *dev = ds->priv; 1399 int ret = 0; 1400 1401 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 1402 dev->num_vlans, GFP_KERNEL); 1403 if (!dev->vlan_cache) 1404 return -ENOMEM; 1405 1406 ret = ksz9477_reset_switch(dev); 1407 if (ret) { 1408 dev_err(ds->dev, "failed to reset switch\n"); 1409 return ret; 1410 } 1411 1412 /* Required for port partitioning. */ 1413 ksz9477_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY, 1414 true); 1415 1416 /* Do not work correctly with tail tagging. */ 1417 ksz_cfg(dev, REG_SW_MAC_CTRL_0, SW_CHECK_LENGTH, false); 1418 1419 /* accept packet up to 2000bytes */ 1420 ksz_cfg(dev, REG_SW_MAC_CTRL_1, SW_LEGAL_PACKET_DISABLE, true); 1421 1422 ksz9477_config_cpu_port(ds); 1423 1424 ksz_cfg(dev, REG_SW_MAC_CTRL_1, MULTICAST_STORM_DISABLE, true); 1425 1426 /* queue based egress rate limit */ 1427 ksz_cfg(dev, REG_SW_MAC_CTRL_5, SW_OUT_RATE_LIMIT_QUEUE_BASED, true); 1428 1429 /* enable global MIB counter freeze function */ 1430 ksz_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true); 1431 1432 /* start switch */ 1433 ksz_cfg(dev, REG_SW_OPERATION, SW_START, true); 1434 1435 ksz_init_mib_timer(dev); 1436 1437 ds->configure_vlan_while_not_filtering = false; 1438 1439 return 0; 1440 } 1441 1442 static const struct dsa_switch_ops ksz9477_switch_ops = { 1443 .get_tag_protocol = ksz9477_get_tag_protocol, 1444 .setup = ksz9477_setup, 1445 .phy_read = ksz9477_phy_read16, 1446 .phy_write = ksz9477_phy_write16, 1447 .phylink_mac_link_down = ksz_mac_link_down, 1448 .port_enable = ksz_enable_port, 1449 .get_strings = ksz9477_get_strings, 1450 .get_ethtool_stats = ksz_get_ethtool_stats, 1451 .get_sset_count = ksz_sset_count, 1452 .port_bridge_join = ksz_port_bridge_join, 1453 .port_bridge_leave = ksz_port_bridge_leave, 1454 .port_stp_state_set = ksz9477_port_stp_state_set, 1455 .port_fast_age = ksz_port_fast_age, 1456 .port_vlan_filtering = ksz9477_port_vlan_filtering, 1457 .port_vlan_add = ksz9477_port_vlan_add, 1458 .port_vlan_del = ksz9477_port_vlan_del, 1459 .port_fdb_dump = ksz9477_port_fdb_dump, 1460 .port_fdb_add = ksz9477_port_fdb_add, 1461 .port_fdb_del = ksz9477_port_fdb_del, 1462 .port_mdb_add = ksz9477_port_mdb_add, 1463 .port_mdb_del = ksz9477_port_mdb_del, 1464 .port_mirror_add = ksz9477_port_mirror_add, 1465 .port_mirror_del = ksz9477_port_mirror_del, 1466 .get_stats64 = ksz9477_get_stats64, 1467 }; 1468 1469 static u32 ksz9477_get_port_addr(int port, int offset) 1470 { 1471 return PORT_CTRL_ADDR(port, offset); 1472 } 1473 1474 static int ksz9477_switch_detect(struct ksz_device *dev) 1475 { 1476 u8 data8; 1477 u8 id_hi; 1478 u8 id_lo; 1479 u32 id32; 1480 int ret; 1481 1482 /* turn off SPI DO Edge select */ 1483 ret = ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8); 1484 if (ret) 1485 return ret; 1486 1487 data8 &= ~SPI_AUTO_EDGE_DETECTION; 1488 ret = ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8); 1489 if (ret) 1490 return ret; 1491 1492 /* read chip id */ 1493 ret = ksz_read32(dev, REG_CHIP_ID0__1, &id32); 1494 if (ret) 1495 return ret; 1496 ret = ksz_read8(dev, REG_GLOBAL_OPTIONS, &data8); 1497 if (ret) 1498 return ret; 1499 1500 /* Number of ports can be reduced depending on chip. */ 1501 dev->phy_port_cnt = 5; 1502 1503 /* Default capability is gigabit capable. */ 1504 dev->features = GBIT_SUPPORT; 1505 1506 dev_dbg(dev->dev, "Switch detect: ID=%08x%02x\n", id32, data8); 1507 id_hi = (u8)(id32 >> 16); 1508 id_lo = (u8)(id32 >> 8); 1509 if ((id_lo & 0xf) == 3) { 1510 /* Chip is from KSZ9893 design. */ 1511 dev_info(dev->dev, "Found KSZ9893\n"); 1512 dev->features |= IS_9893; 1513 1514 /* Chip does not support gigabit. */ 1515 if (data8 & SW_QW_ABLE) 1516 dev->features &= ~GBIT_SUPPORT; 1517 dev->phy_port_cnt = 2; 1518 } else { 1519 dev_info(dev->dev, "Found KSZ9477 or compatible\n"); 1520 /* Chip uses new XMII register definitions. */ 1521 dev->features |= NEW_XMII; 1522 1523 /* Chip does not support gigabit. */ 1524 if (!(data8 & SW_GIGABIT_ABLE)) 1525 dev->features &= ~GBIT_SUPPORT; 1526 } 1527 1528 /* Change chip id to known ones so it can be matched against them. */ 1529 id32 = (id_hi << 16) | (id_lo << 8); 1530 1531 dev->chip_id = id32; 1532 1533 return 0; 1534 } 1535 1536 struct ksz_chip_data { 1537 u32 chip_id; 1538 const char *dev_name; 1539 int num_vlans; 1540 int num_alus; 1541 int num_statics; 1542 int cpu_ports; 1543 int port_cnt; 1544 bool phy_errata_9477; 1545 }; 1546 1547 static const struct ksz_chip_data ksz9477_switch_chips[] = { 1548 { 1549 .chip_id = 0x00947700, 1550 .dev_name = "KSZ9477", 1551 .num_vlans = 4096, 1552 .num_alus = 4096, 1553 .num_statics = 16, 1554 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1555 .port_cnt = 7, /* total physical port count */ 1556 .phy_errata_9477 = true, 1557 }, 1558 { 1559 .chip_id = 0x00989700, 1560 .dev_name = "KSZ9897", 1561 .num_vlans = 4096, 1562 .num_alus = 4096, 1563 .num_statics = 16, 1564 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1565 .port_cnt = 7, /* total physical port count */ 1566 .phy_errata_9477 = true, 1567 }, 1568 { 1569 .chip_id = 0x00989300, 1570 .dev_name = "KSZ9893", 1571 .num_vlans = 4096, 1572 .num_alus = 4096, 1573 .num_statics = 16, 1574 .cpu_ports = 0x07, /* can be configured as cpu port */ 1575 .port_cnt = 3, /* total port count */ 1576 }, 1577 { 1578 .chip_id = 0x00956700, 1579 .dev_name = "KSZ9567", 1580 .num_vlans = 4096, 1581 .num_alus = 4096, 1582 .num_statics = 16, 1583 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1584 .port_cnt = 7, /* total physical port count */ 1585 .phy_errata_9477 = true, 1586 }, 1587 }; 1588 1589 static int ksz9477_switch_init(struct ksz_device *dev) 1590 { 1591 int i; 1592 1593 dev->ds->ops = &ksz9477_switch_ops; 1594 1595 for (i = 0; i < ARRAY_SIZE(ksz9477_switch_chips); i++) { 1596 const struct ksz_chip_data *chip = &ksz9477_switch_chips[i]; 1597 1598 if (dev->chip_id == chip->chip_id) { 1599 dev->name = chip->dev_name; 1600 dev->num_vlans = chip->num_vlans; 1601 dev->num_alus = chip->num_alus; 1602 dev->num_statics = chip->num_statics; 1603 dev->port_cnt = chip->port_cnt; 1604 dev->cpu_ports = chip->cpu_ports; 1605 dev->phy_errata_9477 = chip->phy_errata_9477; 1606 1607 break; 1608 } 1609 } 1610 1611 /* no switch found */ 1612 if (!dev->port_cnt) 1613 return -ENODEV; 1614 1615 dev->port_mask = (1 << dev->port_cnt) - 1; 1616 1617 dev->reg_mib_cnt = SWITCH_COUNTER_NUM; 1618 dev->mib_cnt = TOTAL_SWITCH_COUNTER_NUM; 1619 1620 dev->ports = devm_kzalloc(dev->dev, 1621 dev->port_cnt * sizeof(struct ksz_port), 1622 GFP_KERNEL); 1623 if (!dev->ports) 1624 return -ENOMEM; 1625 for (i = 0; i < dev->port_cnt; i++) { 1626 spin_lock_init(&dev->ports[i].mib.stats64_lock); 1627 mutex_init(&dev->ports[i].mib.cnt_mutex); 1628 dev->ports[i].mib.counters = 1629 devm_kzalloc(dev->dev, 1630 sizeof(u64) * 1631 (TOTAL_SWITCH_COUNTER_NUM + 1), 1632 GFP_KERNEL); 1633 if (!dev->ports[i].mib.counters) 1634 return -ENOMEM; 1635 } 1636 1637 /* set the real number of ports */ 1638 dev->ds->num_ports = dev->port_cnt; 1639 1640 return 0; 1641 } 1642 1643 static void ksz9477_switch_exit(struct ksz_device *dev) 1644 { 1645 ksz9477_reset_switch(dev); 1646 } 1647 1648 static const struct ksz_dev_ops ksz9477_dev_ops = { 1649 .get_port_addr = ksz9477_get_port_addr, 1650 .cfg_port_member = ksz9477_cfg_port_member, 1651 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 1652 .port_setup = ksz9477_port_setup, 1653 .r_mib_cnt = ksz9477_r_mib_cnt, 1654 .r_mib_pkt = ksz9477_r_mib_pkt, 1655 .r_mib_stat64 = ksz9477_r_mib_stats64, 1656 .freeze_mib = ksz9477_freeze_mib, 1657 .port_init_cnt = ksz9477_port_init_cnt, 1658 .shutdown = ksz9477_reset_switch, 1659 .detect = ksz9477_switch_detect, 1660 .init = ksz9477_switch_init, 1661 .exit = ksz9477_switch_exit, 1662 }; 1663 1664 int ksz9477_switch_register(struct ksz_device *dev) 1665 { 1666 int ret, i; 1667 struct phy_device *phydev; 1668 1669 ret = ksz_switch_register(dev, &ksz9477_dev_ops); 1670 if (ret) 1671 return ret; 1672 1673 for (i = 0; i < dev->phy_port_cnt; ++i) { 1674 if (!dsa_is_user_port(dev->ds, i)) 1675 continue; 1676 1677 phydev = dsa_to_port(dev->ds, i)->slave->phydev; 1678 1679 /* The MAC actually cannot run in 1000 half-duplex mode. */ 1680 phy_remove_link_mode(phydev, 1681 ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1682 1683 /* PHY does not support gigabit. */ 1684 if (!(dev->features & GBIT_SUPPORT)) 1685 phy_remove_link_mode(phydev, 1686 ETHTOOL_LINK_MODE_1000baseT_Full_BIT); 1687 } 1688 return ret; 1689 } 1690 EXPORT_SYMBOL(ksz9477_switch_register); 1691 1692 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 1693 MODULE_DESCRIPTION("Microchip KSZ9477 Series Switch DSA Driver"); 1694 MODULE_LICENSE("GPL"); 1695