1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip KSZ9477 switch driver main logic 4 * 5 * Copyright (C) 2017-2019 Microchip Technology Inc. 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/iopoll.h> 11 #include <linux/platform_data/microchip-ksz.h> 12 #include <linux/phy.h> 13 #include <linux/if_bridge.h> 14 #include <net/dsa.h> 15 #include <net/switchdev.h> 16 17 #include "ksz_priv.h" 18 #include "ksz9477_reg.h" 19 #include "ksz_common.h" 20 21 /* Used with variable features to indicate capabilities. */ 22 #define GBIT_SUPPORT BIT(0) 23 #define NEW_XMII BIT(1) 24 #define IS_9893 BIT(2) 25 26 static const struct { 27 int index; 28 char string[ETH_GSTRING_LEN]; 29 } ksz9477_mib_names[TOTAL_SWITCH_COUNTER_NUM] = { 30 { 0x00, "rx_hi" }, 31 { 0x01, "rx_undersize" }, 32 { 0x02, "rx_fragments" }, 33 { 0x03, "rx_oversize" }, 34 { 0x04, "rx_jabbers" }, 35 { 0x05, "rx_symbol_err" }, 36 { 0x06, "rx_crc_err" }, 37 { 0x07, "rx_align_err" }, 38 { 0x08, "rx_mac_ctrl" }, 39 { 0x09, "rx_pause" }, 40 { 0x0A, "rx_bcast" }, 41 { 0x0B, "rx_mcast" }, 42 { 0x0C, "rx_ucast" }, 43 { 0x0D, "rx_64_or_less" }, 44 { 0x0E, "rx_65_127" }, 45 { 0x0F, "rx_128_255" }, 46 { 0x10, "rx_256_511" }, 47 { 0x11, "rx_512_1023" }, 48 { 0x12, "rx_1024_1522" }, 49 { 0x13, "rx_1523_2000" }, 50 { 0x14, "rx_2001" }, 51 { 0x15, "tx_hi" }, 52 { 0x16, "tx_late_col" }, 53 { 0x17, "tx_pause" }, 54 { 0x18, "tx_bcast" }, 55 { 0x19, "tx_mcast" }, 56 { 0x1A, "tx_ucast" }, 57 { 0x1B, "tx_deferred" }, 58 { 0x1C, "tx_total_col" }, 59 { 0x1D, "tx_exc_col" }, 60 { 0x1E, "tx_single_col" }, 61 { 0x1F, "tx_mult_col" }, 62 { 0x80, "rx_total" }, 63 { 0x81, "tx_total" }, 64 { 0x82, "rx_discards" }, 65 { 0x83, "tx_discards" }, 66 }; 67 68 static void ksz9477_cfg32(struct ksz_device *dev, u32 addr, u32 bits, bool set) 69 { 70 u32 data; 71 72 ksz_read32(dev, addr, &data); 73 if (set) 74 data |= bits; 75 else 76 data &= ~bits; 77 ksz_write32(dev, addr, data); 78 } 79 80 static void ksz9477_port_cfg32(struct ksz_device *dev, int port, int offset, 81 u32 bits, bool set) 82 { 83 u32 addr; 84 u32 data; 85 86 addr = PORT_CTRL_ADDR(port, offset); 87 ksz_read32(dev, addr, &data); 88 89 if (set) 90 data |= bits; 91 else 92 data &= ~bits; 93 94 ksz_write32(dev, addr, data); 95 } 96 97 static int ksz9477_wait_vlan_ctrl_ready(struct ksz_device *dev, u32 waiton, 98 int timeout) 99 { 100 u8 data; 101 102 do { 103 ksz_read8(dev, REG_SW_VLAN_CTRL, &data); 104 if (!(data & waiton)) 105 break; 106 usleep_range(1, 10); 107 } while (timeout-- > 0); 108 109 if (timeout <= 0) 110 return -ETIMEDOUT; 111 112 return 0; 113 } 114 115 static int ksz9477_get_vlan_table(struct ksz_device *dev, u16 vid, 116 u32 *vlan_table) 117 { 118 int ret; 119 120 mutex_lock(&dev->vlan_mutex); 121 122 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 123 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_READ | VLAN_START); 124 125 /* wait to be cleared */ 126 ret = ksz9477_wait_vlan_ctrl_ready(dev, VLAN_START, 1000); 127 if (ret < 0) { 128 dev_dbg(dev->dev, "Failed to read vlan table\n"); 129 goto exit; 130 } 131 132 ksz_read32(dev, REG_SW_VLAN_ENTRY__4, &vlan_table[0]); 133 ksz_read32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, &vlan_table[1]); 134 ksz_read32(dev, REG_SW_VLAN_ENTRY_PORTS__4, &vlan_table[2]); 135 136 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 137 138 exit: 139 mutex_unlock(&dev->vlan_mutex); 140 141 return ret; 142 } 143 144 static int ksz9477_set_vlan_table(struct ksz_device *dev, u16 vid, 145 u32 *vlan_table) 146 { 147 int ret; 148 149 mutex_lock(&dev->vlan_mutex); 150 151 ksz_write32(dev, REG_SW_VLAN_ENTRY__4, vlan_table[0]); 152 ksz_write32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, vlan_table[1]); 153 ksz_write32(dev, REG_SW_VLAN_ENTRY_PORTS__4, vlan_table[2]); 154 155 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 156 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_START | VLAN_WRITE); 157 158 /* wait to be cleared */ 159 ret = ksz9477_wait_vlan_ctrl_ready(dev, VLAN_START, 1000); 160 if (ret < 0) { 161 dev_dbg(dev->dev, "Failed to write vlan table\n"); 162 goto exit; 163 } 164 165 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 166 167 /* update vlan cache table */ 168 dev->vlan_cache[vid].table[0] = vlan_table[0]; 169 dev->vlan_cache[vid].table[1] = vlan_table[1]; 170 dev->vlan_cache[vid].table[2] = vlan_table[2]; 171 172 exit: 173 mutex_unlock(&dev->vlan_mutex); 174 175 return ret; 176 } 177 178 static void ksz9477_read_table(struct ksz_device *dev, u32 *table) 179 { 180 ksz_read32(dev, REG_SW_ALU_VAL_A, &table[0]); 181 ksz_read32(dev, REG_SW_ALU_VAL_B, &table[1]); 182 ksz_read32(dev, REG_SW_ALU_VAL_C, &table[2]); 183 ksz_read32(dev, REG_SW_ALU_VAL_D, &table[3]); 184 } 185 186 static void ksz9477_write_table(struct ksz_device *dev, u32 *table) 187 { 188 ksz_write32(dev, REG_SW_ALU_VAL_A, table[0]); 189 ksz_write32(dev, REG_SW_ALU_VAL_B, table[1]); 190 ksz_write32(dev, REG_SW_ALU_VAL_C, table[2]); 191 ksz_write32(dev, REG_SW_ALU_VAL_D, table[3]); 192 } 193 194 static int ksz9477_wait_alu_ready(struct ksz_device *dev, u32 waiton, 195 int timeout) 196 { 197 u32 data; 198 199 do { 200 ksz_read32(dev, REG_SW_ALU_CTRL__4, &data); 201 if (!(data & waiton)) 202 break; 203 usleep_range(1, 10); 204 } while (timeout-- > 0); 205 206 if (timeout <= 0) 207 return -ETIMEDOUT; 208 209 return 0; 210 } 211 212 static int ksz9477_wait_alu_sta_ready(struct ksz_device *dev, u32 waiton, 213 int timeout) 214 { 215 u32 data; 216 217 do { 218 ksz_read32(dev, REG_SW_ALU_STAT_CTRL__4, &data); 219 if (!(data & waiton)) 220 break; 221 usleep_range(1, 10); 222 } while (timeout-- > 0); 223 224 if (timeout <= 0) 225 return -ETIMEDOUT; 226 227 return 0; 228 } 229 230 static int ksz9477_reset_switch(struct ksz_device *dev) 231 { 232 u8 data8; 233 u16 data16; 234 u32 data32; 235 236 /* reset switch */ 237 ksz_cfg(dev, REG_SW_OPERATION, SW_RESET, true); 238 239 /* turn off SPI DO Edge select */ 240 ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8); 241 data8 &= ~SPI_AUTO_EDGE_DETECTION; 242 ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8); 243 244 /* default configuration */ 245 ksz_read8(dev, REG_SW_LUE_CTRL_1, &data8); 246 data8 = SW_AGING_ENABLE | SW_LINK_AUTO_AGING | 247 SW_SRC_ADDR_FILTER | SW_FLUSH_STP_TABLE | SW_FLUSH_MSTP_TABLE; 248 ksz_write8(dev, REG_SW_LUE_CTRL_1, data8); 249 250 /* disable interrupts */ 251 ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK); 252 ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0x7F); 253 ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32); 254 255 /* set broadcast storm protection 10% rate */ 256 ksz_read16(dev, REG_SW_MAC_CTRL_2, &data16); 257 data16 &= ~BROADCAST_STORM_RATE; 258 data16 |= (BROADCAST_STORM_VALUE * BROADCAST_STORM_PROT_RATE) / 100; 259 ksz_write16(dev, REG_SW_MAC_CTRL_2, data16); 260 261 if (dev->synclko_125) 262 ksz_write8(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1, 263 SW_ENABLE_REFCLKO | SW_REFCLKO_IS_125MHZ); 264 265 return 0; 266 } 267 268 static void ksz9477_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, 269 u64 *cnt) 270 { 271 struct ksz_poll_ctx ctx = { 272 .dev = dev, 273 .port = port, 274 .offset = REG_PORT_MIB_CTRL_STAT__4, 275 }; 276 struct ksz_port *p = &dev->ports[port]; 277 u32 data; 278 int ret; 279 280 /* retain the flush/freeze bit */ 281 data = p->freeze ? MIB_COUNTER_FLUSH_FREEZE : 0; 282 data |= MIB_COUNTER_READ; 283 data |= (addr << MIB_COUNTER_INDEX_S); 284 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, data); 285 286 ret = readx_poll_timeout(ksz_pread32_poll, &ctx, data, 287 !(data & MIB_COUNTER_READ), 10, 1000); 288 289 /* failed to read MIB. get out of loop */ 290 if (ret < 0) { 291 dev_dbg(dev->dev, "Failed to get MIB\n"); 292 return; 293 } 294 295 /* count resets upon read */ 296 ksz_pread32(dev, port, REG_PORT_MIB_DATA, &data); 297 *cnt += data; 298 } 299 300 static void ksz9477_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 301 u64 *dropped, u64 *cnt) 302 { 303 addr = ksz9477_mib_names[addr].index; 304 ksz9477_r_mib_cnt(dev, port, addr, cnt); 305 } 306 307 static void ksz9477_freeze_mib(struct ksz_device *dev, int port, bool freeze) 308 { 309 u32 val = freeze ? MIB_COUNTER_FLUSH_FREEZE : 0; 310 struct ksz_port *p = &dev->ports[port]; 311 312 /* enable/disable the port for flush/freeze function */ 313 mutex_lock(&p->mib.cnt_mutex); 314 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, val); 315 316 /* used by MIB counter reading code to know freeze is enabled */ 317 p->freeze = freeze; 318 mutex_unlock(&p->mib.cnt_mutex); 319 } 320 321 static void ksz9477_port_init_cnt(struct ksz_device *dev, int port) 322 { 323 struct ksz_port_mib *mib = &dev->ports[port].mib; 324 325 /* flush all enabled port MIB counters */ 326 mutex_lock(&mib->cnt_mutex); 327 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 328 MIB_COUNTER_FLUSH_FREEZE); 329 ksz_write8(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FLUSH); 330 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 0); 331 mutex_unlock(&mib->cnt_mutex); 332 333 mib->cnt_ptr = 0; 334 memset(mib->counters, 0, dev->mib_cnt * sizeof(u64)); 335 } 336 337 static enum dsa_tag_protocol ksz9477_get_tag_protocol(struct dsa_switch *ds, 338 int port) 339 { 340 enum dsa_tag_protocol proto = DSA_TAG_PROTO_KSZ9477; 341 struct ksz_device *dev = ds->priv; 342 343 if (dev->features & IS_9893) 344 proto = DSA_TAG_PROTO_KSZ9893; 345 return proto; 346 } 347 348 static int ksz9477_phy_read16(struct dsa_switch *ds, int addr, int reg) 349 { 350 struct ksz_device *dev = ds->priv; 351 u16 val = 0xffff; 352 353 /* No real PHY after this. Simulate the PHY. 354 * A fixed PHY can be setup in the device tree, but this function is 355 * still called for that port during initialization. 356 * For RGMII PHY there is no way to access it so the fixed PHY should 357 * be used. For SGMII PHY the supporting code will be added later. 358 */ 359 if (addr >= dev->phy_port_cnt) { 360 struct ksz_port *p = &dev->ports[addr]; 361 362 switch (reg) { 363 case MII_BMCR: 364 val = 0x1140; 365 break; 366 case MII_BMSR: 367 val = 0x796d; 368 break; 369 case MII_PHYSID1: 370 val = 0x0022; 371 break; 372 case MII_PHYSID2: 373 val = 0x1631; 374 break; 375 case MII_ADVERTISE: 376 val = 0x05e1; 377 break; 378 case MII_LPA: 379 val = 0xc5e1; 380 break; 381 case MII_CTRL1000: 382 val = 0x0700; 383 break; 384 case MII_STAT1000: 385 if (p->phydev.speed == SPEED_1000) 386 val = 0x3800; 387 else 388 val = 0; 389 break; 390 } 391 } else { 392 ksz_pread16(dev, addr, 0x100 + (reg << 1), &val); 393 } 394 395 return val; 396 } 397 398 static int ksz9477_phy_write16(struct dsa_switch *ds, int addr, int reg, 399 u16 val) 400 { 401 struct ksz_device *dev = ds->priv; 402 403 /* No real PHY after this. */ 404 if (addr >= dev->phy_port_cnt) 405 return 0; 406 407 /* No gigabit support. Do not write to this register. */ 408 if (!(dev->features & GBIT_SUPPORT) && reg == MII_CTRL1000) 409 return 0; 410 ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val); 411 412 return 0; 413 } 414 415 static void ksz9477_get_strings(struct dsa_switch *ds, int port, 416 u32 stringset, uint8_t *buf) 417 { 418 int i; 419 420 if (stringset != ETH_SS_STATS) 421 return; 422 423 for (i = 0; i < TOTAL_SWITCH_COUNTER_NUM; i++) { 424 memcpy(buf + i * ETH_GSTRING_LEN, ksz9477_mib_names[i].string, 425 ETH_GSTRING_LEN); 426 } 427 } 428 429 static void ksz9477_cfg_port_member(struct ksz_device *dev, int port, 430 u8 member) 431 { 432 ksz_pwrite32(dev, port, REG_PORT_VLAN_MEMBERSHIP__4, member); 433 dev->ports[port].member = member; 434 } 435 436 static void ksz9477_port_stp_state_set(struct dsa_switch *ds, int port, 437 u8 state) 438 { 439 struct ksz_device *dev = ds->priv; 440 struct ksz_port *p = &dev->ports[port]; 441 u8 data; 442 int member = -1; 443 int forward = dev->member; 444 445 ksz_pread8(dev, port, P_STP_CTRL, &data); 446 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 447 448 switch (state) { 449 case BR_STATE_DISABLED: 450 data |= PORT_LEARN_DISABLE; 451 if (port != dev->cpu_port) 452 member = 0; 453 break; 454 case BR_STATE_LISTENING: 455 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 456 if (port != dev->cpu_port && 457 p->stp_state == BR_STATE_DISABLED) 458 member = dev->host_mask | p->vid_member; 459 break; 460 case BR_STATE_LEARNING: 461 data |= PORT_RX_ENABLE; 462 break; 463 case BR_STATE_FORWARDING: 464 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 465 466 /* This function is also used internally. */ 467 if (port == dev->cpu_port) 468 break; 469 470 member = dev->host_mask | p->vid_member; 471 mutex_lock(&dev->dev_mutex); 472 473 /* Port is a member of a bridge. */ 474 if (dev->br_member & (1 << port)) { 475 dev->member |= (1 << port); 476 member = dev->member; 477 } 478 mutex_unlock(&dev->dev_mutex); 479 break; 480 case BR_STATE_BLOCKING: 481 data |= PORT_LEARN_DISABLE; 482 if (port != dev->cpu_port && 483 p->stp_state == BR_STATE_DISABLED) 484 member = dev->host_mask | p->vid_member; 485 break; 486 default: 487 dev_err(ds->dev, "invalid STP state: %d\n", state); 488 return; 489 } 490 491 ksz_pwrite8(dev, port, P_STP_CTRL, data); 492 p->stp_state = state; 493 mutex_lock(&dev->dev_mutex); 494 if (data & PORT_RX_ENABLE) 495 dev->rx_ports |= (1 << port); 496 else 497 dev->rx_ports &= ~(1 << port); 498 if (data & PORT_TX_ENABLE) 499 dev->tx_ports |= (1 << port); 500 else 501 dev->tx_ports &= ~(1 << port); 502 503 /* Port membership may share register with STP state. */ 504 if (member >= 0 && member != p->member) 505 ksz9477_cfg_port_member(dev, port, (u8)member); 506 507 /* Check if forwarding needs to be updated. */ 508 if (state != BR_STATE_FORWARDING) { 509 if (dev->br_member & (1 << port)) 510 dev->member &= ~(1 << port); 511 } 512 513 /* When topology has changed the function ksz_update_port_member 514 * should be called to modify port forwarding behavior. 515 */ 516 if (forward != dev->member) 517 ksz_update_port_member(dev, port); 518 mutex_unlock(&dev->dev_mutex); 519 } 520 521 static void ksz9477_flush_dyn_mac_table(struct ksz_device *dev, int port) 522 { 523 u8 data; 524 525 ksz_read8(dev, REG_SW_LUE_CTRL_2, &data); 526 data &= ~(SW_FLUSH_OPTION_M << SW_FLUSH_OPTION_S); 527 data |= (SW_FLUSH_OPTION_DYN_MAC << SW_FLUSH_OPTION_S); 528 ksz_write8(dev, REG_SW_LUE_CTRL_2, data); 529 if (port < dev->mib_port_cnt) { 530 /* flush individual port */ 531 ksz_pread8(dev, port, P_STP_CTRL, &data); 532 if (!(data & PORT_LEARN_DISABLE)) 533 ksz_pwrite8(dev, port, P_STP_CTRL, 534 data | PORT_LEARN_DISABLE); 535 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true); 536 ksz_pwrite8(dev, port, P_STP_CTRL, data); 537 } else { 538 /* flush all */ 539 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_STP_TABLE, true); 540 } 541 } 542 543 static int ksz9477_port_vlan_filtering(struct dsa_switch *ds, int port, 544 bool flag) 545 { 546 struct ksz_device *dev = ds->priv; 547 548 if (flag) { 549 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 550 PORT_VLAN_LOOKUP_VID_0, true); 551 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, true); 552 } else { 553 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, false); 554 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 555 PORT_VLAN_LOOKUP_VID_0, false); 556 } 557 558 return 0; 559 } 560 561 static void ksz9477_port_vlan_add(struct dsa_switch *ds, int port, 562 const struct switchdev_obj_port_vlan *vlan) 563 { 564 struct ksz_device *dev = ds->priv; 565 u32 vlan_table[3]; 566 u16 vid; 567 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 568 569 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 570 if (ksz9477_get_vlan_table(dev, vid, vlan_table)) { 571 dev_dbg(dev->dev, "Failed to get vlan table\n"); 572 return; 573 } 574 575 vlan_table[0] = VLAN_VALID | (vid & VLAN_FID_M); 576 if (untagged) 577 vlan_table[1] |= BIT(port); 578 else 579 vlan_table[1] &= ~BIT(port); 580 vlan_table[1] &= ~(BIT(dev->cpu_port)); 581 582 vlan_table[2] |= BIT(port) | BIT(dev->cpu_port); 583 584 if (ksz9477_set_vlan_table(dev, vid, vlan_table)) { 585 dev_dbg(dev->dev, "Failed to set vlan table\n"); 586 return; 587 } 588 589 /* change PVID */ 590 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) 591 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, vid); 592 } 593 } 594 595 static int ksz9477_port_vlan_del(struct dsa_switch *ds, int port, 596 const struct switchdev_obj_port_vlan *vlan) 597 { 598 struct ksz_device *dev = ds->priv; 599 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 600 u32 vlan_table[3]; 601 u16 vid; 602 u16 pvid; 603 604 ksz_pread16(dev, port, REG_PORT_DEFAULT_VID, &pvid); 605 pvid = pvid & 0xFFF; 606 607 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 608 if (ksz9477_get_vlan_table(dev, vid, vlan_table)) { 609 dev_dbg(dev->dev, "Failed to get vlan table\n"); 610 return -ETIMEDOUT; 611 } 612 613 vlan_table[2] &= ~BIT(port); 614 615 if (pvid == vid) 616 pvid = 1; 617 618 if (untagged) 619 vlan_table[1] &= ~BIT(port); 620 621 if (ksz9477_set_vlan_table(dev, vid, vlan_table)) { 622 dev_dbg(dev->dev, "Failed to set vlan table\n"); 623 return -ETIMEDOUT; 624 } 625 } 626 627 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, pvid); 628 629 return 0; 630 } 631 632 static int ksz9477_port_fdb_add(struct dsa_switch *ds, int port, 633 const unsigned char *addr, u16 vid) 634 { 635 struct ksz_device *dev = ds->priv; 636 u32 alu_table[4]; 637 u32 data; 638 int ret = 0; 639 640 mutex_lock(&dev->alu_mutex); 641 642 /* find any entry with mac & vid */ 643 data = vid << ALU_FID_INDEX_S; 644 data |= ((addr[0] << 8) | addr[1]); 645 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 646 647 data = ((addr[2] << 24) | (addr[3] << 16)); 648 data |= ((addr[4] << 8) | addr[5]); 649 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 650 651 /* start read operation */ 652 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 653 654 /* wait to be finished */ 655 ret = ksz9477_wait_alu_ready(dev, ALU_START, 1000); 656 if (ret < 0) { 657 dev_dbg(dev->dev, "Failed to read ALU\n"); 658 goto exit; 659 } 660 661 /* read ALU entry */ 662 ksz9477_read_table(dev, alu_table); 663 664 /* update ALU entry */ 665 alu_table[0] = ALU_V_STATIC_VALID; 666 alu_table[1] |= BIT(port); 667 if (vid) 668 alu_table[1] |= ALU_V_USE_FID; 669 alu_table[2] = (vid << ALU_V_FID_S); 670 alu_table[2] |= ((addr[0] << 8) | addr[1]); 671 alu_table[3] = ((addr[2] << 24) | (addr[3] << 16)); 672 alu_table[3] |= ((addr[4] << 8) | addr[5]); 673 674 ksz9477_write_table(dev, alu_table); 675 676 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 677 678 /* wait to be finished */ 679 ret = ksz9477_wait_alu_ready(dev, ALU_START, 1000); 680 if (ret < 0) 681 dev_dbg(dev->dev, "Failed to write ALU\n"); 682 683 exit: 684 mutex_unlock(&dev->alu_mutex); 685 686 return ret; 687 } 688 689 static int ksz9477_port_fdb_del(struct dsa_switch *ds, int port, 690 const unsigned char *addr, u16 vid) 691 { 692 struct ksz_device *dev = ds->priv; 693 u32 alu_table[4]; 694 u32 data; 695 int ret = 0; 696 697 mutex_lock(&dev->alu_mutex); 698 699 /* read any entry with mac & vid */ 700 data = vid << ALU_FID_INDEX_S; 701 data |= ((addr[0] << 8) | addr[1]); 702 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 703 704 data = ((addr[2] << 24) | (addr[3] << 16)); 705 data |= ((addr[4] << 8) | addr[5]); 706 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 707 708 /* start read operation */ 709 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 710 711 /* wait to be finished */ 712 ret = ksz9477_wait_alu_ready(dev, ALU_START, 1000); 713 if (ret < 0) { 714 dev_dbg(dev->dev, "Failed to read ALU\n"); 715 goto exit; 716 } 717 718 ksz_read32(dev, REG_SW_ALU_VAL_A, &alu_table[0]); 719 if (alu_table[0] & ALU_V_STATIC_VALID) { 720 ksz_read32(dev, REG_SW_ALU_VAL_B, &alu_table[1]); 721 ksz_read32(dev, REG_SW_ALU_VAL_C, &alu_table[2]); 722 ksz_read32(dev, REG_SW_ALU_VAL_D, &alu_table[3]); 723 724 /* clear forwarding port */ 725 alu_table[2] &= ~BIT(port); 726 727 /* if there is no port to forward, clear table */ 728 if ((alu_table[2] & ALU_V_PORT_MAP) == 0) { 729 alu_table[0] = 0; 730 alu_table[1] = 0; 731 alu_table[2] = 0; 732 alu_table[3] = 0; 733 } 734 } else { 735 alu_table[0] = 0; 736 alu_table[1] = 0; 737 alu_table[2] = 0; 738 alu_table[3] = 0; 739 } 740 741 ksz9477_write_table(dev, alu_table); 742 743 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 744 745 /* wait to be finished */ 746 ret = ksz9477_wait_alu_ready(dev, ALU_START, 1000); 747 if (ret < 0) 748 dev_dbg(dev->dev, "Failed to write ALU\n"); 749 750 exit: 751 mutex_unlock(&dev->alu_mutex); 752 753 return ret; 754 } 755 756 static void ksz9477_convert_alu(struct alu_struct *alu, u32 *alu_table) 757 { 758 alu->is_static = !!(alu_table[0] & ALU_V_STATIC_VALID); 759 alu->is_src_filter = !!(alu_table[0] & ALU_V_SRC_FILTER); 760 alu->is_dst_filter = !!(alu_table[0] & ALU_V_DST_FILTER); 761 alu->prio_age = (alu_table[0] >> ALU_V_PRIO_AGE_CNT_S) & 762 ALU_V_PRIO_AGE_CNT_M; 763 alu->mstp = alu_table[0] & ALU_V_MSTP_M; 764 765 alu->is_override = !!(alu_table[1] & ALU_V_OVERRIDE); 766 alu->is_use_fid = !!(alu_table[1] & ALU_V_USE_FID); 767 alu->port_forward = alu_table[1] & ALU_V_PORT_MAP; 768 769 alu->fid = (alu_table[2] >> ALU_V_FID_S) & ALU_V_FID_M; 770 771 alu->mac[0] = (alu_table[2] >> 8) & 0xFF; 772 alu->mac[1] = alu_table[2] & 0xFF; 773 alu->mac[2] = (alu_table[3] >> 24) & 0xFF; 774 alu->mac[3] = (alu_table[3] >> 16) & 0xFF; 775 alu->mac[4] = (alu_table[3] >> 8) & 0xFF; 776 alu->mac[5] = alu_table[3] & 0xFF; 777 } 778 779 static int ksz9477_port_fdb_dump(struct dsa_switch *ds, int port, 780 dsa_fdb_dump_cb_t *cb, void *data) 781 { 782 struct ksz_device *dev = ds->priv; 783 int ret = 0; 784 u32 ksz_data; 785 u32 alu_table[4]; 786 struct alu_struct alu; 787 int timeout; 788 789 mutex_lock(&dev->alu_mutex); 790 791 /* start ALU search */ 792 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_START | ALU_SEARCH); 793 794 do { 795 timeout = 1000; 796 do { 797 ksz_read32(dev, REG_SW_ALU_CTRL__4, &ksz_data); 798 if ((ksz_data & ALU_VALID) || !(ksz_data & ALU_START)) 799 break; 800 usleep_range(1, 10); 801 } while (timeout-- > 0); 802 803 if (!timeout) { 804 dev_dbg(dev->dev, "Failed to search ALU\n"); 805 ret = -ETIMEDOUT; 806 goto exit; 807 } 808 809 /* read ALU table */ 810 ksz9477_read_table(dev, alu_table); 811 812 ksz9477_convert_alu(&alu, alu_table); 813 814 if (alu.port_forward & BIT(port)) { 815 ret = cb(alu.mac, alu.fid, alu.is_static, data); 816 if (ret) 817 goto exit; 818 } 819 } while (ksz_data & ALU_START); 820 821 exit: 822 823 /* stop ALU search */ 824 ksz_write32(dev, REG_SW_ALU_CTRL__4, 0); 825 826 mutex_unlock(&dev->alu_mutex); 827 828 return ret; 829 } 830 831 static void ksz9477_port_mdb_add(struct dsa_switch *ds, int port, 832 const struct switchdev_obj_port_mdb *mdb) 833 { 834 struct ksz_device *dev = ds->priv; 835 u32 static_table[4]; 836 u32 data; 837 int index; 838 u32 mac_hi, mac_lo; 839 840 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 841 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 842 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 843 844 mutex_lock(&dev->alu_mutex); 845 846 for (index = 0; index < dev->num_statics; index++) { 847 /* find empty slot first */ 848 data = (index << ALU_STAT_INDEX_S) | 849 ALU_STAT_READ | ALU_STAT_START; 850 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 851 852 /* wait to be finished */ 853 if (ksz9477_wait_alu_sta_ready(dev, ALU_STAT_START, 1000) < 0) { 854 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 855 goto exit; 856 } 857 858 /* read ALU static table */ 859 ksz9477_read_table(dev, static_table); 860 861 if (static_table[0] & ALU_V_STATIC_VALID) { 862 /* check this has same vid & mac address */ 863 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 864 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 865 static_table[3] == mac_lo) { 866 /* found matching one */ 867 break; 868 } 869 } else { 870 /* found empty one */ 871 break; 872 } 873 } 874 875 /* no available entry */ 876 if (index == dev->num_statics) 877 goto exit; 878 879 /* add entry */ 880 static_table[0] = ALU_V_STATIC_VALID; 881 static_table[1] |= BIT(port); 882 if (mdb->vid) 883 static_table[1] |= ALU_V_USE_FID; 884 static_table[2] = (mdb->vid << ALU_V_FID_S); 885 static_table[2] |= mac_hi; 886 static_table[3] = mac_lo; 887 888 ksz9477_write_table(dev, static_table); 889 890 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START; 891 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 892 893 /* wait to be finished */ 894 if (ksz9477_wait_alu_sta_ready(dev, ALU_STAT_START, 1000) < 0) 895 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 896 897 exit: 898 mutex_unlock(&dev->alu_mutex); 899 } 900 901 static int ksz9477_port_mdb_del(struct dsa_switch *ds, int port, 902 const struct switchdev_obj_port_mdb *mdb) 903 { 904 struct ksz_device *dev = ds->priv; 905 u32 static_table[4]; 906 u32 data; 907 int index; 908 int ret = 0; 909 u32 mac_hi, mac_lo; 910 911 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 912 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 913 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 914 915 mutex_lock(&dev->alu_mutex); 916 917 for (index = 0; index < dev->num_statics; index++) { 918 /* find empty slot first */ 919 data = (index << ALU_STAT_INDEX_S) | 920 ALU_STAT_READ | ALU_STAT_START; 921 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 922 923 /* wait to be finished */ 924 ret = ksz9477_wait_alu_sta_ready(dev, ALU_STAT_START, 1000); 925 if (ret < 0) { 926 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 927 goto exit; 928 } 929 930 /* read ALU static table */ 931 ksz9477_read_table(dev, static_table); 932 933 if (static_table[0] & ALU_V_STATIC_VALID) { 934 /* check this has same vid & mac address */ 935 936 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 937 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 938 static_table[3] == mac_lo) { 939 /* found matching one */ 940 break; 941 } 942 } 943 } 944 945 /* no available entry */ 946 if (index == dev->num_statics) 947 goto exit; 948 949 /* clear port */ 950 static_table[1] &= ~BIT(port); 951 952 if ((static_table[1] & ALU_V_PORT_MAP) == 0) { 953 /* delete entry */ 954 static_table[0] = 0; 955 static_table[1] = 0; 956 static_table[2] = 0; 957 static_table[3] = 0; 958 } 959 960 ksz9477_write_table(dev, static_table); 961 962 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START; 963 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 964 965 /* wait to be finished */ 966 ret = ksz9477_wait_alu_sta_ready(dev, ALU_STAT_START, 1000); 967 if (ret < 0) 968 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 969 970 exit: 971 mutex_unlock(&dev->alu_mutex); 972 973 return ret; 974 } 975 976 static int ksz9477_port_mirror_add(struct dsa_switch *ds, int port, 977 struct dsa_mall_mirror_tc_entry *mirror, 978 bool ingress) 979 { 980 struct ksz_device *dev = ds->priv; 981 982 if (ingress) 983 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true); 984 else 985 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true); 986 987 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false); 988 989 /* configure mirror port */ 990 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 991 PORT_MIRROR_SNIFFER, true); 992 993 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false); 994 995 return 0; 996 } 997 998 static void ksz9477_port_mirror_del(struct dsa_switch *ds, int port, 999 struct dsa_mall_mirror_tc_entry *mirror) 1000 { 1001 struct ksz_device *dev = ds->priv; 1002 u8 data; 1003 1004 if (mirror->ingress) 1005 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false); 1006 else 1007 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false); 1008 1009 ksz_pread8(dev, port, P_MIRROR_CTRL, &data); 1010 1011 if (!(data & (PORT_MIRROR_RX | PORT_MIRROR_TX))) 1012 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 1013 PORT_MIRROR_SNIFFER, false); 1014 } 1015 1016 static void ksz9477_phy_setup(struct ksz_device *dev, int port, 1017 struct phy_device *phy) 1018 { 1019 /* Only apply to port with PHY. */ 1020 if (port >= dev->phy_port_cnt) 1021 return; 1022 1023 /* The MAC actually cannot run in 1000 half-duplex mode. */ 1024 phy_remove_link_mode(phy, 1025 ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1026 1027 /* PHY does not support gigabit. */ 1028 if (!(dev->features & GBIT_SUPPORT)) 1029 phy_remove_link_mode(phy, 1030 ETHTOOL_LINK_MODE_1000baseT_Full_BIT); 1031 } 1032 1033 static bool ksz9477_get_gbit(struct ksz_device *dev, u8 data) 1034 { 1035 bool gbit; 1036 1037 if (dev->features & NEW_XMII) 1038 gbit = !(data & PORT_MII_NOT_1GBIT); 1039 else 1040 gbit = !!(data & PORT_MII_1000MBIT_S1); 1041 return gbit; 1042 } 1043 1044 static void ksz9477_set_gbit(struct ksz_device *dev, bool gbit, u8 *data) 1045 { 1046 if (dev->features & NEW_XMII) { 1047 if (gbit) 1048 *data &= ~PORT_MII_NOT_1GBIT; 1049 else 1050 *data |= PORT_MII_NOT_1GBIT; 1051 } else { 1052 if (gbit) 1053 *data |= PORT_MII_1000MBIT_S1; 1054 else 1055 *data &= ~PORT_MII_1000MBIT_S1; 1056 } 1057 } 1058 1059 static int ksz9477_get_xmii(struct ksz_device *dev, u8 data) 1060 { 1061 int mode; 1062 1063 if (dev->features & NEW_XMII) { 1064 switch (data & PORT_MII_SEL_M) { 1065 case PORT_MII_SEL: 1066 mode = 0; 1067 break; 1068 case PORT_RMII_SEL: 1069 mode = 1; 1070 break; 1071 case PORT_GMII_SEL: 1072 mode = 2; 1073 break; 1074 default: 1075 mode = 3; 1076 } 1077 } else { 1078 switch (data & PORT_MII_SEL_M) { 1079 case PORT_MII_SEL_S1: 1080 mode = 0; 1081 break; 1082 case PORT_RMII_SEL_S1: 1083 mode = 1; 1084 break; 1085 case PORT_GMII_SEL_S1: 1086 mode = 2; 1087 break; 1088 default: 1089 mode = 3; 1090 } 1091 } 1092 return mode; 1093 } 1094 1095 static void ksz9477_set_xmii(struct ksz_device *dev, int mode, u8 *data) 1096 { 1097 u8 xmii; 1098 1099 if (dev->features & NEW_XMII) { 1100 switch (mode) { 1101 case 0: 1102 xmii = PORT_MII_SEL; 1103 break; 1104 case 1: 1105 xmii = PORT_RMII_SEL; 1106 break; 1107 case 2: 1108 xmii = PORT_GMII_SEL; 1109 break; 1110 default: 1111 xmii = PORT_RGMII_SEL; 1112 break; 1113 } 1114 } else { 1115 switch (mode) { 1116 case 0: 1117 xmii = PORT_MII_SEL_S1; 1118 break; 1119 case 1: 1120 xmii = PORT_RMII_SEL_S1; 1121 break; 1122 case 2: 1123 xmii = PORT_GMII_SEL_S1; 1124 break; 1125 default: 1126 xmii = PORT_RGMII_SEL_S1; 1127 break; 1128 } 1129 } 1130 *data &= ~PORT_MII_SEL_M; 1131 *data |= xmii; 1132 } 1133 1134 static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port) 1135 { 1136 phy_interface_t interface; 1137 bool gbit; 1138 int mode; 1139 u8 data8; 1140 1141 if (port < dev->phy_port_cnt) 1142 return PHY_INTERFACE_MODE_NA; 1143 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8); 1144 gbit = ksz9477_get_gbit(dev, data8); 1145 mode = ksz9477_get_xmii(dev, data8); 1146 switch (mode) { 1147 case 2: 1148 interface = PHY_INTERFACE_MODE_GMII; 1149 if (gbit) 1150 break; 1151 /* fall through */ 1152 case 0: 1153 interface = PHY_INTERFACE_MODE_MII; 1154 break; 1155 case 1: 1156 interface = PHY_INTERFACE_MODE_RMII; 1157 break; 1158 default: 1159 interface = PHY_INTERFACE_MODE_RGMII; 1160 if (data8 & PORT_RGMII_ID_EG_ENABLE) 1161 interface = PHY_INTERFACE_MODE_RGMII_TXID; 1162 if (data8 & PORT_RGMII_ID_IG_ENABLE) { 1163 interface = PHY_INTERFACE_MODE_RGMII_RXID; 1164 if (data8 & PORT_RGMII_ID_EG_ENABLE) 1165 interface = PHY_INTERFACE_MODE_RGMII_ID; 1166 } 1167 break; 1168 } 1169 return interface; 1170 } 1171 1172 static void ksz9477_port_mmd_write(struct ksz_device *dev, int port, 1173 u8 dev_addr, u16 reg_addr, u16 val) 1174 { 1175 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, 1176 MMD_SETUP(PORT_MMD_OP_INDEX, dev_addr)); 1177 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, reg_addr); 1178 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, 1179 MMD_SETUP(PORT_MMD_OP_DATA_NO_INCR, dev_addr)); 1180 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, val); 1181 } 1182 1183 static void ksz9477_phy_errata_setup(struct ksz_device *dev, int port) 1184 { 1185 /* Apply PHY settings to address errata listed in 1186 * KSZ9477, KSZ9897, KSZ9896, KSZ9567, KSZ8565 1187 * Silicon Errata and Data Sheet Clarification documents: 1188 * 1189 * Register settings are needed to improve PHY receive performance 1190 */ 1191 ksz9477_port_mmd_write(dev, port, 0x01, 0x6f, 0xdd0b); 1192 ksz9477_port_mmd_write(dev, port, 0x01, 0x8f, 0x6032); 1193 ksz9477_port_mmd_write(dev, port, 0x01, 0x9d, 0x248c); 1194 ksz9477_port_mmd_write(dev, port, 0x01, 0x75, 0x0060); 1195 ksz9477_port_mmd_write(dev, port, 0x01, 0xd3, 0x7777); 1196 ksz9477_port_mmd_write(dev, port, 0x1c, 0x06, 0x3008); 1197 ksz9477_port_mmd_write(dev, port, 0x1c, 0x08, 0x2001); 1198 1199 /* Transmit waveform amplitude can be improved 1200 * (1000BASE-T, 100BASE-TX, 10BASE-Te) 1201 */ 1202 ksz9477_port_mmd_write(dev, port, 0x1c, 0x04, 0x00d0); 1203 1204 /* Energy Efficient Ethernet (EEE) feature select must 1205 * be manually disabled (except on KSZ8565 which is 100Mbit) 1206 */ 1207 if (dev->features & GBIT_SUPPORT) 1208 ksz9477_port_mmd_write(dev, port, 0x07, 0x3c, 0x0000); 1209 1210 /* Register settings are required to meet data sheet 1211 * supply current specifications 1212 */ 1213 ksz9477_port_mmd_write(dev, port, 0x1c, 0x13, 0x6eff); 1214 ksz9477_port_mmd_write(dev, port, 0x1c, 0x14, 0xe6ff); 1215 ksz9477_port_mmd_write(dev, port, 0x1c, 0x15, 0x6eff); 1216 ksz9477_port_mmd_write(dev, port, 0x1c, 0x16, 0xe6ff); 1217 ksz9477_port_mmd_write(dev, port, 0x1c, 0x17, 0x00ff); 1218 ksz9477_port_mmd_write(dev, port, 0x1c, 0x18, 0x43ff); 1219 ksz9477_port_mmd_write(dev, port, 0x1c, 0x19, 0xc3ff); 1220 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1a, 0x6fff); 1221 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1b, 0x07ff); 1222 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1c, 0x0fff); 1223 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1d, 0xe7ff); 1224 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1e, 0xefff); 1225 ksz9477_port_mmd_write(dev, port, 0x1c, 0x20, 0xeeee); 1226 } 1227 1228 static void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port) 1229 { 1230 u8 data8; 1231 u8 member; 1232 u16 data16; 1233 struct ksz_port *p = &dev->ports[port]; 1234 1235 /* enable tag tail for host port */ 1236 if (cpu_port) 1237 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_TAIL_TAG_ENABLE, 1238 true); 1239 1240 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_MAC_LOOPBACK, false); 1241 1242 /* set back pressure */ 1243 ksz_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, true); 1244 1245 /* enable broadcast storm limit */ 1246 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true); 1247 1248 /* disable DiffServ priority */ 1249 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_PRIO_ENABLE, false); 1250 1251 /* replace priority */ 1252 ksz_port_cfg(dev, port, REG_PORT_MRI_MAC_CTRL, PORT_USER_PRIO_CEILING, 1253 false); 1254 ksz9477_port_cfg32(dev, port, REG_PORT_MTI_QUEUE_CTRL_0__4, 1255 MTI_PVID_REPLACE, false); 1256 1257 /* enable 802.1p priority */ 1258 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true); 1259 1260 if (port < dev->phy_port_cnt) { 1261 /* do not force flow control */ 1262 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, 1263 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, 1264 false); 1265 1266 if (dev->phy_errata_9477) 1267 ksz9477_phy_errata_setup(dev, port); 1268 } else { 1269 /* force flow control */ 1270 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, 1271 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, 1272 true); 1273 1274 /* configure MAC to 1G & RGMII mode */ 1275 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8); 1276 switch (dev->interface) { 1277 case PHY_INTERFACE_MODE_MII: 1278 ksz9477_set_xmii(dev, 0, &data8); 1279 ksz9477_set_gbit(dev, false, &data8); 1280 p->phydev.speed = SPEED_100; 1281 break; 1282 case PHY_INTERFACE_MODE_RMII: 1283 ksz9477_set_xmii(dev, 1, &data8); 1284 ksz9477_set_gbit(dev, false, &data8); 1285 p->phydev.speed = SPEED_100; 1286 break; 1287 case PHY_INTERFACE_MODE_GMII: 1288 ksz9477_set_xmii(dev, 2, &data8); 1289 ksz9477_set_gbit(dev, true, &data8); 1290 p->phydev.speed = SPEED_1000; 1291 break; 1292 default: 1293 ksz9477_set_xmii(dev, 3, &data8); 1294 ksz9477_set_gbit(dev, true, &data8); 1295 data8 &= ~PORT_RGMII_ID_IG_ENABLE; 1296 data8 &= ~PORT_RGMII_ID_EG_ENABLE; 1297 if (dev->interface == PHY_INTERFACE_MODE_RGMII_ID || 1298 dev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 1299 data8 |= PORT_RGMII_ID_IG_ENABLE; 1300 if (dev->interface == PHY_INTERFACE_MODE_RGMII_ID || 1301 dev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 1302 data8 |= PORT_RGMII_ID_EG_ENABLE; 1303 p->phydev.speed = SPEED_1000; 1304 break; 1305 } 1306 ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, data8); 1307 p->phydev.duplex = 1; 1308 } 1309 mutex_lock(&dev->dev_mutex); 1310 if (cpu_port) { 1311 member = dev->port_mask; 1312 dev->on_ports = dev->host_mask; 1313 dev->live_ports = dev->host_mask; 1314 } else { 1315 member = dev->host_mask | p->vid_member; 1316 dev->on_ports |= (1 << port); 1317 1318 /* Link was detected before port is enabled. */ 1319 if (p->phydev.link) 1320 dev->live_ports |= (1 << port); 1321 } 1322 mutex_unlock(&dev->dev_mutex); 1323 ksz9477_cfg_port_member(dev, port, member); 1324 1325 /* clear pending interrupts */ 1326 if (port < dev->phy_port_cnt) 1327 ksz_pread16(dev, port, REG_PORT_PHY_INT_ENABLE, &data16); 1328 } 1329 1330 static void ksz9477_config_cpu_port(struct dsa_switch *ds) 1331 { 1332 struct ksz_device *dev = ds->priv; 1333 struct ksz_port *p; 1334 int i; 1335 1336 ds->num_ports = dev->port_cnt; 1337 1338 for (i = 0; i < dev->port_cnt; i++) { 1339 if (dsa_is_cpu_port(ds, i) && (dev->cpu_ports & (1 << i))) { 1340 phy_interface_t interface; 1341 1342 dev->cpu_port = i; 1343 dev->host_mask = (1 << dev->cpu_port); 1344 dev->port_mask |= dev->host_mask; 1345 1346 /* Read from XMII register to determine host port 1347 * interface. If set specifically in device tree 1348 * note the difference to help debugging. 1349 */ 1350 interface = ksz9477_get_interface(dev, i); 1351 if (!dev->interface) 1352 dev->interface = interface; 1353 if (interface && interface != dev->interface) 1354 dev_info(dev->dev, 1355 "use %s instead of %s\n", 1356 phy_modes(dev->interface), 1357 phy_modes(interface)); 1358 1359 /* enable cpu port */ 1360 ksz9477_port_setup(dev, i, true); 1361 p = &dev->ports[dev->cpu_port]; 1362 p->vid_member = dev->port_mask; 1363 p->on = 1; 1364 } 1365 } 1366 1367 dev->member = dev->host_mask; 1368 1369 for (i = 0; i < dev->mib_port_cnt; i++) { 1370 if (i == dev->cpu_port) 1371 continue; 1372 p = &dev->ports[i]; 1373 1374 /* Initialize to non-zero so that ksz_cfg_port_member() will 1375 * be called. 1376 */ 1377 p->vid_member = (1 << i); 1378 p->member = dev->port_mask; 1379 ksz9477_port_stp_state_set(ds, i, BR_STATE_DISABLED); 1380 p->on = 1; 1381 if (i < dev->phy_port_cnt) 1382 p->phy = 1; 1383 if (dev->chip_id == 0x00947700 && i == 6) { 1384 p->sgmii = 1; 1385 1386 /* SGMII PHY detection code is not implemented yet. */ 1387 p->phy = 0; 1388 } 1389 } 1390 } 1391 1392 static int ksz9477_setup(struct dsa_switch *ds) 1393 { 1394 struct ksz_device *dev = ds->priv; 1395 int ret = 0; 1396 1397 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 1398 dev->num_vlans, GFP_KERNEL); 1399 if (!dev->vlan_cache) 1400 return -ENOMEM; 1401 1402 ret = ksz9477_reset_switch(dev); 1403 if (ret) { 1404 dev_err(ds->dev, "failed to reset switch\n"); 1405 return ret; 1406 } 1407 1408 /* Required for port partitioning. */ 1409 ksz9477_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY, 1410 true); 1411 1412 /* Do not work correctly with tail tagging. */ 1413 ksz_cfg(dev, REG_SW_MAC_CTRL_0, SW_CHECK_LENGTH, false); 1414 1415 /* accept packet up to 2000bytes */ 1416 ksz_cfg(dev, REG_SW_MAC_CTRL_1, SW_LEGAL_PACKET_DISABLE, true); 1417 1418 ksz9477_config_cpu_port(ds); 1419 1420 ksz_cfg(dev, REG_SW_MAC_CTRL_1, MULTICAST_STORM_DISABLE, true); 1421 1422 /* queue based egress rate limit */ 1423 ksz_cfg(dev, REG_SW_MAC_CTRL_5, SW_OUT_RATE_LIMIT_QUEUE_BASED, true); 1424 1425 /* enable global MIB counter freeze function */ 1426 ksz_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true); 1427 1428 /* start switch */ 1429 ksz_cfg(dev, REG_SW_OPERATION, SW_START, true); 1430 1431 ksz_init_mib_timer(dev); 1432 1433 return 0; 1434 } 1435 1436 static const struct dsa_switch_ops ksz9477_switch_ops = { 1437 .get_tag_protocol = ksz9477_get_tag_protocol, 1438 .setup = ksz9477_setup, 1439 .phy_read = ksz9477_phy_read16, 1440 .phy_write = ksz9477_phy_write16, 1441 .adjust_link = ksz_adjust_link, 1442 .port_enable = ksz_enable_port, 1443 .port_disable = ksz_disable_port, 1444 .get_strings = ksz9477_get_strings, 1445 .get_ethtool_stats = ksz_get_ethtool_stats, 1446 .get_sset_count = ksz_sset_count, 1447 .port_bridge_join = ksz_port_bridge_join, 1448 .port_bridge_leave = ksz_port_bridge_leave, 1449 .port_stp_state_set = ksz9477_port_stp_state_set, 1450 .port_fast_age = ksz_port_fast_age, 1451 .port_vlan_filtering = ksz9477_port_vlan_filtering, 1452 .port_vlan_prepare = ksz_port_vlan_prepare, 1453 .port_vlan_add = ksz9477_port_vlan_add, 1454 .port_vlan_del = ksz9477_port_vlan_del, 1455 .port_fdb_dump = ksz9477_port_fdb_dump, 1456 .port_fdb_add = ksz9477_port_fdb_add, 1457 .port_fdb_del = ksz9477_port_fdb_del, 1458 .port_mdb_prepare = ksz_port_mdb_prepare, 1459 .port_mdb_add = ksz9477_port_mdb_add, 1460 .port_mdb_del = ksz9477_port_mdb_del, 1461 .port_mirror_add = ksz9477_port_mirror_add, 1462 .port_mirror_del = ksz9477_port_mirror_del, 1463 }; 1464 1465 static u32 ksz9477_get_port_addr(int port, int offset) 1466 { 1467 return PORT_CTRL_ADDR(port, offset); 1468 } 1469 1470 static int ksz9477_switch_detect(struct ksz_device *dev) 1471 { 1472 u8 data8; 1473 u8 id_hi; 1474 u8 id_lo; 1475 u32 id32; 1476 int ret; 1477 1478 /* turn off SPI DO Edge select */ 1479 ret = ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8); 1480 if (ret) 1481 return ret; 1482 1483 data8 &= ~SPI_AUTO_EDGE_DETECTION; 1484 ret = ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8); 1485 if (ret) 1486 return ret; 1487 1488 /* read chip id */ 1489 ret = ksz_read32(dev, REG_CHIP_ID0__1, &id32); 1490 if (ret) 1491 return ret; 1492 ret = ksz_read8(dev, REG_GLOBAL_OPTIONS, &data8); 1493 if (ret) 1494 return ret; 1495 1496 /* Number of ports can be reduced depending on chip. */ 1497 dev->mib_port_cnt = TOTAL_PORT_NUM; 1498 dev->phy_port_cnt = 5; 1499 1500 /* Default capability is gigabit capable. */ 1501 dev->features = GBIT_SUPPORT; 1502 1503 id_hi = (u8)(id32 >> 16); 1504 id_lo = (u8)(id32 >> 8); 1505 if ((id_lo & 0xf) == 3) { 1506 /* Chip is from KSZ9893 design. */ 1507 dev->features |= IS_9893; 1508 1509 /* Chip does not support gigabit. */ 1510 if (data8 & SW_QW_ABLE) 1511 dev->features &= ~GBIT_SUPPORT; 1512 dev->mib_port_cnt = 3; 1513 dev->phy_port_cnt = 2; 1514 } else { 1515 /* Chip uses new XMII register definitions. */ 1516 dev->features |= NEW_XMII; 1517 1518 /* Chip does not support gigabit. */ 1519 if (!(data8 & SW_GIGABIT_ABLE)) 1520 dev->features &= ~GBIT_SUPPORT; 1521 } 1522 1523 /* Change chip id to known ones so it can be matched against them. */ 1524 id32 = (id_hi << 16) | (id_lo << 8); 1525 1526 dev->chip_id = id32; 1527 1528 return 0; 1529 } 1530 1531 struct ksz_chip_data { 1532 u32 chip_id; 1533 const char *dev_name; 1534 int num_vlans; 1535 int num_alus; 1536 int num_statics; 1537 int cpu_ports; 1538 int port_cnt; 1539 bool phy_errata_9477; 1540 }; 1541 1542 static const struct ksz_chip_data ksz9477_switch_chips[] = { 1543 { 1544 .chip_id = 0x00947700, 1545 .dev_name = "KSZ9477", 1546 .num_vlans = 4096, 1547 .num_alus = 4096, 1548 .num_statics = 16, 1549 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1550 .port_cnt = 7, /* total physical port count */ 1551 .phy_errata_9477 = true, 1552 }, 1553 { 1554 .chip_id = 0x00989700, 1555 .dev_name = "KSZ9897", 1556 .num_vlans = 4096, 1557 .num_alus = 4096, 1558 .num_statics = 16, 1559 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1560 .port_cnt = 7, /* total physical port count */ 1561 .phy_errata_9477 = true, 1562 }, 1563 { 1564 .chip_id = 0x00989300, 1565 .dev_name = "KSZ9893", 1566 .num_vlans = 4096, 1567 .num_alus = 4096, 1568 .num_statics = 16, 1569 .cpu_ports = 0x07, /* can be configured as cpu port */ 1570 .port_cnt = 3, /* total port count */ 1571 }, 1572 }; 1573 1574 static int ksz9477_switch_init(struct ksz_device *dev) 1575 { 1576 int i; 1577 1578 dev->ds->ops = &ksz9477_switch_ops; 1579 1580 for (i = 0; i < ARRAY_SIZE(ksz9477_switch_chips); i++) { 1581 const struct ksz_chip_data *chip = &ksz9477_switch_chips[i]; 1582 1583 if (dev->chip_id == chip->chip_id) { 1584 dev->name = chip->dev_name; 1585 dev->num_vlans = chip->num_vlans; 1586 dev->num_alus = chip->num_alus; 1587 dev->num_statics = chip->num_statics; 1588 dev->port_cnt = chip->port_cnt; 1589 dev->cpu_ports = chip->cpu_ports; 1590 dev->phy_errata_9477 = chip->phy_errata_9477; 1591 1592 break; 1593 } 1594 } 1595 1596 /* no switch found */ 1597 if (!dev->port_cnt) 1598 return -ENODEV; 1599 1600 dev->port_mask = (1 << dev->port_cnt) - 1; 1601 1602 dev->reg_mib_cnt = SWITCH_COUNTER_NUM; 1603 dev->mib_cnt = TOTAL_SWITCH_COUNTER_NUM; 1604 1605 i = dev->mib_port_cnt; 1606 dev->ports = devm_kzalloc(dev->dev, sizeof(struct ksz_port) * i, 1607 GFP_KERNEL); 1608 if (!dev->ports) 1609 return -ENOMEM; 1610 for (i = 0; i < dev->mib_port_cnt; i++) { 1611 mutex_init(&dev->ports[i].mib.cnt_mutex); 1612 dev->ports[i].mib.counters = 1613 devm_kzalloc(dev->dev, 1614 sizeof(u64) * 1615 (TOTAL_SWITCH_COUNTER_NUM + 1), 1616 GFP_KERNEL); 1617 if (!dev->ports[i].mib.counters) 1618 return -ENOMEM; 1619 } 1620 1621 return 0; 1622 } 1623 1624 static void ksz9477_switch_exit(struct ksz_device *dev) 1625 { 1626 ksz9477_reset_switch(dev); 1627 } 1628 1629 static const struct ksz_dev_ops ksz9477_dev_ops = { 1630 .get_port_addr = ksz9477_get_port_addr, 1631 .cfg_port_member = ksz9477_cfg_port_member, 1632 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 1633 .phy_setup = ksz9477_phy_setup, 1634 .port_setup = ksz9477_port_setup, 1635 .r_mib_cnt = ksz9477_r_mib_cnt, 1636 .r_mib_pkt = ksz9477_r_mib_pkt, 1637 .freeze_mib = ksz9477_freeze_mib, 1638 .port_init_cnt = ksz9477_port_init_cnt, 1639 .shutdown = ksz9477_reset_switch, 1640 .detect = ksz9477_switch_detect, 1641 .init = ksz9477_switch_init, 1642 .exit = ksz9477_switch_exit, 1643 }; 1644 1645 int ksz9477_switch_register(struct ksz_device *dev) 1646 { 1647 return ksz_switch_register(dev, &ksz9477_dev_ops); 1648 } 1649 EXPORT_SYMBOL(ksz9477_switch_register); 1650 1651 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 1652 MODULE_DESCRIPTION("Microchip KSZ9477 Series Switch DSA Driver"); 1653 MODULE_LICENSE("GPL"); 1654