1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip KSZ9477 switch driver main logic 4 * 5 * Copyright (C) 2017-2019 Microchip Technology Inc. 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/iopoll.h> 11 #include <linux/platform_data/microchip-ksz.h> 12 #include <linux/phy.h> 13 #include <linux/if_bridge.h> 14 #include <linux/if_vlan.h> 15 #include <net/dsa.h> 16 #include <net/switchdev.h> 17 18 #include "ksz9477_reg.h" 19 #include "ksz_common.h" 20 #include "ksz9477.h" 21 22 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) 23 { 24 regmap_update_bits(ksz_regmap_8(dev), addr, bits, set ? bits : 0); 25 } 26 27 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits, 28 bool set) 29 { 30 regmap_update_bits(ksz_regmap_8(dev), PORT_CTRL_ADDR(port, offset), 31 bits, set ? bits : 0); 32 } 33 34 static void ksz9477_cfg32(struct ksz_device *dev, u32 addr, u32 bits, bool set) 35 { 36 regmap_update_bits(ksz_regmap_32(dev), addr, bits, set ? bits : 0); 37 } 38 39 static void ksz9477_port_cfg32(struct ksz_device *dev, int port, int offset, 40 u32 bits, bool set) 41 { 42 regmap_update_bits(ksz_regmap_32(dev), PORT_CTRL_ADDR(port, offset), 43 bits, set ? bits : 0); 44 } 45 46 int ksz9477_change_mtu(struct ksz_device *dev, int port, int mtu) 47 { 48 u16 frame_size; 49 50 if (!dsa_is_cpu_port(dev->ds, port)) 51 return 0; 52 53 frame_size = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 54 55 return regmap_update_bits(ksz_regmap_16(dev), REG_SW_MTU__2, 56 REG_SW_MTU_MASK, frame_size); 57 } 58 59 /** 60 * ksz9477_handle_wake_reason - Handle wake reason on a specified port. 61 * @dev: The device structure. 62 * @port: The port number. 63 * 64 * This function reads the PME (Power Management Event) status register of a 65 * specified port to determine the wake reason. If there is no wake event, it 66 * returns early. Otherwise, it logs the wake reason which could be due to a 67 * "Magic Packet", "Link Up", or "Energy Detect" event. The PME status register 68 * is then cleared to acknowledge the handling of the wake event. 69 * 70 * Return: 0 on success, or an error code on failure. 71 */ 72 static int ksz9477_handle_wake_reason(struct ksz_device *dev, int port) 73 { 74 u8 pme_status; 75 int ret; 76 77 ret = ksz_pread8(dev, port, REG_PORT_PME_STATUS, &pme_status); 78 if (ret) 79 return ret; 80 81 if (!pme_status) 82 return 0; 83 84 dev_dbg(dev->dev, "Wake event on port %d due to:%s%s%s\n", port, 85 pme_status & PME_WOL_MAGICPKT ? " \"Magic Packet\"" : "", 86 pme_status & PME_WOL_LINKUP ? " \"Link Up\"" : "", 87 pme_status & PME_WOL_ENERGY ? " \"Energy detect\"" : ""); 88 89 return ksz_pwrite8(dev, port, REG_PORT_PME_STATUS, pme_status); 90 } 91 92 /** 93 * ksz9477_get_wol - Get Wake-on-LAN settings for a specified port. 94 * @dev: The device structure. 95 * @port: The port number. 96 * @wol: Pointer to ethtool Wake-on-LAN settings structure. 97 * 98 * This function checks the PME Pin Control Register to see if PME Pin Output 99 * Enable is set, indicating PME is enabled. If enabled, it sets the supported 100 * and active WoL flags. 101 */ 102 void ksz9477_get_wol(struct ksz_device *dev, int port, 103 struct ethtool_wolinfo *wol) 104 { 105 u8 pme_ctrl; 106 int ret; 107 108 if (!dev->wakeup_source) 109 return; 110 111 wol->supported = WAKE_PHY; 112 113 /* Check if the current MAC address on this port can be set 114 * as global for WAKE_MAGIC support. The result may vary 115 * dynamically based on other ports configurations. 116 */ 117 if (ksz_is_port_mac_global_usable(dev->ds, port)) 118 wol->supported |= WAKE_MAGIC; 119 120 ret = ksz_pread8(dev, port, REG_PORT_PME_CTRL, &pme_ctrl); 121 if (ret) 122 return; 123 124 if (pme_ctrl & PME_WOL_MAGICPKT) 125 wol->wolopts |= WAKE_MAGIC; 126 if (pme_ctrl & (PME_WOL_LINKUP | PME_WOL_ENERGY)) 127 wol->wolopts |= WAKE_PHY; 128 } 129 130 /** 131 * ksz9477_set_wol - Set Wake-on-LAN settings for a specified port. 132 * @dev: The device structure. 133 * @port: The port number. 134 * @wol: Pointer to ethtool Wake-on-LAN settings structure. 135 * 136 * This function configures Wake-on-LAN (WoL) settings for a specified port. 137 * It validates the provided WoL options, checks if PME is enabled via the 138 * switch's PME Pin Control Register, clears any previous wake reasons, 139 * and sets the Magic Packet flag in the port's PME control register if 140 * specified. 141 * 142 * Return: 0 on success, or other error codes on failure. 143 */ 144 int ksz9477_set_wol(struct ksz_device *dev, int port, 145 struct ethtool_wolinfo *wol) 146 { 147 u8 pme_ctrl = 0, pme_ctrl_old = 0; 148 bool magic_switched_off; 149 bool magic_switched_on; 150 int ret; 151 152 if (wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC)) 153 return -EINVAL; 154 155 if (!dev->wakeup_source) 156 return -EOPNOTSUPP; 157 158 ret = ksz9477_handle_wake_reason(dev, port); 159 if (ret) 160 return ret; 161 162 if (wol->wolopts & WAKE_MAGIC) 163 pme_ctrl |= PME_WOL_MAGICPKT; 164 if (wol->wolopts & WAKE_PHY) 165 pme_ctrl |= PME_WOL_LINKUP | PME_WOL_ENERGY; 166 167 ret = ksz_pread8(dev, port, REG_PORT_PME_CTRL, &pme_ctrl_old); 168 if (ret) 169 return ret; 170 171 if (pme_ctrl_old == pme_ctrl) 172 return 0; 173 174 magic_switched_off = (pme_ctrl_old & PME_WOL_MAGICPKT) && 175 !(pme_ctrl & PME_WOL_MAGICPKT); 176 magic_switched_on = !(pme_ctrl_old & PME_WOL_MAGICPKT) && 177 (pme_ctrl & PME_WOL_MAGICPKT); 178 179 /* To keep reference count of MAC address, we should do this 180 * operation only on change of WOL settings. 181 */ 182 if (magic_switched_on) { 183 ret = ksz_switch_macaddr_get(dev->ds, port, NULL); 184 if (ret) 185 return ret; 186 } else if (magic_switched_off) { 187 ksz_switch_macaddr_put(dev->ds); 188 } 189 190 ret = ksz_pwrite8(dev, port, REG_PORT_PME_CTRL, pme_ctrl); 191 if (ret) { 192 if (magic_switched_on) 193 ksz_switch_macaddr_put(dev->ds); 194 return ret; 195 } 196 197 return 0; 198 } 199 200 /** 201 * ksz9477_wol_pre_shutdown - Prepares the switch device for shutdown while 202 * considering Wake-on-LAN (WoL) settings. 203 * @dev: The switch device structure. 204 * @wol_enabled: Pointer to a boolean which will be set to true if WoL is 205 * enabled on any port. 206 * 207 * This function prepares the switch device for a safe shutdown while taking 208 * into account the Wake-on-LAN (WoL) settings on the user ports. It updates 209 * the wol_enabled flag accordingly to reflect whether WoL is active on any 210 * port. 211 */ 212 void ksz9477_wol_pre_shutdown(struct ksz_device *dev, bool *wol_enabled) 213 { 214 struct dsa_port *dp; 215 int ret; 216 217 *wol_enabled = false; 218 219 if (!dev->wakeup_source) 220 return; 221 222 dsa_switch_for_each_user_port(dp, dev->ds) { 223 u8 pme_ctrl = 0; 224 225 ret = ksz_pread8(dev, dp->index, REG_PORT_PME_CTRL, &pme_ctrl); 226 if (!ret && pme_ctrl) 227 *wol_enabled = true; 228 229 /* make sure there are no pending wake events which would 230 * prevent the device from going to sleep/shutdown. 231 */ 232 ksz9477_handle_wake_reason(dev, dp->index); 233 } 234 235 /* Now we are save to enable PME pin. */ 236 if (*wol_enabled) 237 ksz_write8(dev, REG_SW_PME_CTRL, PME_ENABLE); 238 } 239 240 static int ksz9477_wait_vlan_ctrl_ready(struct ksz_device *dev) 241 { 242 unsigned int val; 243 244 return regmap_read_poll_timeout(ksz_regmap_8(dev), REG_SW_VLAN_CTRL, 245 val, !(val & VLAN_START), 10, 1000); 246 } 247 248 static int ksz9477_get_vlan_table(struct ksz_device *dev, u16 vid, 249 u32 *vlan_table) 250 { 251 int ret; 252 253 mutex_lock(&dev->vlan_mutex); 254 255 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 256 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_READ | VLAN_START); 257 258 /* wait to be cleared */ 259 ret = ksz9477_wait_vlan_ctrl_ready(dev); 260 if (ret) { 261 dev_dbg(dev->dev, "Failed to read vlan table\n"); 262 goto exit; 263 } 264 265 ksz_read32(dev, REG_SW_VLAN_ENTRY__4, &vlan_table[0]); 266 ksz_read32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, &vlan_table[1]); 267 ksz_read32(dev, REG_SW_VLAN_ENTRY_PORTS__4, &vlan_table[2]); 268 269 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 270 271 exit: 272 mutex_unlock(&dev->vlan_mutex); 273 274 return ret; 275 } 276 277 static int ksz9477_set_vlan_table(struct ksz_device *dev, u16 vid, 278 u32 *vlan_table) 279 { 280 int ret; 281 282 mutex_lock(&dev->vlan_mutex); 283 284 ksz_write32(dev, REG_SW_VLAN_ENTRY__4, vlan_table[0]); 285 ksz_write32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, vlan_table[1]); 286 ksz_write32(dev, REG_SW_VLAN_ENTRY_PORTS__4, vlan_table[2]); 287 288 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 289 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_START | VLAN_WRITE); 290 291 /* wait to be cleared */ 292 ret = ksz9477_wait_vlan_ctrl_ready(dev); 293 if (ret) { 294 dev_dbg(dev->dev, "Failed to write vlan table\n"); 295 goto exit; 296 } 297 298 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 299 300 /* update vlan cache table */ 301 dev->vlan_cache[vid].table[0] = vlan_table[0]; 302 dev->vlan_cache[vid].table[1] = vlan_table[1]; 303 dev->vlan_cache[vid].table[2] = vlan_table[2]; 304 305 exit: 306 mutex_unlock(&dev->vlan_mutex); 307 308 return ret; 309 } 310 311 static void ksz9477_read_table(struct ksz_device *dev, u32 *table) 312 { 313 ksz_read32(dev, REG_SW_ALU_VAL_A, &table[0]); 314 ksz_read32(dev, REG_SW_ALU_VAL_B, &table[1]); 315 ksz_read32(dev, REG_SW_ALU_VAL_C, &table[2]); 316 ksz_read32(dev, REG_SW_ALU_VAL_D, &table[3]); 317 } 318 319 static void ksz9477_write_table(struct ksz_device *dev, u32 *table) 320 { 321 ksz_write32(dev, REG_SW_ALU_VAL_A, table[0]); 322 ksz_write32(dev, REG_SW_ALU_VAL_B, table[1]); 323 ksz_write32(dev, REG_SW_ALU_VAL_C, table[2]); 324 ksz_write32(dev, REG_SW_ALU_VAL_D, table[3]); 325 } 326 327 static int ksz9477_wait_alu_ready(struct ksz_device *dev) 328 { 329 unsigned int val; 330 331 return regmap_read_poll_timeout(ksz_regmap_32(dev), REG_SW_ALU_CTRL__4, 332 val, !(val & ALU_START), 10, 1000); 333 } 334 335 static int ksz9477_wait_alu_sta_ready(struct ksz_device *dev) 336 { 337 unsigned int val; 338 339 return regmap_read_poll_timeout(ksz_regmap_32(dev), 340 REG_SW_ALU_STAT_CTRL__4, 341 val, !(val & ALU_STAT_START), 342 10, 1000); 343 } 344 345 int ksz9477_reset_switch(struct ksz_device *dev) 346 { 347 u8 data8; 348 u32 data32; 349 350 /* reset switch */ 351 ksz_cfg(dev, REG_SW_OPERATION, SW_RESET, true); 352 353 /* turn off SPI DO Edge select */ 354 regmap_update_bits(ksz_regmap_8(dev), REG_SW_GLOBAL_SERIAL_CTRL_0, 355 SPI_AUTO_EDGE_DETECTION, 0); 356 357 /* default configuration */ 358 ksz_write8(dev, REG_SW_LUE_CTRL_1, 359 SW_AGING_ENABLE | SW_LINK_AUTO_AGING | SW_SRC_ADDR_FILTER); 360 361 /* disable interrupts */ 362 ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK); 363 ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0x7F); 364 ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32); 365 366 /* KSZ9893 compatible chips do not support refclk configuration */ 367 if (dev->chip_id == KSZ9893_CHIP_ID || 368 dev->chip_id == KSZ8563_CHIP_ID || 369 dev->chip_id == KSZ9563_CHIP_ID) 370 return 0; 371 372 data8 = SW_ENABLE_REFCLKO; 373 if (dev->synclko_disable) 374 data8 = 0; 375 else if (dev->synclko_125) 376 data8 = SW_ENABLE_REFCLKO | SW_REFCLKO_IS_125MHZ; 377 ksz_write8(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1, data8); 378 379 return 0; 380 } 381 382 void ksz9477_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, u64 *cnt) 383 { 384 struct ksz_port *p = &dev->ports[port]; 385 unsigned int val; 386 u32 data; 387 int ret; 388 389 /* retain the flush/freeze bit */ 390 data = p->freeze ? MIB_COUNTER_FLUSH_FREEZE : 0; 391 data |= MIB_COUNTER_READ; 392 data |= (addr << MIB_COUNTER_INDEX_S); 393 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, data); 394 395 ret = regmap_read_poll_timeout(ksz_regmap_32(dev), 396 PORT_CTRL_ADDR(port, REG_PORT_MIB_CTRL_STAT__4), 397 val, !(val & MIB_COUNTER_READ), 10, 1000); 398 /* failed to read MIB. get out of loop */ 399 if (ret) { 400 dev_dbg(dev->dev, "Failed to get MIB\n"); 401 return; 402 } 403 404 /* count resets upon read */ 405 ksz_pread32(dev, port, REG_PORT_MIB_DATA, &data); 406 *cnt += data; 407 } 408 409 void ksz9477_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 410 u64 *dropped, u64 *cnt) 411 { 412 addr = dev->info->mib_names[addr].index; 413 ksz9477_r_mib_cnt(dev, port, addr, cnt); 414 } 415 416 void ksz9477_freeze_mib(struct ksz_device *dev, int port, bool freeze) 417 { 418 u32 val = freeze ? MIB_COUNTER_FLUSH_FREEZE : 0; 419 struct ksz_port *p = &dev->ports[port]; 420 421 /* enable/disable the port for flush/freeze function */ 422 mutex_lock(&p->mib.cnt_mutex); 423 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, val); 424 425 /* used by MIB counter reading code to know freeze is enabled */ 426 p->freeze = freeze; 427 mutex_unlock(&p->mib.cnt_mutex); 428 } 429 430 void ksz9477_port_init_cnt(struct ksz_device *dev, int port) 431 { 432 struct ksz_port_mib *mib = &dev->ports[port].mib; 433 434 /* flush all enabled port MIB counters */ 435 mutex_lock(&mib->cnt_mutex); 436 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 437 MIB_COUNTER_FLUSH_FREEZE); 438 ksz_write8(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FLUSH); 439 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 0); 440 mutex_unlock(&mib->cnt_mutex); 441 } 442 443 static void ksz9477_r_phy_quirks(struct ksz_device *dev, u16 addr, u16 reg, 444 u16 *data) 445 { 446 /* KSZ8563R do not have extended registers but BMSR_ESTATEN and 447 * BMSR_ERCAP bits are set. 448 */ 449 if (dev->chip_id == KSZ8563_CHIP_ID && reg == MII_BMSR) 450 *data &= ~(BMSR_ESTATEN | BMSR_ERCAP); 451 } 452 453 int ksz9477_r_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 *data) 454 { 455 u16 val = 0xffff; 456 int ret; 457 458 /* No real PHY after this. Simulate the PHY. 459 * A fixed PHY can be setup in the device tree, but this function is 460 * still called for that port during initialization. 461 * For RGMII PHY there is no way to access it so the fixed PHY should 462 * be used. For SGMII PHY the supporting code will be added later. 463 */ 464 if (!dev->info->internal_phy[addr]) { 465 struct ksz_port *p = &dev->ports[addr]; 466 467 switch (reg) { 468 case MII_BMCR: 469 val = 0x1140; 470 break; 471 case MII_BMSR: 472 val = 0x796d; 473 break; 474 case MII_PHYSID1: 475 val = 0x0022; 476 break; 477 case MII_PHYSID2: 478 val = 0x1631; 479 break; 480 case MII_ADVERTISE: 481 val = 0x05e1; 482 break; 483 case MII_LPA: 484 val = 0xc5e1; 485 break; 486 case MII_CTRL1000: 487 val = 0x0700; 488 break; 489 case MII_STAT1000: 490 if (p->phydev.speed == SPEED_1000) 491 val = 0x3800; 492 else 493 val = 0; 494 break; 495 } 496 } else { 497 ret = ksz_pread16(dev, addr, 0x100 + (reg << 1), &val); 498 if (ret) 499 return ret; 500 501 ksz9477_r_phy_quirks(dev, addr, reg, &val); 502 } 503 504 *data = val; 505 506 return 0; 507 } 508 509 int ksz9477_w_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 val) 510 { 511 u32 mask, val32; 512 513 /* No real PHY after this. */ 514 if (!dev->info->internal_phy[addr]) 515 return 0; 516 517 if (reg < 0x10) 518 return ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val); 519 520 /* Errata: When using SPI, I2C, or in-band register access, 521 * writes to certain PHY registers should be performed as 522 * 32-bit writes instead of 16-bit writes. 523 */ 524 val32 = val; 525 mask = 0xffff; 526 if ((reg & 1) == 0) { 527 val32 <<= 16; 528 mask <<= 16; 529 } 530 reg &= ~1; 531 return ksz_prmw32(dev, addr, 0x100 + (reg << 1), mask, val32); 532 } 533 534 void ksz9477_cfg_port_member(struct ksz_device *dev, int port, u8 member) 535 { 536 ksz_pwrite32(dev, port, REG_PORT_VLAN_MEMBERSHIP__4, member); 537 } 538 539 void ksz9477_flush_dyn_mac_table(struct ksz_device *dev, int port) 540 { 541 const u16 *regs = dev->info->regs; 542 u8 data; 543 544 regmap_update_bits(ksz_regmap_8(dev), REG_SW_LUE_CTRL_2, 545 SW_FLUSH_OPTION_M << SW_FLUSH_OPTION_S, 546 SW_FLUSH_OPTION_DYN_MAC << SW_FLUSH_OPTION_S); 547 548 if (port < dev->info->port_cnt) { 549 /* flush individual port */ 550 ksz_pread8(dev, port, regs[P_STP_CTRL], &data); 551 if (!(data & PORT_LEARN_DISABLE)) 552 ksz_pwrite8(dev, port, regs[P_STP_CTRL], 553 data | PORT_LEARN_DISABLE); 554 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true); 555 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data); 556 } else { 557 /* flush all */ 558 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_STP_TABLE, true); 559 } 560 } 561 562 int ksz9477_port_vlan_filtering(struct ksz_device *dev, int port, 563 bool flag, struct netlink_ext_ack *extack) 564 { 565 if (flag) { 566 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 567 PORT_VLAN_LOOKUP_VID_0, true); 568 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, true); 569 } else { 570 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, false); 571 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 572 PORT_VLAN_LOOKUP_VID_0, false); 573 } 574 575 return 0; 576 } 577 578 int ksz9477_port_vlan_add(struct ksz_device *dev, int port, 579 const struct switchdev_obj_port_vlan *vlan, 580 struct netlink_ext_ack *extack) 581 { 582 u32 vlan_table[3]; 583 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 584 int err; 585 586 err = ksz9477_get_vlan_table(dev, vlan->vid, vlan_table); 587 if (err) { 588 NL_SET_ERR_MSG_MOD(extack, "Failed to get vlan table"); 589 return err; 590 } 591 592 vlan_table[0] = VLAN_VALID | (vlan->vid & VLAN_FID_M); 593 if (untagged) 594 vlan_table[1] |= BIT(port); 595 else 596 vlan_table[1] &= ~BIT(port); 597 vlan_table[1] &= ~(BIT(dev->cpu_port)); 598 599 vlan_table[2] |= BIT(port) | BIT(dev->cpu_port); 600 601 err = ksz9477_set_vlan_table(dev, vlan->vid, vlan_table); 602 if (err) { 603 NL_SET_ERR_MSG_MOD(extack, "Failed to set vlan table"); 604 return err; 605 } 606 607 /* change PVID */ 608 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) 609 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, vlan->vid); 610 611 return 0; 612 } 613 614 int ksz9477_port_vlan_del(struct ksz_device *dev, int port, 615 const struct switchdev_obj_port_vlan *vlan) 616 { 617 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 618 u32 vlan_table[3]; 619 u16 pvid; 620 621 ksz_pread16(dev, port, REG_PORT_DEFAULT_VID, &pvid); 622 pvid = pvid & 0xFFF; 623 624 if (ksz9477_get_vlan_table(dev, vlan->vid, vlan_table)) { 625 dev_dbg(dev->dev, "Failed to get vlan table\n"); 626 return -ETIMEDOUT; 627 } 628 629 vlan_table[2] &= ~BIT(port); 630 631 if (pvid == vlan->vid) 632 pvid = 1; 633 634 if (untagged) 635 vlan_table[1] &= ~BIT(port); 636 637 if (ksz9477_set_vlan_table(dev, vlan->vid, vlan_table)) { 638 dev_dbg(dev->dev, "Failed to set vlan table\n"); 639 return -ETIMEDOUT; 640 } 641 642 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, pvid); 643 644 return 0; 645 } 646 647 int ksz9477_fdb_add(struct ksz_device *dev, int port, 648 const unsigned char *addr, u16 vid, struct dsa_db db) 649 { 650 u32 alu_table[4]; 651 u32 data; 652 int ret = 0; 653 654 mutex_lock(&dev->alu_mutex); 655 656 /* find any entry with mac & vid */ 657 data = vid << ALU_FID_INDEX_S; 658 data |= ((addr[0] << 8) | addr[1]); 659 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 660 661 data = ((addr[2] << 24) | (addr[3] << 16)); 662 data |= ((addr[4] << 8) | addr[5]); 663 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 664 665 /* start read operation */ 666 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 667 668 /* wait to be finished */ 669 ret = ksz9477_wait_alu_ready(dev); 670 if (ret) { 671 dev_dbg(dev->dev, "Failed to read ALU\n"); 672 goto exit; 673 } 674 675 /* read ALU entry */ 676 ksz9477_read_table(dev, alu_table); 677 678 /* update ALU entry */ 679 alu_table[0] = ALU_V_STATIC_VALID; 680 alu_table[1] |= BIT(port); 681 if (vid) 682 alu_table[1] |= ALU_V_USE_FID; 683 alu_table[2] = (vid << ALU_V_FID_S); 684 alu_table[2] |= ((addr[0] << 8) | addr[1]); 685 alu_table[3] = ((addr[2] << 24) | (addr[3] << 16)); 686 alu_table[3] |= ((addr[4] << 8) | addr[5]); 687 688 ksz9477_write_table(dev, alu_table); 689 690 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 691 692 /* wait to be finished */ 693 ret = ksz9477_wait_alu_ready(dev); 694 if (ret) 695 dev_dbg(dev->dev, "Failed to write ALU\n"); 696 697 exit: 698 mutex_unlock(&dev->alu_mutex); 699 700 return ret; 701 } 702 703 int ksz9477_fdb_del(struct ksz_device *dev, int port, 704 const unsigned char *addr, u16 vid, struct dsa_db db) 705 { 706 u32 alu_table[4]; 707 u32 data; 708 int ret = 0; 709 710 mutex_lock(&dev->alu_mutex); 711 712 /* read any entry with mac & vid */ 713 data = vid << ALU_FID_INDEX_S; 714 data |= ((addr[0] << 8) | addr[1]); 715 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 716 717 data = ((addr[2] << 24) | (addr[3] << 16)); 718 data |= ((addr[4] << 8) | addr[5]); 719 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 720 721 /* start read operation */ 722 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 723 724 /* wait to be finished */ 725 ret = ksz9477_wait_alu_ready(dev); 726 if (ret) { 727 dev_dbg(dev->dev, "Failed to read ALU\n"); 728 goto exit; 729 } 730 731 ksz_read32(dev, REG_SW_ALU_VAL_A, &alu_table[0]); 732 if (alu_table[0] & ALU_V_STATIC_VALID) { 733 ksz_read32(dev, REG_SW_ALU_VAL_B, &alu_table[1]); 734 ksz_read32(dev, REG_SW_ALU_VAL_C, &alu_table[2]); 735 ksz_read32(dev, REG_SW_ALU_VAL_D, &alu_table[3]); 736 737 /* clear forwarding port */ 738 alu_table[1] &= ~BIT(port); 739 740 /* if there is no port to forward, clear table */ 741 if ((alu_table[1] & ALU_V_PORT_MAP) == 0) { 742 alu_table[0] = 0; 743 alu_table[1] = 0; 744 alu_table[2] = 0; 745 alu_table[3] = 0; 746 } 747 } else { 748 alu_table[0] = 0; 749 alu_table[1] = 0; 750 alu_table[2] = 0; 751 alu_table[3] = 0; 752 } 753 754 ksz9477_write_table(dev, alu_table); 755 756 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 757 758 /* wait to be finished */ 759 ret = ksz9477_wait_alu_ready(dev); 760 if (ret) 761 dev_dbg(dev->dev, "Failed to write ALU\n"); 762 763 exit: 764 mutex_unlock(&dev->alu_mutex); 765 766 return ret; 767 } 768 769 static void ksz9477_convert_alu(struct alu_struct *alu, u32 *alu_table) 770 { 771 alu->is_static = !!(alu_table[0] & ALU_V_STATIC_VALID); 772 alu->is_src_filter = !!(alu_table[0] & ALU_V_SRC_FILTER); 773 alu->is_dst_filter = !!(alu_table[0] & ALU_V_DST_FILTER); 774 alu->prio_age = (alu_table[0] >> ALU_V_PRIO_AGE_CNT_S) & 775 ALU_V_PRIO_AGE_CNT_M; 776 alu->mstp = alu_table[0] & ALU_V_MSTP_M; 777 778 alu->is_override = !!(alu_table[1] & ALU_V_OVERRIDE); 779 alu->is_use_fid = !!(alu_table[1] & ALU_V_USE_FID); 780 alu->port_forward = alu_table[1] & ALU_V_PORT_MAP; 781 782 alu->fid = (alu_table[2] >> ALU_V_FID_S) & ALU_V_FID_M; 783 784 alu->mac[0] = (alu_table[2] >> 8) & 0xFF; 785 alu->mac[1] = alu_table[2] & 0xFF; 786 alu->mac[2] = (alu_table[3] >> 24) & 0xFF; 787 alu->mac[3] = (alu_table[3] >> 16) & 0xFF; 788 alu->mac[4] = (alu_table[3] >> 8) & 0xFF; 789 alu->mac[5] = alu_table[3] & 0xFF; 790 } 791 792 int ksz9477_fdb_dump(struct ksz_device *dev, int port, 793 dsa_fdb_dump_cb_t *cb, void *data) 794 { 795 int ret = 0; 796 u32 ksz_data; 797 u32 alu_table[4]; 798 struct alu_struct alu; 799 int timeout; 800 801 mutex_lock(&dev->alu_mutex); 802 803 /* start ALU search */ 804 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_START | ALU_SEARCH); 805 806 do { 807 timeout = 1000; 808 do { 809 ksz_read32(dev, REG_SW_ALU_CTRL__4, &ksz_data); 810 if ((ksz_data & ALU_VALID) || !(ksz_data & ALU_START)) 811 break; 812 usleep_range(1, 10); 813 } while (timeout-- > 0); 814 815 if (!timeout) { 816 dev_dbg(dev->dev, "Failed to search ALU\n"); 817 ret = -ETIMEDOUT; 818 goto exit; 819 } 820 821 if (!(ksz_data & ALU_VALID)) 822 continue; 823 824 /* read ALU table */ 825 ksz9477_read_table(dev, alu_table); 826 827 ksz9477_convert_alu(&alu, alu_table); 828 829 if (alu.port_forward & BIT(port)) { 830 ret = cb(alu.mac, alu.fid, alu.is_static, data); 831 if (ret) 832 goto exit; 833 } 834 } while (ksz_data & ALU_START); 835 836 exit: 837 838 /* stop ALU search */ 839 ksz_write32(dev, REG_SW_ALU_CTRL__4, 0); 840 841 mutex_unlock(&dev->alu_mutex); 842 843 return ret; 844 } 845 846 int ksz9477_mdb_add(struct ksz_device *dev, int port, 847 const struct switchdev_obj_port_mdb *mdb, struct dsa_db db) 848 { 849 u32 static_table[4]; 850 const u8 *shifts; 851 const u32 *masks; 852 u32 data; 853 int index; 854 u32 mac_hi, mac_lo; 855 int err = 0; 856 857 shifts = dev->info->shifts; 858 masks = dev->info->masks; 859 860 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 861 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 862 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 863 864 mutex_lock(&dev->alu_mutex); 865 866 for (index = 0; index < dev->info->num_statics; index++) { 867 /* find empty slot first */ 868 data = (index << shifts[ALU_STAT_INDEX]) | 869 masks[ALU_STAT_READ] | ALU_STAT_START; 870 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 871 872 /* wait to be finished */ 873 err = ksz9477_wait_alu_sta_ready(dev); 874 if (err) { 875 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 876 goto exit; 877 } 878 879 /* read ALU static table */ 880 ksz9477_read_table(dev, static_table); 881 882 if (static_table[0] & ALU_V_STATIC_VALID) { 883 /* check this has same vid & mac address */ 884 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 885 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 886 static_table[3] == mac_lo) { 887 /* found matching one */ 888 break; 889 } 890 } else { 891 /* found empty one */ 892 break; 893 } 894 } 895 896 /* no available entry */ 897 if (index == dev->info->num_statics) { 898 err = -ENOSPC; 899 goto exit; 900 } 901 902 /* add entry */ 903 static_table[0] = ALU_V_STATIC_VALID; 904 static_table[1] |= BIT(port); 905 if (mdb->vid) 906 static_table[1] |= ALU_V_USE_FID; 907 static_table[2] = (mdb->vid << ALU_V_FID_S); 908 static_table[2] |= mac_hi; 909 static_table[3] = mac_lo; 910 911 ksz9477_write_table(dev, static_table); 912 913 data = (index << shifts[ALU_STAT_INDEX]) | ALU_STAT_START; 914 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 915 916 /* wait to be finished */ 917 if (ksz9477_wait_alu_sta_ready(dev)) 918 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 919 920 exit: 921 mutex_unlock(&dev->alu_mutex); 922 return err; 923 } 924 925 int ksz9477_mdb_del(struct ksz_device *dev, int port, 926 const struct switchdev_obj_port_mdb *mdb, struct dsa_db db) 927 { 928 u32 static_table[4]; 929 const u8 *shifts; 930 const u32 *masks; 931 u32 data; 932 int index; 933 int ret = 0; 934 u32 mac_hi, mac_lo; 935 936 shifts = dev->info->shifts; 937 masks = dev->info->masks; 938 939 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 940 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 941 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 942 943 mutex_lock(&dev->alu_mutex); 944 945 for (index = 0; index < dev->info->num_statics; index++) { 946 /* find empty slot first */ 947 data = (index << shifts[ALU_STAT_INDEX]) | 948 masks[ALU_STAT_READ] | ALU_STAT_START; 949 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 950 951 /* wait to be finished */ 952 ret = ksz9477_wait_alu_sta_ready(dev); 953 if (ret) { 954 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 955 goto exit; 956 } 957 958 /* read ALU static table */ 959 ksz9477_read_table(dev, static_table); 960 961 if (static_table[0] & ALU_V_STATIC_VALID) { 962 /* check this has same vid & mac address */ 963 964 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 965 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 966 static_table[3] == mac_lo) { 967 /* found matching one */ 968 break; 969 } 970 } 971 } 972 973 /* no available entry */ 974 if (index == dev->info->num_statics) 975 goto exit; 976 977 /* clear port */ 978 static_table[1] &= ~BIT(port); 979 980 if ((static_table[1] & ALU_V_PORT_MAP) == 0) { 981 /* delete entry */ 982 static_table[0] = 0; 983 static_table[1] = 0; 984 static_table[2] = 0; 985 static_table[3] = 0; 986 } 987 988 ksz9477_write_table(dev, static_table); 989 990 data = (index << shifts[ALU_STAT_INDEX]) | ALU_STAT_START; 991 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 992 993 /* wait to be finished */ 994 ret = ksz9477_wait_alu_sta_ready(dev); 995 if (ret) 996 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 997 998 exit: 999 mutex_unlock(&dev->alu_mutex); 1000 1001 return ret; 1002 } 1003 1004 int ksz9477_port_mirror_add(struct ksz_device *dev, int port, 1005 struct dsa_mall_mirror_tc_entry *mirror, 1006 bool ingress, struct netlink_ext_ack *extack) 1007 { 1008 u8 data; 1009 int p; 1010 1011 /* Limit to one sniffer port 1012 * Check if any of the port is already set for sniffing 1013 * If yes, instruct the user to remove the previous entry & exit 1014 */ 1015 for (p = 0; p < dev->info->port_cnt; p++) { 1016 /* Skip the current sniffing port */ 1017 if (p == mirror->to_local_port) 1018 continue; 1019 1020 ksz_pread8(dev, p, P_MIRROR_CTRL, &data); 1021 1022 if (data & PORT_MIRROR_SNIFFER) { 1023 NL_SET_ERR_MSG_MOD(extack, 1024 "Sniffer port is already configured, delete existing rules & retry"); 1025 return -EBUSY; 1026 } 1027 } 1028 1029 if (ingress) 1030 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true); 1031 else 1032 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true); 1033 1034 /* configure mirror port */ 1035 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 1036 PORT_MIRROR_SNIFFER, true); 1037 1038 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false); 1039 1040 return 0; 1041 } 1042 1043 void ksz9477_port_mirror_del(struct ksz_device *dev, int port, 1044 struct dsa_mall_mirror_tc_entry *mirror) 1045 { 1046 bool in_use = false; 1047 u8 data; 1048 int p; 1049 1050 if (mirror->ingress) 1051 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false); 1052 else 1053 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false); 1054 1055 1056 /* Check if any of the port is still referring to sniffer port */ 1057 for (p = 0; p < dev->info->port_cnt; p++) { 1058 ksz_pread8(dev, p, P_MIRROR_CTRL, &data); 1059 1060 if ((data & (PORT_MIRROR_RX | PORT_MIRROR_TX))) { 1061 in_use = true; 1062 break; 1063 } 1064 } 1065 1066 /* delete sniffing if there are no other mirroring rules */ 1067 if (!in_use) 1068 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 1069 PORT_MIRROR_SNIFFER, false); 1070 } 1071 1072 static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port) 1073 { 1074 phy_interface_t interface; 1075 bool gbit; 1076 1077 if (dev->info->internal_phy[port]) 1078 return PHY_INTERFACE_MODE_NA; 1079 1080 gbit = ksz_get_gbit(dev, port); 1081 1082 interface = ksz_get_xmii(dev, port, gbit); 1083 1084 return interface; 1085 } 1086 1087 void ksz9477_get_caps(struct ksz_device *dev, int port, 1088 struct phylink_config *config) 1089 { 1090 config->mac_capabilities = MAC_10 | MAC_100 | MAC_ASYM_PAUSE | 1091 MAC_SYM_PAUSE; 1092 1093 if (dev->info->gbit_capable[port]) 1094 config->mac_capabilities |= MAC_1000FD; 1095 } 1096 1097 int ksz9477_set_ageing_time(struct ksz_device *dev, unsigned int msecs) 1098 { 1099 u32 secs = msecs / 1000; 1100 u8 value; 1101 u8 data; 1102 int ret; 1103 1104 value = FIELD_GET(SW_AGE_PERIOD_7_0_M, secs); 1105 1106 ret = ksz_write8(dev, REG_SW_LUE_CTRL_3, value); 1107 if (ret < 0) 1108 return ret; 1109 1110 data = FIELD_GET(SW_AGE_PERIOD_10_8_M, secs); 1111 1112 ret = ksz_read8(dev, REG_SW_LUE_CTRL_0, &value); 1113 if (ret < 0) 1114 return ret; 1115 1116 value &= ~SW_AGE_CNT_M; 1117 value |= FIELD_PREP(SW_AGE_CNT_M, data); 1118 1119 return ksz_write8(dev, REG_SW_LUE_CTRL_0, value); 1120 } 1121 1122 void ksz9477_port_queue_split(struct ksz_device *dev, int port) 1123 { 1124 u8 data; 1125 1126 if (dev->info->num_tx_queues == 8) 1127 data = PORT_EIGHT_QUEUE; 1128 else if (dev->info->num_tx_queues == 4) 1129 data = PORT_FOUR_QUEUE; 1130 else if (dev->info->num_tx_queues == 2) 1131 data = PORT_TWO_QUEUE; 1132 else 1133 data = PORT_SINGLE_QUEUE; 1134 1135 ksz_prmw8(dev, port, REG_PORT_CTRL_0, PORT_QUEUE_SPLIT_MASK, data); 1136 } 1137 1138 void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port) 1139 { 1140 struct dsa_switch *ds = dev->ds; 1141 u16 data16; 1142 u8 member; 1143 1144 /* enable tag tail for host port */ 1145 if (cpu_port) 1146 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_TAIL_TAG_ENABLE, 1147 true); 1148 1149 ksz9477_port_queue_split(dev, port); 1150 1151 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_MAC_LOOPBACK, false); 1152 1153 /* set back pressure */ 1154 ksz_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, true); 1155 1156 /* enable broadcast storm limit */ 1157 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true); 1158 1159 /* replace priority */ 1160 ksz_port_cfg(dev, port, REG_PORT_MRI_MAC_CTRL, PORT_USER_PRIO_CEILING, 1161 false); 1162 ksz9477_port_cfg32(dev, port, REG_PORT_MTI_QUEUE_CTRL_0__4, 1163 MTI_PVID_REPLACE, false); 1164 1165 /* force flow control for non-PHY ports only */ 1166 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, 1167 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, 1168 !dev->info->internal_phy[port]); 1169 1170 if (cpu_port) 1171 member = dsa_user_ports(ds); 1172 else 1173 member = BIT(dsa_upstream_port(ds, port)); 1174 1175 ksz9477_cfg_port_member(dev, port, member); 1176 1177 /* clear pending interrupts */ 1178 if (dev->info->internal_phy[port]) 1179 ksz_pread16(dev, port, REG_PORT_PHY_INT_ENABLE, &data16); 1180 1181 ksz9477_port_acl_init(dev, port); 1182 1183 /* clear pending wake flags */ 1184 ksz9477_handle_wake_reason(dev, port); 1185 1186 /* Disable all WoL options by default. Otherwise 1187 * ksz_switch_macaddr_get/put logic will not work properly. 1188 */ 1189 ksz_pwrite8(dev, port, REG_PORT_PME_CTRL, 0); 1190 } 1191 1192 void ksz9477_config_cpu_port(struct dsa_switch *ds) 1193 { 1194 struct ksz_device *dev = ds->priv; 1195 struct ksz_port *p; 1196 int i; 1197 1198 for (i = 0; i < dev->info->port_cnt; i++) { 1199 if (dsa_is_cpu_port(ds, i) && 1200 (dev->info->cpu_ports & (1 << i))) { 1201 phy_interface_t interface; 1202 const char *prev_msg; 1203 const char *prev_mode; 1204 1205 dev->cpu_port = i; 1206 p = &dev->ports[i]; 1207 1208 /* Read from XMII register to determine host port 1209 * interface. If set specifically in device tree 1210 * note the difference to help debugging. 1211 */ 1212 interface = ksz9477_get_interface(dev, i); 1213 if (!p->interface) { 1214 if (dev->compat_interface) { 1215 dev_warn(dev->dev, 1216 "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. " 1217 "Please update your device tree.\n", 1218 i); 1219 p->interface = dev->compat_interface; 1220 } else { 1221 p->interface = interface; 1222 } 1223 } 1224 if (interface && interface != p->interface) { 1225 prev_msg = " instead of "; 1226 prev_mode = phy_modes(interface); 1227 } else { 1228 prev_msg = ""; 1229 prev_mode = ""; 1230 } 1231 dev_info(dev->dev, 1232 "Port%d: using phy mode %s%s%s\n", 1233 i, 1234 phy_modes(p->interface), 1235 prev_msg, 1236 prev_mode); 1237 1238 /* enable cpu port */ 1239 ksz9477_port_setup(dev, i, true); 1240 } 1241 } 1242 1243 for (i = 0; i < dev->info->port_cnt; i++) { 1244 if (i == dev->cpu_port) 1245 continue; 1246 ksz_port_stp_state_set(ds, i, BR_STATE_DISABLED); 1247 } 1248 } 1249 1250 int ksz9477_enable_stp_addr(struct ksz_device *dev) 1251 { 1252 const u32 *masks; 1253 u32 data; 1254 int ret; 1255 1256 masks = dev->info->masks; 1257 1258 /* Enable Reserved multicast table */ 1259 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_RESV_MCAST_ENABLE, true); 1260 1261 /* Set the Override bit for forwarding BPDU packet to CPU */ 1262 ret = ksz_write32(dev, REG_SW_ALU_VAL_B, 1263 ALU_V_OVERRIDE | BIT(dev->cpu_port)); 1264 if (ret < 0) 1265 return ret; 1266 1267 data = ALU_STAT_START | ALU_RESV_MCAST_ADDR | masks[ALU_STAT_WRITE]; 1268 1269 ret = ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 1270 if (ret < 0) 1271 return ret; 1272 1273 /* wait to be finished */ 1274 ret = ksz9477_wait_alu_sta_ready(dev); 1275 if (ret < 0) { 1276 dev_err(dev->dev, "Failed to update Reserved Multicast table\n"); 1277 return ret; 1278 } 1279 1280 return 0; 1281 } 1282 1283 int ksz9477_setup(struct dsa_switch *ds) 1284 { 1285 struct ksz_device *dev = ds->priv; 1286 int ret = 0; 1287 1288 ds->mtu_enforcement_ingress = true; 1289 1290 /* Required for port partitioning. */ 1291 ksz9477_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY, 1292 true); 1293 1294 /* Do not work correctly with tail tagging. */ 1295 ksz_cfg(dev, REG_SW_MAC_CTRL_0, SW_CHECK_LENGTH, false); 1296 1297 /* Enable REG_SW_MTU__2 reg by setting SW_JUMBO_PACKET */ 1298 ksz_cfg(dev, REG_SW_MAC_CTRL_1, SW_JUMBO_PACKET, true); 1299 1300 /* Now we can configure default MTU value */ 1301 ret = regmap_update_bits(ksz_regmap_16(dev), REG_SW_MTU__2, REG_SW_MTU_MASK, 1302 VLAN_ETH_FRAME_LEN + ETH_FCS_LEN); 1303 if (ret) 1304 return ret; 1305 1306 /* queue based egress rate limit */ 1307 ksz_cfg(dev, REG_SW_MAC_CTRL_5, SW_OUT_RATE_LIMIT_QUEUE_BASED, true); 1308 1309 /* enable global MIB counter freeze function */ 1310 ksz_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true); 1311 1312 /* Make sure PME (WoL) is not enabled. If requested, it will be 1313 * enabled by ksz9477_wol_pre_shutdown(). Otherwise, some PMICs do not 1314 * like PME events changes before shutdown. 1315 */ 1316 ksz_write8(dev, REG_SW_PME_CTRL, 0); 1317 1318 return 0; 1319 } 1320 1321 u32 ksz9477_get_port_addr(int port, int offset) 1322 { 1323 return PORT_CTRL_ADDR(port, offset); 1324 } 1325 1326 int ksz9477_tc_cbs_set_cinc(struct ksz_device *dev, int port, u32 val) 1327 { 1328 val = val >> 8; 1329 1330 return ksz_pwrite16(dev, port, REG_PORT_MTI_CREDIT_INCREMENT, val); 1331 } 1332 1333 /* The KSZ9477 provides following HW features to accelerate 1334 * HSR frames handling: 1335 * 1336 * 1. TX PACKET DUPLICATION FROM HOST TO SWITCH 1337 * 2. RX PACKET DUPLICATION DISCARDING 1338 * 3. PREVENTING PACKET LOOP IN THE RING BY SELF-ADDRESS FILTERING 1339 * 1340 * Only one from point 1. has the NETIF_F* flag available. 1341 * 1342 * Ones from point 2 and 3 are "best effort" - i.e. those will 1343 * work correctly most of the time, but it may happen that some 1344 * frames will not be caught - to be more specific; there is a race 1345 * condition in hardware such that, when duplicate packets are received 1346 * on member ports very close in time to each other, the hardware fails 1347 * to detect that they are duplicates. 1348 * 1349 * Hence, the SW needs to handle those special cases. However, the speed 1350 * up gain is considerable when above features are used. 1351 * 1352 * Moreover, the NETIF_F_HW_HSR_FWD feature is also enabled, as HSR frames 1353 * can be forwarded in the switch fabric between HSR ports. 1354 */ 1355 #define KSZ9477_SUPPORTED_HSR_FEATURES (NETIF_F_HW_HSR_DUP | NETIF_F_HW_HSR_FWD) 1356 1357 void ksz9477_hsr_join(struct dsa_switch *ds, int port, struct net_device *hsr) 1358 { 1359 struct ksz_device *dev = ds->priv; 1360 struct net_device *user; 1361 struct dsa_port *hsr_dp; 1362 u8 data, hsr_ports = 0; 1363 1364 /* Program which port(s) shall support HSR */ 1365 ksz_rmw32(dev, REG_HSR_PORT_MAP__4, BIT(port), BIT(port)); 1366 1367 /* Forward frames between HSR ports (i.e. bridge together HSR ports) */ 1368 if (dev->hsr_ports) { 1369 dsa_hsr_foreach_port(hsr_dp, ds, hsr) 1370 hsr_ports |= BIT(hsr_dp->index); 1371 1372 hsr_ports |= BIT(dsa_upstream_port(ds, port)); 1373 dsa_hsr_foreach_port(hsr_dp, ds, hsr) 1374 ksz9477_cfg_port_member(dev, hsr_dp->index, hsr_ports); 1375 } 1376 1377 if (!dev->hsr_ports) { 1378 /* Enable discarding of received HSR frames */ 1379 ksz_read8(dev, REG_HSR_ALU_CTRL_0__1, &data); 1380 data |= HSR_DUPLICATE_DISCARD; 1381 data &= ~HSR_NODE_UNICAST; 1382 ksz_write8(dev, REG_HSR_ALU_CTRL_0__1, data); 1383 } 1384 1385 /* Enable per port self-address filtering. 1386 * The global self-address filtering has already been enabled in the 1387 * ksz9477_reset_switch() function. 1388 */ 1389 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, PORT_SRC_ADDR_FILTER, true); 1390 1391 /* Setup HW supported features for lan HSR ports */ 1392 user = dsa_to_port(ds, port)->user; 1393 user->features |= KSZ9477_SUPPORTED_HSR_FEATURES; 1394 } 1395 1396 void ksz9477_hsr_leave(struct dsa_switch *ds, int port, struct net_device *hsr) 1397 { 1398 struct ksz_device *dev = ds->priv; 1399 1400 /* Clear port HSR support */ 1401 ksz_rmw32(dev, REG_HSR_PORT_MAP__4, BIT(port), 0); 1402 1403 /* Disable forwarding frames between HSR ports */ 1404 ksz9477_cfg_port_member(dev, port, BIT(dsa_upstream_port(ds, port))); 1405 1406 /* Disable per port self-address filtering */ 1407 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, PORT_SRC_ADDR_FILTER, false); 1408 } 1409 1410 int ksz9477_switch_init(struct ksz_device *dev) 1411 { 1412 u8 data8; 1413 int ret; 1414 1415 dev->port_mask = (1 << dev->info->port_cnt) - 1; 1416 1417 /* turn off SPI DO Edge select */ 1418 ret = ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8); 1419 if (ret) 1420 return ret; 1421 1422 data8 &= ~SPI_AUTO_EDGE_DETECTION; 1423 ret = ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8); 1424 if (ret) 1425 return ret; 1426 1427 return 0; 1428 } 1429 1430 void ksz9477_switch_exit(struct ksz_device *dev) 1431 { 1432 ksz9477_reset_switch(dev); 1433 } 1434 1435 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 1436 MODULE_DESCRIPTION("Microchip KSZ9477 Series Switch DSA Driver"); 1437 MODULE_LICENSE("GPL"); 1438