1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip KSZ9477 switch driver main logic 4 * 5 * Copyright (C) 2017-2019 Microchip Technology Inc. 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/iopoll.h> 11 #include <linux/platform_data/microchip-ksz.h> 12 #include <linux/phy.h> 13 #include <linux/if_bridge.h> 14 #include <net/dsa.h> 15 #include <net/switchdev.h> 16 17 #include "ksz9477_reg.h" 18 #include "ksz_common.h" 19 20 /* Used with variable features to indicate capabilities. */ 21 #define GBIT_SUPPORT BIT(0) 22 #define NEW_XMII BIT(1) 23 #define IS_9893 BIT(2) 24 25 static const struct { 26 int index; 27 char string[ETH_GSTRING_LEN]; 28 } ksz9477_mib_names[TOTAL_SWITCH_COUNTER_NUM] = { 29 { 0x00, "rx_hi" }, 30 { 0x01, "rx_undersize" }, 31 { 0x02, "rx_fragments" }, 32 { 0x03, "rx_oversize" }, 33 { 0x04, "rx_jabbers" }, 34 { 0x05, "rx_symbol_err" }, 35 { 0x06, "rx_crc_err" }, 36 { 0x07, "rx_align_err" }, 37 { 0x08, "rx_mac_ctrl" }, 38 { 0x09, "rx_pause" }, 39 { 0x0A, "rx_bcast" }, 40 { 0x0B, "rx_mcast" }, 41 { 0x0C, "rx_ucast" }, 42 { 0x0D, "rx_64_or_less" }, 43 { 0x0E, "rx_65_127" }, 44 { 0x0F, "rx_128_255" }, 45 { 0x10, "rx_256_511" }, 46 { 0x11, "rx_512_1023" }, 47 { 0x12, "rx_1024_1522" }, 48 { 0x13, "rx_1523_2000" }, 49 { 0x14, "rx_2001" }, 50 { 0x15, "tx_hi" }, 51 { 0x16, "tx_late_col" }, 52 { 0x17, "tx_pause" }, 53 { 0x18, "tx_bcast" }, 54 { 0x19, "tx_mcast" }, 55 { 0x1A, "tx_ucast" }, 56 { 0x1B, "tx_deferred" }, 57 { 0x1C, "tx_total_col" }, 58 { 0x1D, "tx_exc_col" }, 59 { 0x1E, "tx_single_col" }, 60 { 0x1F, "tx_mult_col" }, 61 { 0x80, "rx_total" }, 62 { 0x81, "tx_total" }, 63 { 0x82, "rx_discards" }, 64 { 0x83, "tx_discards" }, 65 }; 66 67 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) 68 { 69 regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0); 70 } 71 72 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits, 73 bool set) 74 { 75 regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset), 76 bits, set ? bits : 0); 77 } 78 79 static void ksz9477_cfg32(struct ksz_device *dev, u32 addr, u32 bits, bool set) 80 { 81 regmap_update_bits(dev->regmap[2], addr, bits, set ? bits : 0); 82 } 83 84 static void ksz9477_port_cfg32(struct ksz_device *dev, int port, int offset, 85 u32 bits, bool set) 86 { 87 regmap_update_bits(dev->regmap[2], PORT_CTRL_ADDR(port, offset), 88 bits, set ? bits : 0); 89 } 90 91 static int ksz9477_wait_vlan_ctrl_ready(struct ksz_device *dev) 92 { 93 unsigned int val; 94 95 return regmap_read_poll_timeout(dev->regmap[0], REG_SW_VLAN_CTRL, 96 val, !(val & VLAN_START), 10, 1000); 97 } 98 99 static int ksz9477_get_vlan_table(struct ksz_device *dev, u16 vid, 100 u32 *vlan_table) 101 { 102 int ret; 103 104 mutex_lock(&dev->vlan_mutex); 105 106 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 107 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_READ | VLAN_START); 108 109 /* wait to be cleared */ 110 ret = ksz9477_wait_vlan_ctrl_ready(dev); 111 if (ret) { 112 dev_dbg(dev->dev, "Failed to read vlan table\n"); 113 goto exit; 114 } 115 116 ksz_read32(dev, REG_SW_VLAN_ENTRY__4, &vlan_table[0]); 117 ksz_read32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, &vlan_table[1]); 118 ksz_read32(dev, REG_SW_VLAN_ENTRY_PORTS__4, &vlan_table[2]); 119 120 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 121 122 exit: 123 mutex_unlock(&dev->vlan_mutex); 124 125 return ret; 126 } 127 128 static int ksz9477_set_vlan_table(struct ksz_device *dev, u16 vid, 129 u32 *vlan_table) 130 { 131 int ret; 132 133 mutex_lock(&dev->vlan_mutex); 134 135 ksz_write32(dev, REG_SW_VLAN_ENTRY__4, vlan_table[0]); 136 ksz_write32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, vlan_table[1]); 137 ksz_write32(dev, REG_SW_VLAN_ENTRY_PORTS__4, vlan_table[2]); 138 139 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 140 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_START | VLAN_WRITE); 141 142 /* wait to be cleared */ 143 ret = ksz9477_wait_vlan_ctrl_ready(dev); 144 if (ret) { 145 dev_dbg(dev->dev, "Failed to write vlan table\n"); 146 goto exit; 147 } 148 149 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 150 151 /* update vlan cache table */ 152 dev->vlan_cache[vid].table[0] = vlan_table[0]; 153 dev->vlan_cache[vid].table[1] = vlan_table[1]; 154 dev->vlan_cache[vid].table[2] = vlan_table[2]; 155 156 exit: 157 mutex_unlock(&dev->vlan_mutex); 158 159 return ret; 160 } 161 162 static void ksz9477_read_table(struct ksz_device *dev, u32 *table) 163 { 164 ksz_read32(dev, REG_SW_ALU_VAL_A, &table[0]); 165 ksz_read32(dev, REG_SW_ALU_VAL_B, &table[1]); 166 ksz_read32(dev, REG_SW_ALU_VAL_C, &table[2]); 167 ksz_read32(dev, REG_SW_ALU_VAL_D, &table[3]); 168 } 169 170 static void ksz9477_write_table(struct ksz_device *dev, u32 *table) 171 { 172 ksz_write32(dev, REG_SW_ALU_VAL_A, table[0]); 173 ksz_write32(dev, REG_SW_ALU_VAL_B, table[1]); 174 ksz_write32(dev, REG_SW_ALU_VAL_C, table[2]); 175 ksz_write32(dev, REG_SW_ALU_VAL_D, table[3]); 176 } 177 178 static int ksz9477_wait_alu_ready(struct ksz_device *dev) 179 { 180 unsigned int val; 181 182 return regmap_read_poll_timeout(dev->regmap[2], REG_SW_ALU_CTRL__4, 183 val, !(val & ALU_START), 10, 1000); 184 } 185 186 static int ksz9477_wait_alu_sta_ready(struct ksz_device *dev) 187 { 188 unsigned int val; 189 190 return regmap_read_poll_timeout(dev->regmap[2], 191 REG_SW_ALU_STAT_CTRL__4, 192 val, !(val & ALU_STAT_START), 193 10, 1000); 194 } 195 196 static int ksz9477_reset_switch(struct ksz_device *dev) 197 { 198 u8 data8; 199 u32 data32; 200 201 /* reset switch */ 202 ksz_cfg(dev, REG_SW_OPERATION, SW_RESET, true); 203 204 /* turn off SPI DO Edge select */ 205 regmap_update_bits(dev->regmap[0], REG_SW_GLOBAL_SERIAL_CTRL_0, 206 SPI_AUTO_EDGE_DETECTION, 0); 207 208 /* default configuration */ 209 ksz_read8(dev, REG_SW_LUE_CTRL_1, &data8); 210 data8 = SW_AGING_ENABLE | SW_LINK_AUTO_AGING | 211 SW_SRC_ADDR_FILTER | SW_FLUSH_STP_TABLE | SW_FLUSH_MSTP_TABLE; 212 ksz_write8(dev, REG_SW_LUE_CTRL_1, data8); 213 214 /* disable interrupts */ 215 ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK); 216 ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0x7F); 217 ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32); 218 219 /* set broadcast storm protection 10% rate */ 220 regmap_update_bits(dev->regmap[1], REG_SW_MAC_CTRL_2, 221 BROADCAST_STORM_RATE, 222 (BROADCAST_STORM_VALUE * 223 BROADCAST_STORM_PROT_RATE) / 100); 224 225 data8 = SW_ENABLE_REFCLKO; 226 if (dev->synclko_disable) 227 data8 = 0; 228 else if (dev->synclko_125) 229 data8 = SW_ENABLE_REFCLKO | SW_REFCLKO_IS_125MHZ; 230 ksz_write8(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1, data8); 231 232 return 0; 233 } 234 235 static void ksz9477_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, 236 u64 *cnt) 237 { 238 struct ksz_port *p = &dev->ports[port]; 239 unsigned int val; 240 u32 data; 241 int ret; 242 243 /* retain the flush/freeze bit */ 244 data = p->freeze ? MIB_COUNTER_FLUSH_FREEZE : 0; 245 data |= MIB_COUNTER_READ; 246 data |= (addr << MIB_COUNTER_INDEX_S); 247 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, data); 248 249 ret = regmap_read_poll_timeout(dev->regmap[2], 250 PORT_CTRL_ADDR(port, REG_PORT_MIB_CTRL_STAT__4), 251 val, !(val & MIB_COUNTER_READ), 10, 1000); 252 /* failed to read MIB. get out of loop */ 253 if (ret) { 254 dev_dbg(dev->dev, "Failed to get MIB\n"); 255 return; 256 } 257 258 /* count resets upon read */ 259 ksz_pread32(dev, port, REG_PORT_MIB_DATA, &data); 260 *cnt += data; 261 } 262 263 static void ksz9477_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 264 u64 *dropped, u64 *cnt) 265 { 266 addr = ksz9477_mib_names[addr].index; 267 ksz9477_r_mib_cnt(dev, port, addr, cnt); 268 } 269 270 static void ksz9477_freeze_mib(struct ksz_device *dev, int port, bool freeze) 271 { 272 u32 val = freeze ? MIB_COUNTER_FLUSH_FREEZE : 0; 273 struct ksz_port *p = &dev->ports[port]; 274 275 /* enable/disable the port for flush/freeze function */ 276 mutex_lock(&p->mib.cnt_mutex); 277 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, val); 278 279 /* used by MIB counter reading code to know freeze is enabled */ 280 p->freeze = freeze; 281 mutex_unlock(&p->mib.cnt_mutex); 282 } 283 284 static void ksz9477_port_init_cnt(struct ksz_device *dev, int port) 285 { 286 struct ksz_port_mib *mib = &dev->ports[port].mib; 287 288 /* flush all enabled port MIB counters */ 289 mutex_lock(&mib->cnt_mutex); 290 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 291 MIB_COUNTER_FLUSH_FREEZE); 292 ksz_write8(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FLUSH); 293 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 0); 294 mutex_unlock(&mib->cnt_mutex); 295 296 mib->cnt_ptr = 0; 297 memset(mib->counters, 0, dev->mib_cnt * sizeof(u64)); 298 } 299 300 static enum dsa_tag_protocol ksz9477_get_tag_protocol(struct dsa_switch *ds, 301 int port, 302 enum dsa_tag_protocol mp) 303 { 304 enum dsa_tag_protocol proto = DSA_TAG_PROTO_KSZ9477; 305 struct ksz_device *dev = ds->priv; 306 307 if (dev->features & IS_9893) 308 proto = DSA_TAG_PROTO_KSZ9893; 309 return proto; 310 } 311 312 static int ksz9477_phy_read16(struct dsa_switch *ds, int addr, int reg) 313 { 314 struct ksz_device *dev = ds->priv; 315 u16 val = 0xffff; 316 317 /* No real PHY after this. Simulate the PHY. 318 * A fixed PHY can be setup in the device tree, but this function is 319 * still called for that port during initialization. 320 * For RGMII PHY there is no way to access it so the fixed PHY should 321 * be used. For SGMII PHY the supporting code will be added later. 322 */ 323 if (addr >= dev->phy_port_cnt) { 324 struct ksz_port *p = &dev->ports[addr]; 325 326 switch (reg) { 327 case MII_BMCR: 328 val = 0x1140; 329 break; 330 case MII_BMSR: 331 val = 0x796d; 332 break; 333 case MII_PHYSID1: 334 val = 0x0022; 335 break; 336 case MII_PHYSID2: 337 val = 0x1631; 338 break; 339 case MII_ADVERTISE: 340 val = 0x05e1; 341 break; 342 case MII_LPA: 343 val = 0xc5e1; 344 break; 345 case MII_CTRL1000: 346 val = 0x0700; 347 break; 348 case MII_STAT1000: 349 if (p->phydev.speed == SPEED_1000) 350 val = 0x3800; 351 else 352 val = 0; 353 break; 354 } 355 } else { 356 ksz_pread16(dev, addr, 0x100 + (reg << 1), &val); 357 } 358 359 return val; 360 } 361 362 static int ksz9477_phy_write16(struct dsa_switch *ds, int addr, int reg, 363 u16 val) 364 { 365 struct ksz_device *dev = ds->priv; 366 367 /* No real PHY after this. */ 368 if (addr >= dev->phy_port_cnt) 369 return 0; 370 371 /* No gigabit support. Do not write to this register. */ 372 if (!(dev->features & GBIT_SUPPORT) && reg == MII_CTRL1000) 373 return 0; 374 ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val); 375 376 return 0; 377 } 378 379 static void ksz9477_get_strings(struct dsa_switch *ds, int port, 380 u32 stringset, uint8_t *buf) 381 { 382 int i; 383 384 if (stringset != ETH_SS_STATS) 385 return; 386 387 for (i = 0; i < TOTAL_SWITCH_COUNTER_NUM; i++) { 388 memcpy(buf + i * ETH_GSTRING_LEN, ksz9477_mib_names[i].string, 389 ETH_GSTRING_LEN); 390 } 391 } 392 393 static void ksz9477_cfg_port_member(struct ksz_device *dev, int port, 394 u8 member) 395 { 396 ksz_pwrite32(dev, port, REG_PORT_VLAN_MEMBERSHIP__4, member); 397 } 398 399 static void ksz9477_port_stp_state_set(struct dsa_switch *ds, int port, 400 u8 state) 401 { 402 struct ksz_device *dev = ds->priv; 403 struct ksz_port *p = &dev->ports[port]; 404 u8 data; 405 406 ksz_pread8(dev, port, P_STP_CTRL, &data); 407 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 408 409 switch (state) { 410 case BR_STATE_DISABLED: 411 data |= PORT_LEARN_DISABLE; 412 break; 413 case BR_STATE_LISTENING: 414 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 415 break; 416 case BR_STATE_LEARNING: 417 data |= PORT_RX_ENABLE; 418 break; 419 case BR_STATE_FORWARDING: 420 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 421 break; 422 case BR_STATE_BLOCKING: 423 data |= PORT_LEARN_DISABLE; 424 break; 425 default: 426 dev_err(ds->dev, "invalid STP state: %d\n", state); 427 return; 428 } 429 430 ksz_pwrite8(dev, port, P_STP_CTRL, data); 431 p->stp_state = state; 432 433 ksz_update_port_member(dev, port); 434 } 435 436 static void ksz9477_flush_dyn_mac_table(struct ksz_device *dev, int port) 437 { 438 u8 data; 439 440 regmap_update_bits(dev->regmap[0], REG_SW_LUE_CTRL_2, 441 SW_FLUSH_OPTION_M << SW_FLUSH_OPTION_S, 442 SW_FLUSH_OPTION_DYN_MAC << SW_FLUSH_OPTION_S); 443 444 if (port < dev->port_cnt) { 445 /* flush individual port */ 446 ksz_pread8(dev, port, P_STP_CTRL, &data); 447 if (!(data & PORT_LEARN_DISABLE)) 448 ksz_pwrite8(dev, port, P_STP_CTRL, 449 data | PORT_LEARN_DISABLE); 450 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true); 451 ksz_pwrite8(dev, port, P_STP_CTRL, data); 452 } else { 453 /* flush all */ 454 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_STP_TABLE, true); 455 } 456 } 457 458 static int ksz9477_port_vlan_filtering(struct dsa_switch *ds, int port, 459 bool flag, 460 struct netlink_ext_ack *extack) 461 { 462 struct ksz_device *dev = ds->priv; 463 464 if (flag) { 465 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 466 PORT_VLAN_LOOKUP_VID_0, true); 467 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, true); 468 } else { 469 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, false); 470 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 471 PORT_VLAN_LOOKUP_VID_0, false); 472 } 473 474 return 0; 475 } 476 477 static int ksz9477_port_vlan_add(struct dsa_switch *ds, int port, 478 const struct switchdev_obj_port_vlan *vlan, 479 struct netlink_ext_ack *extack) 480 { 481 struct ksz_device *dev = ds->priv; 482 u32 vlan_table[3]; 483 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 484 int err; 485 486 err = ksz9477_get_vlan_table(dev, vlan->vid, vlan_table); 487 if (err) { 488 NL_SET_ERR_MSG_MOD(extack, "Failed to get vlan table"); 489 return err; 490 } 491 492 vlan_table[0] = VLAN_VALID | (vlan->vid & VLAN_FID_M); 493 if (untagged) 494 vlan_table[1] |= BIT(port); 495 else 496 vlan_table[1] &= ~BIT(port); 497 vlan_table[1] &= ~(BIT(dev->cpu_port)); 498 499 vlan_table[2] |= BIT(port) | BIT(dev->cpu_port); 500 501 err = ksz9477_set_vlan_table(dev, vlan->vid, vlan_table); 502 if (err) { 503 NL_SET_ERR_MSG_MOD(extack, "Failed to set vlan table"); 504 return err; 505 } 506 507 /* change PVID */ 508 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) 509 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, vlan->vid); 510 511 return 0; 512 } 513 514 static int ksz9477_port_vlan_del(struct dsa_switch *ds, int port, 515 const struct switchdev_obj_port_vlan *vlan) 516 { 517 struct ksz_device *dev = ds->priv; 518 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 519 u32 vlan_table[3]; 520 u16 pvid; 521 522 ksz_pread16(dev, port, REG_PORT_DEFAULT_VID, &pvid); 523 pvid = pvid & 0xFFF; 524 525 if (ksz9477_get_vlan_table(dev, vlan->vid, vlan_table)) { 526 dev_dbg(dev->dev, "Failed to get vlan table\n"); 527 return -ETIMEDOUT; 528 } 529 530 vlan_table[2] &= ~BIT(port); 531 532 if (pvid == vlan->vid) 533 pvid = 1; 534 535 if (untagged) 536 vlan_table[1] &= ~BIT(port); 537 538 if (ksz9477_set_vlan_table(dev, vlan->vid, vlan_table)) { 539 dev_dbg(dev->dev, "Failed to set vlan table\n"); 540 return -ETIMEDOUT; 541 } 542 543 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, pvid); 544 545 return 0; 546 } 547 548 static int ksz9477_port_fdb_add(struct dsa_switch *ds, int port, 549 const unsigned char *addr, u16 vid) 550 { 551 struct ksz_device *dev = ds->priv; 552 u32 alu_table[4]; 553 u32 data; 554 int ret = 0; 555 556 mutex_lock(&dev->alu_mutex); 557 558 /* find any entry with mac & vid */ 559 data = vid << ALU_FID_INDEX_S; 560 data |= ((addr[0] << 8) | addr[1]); 561 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 562 563 data = ((addr[2] << 24) | (addr[3] << 16)); 564 data |= ((addr[4] << 8) | addr[5]); 565 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 566 567 /* start read operation */ 568 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 569 570 /* wait to be finished */ 571 ret = ksz9477_wait_alu_ready(dev); 572 if (ret) { 573 dev_dbg(dev->dev, "Failed to read ALU\n"); 574 goto exit; 575 } 576 577 /* read ALU entry */ 578 ksz9477_read_table(dev, alu_table); 579 580 /* update ALU entry */ 581 alu_table[0] = ALU_V_STATIC_VALID; 582 alu_table[1] |= BIT(port); 583 if (vid) 584 alu_table[1] |= ALU_V_USE_FID; 585 alu_table[2] = (vid << ALU_V_FID_S); 586 alu_table[2] |= ((addr[0] << 8) | addr[1]); 587 alu_table[3] = ((addr[2] << 24) | (addr[3] << 16)); 588 alu_table[3] |= ((addr[4] << 8) | addr[5]); 589 590 ksz9477_write_table(dev, alu_table); 591 592 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 593 594 /* wait to be finished */ 595 ret = ksz9477_wait_alu_ready(dev); 596 if (ret) 597 dev_dbg(dev->dev, "Failed to write ALU\n"); 598 599 exit: 600 mutex_unlock(&dev->alu_mutex); 601 602 return ret; 603 } 604 605 static int ksz9477_port_fdb_del(struct dsa_switch *ds, int port, 606 const unsigned char *addr, u16 vid) 607 { 608 struct ksz_device *dev = ds->priv; 609 u32 alu_table[4]; 610 u32 data; 611 int ret = 0; 612 613 mutex_lock(&dev->alu_mutex); 614 615 /* read any entry with mac & vid */ 616 data = vid << ALU_FID_INDEX_S; 617 data |= ((addr[0] << 8) | addr[1]); 618 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 619 620 data = ((addr[2] << 24) | (addr[3] << 16)); 621 data |= ((addr[4] << 8) | addr[5]); 622 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 623 624 /* start read operation */ 625 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 626 627 /* wait to be finished */ 628 ret = ksz9477_wait_alu_ready(dev); 629 if (ret) { 630 dev_dbg(dev->dev, "Failed to read ALU\n"); 631 goto exit; 632 } 633 634 ksz_read32(dev, REG_SW_ALU_VAL_A, &alu_table[0]); 635 if (alu_table[0] & ALU_V_STATIC_VALID) { 636 ksz_read32(dev, REG_SW_ALU_VAL_B, &alu_table[1]); 637 ksz_read32(dev, REG_SW_ALU_VAL_C, &alu_table[2]); 638 ksz_read32(dev, REG_SW_ALU_VAL_D, &alu_table[3]); 639 640 /* clear forwarding port */ 641 alu_table[2] &= ~BIT(port); 642 643 /* if there is no port to forward, clear table */ 644 if ((alu_table[2] & ALU_V_PORT_MAP) == 0) { 645 alu_table[0] = 0; 646 alu_table[1] = 0; 647 alu_table[2] = 0; 648 alu_table[3] = 0; 649 } 650 } else { 651 alu_table[0] = 0; 652 alu_table[1] = 0; 653 alu_table[2] = 0; 654 alu_table[3] = 0; 655 } 656 657 ksz9477_write_table(dev, alu_table); 658 659 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 660 661 /* wait to be finished */ 662 ret = ksz9477_wait_alu_ready(dev); 663 if (ret) 664 dev_dbg(dev->dev, "Failed to write ALU\n"); 665 666 exit: 667 mutex_unlock(&dev->alu_mutex); 668 669 return ret; 670 } 671 672 static void ksz9477_convert_alu(struct alu_struct *alu, u32 *alu_table) 673 { 674 alu->is_static = !!(alu_table[0] & ALU_V_STATIC_VALID); 675 alu->is_src_filter = !!(alu_table[0] & ALU_V_SRC_FILTER); 676 alu->is_dst_filter = !!(alu_table[0] & ALU_V_DST_FILTER); 677 alu->prio_age = (alu_table[0] >> ALU_V_PRIO_AGE_CNT_S) & 678 ALU_V_PRIO_AGE_CNT_M; 679 alu->mstp = alu_table[0] & ALU_V_MSTP_M; 680 681 alu->is_override = !!(alu_table[1] & ALU_V_OVERRIDE); 682 alu->is_use_fid = !!(alu_table[1] & ALU_V_USE_FID); 683 alu->port_forward = alu_table[1] & ALU_V_PORT_MAP; 684 685 alu->fid = (alu_table[2] >> ALU_V_FID_S) & ALU_V_FID_M; 686 687 alu->mac[0] = (alu_table[2] >> 8) & 0xFF; 688 alu->mac[1] = alu_table[2] & 0xFF; 689 alu->mac[2] = (alu_table[3] >> 24) & 0xFF; 690 alu->mac[3] = (alu_table[3] >> 16) & 0xFF; 691 alu->mac[4] = (alu_table[3] >> 8) & 0xFF; 692 alu->mac[5] = alu_table[3] & 0xFF; 693 } 694 695 static int ksz9477_port_fdb_dump(struct dsa_switch *ds, int port, 696 dsa_fdb_dump_cb_t *cb, void *data) 697 { 698 struct ksz_device *dev = ds->priv; 699 int ret = 0; 700 u32 ksz_data; 701 u32 alu_table[4]; 702 struct alu_struct alu; 703 int timeout; 704 705 mutex_lock(&dev->alu_mutex); 706 707 /* start ALU search */ 708 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_START | ALU_SEARCH); 709 710 do { 711 timeout = 1000; 712 do { 713 ksz_read32(dev, REG_SW_ALU_CTRL__4, &ksz_data); 714 if ((ksz_data & ALU_VALID) || !(ksz_data & ALU_START)) 715 break; 716 usleep_range(1, 10); 717 } while (timeout-- > 0); 718 719 if (!timeout) { 720 dev_dbg(dev->dev, "Failed to search ALU\n"); 721 ret = -ETIMEDOUT; 722 goto exit; 723 } 724 725 /* read ALU table */ 726 ksz9477_read_table(dev, alu_table); 727 728 ksz9477_convert_alu(&alu, alu_table); 729 730 if (alu.port_forward & BIT(port)) { 731 ret = cb(alu.mac, alu.fid, alu.is_static, data); 732 if (ret) 733 goto exit; 734 } 735 } while (ksz_data & ALU_START); 736 737 exit: 738 739 /* stop ALU search */ 740 ksz_write32(dev, REG_SW_ALU_CTRL__4, 0); 741 742 mutex_unlock(&dev->alu_mutex); 743 744 return ret; 745 } 746 747 static int ksz9477_port_mdb_add(struct dsa_switch *ds, int port, 748 const struct switchdev_obj_port_mdb *mdb) 749 { 750 struct ksz_device *dev = ds->priv; 751 u32 static_table[4]; 752 u32 data; 753 int index; 754 u32 mac_hi, mac_lo; 755 int err = 0; 756 757 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 758 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 759 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 760 761 mutex_lock(&dev->alu_mutex); 762 763 for (index = 0; index < dev->num_statics; index++) { 764 /* find empty slot first */ 765 data = (index << ALU_STAT_INDEX_S) | 766 ALU_STAT_READ | ALU_STAT_START; 767 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 768 769 /* wait to be finished */ 770 err = ksz9477_wait_alu_sta_ready(dev); 771 if (err) { 772 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 773 goto exit; 774 } 775 776 /* read ALU static table */ 777 ksz9477_read_table(dev, static_table); 778 779 if (static_table[0] & ALU_V_STATIC_VALID) { 780 /* check this has same vid & mac address */ 781 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 782 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 783 static_table[3] == mac_lo) { 784 /* found matching one */ 785 break; 786 } 787 } else { 788 /* found empty one */ 789 break; 790 } 791 } 792 793 /* no available entry */ 794 if (index == dev->num_statics) { 795 err = -ENOSPC; 796 goto exit; 797 } 798 799 /* add entry */ 800 static_table[0] = ALU_V_STATIC_VALID; 801 static_table[1] |= BIT(port); 802 if (mdb->vid) 803 static_table[1] |= ALU_V_USE_FID; 804 static_table[2] = (mdb->vid << ALU_V_FID_S); 805 static_table[2] |= mac_hi; 806 static_table[3] = mac_lo; 807 808 ksz9477_write_table(dev, static_table); 809 810 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START; 811 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 812 813 /* wait to be finished */ 814 if (ksz9477_wait_alu_sta_ready(dev)) 815 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 816 817 exit: 818 mutex_unlock(&dev->alu_mutex); 819 return err; 820 } 821 822 static int ksz9477_port_mdb_del(struct dsa_switch *ds, int port, 823 const struct switchdev_obj_port_mdb *mdb) 824 { 825 struct ksz_device *dev = ds->priv; 826 u32 static_table[4]; 827 u32 data; 828 int index; 829 int ret = 0; 830 u32 mac_hi, mac_lo; 831 832 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 833 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 834 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 835 836 mutex_lock(&dev->alu_mutex); 837 838 for (index = 0; index < dev->num_statics; index++) { 839 /* find empty slot first */ 840 data = (index << ALU_STAT_INDEX_S) | 841 ALU_STAT_READ | ALU_STAT_START; 842 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 843 844 /* wait to be finished */ 845 ret = ksz9477_wait_alu_sta_ready(dev); 846 if (ret) { 847 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 848 goto exit; 849 } 850 851 /* read ALU static table */ 852 ksz9477_read_table(dev, static_table); 853 854 if (static_table[0] & ALU_V_STATIC_VALID) { 855 /* check this has same vid & mac address */ 856 857 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 858 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 859 static_table[3] == mac_lo) { 860 /* found matching one */ 861 break; 862 } 863 } 864 } 865 866 /* no available entry */ 867 if (index == dev->num_statics) 868 goto exit; 869 870 /* clear port */ 871 static_table[1] &= ~BIT(port); 872 873 if ((static_table[1] & ALU_V_PORT_MAP) == 0) { 874 /* delete entry */ 875 static_table[0] = 0; 876 static_table[1] = 0; 877 static_table[2] = 0; 878 static_table[3] = 0; 879 } 880 881 ksz9477_write_table(dev, static_table); 882 883 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START; 884 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 885 886 /* wait to be finished */ 887 ret = ksz9477_wait_alu_sta_ready(dev); 888 if (ret) 889 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 890 891 exit: 892 mutex_unlock(&dev->alu_mutex); 893 894 return ret; 895 } 896 897 static int ksz9477_port_mirror_add(struct dsa_switch *ds, int port, 898 struct dsa_mall_mirror_tc_entry *mirror, 899 bool ingress) 900 { 901 struct ksz_device *dev = ds->priv; 902 903 if (ingress) 904 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true); 905 else 906 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true); 907 908 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false); 909 910 /* configure mirror port */ 911 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 912 PORT_MIRROR_SNIFFER, true); 913 914 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false); 915 916 return 0; 917 } 918 919 static void ksz9477_port_mirror_del(struct dsa_switch *ds, int port, 920 struct dsa_mall_mirror_tc_entry *mirror) 921 { 922 struct ksz_device *dev = ds->priv; 923 u8 data; 924 925 if (mirror->ingress) 926 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false); 927 else 928 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false); 929 930 ksz_pread8(dev, port, P_MIRROR_CTRL, &data); 931 932 if (!(data & (PORT_MIRROR_RX | PORT_MIRROR_TX))) 933 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 934 PORT_MIRROR_SNIFFER, false); 935 } 936 937 static bool ksz9477_get_gbit(struct ksz_device *dev, u8 data) 938 { 939 bool gbit; 940 941 if (dev->features & NEW_XMII) 942 gbit = !(data & PORT_MII_NOT_1GBIT); 943 else 944 gbit = !!(data & PORT_MII_1000MBIT_S1); 945 return gbit; 946 } 947 948 static void ksz9477_set_gbit(struct ksz_device *dev, bool gbit, u8 *data) 949 { 950 if (dev->features & NEW_XMII) { 951 if (gbit) 952 *data &= ~PORT_MII_NOT_1GBIT; 953 else 954 *data |= PORT_MII_NOT_1GBIT; 955 } else { 956 if (gbit) 957 *data |= PORT_MII_1000MBIT_S1; 958 else 959 *data &= ~PORT_MII_1000MBIT_S1; 960 } 961 } 962 963 static int ksz9477_get_xmii(struct ksz_device *dev, u8 data) 964 { 965 int mode; 966 967 if (dev->features & NEW_XMII) { 968 switch (data & PORT_MII_SEL_M) { 969 case PORT_MII_SEL: 970 mode = 0; 971 break; 972 case PORT_RMII_SEL: 973 mode = 1; 974 break; 975 case PORT_GMII_SEL: 976 mode = 2; 977 break; 978 default: 979 mode = 3; 980 } 981 } else { 982 switch (data & PORT_MII_SEL_M) { 983 case PORT_MII_SEL_S1: 984 mode = 0; 985 break; 986 case PORT_RMII_SEL_S1: 987 mode = 1; 988 break; 989 case PORT_GMII_SEL_S1: 990 mode = 2; 991 break; 992 default: 993 mode = 3; 994 } 995 } 996 return mode; 997 } 998 999 static void ksz9477_set_xmii(struct ksz_device *dev, int mode, u8 *data) 1000 { 1001 u8 xmii; 1002 1003 if (dev->features & NEW_XMII) { 1004 switch (mode) { 1005 case 0: 1006 xmii = PORT_MII_SEL; 1007 break; 1008 case 1: 1009 xmii = PORT_RMII_SEL; 1010 break; 1011 case 2: 1012 xmii = PORT_GMII_SEL; 1013 break; 1014 default: 1015 xmii = PORT_RGMII_SEL; 1016 break; 1017 } 1018 } else { 1019 switch (mode) { 1020 case 0: 1021 xmii = PORT_MII_SEL_S1; 1022 break; 1023 case 1: 1024 xmii = PORT_RMII_SEL_S1; 1025 break; 1026 case 2: 1027 xmii = PORT_GMII_SEL_S1; 1028 break; 1029 default: 1030 xmii = PORT_RGMII_SEL_S1; 1031 break; 1032 } 1033 } 1034 *data &= ~PORT_MII_SEL_M; 1035 *data |= xmii; 1036 } 1037 1038 static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port) 1039 { 1040 phy_interface_t interface; 1041 bool gbit; 1042 int mode; 1043 u8 data8; 1044 1045 if (port < dev->phy_port_cnt) 1046 return PHY_INTERFACE_MODE_NA; 1047 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8); 1048 gbit = ksz9477_get_gbit(dev, data8); 1049 mode = ksz9477_get_xmii(dev, data8); 1050 switch (mode) { 1051 case 2: 1052 interface = PHY_INTERFACE_MODE_GMII; 1053 if (gbit) 1054 break; 1055 fallthrough; 1056 case 0: 1057 interface = PHY_INTERFACE_MODE_MII; 1058 break; 1059 case 1: 1060 interface = PHY_INTERFACE_MODE_RMII; 1061 break; 1062 default: 1063 interface = PHY_INTERFACE_MODE_RGMII; 1064 if (data8 & PORT_RGMII_ID_EG_ENABLE) 1065 interface = PHY_INTERFACE_MODE_RGMII_TXID; 1066 if (data8 & PORT_RGMII_ID_IG_ENABLE) { 1067 interface = PHY_INTERFACE_MODE_RGMII_RXID; 1068 if (data8 & PORT_RGMII_ID_EG_ENABLE) 1069 interface = PHY_INTERFACE_MODE_RGMII_ID; 1070 } 1071 break; 1072 } 1073 return interface; 1074 } 1075 1076 static void ksz9477_port_mmd_write(struct ksz_device *dev, int port, 1077 u8 dev_addr, u16 reg_addr, u16 val) 1078 { 1079 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, 1080 MMD_SETUP(PORT_MMD_OP_INDEX, dev_addr)); 1081 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, reg_addr); 1082 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, 1083 MMD_SETUP(PORT_MMD_OP_DATA_NO_INCR, dev_addr)); 1084 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, val); 1085 } 1086 1087 static void ksz9477_phy_errata_setup(struct ksz_device *dev, int port) 1088 { 1089 /* Apply PHY settings to address errata listed in 1090 * KSZ9477, KSZ9897, KSZ9896, KSZ9567, KSZ8565 1091 * Silicon Errata and Data Sheet Clarification documents: 1092 * 1093 * Register settings are needed to improve PHY receive performance 1094 */ 1095 ksz9477_port_mmd_write(dev, port, 0x01, 0x6f, 0xdd0b); 1096 ksz9477_port_mmd_write(dev, port, 0x01, 0x8f, 0x6032); 1097 ksz9477_port_mmd_write(dev, port, 0x01, 0x9d, 0x248c); 1098 ksz9477_port_mmd_write(dev, port, 0x01, 0x75, 0x0060); 1099 ksz9477_port_mmd_write(dev, port, 0x01, 0xd3, 0x7777); 1100 ksz9477_port_mmd_write(dev, port, 0x1c, 0x06, 0x3008); 1101 ksz9477_port_mmd_write(dev, port, 0x1c, 0x08, 0x2001); 1102 1103 /* Transmit waveform amplitude can be improved 1104 * (1000BASE-T, 100BASE-TX, 10BASE-Te) 1105 */ 1106 ksz9477_port_mmd_write(dev, port, 0x1c, 0x04, 0x00d0); 1107 1108 /* Energy Efficient Ethernet (EEE) feature select must 1109 * be manually disabled (except on KSZ8565 which is 100Mbit) 1110 */ 1111 if (dev->features & GBIT_SUPPORT) 1112 ksz9477_port_mmd_write(dev, port, 0x07, 0x3c, 0x0000); 1113 1114 /* Register settings are required to meet data sheet 1115 * supply current specifications 1116 */ 1117 ksz9477_port_mmd_write(dev, port, 0x1c, 0x13, 0x6eff); 1118 ksz9477_port_mmd_write(dev, port, 0x1c, 0x14, 0xe6ff); 1119 ksz9477_port_mmd_write(dev, port, 0x1c, 0x15, 0x6eff); 1120 ksz9477_port_mmd_write(dev, port, 0x1c, 0x16, 0xe6ff); 1121 ksz9477_port_mmd_write(dev, port, 0x1c, 0x17, 0x00ff); 1122 ksz9477_port_mmd_write(dev, port, 0x1c, 0x18, 0x43ff); 1123 ksz9477_port_mmd_write(dev, port, 0x1c, 0x19, 0xc3ff); 1124 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1a, 0x6fff); 1125 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1b, 0x07ff); 1126 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1c, 0x0fff); 1127 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1d, 0xe7ff); 1128 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1e, 0xefff); 1129 ksz9477_port_mmd_write(dev, port, 0x1c, 0x20, 0xeeee); 1130 } 1131 1132 static void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port) 1133 { 1134 struct ksz_port *p = &dev->ports[port]; 1135 struct dsa_switch *ds = dev->ds; 1136 u8 data8, member; 1137 u16 data16; 1138 1139 /* enable tag tail for host port */ 1140 if (cpu_port) 1141 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_TAIL_TAG_ENABLE, 1142 true); 1143 1144 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_MAC_LOOPBACK, false); 1145 1146 /* set back pressure */ 1147 ksz_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, true); 1148 1149 /* enable broadcast storm limit */ 1150 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true); 1151 1152 /* disable DiffServ priority */ 1153 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_PRIO_ENABLE, false); 1154 1155 /* replace priority */ 1156 ksz_port_cfg(dev, port, REG_PORT_MRI_MAC_CTRL, PORT_USER_PRIO_CEILING, 1157 false); 1158 ksz9477_port_cfg32(dev, port, REG_PORT_MTI_QUEUE_CTRL_0__4, 1159 MTI_PVID_REPLACE, false); 1160 1161 /* enable 802.1p priority */ 1162 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true); 1163 1164 if (port < dev->phy_port_cnt) { 1165 /* do not force flow control */ 1166 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, 1167 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, 1168 false); 1169 1170 if (dev->phy_errata_9477) 1171 ksz9477_phy_errata_setup(dev, port); 1172 } else { 1173 /* force flow control */ 1174 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, 1175 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, 1176 true); 1177 1178 /* configure MAC to 1G & RGMII mode */ 1179 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8); 1180 switch (p->interface) { 1181 case PHY_INTERFACE_MODE_MII: 1182 ksz9477_set_xmii(dev, 0, &data8); 1183 ksz9477_set_gbit(dev, false, &data8); 1184 p->phydev.speed = SPEED_100; 1185 break; 1186 case PHY_INTERFACE_MODE_RMII: 1187 ksz9477_set_xmii(dev, 1, &data8); 1188 ksz9477_set_gbit(dev, false, &data8); 1189 p->phydev.speed = SPEED_100; 1190 break; 1191 case PHY_INTERFACE_MODE_GMII: 1192 ksz9477_set_xmii(dev, 2, &data8); 1193 ksz9477_set_gbit(dev, true, &data8); 1194 p->phydev.speed = SPEED_1000; 1195 break; 1196 default: 1197 ksz9477_set_xmii(dev, 3, &data8); 1198 ksz9477_set_gbit(dev, true, &data8); 1199 data8 &= ~PORT_RGMII_ID_IG_ENABLE; 1200 data8 &= ~PORT_RGMII_ID_EG_ENABLE; 1201 if (p->interface == PHY_INTERFACE_MODE_RGMII_ID || 1202 p->interface == PHY_INTERFACE_MODE_RGMII_RXID) 1203 data8 |= PORT_RGMII_ID_IG_ENABLE; 1204 if (p->interface == PHY_INTERFACE_MODE_RGMII_ID || 1205 p->interface == PHY_INTERFACE_MODE_RGMII_TXID) 1206 data8 |= PORT_RGMII_ID_EG_ENABLE; 1207 /* On KSZ9893, disable RGMII in-band status support */ 1208 if (dev->features & IS_9893) 1209 data8 &= ~PORT_MII_MAC_MODE; 1210 p->phydev.speed = SPEED_1000; 1211 break; 1212 } 1213 ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, data8); 1214 p->phydev.duplex = 1; 1215 } 1216 1217 if (cpu_port) 1218 member = dsa_user_ports(ds); 1219 else 1220 member = BIT(dsa_upstream_port(ds, port)); 1221 1222 ksz9477_cfg_port_member(dev, port, member); 1223 1224 /* clear pending interrupts */ 1225 if (port < dev->phy_port_cnt) 1226 ksz_pread16(dev, port, REG_PORT_PHY_INT_ENABLE, &data16); 1227 } 1228 1229 static void ksz9477_config_cpu_port(struct dsa_switch *ds) 1230 { 1231 struct ksz_device *dev = ds->priv; 1232 struct ksz_port *p; 1233 int i; 1234 1235 for (i = 0; i < dev->port_cnt; i++) { 1236 if (dsa_is_cpu_port(ds, i) && (dev->cpu_ports & (1 << i))) { 1237 phy_interface_t interface; 1238 const char *prev_msg; 1239 const char *prev_mode; 1240 1241 dev->cpu_port = i; 1242 p = &dev->ports[i]; 1243 1244 /* Read from XMII register to determine host port 1245 * interface. If set specifically in device tree 1246 * note the difference to help debugging. 1247 */ 1248 interface = ksz9477_get_interface(dev, i); 1249 if (!p->interface) { 1250 if (dev->compat_interface) { 1251 dev_warn(dev->dev, 1252 "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. " 1253 "Please update your device tree.\n", 1254 i); 1255 p->interface = dev->compat_interface; 1256 } else { 1257 p->interface = interface; 1258 } 1259 } 1260 if (interface && interface != p->interface) { 1261 prev_msg = " instead of "; 1262 prev_mode = phy_modes(interface); 1263 } else { 1264 prev_msg = ""; 1265 prev_mode = ""; 1266 } 1267 dev_info(dev->dev, 1268 "Port%d: using phy mode %s%s%s\n", 1269 i, 1270 phy_modes(p->interface), 1271 prev_msg, 1272 prev_mode); 1273 1274 /* enable cpu port */ 1275 ksz9477_port_setup(dev, i, true); 1276 p->on = 1; 1277 } 1278 } 1279 1280 for (i = 0; i < dev->port_cnt; i++) { 1281 if (i == dev->cpu_port) 1282 continue; 1283 p = &dev->ports[i]; 1284 1285 ksz9477_port_stp_state_set(ds, i, BR_STATE_DISABLED); 1286 p->on = 1; 1287 if (i < dev->phy_port_cnt) 1288 p->phy = 1; 1289 if (dev->chip_id == 0x00947700 && i == 6) { 1290 p->sgmii = 1; 1291 1292 /* SGMII PHY detection code is not implemented yet. */ 1293 p->phy = 0; 1294 } 1295 } 1296 } 1297 1298 static int ksz9477_setup(struct dsa_switch *ds) 1299 { 1300 struct ksz_device *dev = ds->priv; 1301 int ret = 0; 1302 1303 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 1304 dev->num_vlans, GFP_KERNEL); 1305 if (!dev->vlan_cache) 1306 return -ENOMEM; 1307 1308 ret = ksz9477_reset_switch(dev); 1309 if (ret) { 1310 dev_err(ds->dev, "failed to reset switch\n"); 1311 return ret; 1312 } 1313 1314 /* Required for port partitioning. */ 1315 ksz9477_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY, 1316 true); 1317 1318 /* Do not work correctly with tail tagging. */ 1319 ksz_cfg(dev, REG_SW_MAC_CTRL_0, SW_CHECK_LENGTH, false); 1320 1321 /* accept packet up to 2000bytes */ 1322 ksz_cfg(dev, REG_SW_MAC_CTRL_1, SW_LEGAL_PACKET_DISABLE, true); 1323 1324 ksz9477_config_cpu_port(ds); 1325 1326 ksz_cfg(dev, REG_SW_MAC_CTRL_1, MULTICAST_STORM_DISABLE, true); 1327 1328 /* queue based egress rate limit */ 1329 ksz_cfg(dev, REG_SW_MAC_CTRL_5, SW_OUT_RATE_LIMIT_QUEUE_BASED, true); 1330 1331 /* enable global MIB counter freeze function */ 1332 ksz_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true); 1333 1334 /* start switch */ 1335 ksz_cfg(dev, REG_SW_OPERATION, SW_START, true); 1336 1337 ksz_init_mib_timer(dev); 1338 1339 ds->configure_vlan_while_not_filtering = false; 1340 1341 return 0; 1342 } 1343 1344 static const struct dsa_switch_ops ksz9477_switch_ops = { 1345 .get_tag_protocol = ksz9477_get_tag_protocol, 1346 .setup = ksz9477_setup, 1347 .phy_read = ksz9477_phy_read16, 1348 .phy_write = ksz9477_phy_write16, 1349 .phylink_mac_link_down = ksz_mac_link_down, 1350 .port_enable = ksz_enable_port, 1351 .get_strings = ksz9477_get_strings, 1352 .get_ethtool_stats = ksz_get_ethtool_stats, 1353 .get_sset_count = ksz_sset_count, 1354 .port_bridge_join = ksz_port_bridge_join, 1355 .port_bridge_leave = ksz_port_bridge_leave, 1356 .port_stp_state_set = ksz9477_port_stp_state_set, 1357 .port_fast_age = ksz_port_fast_age, 1358 .port_vlan_filtering = ksz9477_port_vlan_filtering, 1359 .port_vlan_add = ksz9477_port_vlan_add, 1360 .port_vlan_del = ksz9477_port_vlan_del, 1361 .port_fdb_dump = ksz9477_port_fdb_dump, 1362 .port_fdb_add = ksz9477_port_fdb_add, 1363 .port_fdb_del = ksz9477_port_fdb_del, 1364 .port_mdb_add = ksz9477_port_mdb_add, 1365 .port_mdb_del = ksz9477_port_mdb_del, 1366 .port_mirror_add = ksz9477_port_mirror_add, 1367 .port_mirror_del = ksz9477_port_mirror_del, 1368 }; 1369 1370 static u32 ksz9477_get_port_addr(int port, int offset) 1371 { 1372 return PORT_CTRL_ADDR(port, offset); 1373 } 1374 1375 static int ksz9477_switch_detect(struct ksz_device *dev) 1376 { 1377 u8 data8; 1378 u8 id_hi; 1379 u8 id_lo; 1380 u32 id32; 1381 int ret; 1382 1383 /* turn off SPI DO Edge select */ 1384 ret = ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8); 1385 if (ret) 1386 return ret; 1387 1388 data8 &= ~SPI_AUTO_EDGE_DETECTION; 1389 ret = ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8); 1390 if (ret) 1391 return ret; 1392 1393 /* read chip id */ 1394 ret = ksz_read32(dev, REG_CHIP_ID0__1, &id32); 1395 if (ret) 1396 return ret; 1397 ret = ksz_read8(dev, REG_GLOBAL_OPTIONS, &data8); 1398 if (ret) 1399 return ret; 1400 1401 /* Number of ports can be reduced depending on chip. */ 1402 dev->phy_port_cnt = 5; 1403 1404 /* Default capability is gigabit capable. */ 1405 dev->features = GBIT_SUPPORT; 1406 1407 dev_dbg(dev->dev, "Switch detect: ID=%08x%02x\n", id32, data8); 1408 id_hi = (u8)(id32 >> 16); 1409 id_lo = (u8)(id32 >> 8); 1410 if ((id_lo & 0xf) == 3) { 1411 /* Chip is from KSZ9893 design. */ 1412 dev_info(dev->dev, "Found KSZ9893\n"); 1413 dev->features |= IS_9893; 1414 1415 /* Chip does not support gigabit. */ 1416 if (data8 & SW_QW_ABLE) 1417 dev->features &= ~GBIT_SUPPORT; 1418 dev->phy_port_cnt = 2; 1419 } else { 1420 dev_info(dev->dev, "Found KSZ9477 or compatible\n"); 1421 /* Chip uses new XMII register definitions. */ 1422 dev->features |= NEW_XMII; 1423 1424 /* Chip does not support gigabit. */ 1425 if (!(data8 & SW_GIGABIT_ABLE)) 1426 dev->features &= ~GBIT_SUPPORT; 1427 } 1428 1429 /* Change chip id to known ones so it can be matched against them. */ 1430 id32 = (id_hi << 16) | (id_lo << 8); 1431 1432 dev->chip_id = id32; 1433 1434 return 0; 1435 } 1436 1437 struct ksz_chip_data { 1438 u32 chip_id; 1439 const char *dev_name; 1440 int num_vlans; 1441 int num_alus; 1442 int num_statics; 1443 int cpu_ports; 1444 int port_cnt; 1445 bool phy_errata_9477; 1446 }; 1447 1448 static const struct ksz_chip_data ksz9477_switch_chips[] = { 1449 { 1450 .chip_id = 0x00947700, 1451 .dev_name = "KSZ9477", 1452 .num_vlans = 4096, 1453 .num_alus = 4096, 1454 .num_statics = 16, 1455 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1456 .port_cnt = 7, /* total physical port count */ 1457 .phy_errata_9477 = true, 1458 }, 1459 { 1460 .chip_id = 0x00989700, 1461 .dev_name = "KSZ9897", 1462 .num_vlans = 4096, 1463 .num_alus = 4096, 1464 .num_statics = 16, 1465 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1466 .port_cnt = 7, /* total physical port count */ 1467 .phy_errata_9477 = true, 1468 }, 1469 { 1470 .chip_id = 0x00989300, 1471 .dev_name = "KSZ9893", 1472 .num_vlans = 4096, 1473 .num_alus = 4096, 1474 .num_statics = 16, 1475 .cpu_ports = 0x07, /* can be configured as cpu port */ 1476 .port_cnt = 3, /* total port count */ 1477 }, 1478 { 1479 .chip_id = 0x00956700, 1480 .dev_name = "KSZ9567", 1481 .num_vlans = 4096, 1482 .num_alus = 4096, 1483 .num_statics = 16, 1484 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1485 .port_cnt = 7, /* total physical port count */ 1486 .phy_errata_9477 = true, 1487 }, 1488 }; 1489 1490 static int ksz9477_switch_init(struct ksz_device *dev) 1491 { 1492 int i; 1493 1494 dev->ds->ops = &ksz9477_switch_ops; 1495 1496 for (i = 0; i < ARRAY_SIZE(ksz9477_switch_chips); i++) { 1497 const struct ksz_chip_data *chip = &ksz9477_switch_chips[i]; 1498 1499 if (dev->chip_id == chip->chip_id) { 1500 dev->name = chip->dev_name; 1501 dev->num_vlans = chip->num_vlans; 1502 dev->num_alus = chip->num_alus; 1503 dev->num_statics = chip->num_statics; 1504 dev->port_cnt = chip->port_cnt; 1505 dev->cpu_ports = chip->cpu_ports; 1506 dev->phy_errata_9477 = chip->phy_errata_9477; 1507 1508 break; 1509 } 1510 } 1511 1512 /* no switch found */ 1513 if (!dev->port_cnt) 1514 return -ENODEV; 1515 1516 dev->port_mask = (1 << dev->port_cnt) - 1; 1517 1518 dev->reg_mib_cnt = SWITCH_COUNTER_NUM; 1519 dev->mib_cnt = TOTAL_SWITCH_COUNTER_NUM; 1520 1521 dev->ports = devm_kzalloc(dev->dev, 1522 dev->port_cnt * sizeof(struct ksz_port), 1523 GFP_KERNEL); 1524 if (!dev->ports) 1525 return -ENOMEM; 1526 for (i = 0; i < dev->port_cnt; i++) { 1527 mutex_init(&dev->ports[i].mib.cnt_mutex); 1528 dev->ports[i].mib.counters = 1529 devm_kzalloc(dev->dev, 1530 sizeof(u64) * 1531 (TOTAL_SWITCH_COUNTER_NUM + 1), 1532 GFP_KERNEL); 1533 if (!dev->ports[i].mib.counters) 1534 return -ENOMEM; 1535 } 1536 1537 /* set the real number of ports */ 1538 dev->ds->num_ports = dev->port_cnt; 1539 1540 return 0; 1541 } 1542 1543 static void ksz9477_switch_exit(struct ksz_device *dev) 1544 { 1545 ksz9477_reset_switch(dev); 1546 } 1547 1548 static const struct ksz_dev_ops ksz9477_dev_ops = { 1549 .get_port_addr = ksz9477_get_port_addr, 1550 .cfg_port_member = ksz9477_cfg_port_member, 1551 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 1552 .port_setup = ksz9477_port_setup, 1553 .r_mib_cnt = ksz9477_r_mib_cnt, 1554 .r_mib_pkt = ksz9477_r_mib_pkt, 1555 .freeze_mib = ksz9477_freeze_mib, 1556 .port_init_cnt = ksz9477_port_init_cnt, 1557 .shutdown = ksz9477_reset_switch, 1558 .detect = ksz9477_switch_detect, 1559 .init = ksz9477_switch_init, 1560 .exit = ksz9477_switch_exit, 1561 }; 1562 1563 int ksz9477_switch_register(struct ksz_device *dev) 1564 { 1565 int ret, i; 1566 struct phy_device *phydev; 1567 1568 ret = ksz_switch_register(dev, &ksz9477_dev_ops); 1569 if (ret) 1570 return ret; 1571 1572 for (i = 0; i < dev->phy_port_cnt; ++i) { 1573 if (!dsa_is_user_port(dev->ds, i)) 1574 continue; 1575 1576 phydev = dsa_to_port(dev->ds, i)->slave->phydev; 1577 1578 /* The MAC actually cannot run in 1000 half-duplex mode. */ 1579 phy_remove_link_mode(phydev, 1580 ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1581 1582 /* PHY does not support gigabit. */ 1583 if (!(dev->features & GBIT_SUPPORT)) 1584 phy_remove_link_mode(phydev, 1585 ETHTOOL_LINK_MODE_1000baseT_Full_BIT); 1586 } 1587 return ret; 1588 } 1589 EXPORT_SYMBOL(ksz9477_switch_register); 1590 1591 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 1592 MODULE_DESCRIPTION("Microchip KSZ9477 Series Switch DSA Driver"); 1593 MODULE_LICENSE("GPL"); 1594