1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip KSZ9477 switch driver main logic 4 * 5 * Copyright (C) 2017-2019 Microchip Technology Inc. 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/iopoll.h> 11 #include <linux/platform_data/microchip-ksz.h> 12 #include <linux/phy.h> 13 #include <linux/if_bridge.h> 14 #include <net/dsa.h> 15 #include <net/switchdev.h> 16 17 #include "ksz9477_reg.h" 18 #include "ksz_common.h" 19 20 /* Used with variable features to indicate capabilities. */ 21 #define GBIT_SUPPORT BIT(0) 22 #define NEW_XMII BIT(1) 23 #define IS_9893 BIT(2) 24 25 static const struct { 26 int index; 27 char string[ETH_GSTRING_LEN]; 28 } ksz9477_mib_names[TOTAL_SWITCH_COUNTER_NUM] = { 29 { 0x00, "rx_hi" }, 30 { 0x01, "rx_undersize" }, 31 { 0x02, "rx_fragments" }, 32 { 0x03, "rx_oversize" }, 33 { 0x04, "rx_jabbers" }, 34 { 0x05, "rx_symbol_err" }, 35 { 0x06, "rx_crc_err" }, 36 { 0x07, "rx_align_err" }, 37 { 0x08, "rx_mac_ctrl" }, 38 { 0x09, "rx_pause" }, 39 { 0x0A, "rx_bcast" }, 40 { 0x0B, "rx_mcast" }, 41 { 0x0C, "rx_ucast" }, 42 { 0x0D, "rx_64_or_less" }, 43 { 0x0E, "rx_65_127" }, 44 { 0x0F, "rx_128_255" }, 45 { 0x10, "rx_256_511" }, 46 { 0x11, "rx_512_1023" }, 47 { 0x12, "rx_1024_1522" }, 48 { 0x13, "rx_1523_2000" }, 49 { 0x14, "rx_2001" }, 50 { 0x15, "tx_hi" }, 51 { 0x16, "tx_late_col" }, 52 { 0x17, "tx_pause" }, 53 { 0x18, "tx_bcast" }, 54 { 0x19, "tx_mcast" }, 55 { 0x1A, "tx_ucast" }, 56 { 0x1B, "tx_deferred" }, 57 { 0x1C, "tx_total_col" }, 58 { 0x1D, "tx_exc_col" }, 59 { 0x1E, "tx_single_col" }, 60 { 0x1F, "tx_mult_col" }, 61 { 0x80, "rx_total" }, 62 { 0x81, "tx_total" }, 63 { 0x82, "rx_discards" }, 64 { 0x83, "tx_discards" }, 65 }; 66 67 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) 68 { 69 regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0); 70 } 71 72 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits, 73 bool set) 74 { 75 regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset), 76 bits, set ? bits : 0); 77 } 78 79 static void ksz9477_cfg32(struct ksz_device *dev, u32 addr, u32 bits, bool set) 80 { 81 regmap_update_bits(dev->regmap[2], addr, bits, set ? bits : 0); 82 } 83 84 static void ksz9477_port_cfg32(struct ksz_device *dev, int port, int offset, 85 u32 bits, bool set) 86 { 87 regmap_update_bits(dev->regmap[2], PORT_CTRL_ADDR(port, offset), 88 bits, set ? bits : 0); 89 } 90 91 static int ksz9477_wait_vlan_ctrl_ready(struct ksz_device *dev) 92 { 93 unsigned int val; 94 95 return regmap_read_poll_timeout(dev->regmap[0], REG_SW_VLAN_CTRL, 96 val, !(val & VLAN_START), 10, 1000); 97 } 98 99 static int ksz9477_get_vlan_table(struct ksz_device *dev, u16 vid, 100 u32 *vlan_table) 101 { 102 int ret; 103 104 mutex_lock(&dev->vlan_mutex); 105 106 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 107 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_READ | VLAN_START); 108 109 /* wait to be cleared */ 110 ret = ksz9477_wait_vlan_ctrl_ready(dev); 111 if (ret) { 112 dev_dbg(dev->dev, "Failed to read vlan table\n"); 113 goto exit; 114 } 115 116 ksz_read32(dev, REG_SW_VLAN_ENTRY__4, &vlan_table[0]); 117 ksz_read32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, &vlan_table[1]); 118 ksz_read32(dev, REG_SW_VLAN_ENTRY_PORTS__4, &vlan_table[2]); 119 120 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 121 122 exit: 123 mutex_unlock(&dev->vlan_mutex); 124 125 return ret; 126 } 127 128 static int ksz9477_set_vlan_table(struct ksz_device *dev, u16 vid, 129 u32 *vlan_table) 130 { 131 int ret; 132 133 mutex_lock(&dev->vlan_mutex); 134 135 ksz_write32(dev, REG_SW_VLAN_ENTRY__4, vlan_table[0]); 136 ksz_write32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, vlan_table[1]); 137 ksz_write32(dev, REG_SW_VLAN_ENTRY_PORTS__4, vlan_table[2]); 138 139 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 140 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_START | VLAN_WRITE); 141 142 /* wait to be cleared */ 143 ret = ksz9477_wait_vlan_ctrl_ready(dev); 144 if (ret) { 145 dev_dbg(dev->dev, "Failed to write vlan table\n"); 146 goto exit; 147 } 148 149 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 150 151 /* update vlan cache table */ 152 dev->vlan_cache[vid].table[0] = vlan_table[0]; 153 dev->vlan_cache[vid].table[1] = vlan_table[1]; 154 dev->vlan_cache[vid].table[2] = vlan_table[2]; 155 156 exit: 157 mutex_unlock(&dev->vlan_mutex); 158 159 return ret; 160 } 161 162 static void ksz9477_read_table(struct ksz_device *dev, u32 *table) 163 { 164 ksz_read32(dev, REG_SW_ALU_VAL_A, &table[0]); 165 ksz_read32(dev, REG_SW_ALU_VAL_B, &table[1]); 166 ksz_read32(dev, REG_SW_ALU_VAL_C, &table[2]); 167 ksz_read32(dev, REG_SW_ALU_VAL_D, &table[3]); 168 } 169 170 static void ksz9477_write_table(struct ksz_device *dev, u32 *table) 171 { 172 ksz_write32(dev, REG_SW_ALU_VAL_A, table[0]); 173 ksz_write32(dev, REG_SW_ALU_VAL_B, table[1]); 174 ksz_write32(dev, REG_SW_ALU_VAL_C, table[2]); 175 ksz_write32(dev, REG_SW_ALU_VAL_D, table[3]); 176 } 177 178 static int ksz9477_wait_alu_ready(struct ksz_device *dev) 179 { 180 unsigned int val; 181 182 return regmap_read_poll_timeout(dev->regmap[2], REG_SW_ALU_CTRL__4, 183 val, !(val & ALU_START), 10, 1000); 184 } 185 186 static int ksz9477_wait_alu_sta_ready(struct ksz_device *dev) 187 { 188 unsigned int val; 189 190 return regmap_read_poll_timeout(dev->regmap[2], 191 REG_SW_ALU_STAT_CTRL__4, 192 val, !(val & ALU_STAT_START), 193 10, 1000); 194 } 195 196 static int ksz9477_reset_switch(struct ksz_device *dev) 197 { 198 u8 data8; 199 u32 data32; 200 201 /* reset switch */ 202 ksz_cfg(dev, REG_SW_OPERATION, SW_RESET, true); 203 204 /* turn off SPI DO Edge select */ 205 regmap_update_bits(dev->regmap[0], REG_SW_GLOBAL_SERIAL_CTRL_0, 206 SPI_AUTO_EDGE_DETECTION, 0); 207 208 /* default configuration */ 209 ksz_read8(dev, REG_SW_LUE_CTRL_1, &data8); 210 data8 = SW_AGING_ENABLE | SW_LINK_AUTO_AGING | 211 SW_SRC_ADDR_FILTER | SW_FLUSH_STP_TABLE | SW_FLUSH_MSTP_TABLE; 212 ksz_write8(dev, REG_SW_LUE_CTRL_1, data8); 213 214 /* disable interrupts */ 215 ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK); 216 ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0x7F); 217 ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32); 218 219 /* set broadcast storm protection 10% rate */ 220 regmap_update_bits(dev->regmap[1], REG_SW_MAC_CTRL_2, 221 BROADCAST_STORM_RATE, 222 (BROADCAST_STORM_VALUE * 223 BROADCAST_STORM_PROT_RATE) / 100); 224 225 if (dev->synclko_125) 226 ksz_write8(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1, 227 SW_ENABLE_REFCLKO | SW_REFCLKO_IS_125MHZ); 228 229 return 0; 230 } 231 232 static void ksz9477_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, 233 u64 *cnt) 234 { 235 struct ksz_port *p = &dev->ports[port]; 236 unsigned int val; 237 u32 data; 238 int ret; 239 240 /* retain the flush/freeze bit */ 241 data = p->freeze ? MIB_COUNTER_FLUSH_FREEZE : 0; 242 data |= MIB_COUNTER_READ; 243 data |= (addr << MIB_COUNTER_INDEX_S); 244 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, data); 245 246 ret = regmap_read_poll_timeout(dev->regmap[2], 247 PORT_CTRL_ADDR(port, REG_PORT_MIB_CTRL_STAT__4), 248 val, !(val & MIB_COUNTER_READ), 10, 1000); 249 /* failed to read MIB. get out of loop */ 250 if (ret) { 251 dev_dbg(dev->dev, "Failed to get MIB\n"); 252 return; 253 } 254 255 /* count resets upon read */ 256 ksz_pread32(dev, port, REG_PORT_MIB_DATA, &data); 257 *cnt += data; 258 } 259 260 static void ksz9477_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 261 u64 *dropped, u64 *cnt) 262 { 263 addr = ksz9477_mib_names[addr].index; 264 ksz9477_r_mib_cnt(dev, port, addr, cnt); 265 } 266 267 static void ksz9477_freeze_mib(struct ksz_device *dev, int port, bool freeze) 268 { 269 u32 val = freeze ? MIB_COUNTER_FLUSH_FREEZE : 0; 270 struct ksz_port *p = &dev->ports[port]; 271 272 /* enable/disable the port for flush/freeze function */ 273 mutex_lock(&p->mib.cnt_mutex); 274 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, val); 275 276 /* used by MIB counter reading code to know freeze is enabled */ 277 p->freeze = freeze; 278 mutex_unlock(&p->mib.cnt_mutex); 279 } 280 281 static void ksz9477_port_init_cnt(struct ksz_device *dev, int port) 282 { 283 struct ksz_port_mib *mib = &dev->ports[port].mib; 284 285 /* flush all enabled port MIB counters */ 286 mutex_lock(&mib->cnt_mutex); 287 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 288 MIB_COUNTER_FLUSH_FREEZE); 289 ksz_write8(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FLUSH); 290 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 0); 291 mutex_unlock(&mib->cnt_mutex); 292 293 mib->cnt_ptr = 0; 294 memset(mib->counters, 0, dev->mib_cnt * sizeof(u64)); 295 } 296 297 static enum dsa_tag_protocol ksz9477_get_tag_protocol(struct dsa_switch *ds, 298 int port, 299 enum dsa_tag_protocol mp) 300 { 301 enum dsa_tag_protocol proto = DSA_TAG_PROTO_KSZ9477; 302 struct ksz_device *dev = ds->priv; 303 304 if (dev->features & IS_9893) 305 proto = DSA_TAG_PROTO_KSZ9893; 306 return proto; 307 } 308 309 static int ksz9477_phy_read16(struct dsa_switch *ds, int addr, int reg) 310 { 311 struct ksz_device *dev = ds->priv; 312 u16 val = 0xffff; 313 314 /* No real PHY after this. Simulate the PHY. 315 * A fixed PHY can be setup in the device tree, but this function is 316 * still called for that port during initialization. 317 * For RGMII PHY there is no way to access it so the fixed PHY should 318 * be used. For SGMII PHY the supporting code will be added later. 319 */ 320 if (addr >= dev->phy_port_cnt) { 321 struct ksz_port *p = &dev->ports[addr]; 322 323 switch (reg) { 324 case MII_BMCR: 325 val = 0x1140; 326 break; 327 case MII_BMSR: 328 val = 0x796d; 329 break; 330 case MII_PHYSID1: 331 val = 0x0022; 332 break; 333 case MII_PHYSID2: 334 val = 0x1631; 335 break; 336 case MII_ADVERTISE: 337 val = 0x05e1; 338 break; 339 case MII_LPA: 340 val = 0xc5e1; 341 break; 342 case MII_CTRL1000: 343 val = 0x0700; 344 break; 345 case MII_STAT1000: 346 if (p->phydev.speed == SPEED_1000) 347 val = 0x3800; 348 else 349 val = 0; 350 break; 351 } 352 } else { 353 ksz_pread16(dev, addr, 0x100 + (reg << 1), &val); 354 } 355 356 return val; 357 } 358 359 static int ksz9477_phy_write16(struct dsa_switch *ds, int addr, int reg, 360 u16 val) 361 { 362 struct ksz_device *dev = ds->priv; 363 364 /* No real PHY after this. */ 365 if (addr >= dev->phy_port_cnt) 366 return 0; 367 368 /* No gigabit support. Do not write to this register. */ 369 if (!(dev->features & GBIT_SUPPORT) && reg == MII_CTRL1000) 370 return 0; 371 ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val); 372 373 return 0; 374 } 375 376 static void ksz9477_get_strings(struct dsa_switch *ds, int port, 377 u32 stringset, uint8_t *buf) 378 { 379 int i; 380 381 if (stringset != ETH_SS_STATS) 382 return; 383 384 for (i = 0; i < TOTAL_SWITCH_COUNTER_NUM; i++) { 385 memcpy(buf + i * ETH_GSTRING_LEN, ksz9477_mib_names[i].string, 386 ETH_GSTRING_LEN); 387 } 388 } 389 390 static void ksz9477_cfg_port_member(struct ksz_device *dev, int port, 391 u8 member) 392 { 393 ksz_pwrite32(dev, port, REG_PORT_VLAN_MEMBERSHIP__4, member); 394 dev->ports[port].member = member; 395 } 396 397 static void ksz9477_port_stp_state_set(struct dsa_switch *ds, int port, 398 u8 state) 399 { 400 struct ksz_device *dev = ds->priv; 401 struct ksz_port *p = &dev->ports[port]; 402 u8 data; 403 int member = -1; 404 int forward = dev->member; 405 406 ksz_pread8(dev, port, P_STP_CTRL, &data); 407 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 408 409 switch (state) { 410 case BR_STATE_DISABLED: 411 data |= PORT_LEARN_DISABLE; 412 if (port != dev->cpu_port) 413 member = 0; 414 break; 415 case BR_STATE_LISTENING: 416 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 417 if (port != dev->cpu_port && 418 p->stp_state == BR_STATE_DISABLED) 419 member = dev->host_mask | p->vid_member; 420 break; 421 case BR_STATE_LEARNING: 422 data |= PORT_RX_ENABLE; 423 break; 424 case BR_STATE_FORWARDING: 425 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 426 427 /* This function is also used internally. */ 428 if (port == dev->cpu_port) 429 break; 430 431 member = dev->host_mask | p->vid_member; 432 mutex_lock(&dev->dev_mutex); 433 434 /* Port is a member of a bridge. */ 435 if (dev->br_member & (1 << port)) { 436 dev->member |= (1 << port); 437 member = dev->member; 438 } 439 mutex_unlock(&dev->dev_mutex); 440 break; 441 case BR_STATE_BLOCKING: 442 data |= PORT_LEARN_DISABLE; 443 if (port != dev->cpu_port && 444 p->stp_state == BR_STATE_DISABLED) 445 member = dev->host_mask | p->vid_member; 446 break; 447 default: 448 dev_err(ds->dev, "invalid STP state: %d\n", state); 449 return; 450 } 451 452 ksz_pwrite8(dev, port, P_STP_CTRL, data); 453 p->stp_state = state; 454 mutex_lock(&dev->dev_mutex); 455 /* Port membership may share register with STP state. */ 456 if (member >= 0 && member != p->member) 457 ksz9477_cfg_port_member(dev, port, (u8)member); 458 459 /* Check if forwarding needs to be updated. */ 460 if (state != BR_STATE_FORWARDING) { 461 if (dev->br_member & (1 << port)) 462 dev->member &= ~(1 << port); 463 } 464 465 /* When topology has changed the function ksz_update_port_member 466 * should be called to modify port forwarding behavior. 467 */ 468 if (forward != dev->member) 469 ksz_update_port_member(dev, port); 470 mutex_unlock(&dev->dev_mutex); 471 } 472 473 static void ksz9477_flush_dyn_mac_table(struct ksz_device *dev, int port) 474 { 475 u8 data; 476 477 regmap_update_bits(dev->regmap[0], REG_SW_LUE_CTRL_2, 478 SW_FLUSH_OPTION_M << SW_FLUSH_OPTION_S, 479 SW_FLUSH_OPTION_DYN_MAC << SW_FLUSH_OPTION_S); 480 481 if (port < dev->port_cnt) { 482 /* flush individual port */ 483 ksz_pread8(dev, port, P_STP_CTRL, &data); 484 if (!(data & PORT_LEARN_DISABLE)) 485 ksz_pwrite8(dev, port, P_STP_CTRL, 486 data | PORT_LEARN_DISABLE); 487 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true); 488 ksz_pwrite8(dev, port, P_STP_CTRL, data); 489 } else { 490 /* flush all */ 491 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_STP_TABLE, true); 492 } 493 } 494 495 static int ksz9477_port_vlan_filtering(struct dsa_switch *ds, int port, 496 bool flag, 497 struct netlink_ext_ack *extack) 498 { 499 struct ksz_device *dev = ds->priv; 500 501 if (flag) { 502 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 503 PORT_VLAN_LOOKUP_VID_0, true); 504 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, true); 505 } else { 506 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, false); 507 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 508 PORT_VLAN_LOOKUP_VID_0, false); 509 } 510 511 return 0; 512 } 513 514 static int ksz9477_port_vlan_add(struct dsa_switch *ds, int port, 515 const struct switchdev_obj_port_vlan *vlan, 516 struct netlink_ext_ack *extack) 517 { 518 struct ksz_device *dev = ds->priv; 519 u32 vlan_table[3]; 520 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 521 int err; 522 523 err = ksz9477_get_vlan_table(dev, vlan->vid, vlan_table); 524 if (err) { 525 NL_SET_ERR_MSG_MOD(extack, "Failed to get vlan table"); 526 return err; 527 } 528 529 vlan_table[0] = VLAN_VALID | (vlan->vid & VLAN_FID_M); 530 if (untagged) 531 vlan_table[1] |= BIT(port); 532 else 533 vlan_table[1] &= ~BIT(port); 534 vlan_table[1] &= ~(BIT(dev->cpu_port)); 535 536 vlan_table[2] |= BIT(port) | BIT(dev->cpu_port); 537 538 err = ksz9477_set_vlan_table(dev, vlan->vid, vlan_table); 539 if (err) { 540 NL_SET_ERR_MSG_MOD(extack, "Failed to set vlan table"); 541 return err; 542 } 543 544 /* change PVID */ 545 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) 546 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, vlan->vid); 547 548 return 0; 549 } 550 551 static int ksz9477_port_vlan_del(struct dsa_switch *ds, int port, 552 const struct switchdev_obj_port_vlan *vlan) 553 { 554 struct ksz_device *dev = ds->priv; 555 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 556 u32 vlan_table[3]; 557 u16 pvid; 558 559 ksz_pread16(dev, port, REG_PORT_DEFAULT_VID, &pvid); 560 pvid = pvid & 0xFFF; 561 562 if (ksz9477_get_vlan_table(dev, vlan->vid, vlan_table)) { 563 dev_dbg(dev->dev, "Failed to get vlan table\n"); 564 return -ETIMEDOUT; 565 } 566 567 vlan_table[2] &= ~BIT(port); 568 569 if (pvid == vlan->vid) 570 pvid = 1; 571 572 if (untagged) 573 vlan_table[1] &= ~BIT(port); 574 575 if (ksz9477_set_vlan_table(dev, vlan->vid, vlan_table)) { 576 dev_dbg(dev->dev, "Failed to set vlan table\n"); 577 return -ETIMEDOUT; 578 } 579 580 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, pvid); 581 582 return 0; 583 } 584 585 static int ksz9477_port_fdb_add(struct dsa_switch *ds, int port, 586 const unsigned char *addr, u16 vid) 587 { 588 struct ksz_device *dev = ds->priv; 589 u32 alu_table[4]; 590 u32 data; 591 int ret = 0; 592 593 mutex_lock(&dev->alu_mutex); 594 595 /* find any entry with mac & vid */ 596 data = vid << ALU_FID_INDEX_S; 597 data |= ((addr[0] << 8) | addr[1]); 598 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 599 600 data = ((addr[2] << 24) | (addr[3] << 16)); 601 data |= ((addr[4] << 8) | addr[5]); 602 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 603 604 /* start read operation */ 605 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 606 607 /* wait to be finished */ 608 ret = ksz9477_wait_alu_ready(dev); 609 if (ret) { 610 dev_dbg(dev->dev, "Failed to read ALU\n"); 611 goto exit; 612 } 613 614 /* read ALU entry */ 615 ksz9477_read_table(dev, alu_table); 616 617 /* update ALU entry */ 618 alu_table[0] = ALU_V_STATIC_VALID; 619 alu_table[1] |= BIT(port); 620 if (vid) 621 alu_table[1] |= ALU_V_USE_FID; 622 alu_table[2] = (vid << ALU_V_FID_S); 623 alu_table[2] |= ((addr[0] << 8) | addr[1]); 624 alu_table[3] = ((addr[2] << 24) | (addr[3] << 16)); 625 alu_table[3] |= ((addr[4] << 8) | addr[5]); 626 627 ksz9477_write_table(dev, alu_table); 628 629 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 630 631 /* wait to be finished */ 632 ret = ksz9477_wait_alu_ready(dev); 633 if (ret) 634 dev_dbg(dev->dev, "Failed to write ALU\n"); 635 636 exit: 637 mutex_unlock(&dev->alu_mutex); 638 639 return ret; 640 } 641 642 static int ksz9477_port_fdb_del(struct dsa_switch *ds, int port, 643 const unsigned char *addr, u16 vid) 644 { 645 struct ksz_device *dev = ds->priv; 646 u32 alu_table[4]; 647 u32 data; 648 int ret = 0; 649 650 mutex_lock(&dev->alu_mutex); 651 652 /* read any entry with mac & vid */ 653 data = vid << ALU_FID_INDEX_S; 654 data |= ((addr[0] << 8) | addr[1]); 655 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 656 657 data = ((addr[2] << 24) | (addr[3] << 16)); 658 data |= ((addr[4] << 8) | addr[5]); 659 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 660 661 /* start read operation */ 662 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 663 664 /* wait to be finished */ 665 ret = ksz9477_wait_alu_ready(dev); 666 if (ret) { 667 dev_dbg(dev->dev, "Failed to read ALU\n"); 668 goto exit; 669 } 670 671 ksz_read32(dev, REG_SW_ALU_VAL_A, &alu_table[0]); 672 if (alu_table[0] & ALU_V_STATIC_VALID) { 673 ksz_read32(dev, REG_SW_ALU_VAL_B, &alu_table[1]); 674 ksz_read32(dev, REG_SW_ALU_VAL_C, &alu_table[2]); 675 ksz_read32(dev, REG_SW_ALU_VAL_D, &alu_table[3]); 676 677 /* clear forwarding port */ 678 alu_table[2] &= ~BIT(port); 679 680 /* if there is no port to forward, clear table */ 681 if ((alu_table[2] & ALU_V_PORT_MAP) == 0) { 682 alu_table[0] = 0; 683 alu_table[1] = 0; 684 alu_table[2] = 0; 685 alu_table[3] = 0; 686 } 687 } else { 688 alu_table[0] = 0; 689 alu_table[1] = 0; 690 alu_table[2] = 0; 691 alu_table[3] = 0; 692 } 693 694 ksz9477_write_table(dev, alu_table); 695 696 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 697 698 /* wait to be finished */ 699 ret = ksz9477_wait_alu_ready(dev); 700 if (ret) 701 dev_dbg(dev->dev, "Failed to write ALU\n"); 702 703 exit: 704 mutex_unlock(&dev->alu_mutex); 705 706 return ret; 707 } 708 709 static void ksz9477_convert_alu(struct alu_struct *alu, u32 *alu_table) 710 { 711 alu->is_static = !!(alu_table[0] & ALU_V_STATIC_VALID); 712 alu->is_src_filter = !!(alu_table[0] & ALU_V_SRC_FILTER); 713 alu->is_dst_filter = !!(alu_table[0] & ALU_V_DST_FILTER); 714 alu->prio_age = (alu_table[0] >> ALU_V_PRIO_AGE_CNT_S) & 715 ALU_V_PRIO_AGE_CNT_M; 716 alu->mstp = alu_table[0] & ALU_V_MSTP_M; 717 718 alu->is_override = !!(alu_table[1] & ALU_V_OVERRIDE); 719 alu->is_use_fid = !!(alu_table[1] & ALU_V_USE_FID); 720 alu->port_forward = alu_table[1] & ALU_V_PORT_MAP; 721 722 alu->fid = (alu_table[2] >> ALU_V_FID_S) & ALU_V_FID_M; 723 724 alu->mac[0] = (alu_table[2] >> 8) & 0xFF; 725 alu->mac[1] = alu_table[2] & 0xFF; 726 alu->mac[2] = (alu_table[3] >> 24) & 0xFF; 727 alu->mac[3] = (alu_table[3] >> 16) & 0xFF; 728 alu->mac[4] = (alu_table[3] >> 8) & 0xFF; 729 alu->mac[5] = alu_table[3] & 0xFF; 730 } 731 732 static int ksz9477_port_fdb_dump(struct dsa_switch *ds, int port, 733 dsa_fdb_dump_cb_t *cb, void *data) 734 { 735 struct ksz_device *dev = ds->priv; 736 int ret = 0; 737 u32 ksz_data; 738 u32 alu_table[4]; 739 struct alu_struct alu; 740 int timeout; 741 742 mutex_lock(&dev->alu_mutex); 743 744 /* start ALU search */ 745 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_START | ALU_SEARCH); 746 747 do { 748 timeout = 1000; 749 do { 750 ksz_read32(dev, REG_SW_ALU_CTRL__4, &ksz_data); 751 if ((ksz_data & ALU_VALID) || !(ksz_data & ALU_START)) 752 break; 753 usleep_range(1, 10); 754 } while (timeout-- > 0); 755 756 if (!timeout) { 757 dev_dbg(dev->dev, "Failed to search ALU\n"); 758 ret = -ETIMEDOUT; 759 goto exit; 760 } 761 762 /* read ALU table */ 763 ksz9477_read_table(dev, alu_table); 764 765 ksz9477_convert_alu(&alu, alu_table); 766 767 if (alu.port_forward & BIT(port)) { 768 ret = cb(alu.mac, alu.fid, alu.is_static, data); 769 if (ret) 770 goto exit; 771 } 772 } while (ksz_data & ALU_START); 773 774 exit: 775 776 /* stop ALU search */ 777 ksz_write32(dev, REG_SW_ALU_CTRL__4, 0); 778 779 mutex_unlock(&dev->alu_mutex); 780 781 return ret; 782 } 783 784 static int ksz9477_port_mdb_add(struct dsa_switch *ds, int port, 785 const struct switchdev_obj_port_mdb *mdb) 786 { 787 struct ksz_device *dev = ds->priv; 788 u32 static_table[4]; 789 u32 data; 790 int index; 791 u32 mac_hi, mac_lo; 792 int err = 0; 793 794 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 795 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 796 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 797 798 mutex_lock(&dev->alu_mutex); 799 800 for (index = 0; index < dev->num_statics; index++) { 801 /* find empty slot first */ 802 data = (index << ALU_STAT_INDEX_S) | 803 ALU_STAT_READ | ALU_STAT_START; 804 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 805 806 /* wait to be finished */ 807 err = ksz9477_wait_alu_sta_ready(dev); 808 if (err) { 809 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 810 goto exit; 811 } 812 813 /* read ALU static table */ 814 ksz9477_read_table(dev, static_table); 815 816 if (static_table[0] & ALU_V_STATIC_VALID) { 817 /* check this has same vid & mac address */ 818 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 819 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 820 static_table[3] == mac_lo) { 821 /* found matching one */ 822 break; 823 } 824 } else { 825 /* found empty one */ 826 break; 827 } 828 } 829 830 /* no available entry */ 831 if (index == dev->num_statics) { 832 err = -ENOSPC; 833 goto exit; 834 } 835 836 /* add entry */ 837 static_table[0] = ALU_V_STATIC_VALID; 838 static_table[1] |= BIT(port); 839 if (mdb->vid) 840 static_table[1] |= ALU_V_USE_FID; 841 static_table[2] = (mdb->vid << ALU_V_FID_S); 842 static_table[2] |= mac_hi; 843 static_table[3] = mac_lo; 844 845 ksz9477_write_table(dev, static_table); 846 847 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START; 848 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 849 850 /* wait to be finished */ 851 if (ksz9477_wait_alu_sta_ready(dev)) 852 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 853 854 exit: 855 mutex_unlock(&dev->alu_mutex); 856 return err; 857 } 858 859 static int ksz9477_port_mdb_del(struct dsa_switch *ds, int port, 860 const struct switchdev_obj_port_mdb *mdb) 861 { 862 struct ksz_device *dev = ds->priv; 863 u32 static_table[4]; 864 u32 data; 865 int index; 866 int ret = 0; 867 u32 mac_hi, mac_lo; 868 869 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 870 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 871 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 872 873 mutex_lock(&dev->alu_mutex); 874 875 for (index = 0; index < dev->num_statics; index++) { 876 /* find empty slot first */ 877 data = (index << ALU_STAT_INDEX_S) | 878 ALU_STAT_READ | ALU_STAT_START; 879 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 880 881 /* wait to be finished */ 882 ret = ksz9477_wait_alu_sta_ready(dev); 883 if (ret) { 884 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 885 goto exit; 886 } 887 888 /* read ALU static table */ 889 ksz9477_read_table(dev, static_table); 890 891 if (static_table[0] & ALU_V_STATIC_VALID) { 892 /* check this has same vid & mac address */ 893 894 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 895 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 896 static_table[3] == mac_lo) { 897 /* found matching one */ 898 break; 899 } 900 } 901 } 902 903 /* no available entry */ 904 if (index == dev->num_statics) 905 goto exit; 906 907 /* clear port */ 908 static_table[1] &= ~BIT(port); 909 910 if ((static_table[1] & ALU_V_PORT_MAP) == 0) { 911 /* delete entry */ 912 static_table[0] = 0; 913 static_table[1] = 0; 914 static_table[2] = 0; 915 static_table[3] = 0; 916 } 917 918 ksz9477_write_table(dev, static_table); 919 920 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START; 921 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 922 923 /* wait to be finished */ 924 ret = ksz9477_wait_alu_sta_ready(dev); 925 if (ret) 926 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 927 928 exit: 929 mutex_unlock(&dev->alu_mutex); 930 931 return ret; 932 } 933 934 static int ksz9477_port_mirror_add(struct dsa_switch *ds, int port, 935 struct dsa_mall_mirror_tc_entry *mirror, 936 bool ingress) 937 { 938 struct ksz_device *dev = ds->priv; 939 940 if (ingress) 941 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true); 942 else 943 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true); 944 945 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false); 946 947 /* configure mirror port */ 948 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 949 PORT_MIRROR_SNIFFER, true); 950 951 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false); 952 953 return 0; 954 } 955 956 static void ksz9477_port_mirror_del(struct dsa_switch *ds, int port, 957 struct dsa_mall_mirror_tc_entry *mirror) 958 { 959 struct ksz_device *dev = ds->priv; 960 u8 data; 961 962 if (mirror->ingress) 963 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false); 964 else 965 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false); 966 967 ksz_pread8(dev, port, P_MIRROR_CTRL, &data); 968 969 if (!(data & (PORT_MIRROR_RX | PORT_MIRROR_TX))) 970 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 971 PORT_MIRROR_SNIFFER, false); 972 } 973 974 static bool ksz9477_get_gbit(struct ksz_device *dev, u8 data) 975 { 976 bool gbit; 977 978 if (dev->features & NEW_XMII) 979 gbit = !(data & PORT_MII_NOT_1GBIT); 980 else 981 gbit = !!(data & PORT_MII_1000MBIT_S1); 982 return gbit; 983 } 984 985 static void ksz9477_set_gbit(struct ksz_device *dev, bool gbit, u8 *data) 986 { 987 if (dev->features & NEW_XMII) { 988 if (gbit) 989 *data &= ~PORT_MII_NOT_1GBIT; 990 else 991 *data |= PORT_MII_NOT_1GBIT; 992 } else { 993 if (gbit) 994 *data |= PORT_MII_1000MBIT_S1; 995 else 996 *data &= ~PORT_MII_1000MBIT_S1; 997 } 998 } 999 1000 static int ksz9477_get_xmii(struct ksz_device *dev, u8 data) 1001 { 1002 int mode; 1003 1004 if (dev->features & NEW_XMII) { 1005 switch (data & PORT_MII_SEL_M) { 1006 case PORT_MII_SEL: 1007 mode = 0; 1008 break; 1009 case PORT_RMII_SEL: 1010 mode = 1; 1011 break; 1012 case PORT_GMII_SEL: 1013 mode = 2; 1014 break; 1015 default: 1016 mode = 3; 1017 } 1018 } else { 1019 switch (data & PORT_MII_SEL_M) { 1020 case PORT_MII_SEL_S1: 1021 mode = 0; 1022 break; 1023 case PORT_RMII_SEL_S1: 1024 mode = 1; 1025 break; 1026 case PORT_GMII_SEL_S1: 1027 mode = 2; 1028 break; 1029 default: 1030 mode = 3; 1031 } 1032 } 1033 return mode; 1034 } 1035 1036 static void ksz9477_set_xmii(struct ksz_device *dev, int mode, u8 *data) 1037 { 1038 u8 xmii; 1039 1040 if (dev->features & NEW_XMII) { 1041 switch (mode) { 1042 case 0: 1043 xmii = PORT_MII_SEL; 1044 break; 1045 case 1: 1046 xmii = PORT_RMII_SEL; 1047 break; 1048 case 2: 1049 xmii = PORT_GMII_SEL; 1050 break; 1051 default: 1052 xmii = PORT_RGMII_SEL; 1053 break; 1054 } 1055 } else { 1056 switch (mode) { 1057 case 0: 1058 xmii = PORT_MII_SEL_S1; 1059 break; 1060 case 1: 1061 xmii = PORT_RMII_SEL_S1; 1062 break; 1063 case 2: 1064 xmii = PORT_GMII_SEL_S1; 1065 break; 1066 default: 1067 xmii = PORT_RGMII_SEL_S1; 1068 break; 1069 } 1070 } 1071 *data &= ~PORT_MII_SEL_M; 1072 *data |= xmii; 1073 } 1074 1075 static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port) 1076 { 1077 phy_interface_t interface; 1078 bool gbit; 1079 int mode; 1080 u8 data8; 1081 1082 if (port < dev->phy_port_cnt) 1083 return PHY_INTERFACE_MODE_NA; 1084 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8); 1085 gbit = ksz9477_get_gbit(dev, data8); 1086 mode = ksz9477_get_xmii(dev, data8); 1087 switch (mode) { 1088 case 2: 1089 interface = PHY_INTERFACE_MODE_GMII; 1090 if (gbit) 1091 break; 1092 fallthrough; 1093 case 0: 1094 interface = PHY_INTERFACE_MODE_MII; 1095 break; 1096 case 1: 1097 interface = PHY_INTERFACE_MODE_RMII; 1098 break; 1099 default: 1100 interface = PHY_INTERFACE_MODE_RGMII; 1101 if (data8 & PORT_RGMII_ID_EG_ENABLE) 1102 interface = PHY_INTERFACE_MODE_RGMII_TXID; 1103 if (data8 & PORT_RGMII_ID_IG_ENABLE) { 1104 interface = PHY_INTERFACE_MODE_RGMII_RXID; 1105 if (data8 & PORT_RGMII_ID_EG_ENABLE) 1106 interface = PHY_INTERFACE_MODE_RGMII_ID; 1107 } 1108 break; 1109 } 1110 return interface; 1111 } 1112 1113 static void ksz9477_port_mmd_write(struct ksz_device *dev, int port, 1114 u8 dev_addr, u16 reg_addr, u16 val) 1115 { 1116 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, 1117 MMD_SETUP(PORT_MMD_OP_INDEX, dev_addr)); 1118 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, reg_addr); 1119 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, 1120 MMD_SETUP(PORT_MMD_OP_DATA_NO_INCR, dev_addr)); 1121 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, val); 1122 } 1123 1124 static void ksz9477_phy_errata_setup(struct ksz_device *dev, int port) 1125 { 1126 /* Apply PHY settings to address errata listed in 1127 * KSZ9477, KSZ9897, KSZ9896, KSZ9567, KSZ8565 1128 * Silicon Errata and Data Sheet Clarification documents: 1129 * 1130 * Register settings are needed to improve PHY receive performance 1131 */ 1132 ksz9477_port_mmd_write(dev, port, 0x01, 0x6f, 0xdd0b); 1133 ksz9477_port_mmd_write(dev, port, 0x01, 0x8f, 0x6032); 1134 ksz9477_port_mmd_write(dev, port, 0x01, 0x9d, 0x248c); 1135 ksz9477_port_mmd_write(dev, port, 0x01, 0x75, 0x0060); 1136 ksz9477_port_mmd_write(dev, port, 0x01, 0xd3, 0x7777); 1137 ksz9477_port_mmd_write(dev, port, 0x1c, 0x06, 0x3008); 1138 ksz9477_port_mmd_write(dev, port, 0x1c, 0x08, 0x2001); 1139 1140 /* Transmit waveform amplitude can be improved 1141 * (1000BASE-T, 100BASE-TX, 10BASE-Te) 1142 */ 1143 ksz9477_port_mmd_write(dev, port, 0x1c, 0x04, 0x00d0); 1144 1145 /* Energy Efficient Ethernet (EEE) feature select must 1146 * be manually disabled (except on KSZ8565 which is 100Mbit) 1147 */ 1148 if (dev->features & GBIT_SUPPORT) 1149 ksz9477_port_mmd_write(dev, port, 0x07, 0x3c, 0x0000); 1150 1151 /* Register settings are required to meet data sheet 1152 * supply current specifications 1153 */ 1154 ksz9477_port_mmd_write(dev, port, 0x1c, 0x13, 0x6eff); 1155 ksz9477_port_mmd_write(dev, port, 0x1c, 0x14, 0xe6ff); 1156 ksz9477_port_mmd_write(dev, port, 0x1c, 0x15, 0x6eff); 1157 ksz9477_port_mmd_write(dev, port, 0x1c, 0x16, 0xe6ff); 1158 ksz9477_port_mmd_write(dev, port, 0x1c, 0x17, 0x00ff); 1159 ksz9477_port_mmd_write(dev, port, 0x1c, 0x18, 0x43ff); 1160 ksz9477_port_mmd_write(dev, port, 0x1c, 0x19, 0xc3ff); 1161 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1a, 0x6fff); 1162 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1b, 0x07ff); 1163 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1c, 0x0fff); 1164 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1d, 0xe7ff); 1165 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1e, 0xefff); 1166 ksz9477_port_mmd_write(dev, port, 0x1c, 0x20, 0xeeee); 1167 } 1168 1169 static void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port) 1170 { 1171 u8 data8; 1172 u8 member; 1173 u16 data16; 1174 struct ksz_port *p = &dev->ports[port]; 1175 1176 /* enable tag tail for host port */ 1177 if (cpu_port) 1178 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_TAIL_TAG_ENABLE, 1179 true); 1180 1181 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_MAC_LOOPBACK, false); 1182 1183 /* set back pressure */ 1184 ksz_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, true); 1185 1186 /* enable broadcast storm limit */ 1187 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true); 1188 1189 /* disable DiffServ priority */ 1190 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_PRIO_ENABLE, false); 1191 1192 /* replace priority */ 1193 ksz_port_cfg(dev, port, REG_PORT_MRI_MAC_CTRL, PORT_USER_PRIO_CEILING, 1194 false); 1195 ksz9477_port_cfg32(dev, port, REG_PORT_MTI_QUEUE_CTRL_0__4, 1196 MTI_PVID_REPLACE, false); 1197 1198 /* enable 802.1p priority */ 1199 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true); 1200 1201 if (port < dev->phy_port_cnt) { 1202 /* do not force flow control */ 1203 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, 1204 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, 1205 false); 1206 1207 if (dev->phy_errata_9477) 1208 ksz9477_phy_errata_setup(dev, port); 1209 } else { 1210 /* force flow control */ 1211 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, 1212 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, 1213 true); 1214 1215 /* configure MAC to 1G & RGMII mode */ 1216 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8); 1217 switch (p->interface) { 1218 case PHY_INTERFACE_MODE_MII: 1219 ksz9477_set_xmii(dev, 0, &data8); 1220 ksz9477_set_gbit(dev, false, &data8); 1221 p->phydev.speed = SPEED_100; 1222 break; 1223 case PHY_INTERFACE_MODE_RMII: 1224 ksz9477_set_xmii(dev, 1, &data8); 1225 ksz9477_set_gbit(dev, false, &data8); 1226 p->phydev.speed = SPEED_100; 1227 break; 1228 case PHY_INTERFACE_MODE_GMII: 1229 ksz9477_set_xmii(dev, 2, &data8); 1230 ksz9477_set_gbit(dev, true, &data8); 1231 p->phydev.speed = SPEED_1000; 1232 break; 1233 default: 1234 ksz9477_set_xmii(dev, 3, &data8); 1235 ksz9477_set_gbit(dev, true, &data8); 1236 data8 &= ~PORT_RGMII_ID_IG_ENABLE; 1237 data8 &= ~PORT_RGMII_ID_EG_ENABLE; 1238 if (p->interface == PHY_INTERFACE_MODE_RGMII_ID || 1239 p->interface == PHY_INTERFACE_MODE_RGMII_RXID) 1240 data8 |= PORT_RGMII_ID_IG_ENABLE; 1241 if (p->interface == PHY_INTERFACE_MODE_RGMII_ID || 1242 p->interface == PHY_INTERFACE_MODE_RGMII_TXID) 1243 data8 |= PORT_RGMII_ID_EG_ENABLE; 1244 /* On KSZ9893, disable RGMII in-band status support */ 1245 if (dev->features & IS_9893) 1246 data8 &= ~PORT_MII_MAC_MODE; 1247 p->phydev.speed = SPEED_1000; 1248 break; 1249 } 1250 ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, data8); 1251 p->phydev.duplex = 1; 1252 } 1253 mutex_lock(&dev->dev_mutex); 1254 if (cpu_port) 1255 member = dev->port_mask; 1256 else 1257 member = dev->host_mask | p->vid_member; 1258 mutex_unlock(&dev->dev_mutex); 1259 ksz9477_cfg_port_member(dev, port, member); 1260 1261 /* clear pending interrupts */ 1262 if (port < dev->phy_port_cnt) 1263 ksz_pread16(dev, port, REG_PORT_PHY_INT_ENABLE, &data16); 1264 } 1265 1266 static void ksz9477_config_cpu_port(struct dsa_switch *ds) 1267 { 1268 struct ksz_device *dev = ds->priv; 1269 struct ksz_port *p; 1270 int i; 1271 1272 for (i = 0; i < dev->port_cnt; i++) { 1273 if (dsa_is_cpu_port(ds, i) && (dev->cpu_ports & (1 << i))) { 1274 phy_interface_t interface; 1275 const char *prev_msg; 1276 const char *prev_mode; 1277 1278 dev->cpu_port = i; 1279 dev->host_mask = (1 << dev->cpu_port); 1280 dev->port_mask |= dev->host_mask; 1281 p = &dev->ports[i]; 1282 1283 /* Read from XMII register to determine host port 1284 * interface. If set specifically in device tree 1285 * note the difference to help debugging. 1286 */ 1287 interface = ksz9477_get_interface(dev, i); 1288 if (!p->interface) { 1289 if (dev->compat_interface) { 1290 dev_warn(dev->dev, 1291 "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. " 1292 "Please update your device tree.\n", 1293 i); 1294 p->interface = dev->compat_interface; 1295 } else { 1296 p->interface = interface; 1297 } 1298 } 1299 if (interface && interface != p->interface) { 1300 prev_msg = " instead of "; 1301 prev_mode = phy_modes(interface); 1302 } else { 1303 prev_msg = ""; 1304 prev_mode = ""; 1305 } 1306 dev_info(dev->dev, 1307 "Port%d: using phy mode %s%s%s\n", 1308 i, 1309 phy_modes(p->interface), 1310 prev_msg, 1311 prev_mode); 1312 1313 /* enable cpu port */ 1314 ksz9477_port_setup(dev, i, true); 1315 p->vid_member = dev->port_mask; 1316 p->on = 1; 1317 } 1318 } 1319 1320 dev->member = dev->host_mask; 1321 1322 for (i = 0; i < dev->port_cnt; i++) { 1323 if (i == dev->cpu_port) 1324 continue; 1325 p = &dev->ports[i]; 1326 1327 /* Initialize to non-zero so that ksz_cfg_port_member() will 1328 * be called. 1329 */ 1330 p->vid_member = (1 << i); 1331 p->member = dev->port_mask; 1332 ksz9477_port_stp_state_set(ds, i, BR_STATE_DISABLED); 1333 p->on = 1; 1334 if (i < dev->phy_port_cnt) 1335 p->phy = 1; 1336 if (dev->chip_id == 0x00947700 && i == 6) { 1337 p->sgmii = 1; 1338 1339 /* SGMII PHY detection code is not implemented yet. */ 1340 p->phy = 0; 1341 } 1342 } 1343 } 1344 1345 static int ksz9477_setup(struct dsa_switch *ds) 1346 { 1347 struct ksz_device *dev = ds->priv; 1348 int ret = 0; 1349 1350 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 1351 dev->num_vlans, GFP_KERNEL); 1352 if (!dev->vlan_cache) 1353 return -ENOMEM; 1354 1355 ret = ksz9477_reset_switch(dev); 1356 if (ret) { 1357 dev_err(ds->dev, "failed to reset switch\n"); 1358 return ret; 1359 } 1360 1361 /* Required for port partitioning. */ 1362 ksz9477_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY, 1363 true); 1364 1365 /* Do not work correctly with tail tagging. */ 1366 ksz_cfg(dev, REG_SW_MAC_CTRL_0, SW_CHECK_LENGTH, false); 1367 1368 /* accept packet up to 2000bytes */ 1369 ksz_cfg(dev, REG_SW_MAC_CTRL_1, SW_LEGAL_PACKET_DISABLE, true); 1370 1371 ksz9477_config_cpu_port(ds); 1372 1373 ksz_cfg(dev, REG_SW_MAC_CTRL_1, MULTICAST_STORM_DISABLE, true); 1374 1375 /* queue based egress rate limit */ 1376 ksz_cfg(dev, REG_SW_MAC_CTRL_5, SW_OUT_RATE_LIMIT_QUEUE_BASED, true); 1377 1378 /* enable global MIB counter freeze function */ 1379 ksz_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true); 1380 1381 /* start switch */ 1382 ksz_cfg(dev, REG_SW_OPERATION, SW_START, true); 1383 1384 ksz_init_mib_timer(dev); 1385 1386 ds->configure_vlan_while_not_filtering = false; 1387 1388 return 0; 1389 } 1390 1391 static const struct dsa_switch_ops ksz9477_switch_ops = { 1392 .get_tag_protocol = ksz9477_get_tag_protocol, 1393 .setup = ksz9477_setup, 1394 .phy_read = ksz9477_phy_read16, 1395 .phy_write = ksz9477_phy_write16, 1396 .phylink_mac_link_down = ksz_mac_link_down, 1397 .port_enable = ksz_enable_port, 1398 .get_strings = ksz9477_get_strings, 1399 .get_ethtool_stats = ksz_get_ethtool_stats, 1400 .get_sset_count = ksz_sset_count, 1401 .port_bridge_join = ksz_port_bridge_join, 1402 .port_bridge_leave = ksz_port_bridge_leave, 1403 .port_stp_state_set = ksz9477_port_stp_state_set, 1404 .port_fast_age = ksz_port_fast_age, 1405 .port_vlan_filtering = ksz9477_port_vlan_filtering, 1406 .port_vlan_add = ksz9477_port_vlan_add, 1407 .port_vlan_del = ksz9477_port_vlan_del, 1408 .port_fdb_dump = ksz9477_port_fdb_dump, 1409 .port_fdb_add = ksz9477_port_fdb_add, 1410 .port_fdb_del = ksz9477_port_fdb_del, 1411 .port_mdb_add = ksz9477_port_mdb_add, 1412 .port_mdb_del = ksz9477_port_mdb_del, 1413 .port_mirror_add = ksz9477_port_mirror_add, 1414 .port_mirror_del = ksz9477_port_mirror_del, 1415 }; 1416 1417 static u32 ksz9477_get_port_addr(int port, int offset) 1418 { 1419 return PORT_CTRL_ADDR(port, offset); 1420 } 1421 1422 static int ksz9477_switch_detect(struct ksz_device *dev) 1423 { 1424 u8 data8; 1425 u8 id_hi; 1426 u8 id_lo; 1427 u32 id32; 1428 int ret; 1429 1430 /* turn off SPI DO Edge select */ 1431 ret = ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8); 1432 if (ret) 1433 return ret; 1434 1435 data8 &= ~SPI_AUTO_EDGE_DETECTION; 1436 ret = ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8); 1437 if (ret) 1438 return ret; 1439 1440 /* read chip id */ 1441 ret = ksz_read32(dev, REG_CHIP_ID0__1, &id32); 1442 if (ret) 1443 return ret; 1444 ret = ksz_read8(dev, REG_GLOBAL_OPTIONS, &data8); 1445 if (ret) 1446 return ret; 1447 1448 /* Number of ports can be reduced depending on chip. */ 1449 dev->phy_port_cnt = 5; 1450 1451 /* Default capability is gigabit capable. */ 1452 dev->features = GBIT_SUPPORT; 1453 1454 dev_dbg(dev->dev, "Switch detect: ID=%08x%02x\n", id32, data8); 1455 id_hi = (u8)(id32 >> 16); 1456 id_lo = (u8)(id32 >> 8); 1457 if ((id_lo & 0xf) == 3) { 1458 /* Chip is from KSZ9893 design. */ 1459 dev_info(dev->dev, "Found KSZ9893\n"); 1460 dev->features |= IS_9893; 1461 1462 /* Chip does not support gigabit. */ 1463 if (data8 & SW_QW_ABLE) 1464 dev->features &= ~GBIT_SUPPORT; 1465 dev->phy_port_cnt = 2; 1466 } else { 1467 dev_info(dev->dev, "Found KSZ9477 or compatible\n"); 1468 /* Chip uses new XMII register definitions. */ 1469 dev->features |= NEW_XMII; 1470 1471 /* Chip does not support gigabit. */ 1472 if (!(data8 & SW_GIGABIT_ABLE)) 1473 dev->features &= ~GBIT_SUPPORT; 1474 } 1475 1476 /* Change chip id to known ones so it can be matched against them. */ 1477 id32 = (id_hi << 16) | (id_lo << 8); 1478 1479 dev->chip_id = id32; 1480 1481 return 0; 1482 } 1483 1484 struct ksz_chip_data { 1485 u32 chip_id; 1486 const char *dev_name; 1487 int num_vlans; 1488 int num_alus; 1489 int num_statics; 1490 int cpu_ports; 1491 int port_cnt; 1492 bool phy_errata_9477; 1493 }; 1494 1495 static const struct ksz_chip_data ksz9477_switch_chips[] = { 1496 { 1497 .chip_id = 0x00947700, 1498 .dev_name = "KSZ9477", 1499 .num_vlans = 4096, 1500 .num_alus = 4096, 1501 .num_statics = 16, 1502 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1503 .port_cnt = 7, /* total physical port count */ 1504 .phy_errata_9477 = true, 1505 }, 1506 { 1507 .chip_id = 0x00989700, 1508 .dev_name = "KSZ9897", 1509 .num_vlans = 4096, 1510 .num_alus = 4096, 1511 .num_statics = 16, 1512 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1513 .port_cnt = 7, /* total physical port count */ 1514 .phy_errata_9477 = true, 1515 }, 1516 { 1517 .chip_id = 0x00989300, 1518 .dev_name = "KSZ9893", 1519 .num_vlans = 4096, 1520 .num_alus = 4096, 1521 .num_statics = 16, 1522 .cpu_ports = 0x07, /* can be configured as cpu port */ 1523 .port_cnt = 3, /* total port count */ 1524 }, 1525 { 1526 .chip_id = 0x00956700, 1527 .dev_name = "KSZ9567", 1528 .num_vlans = 4096, 1529 .num_alus = 4096, 1530 .num_statics = 16, 1531 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1532 .port_cnt = 7, /* total physical port count */ 1533 .phy_errata_9477 = true, 1534 }, 1535 }; 1536 1537 static int ksz9477_switch_init(struct ksz_device *dev) 1538 { 1539 int i; 1540 1541 dev->ds->ops = &ksz9477_switch_ops; 1542 1543 for (i = 0; i < ARRAY_SIZE(ksz9477_switch_chips); i++) { 1544 const struct ksz_chip_data *chip = &ksz9477_switch_chips[i]; 1545 1546 if (dev->chip_id == chip->chip_id) { 1547 dev->name = chip->dev_name; 1548 dev->num_vlans = chip->num_vlans; 1549 dev->num_alus = chip->num_alus; 1550 dev->num_statics = chip->num_statics; 1551 dev->port_cnt = chip->port_cnt; 1552 dev->cpu_ports = chip->cpu_ports; 1553 dev->phy_errata_9477 = chip->phy_errata_9477; 1554 1555 break; 1556 } 1557 } 1558 1559 /* no switch found */ 1560 if (!dev->port_cnt) 1561 return -ENODEV; 1562 1563 dev->port_mask = (1 << dev->port_cnt) - 1; 1564 1565 dev->reg_mib_cnt = SWITCH_COUNTER_NUM; 1566 dev->mib_cnt = TOTAL_SWITCH_COUNTER_NUM; 1567 1568 dev->ports = devm_kzalloc(dev->dev, 1569 dev->port_cnt * sizeof(struct ksz_port), 1570 GFP_KERNEL); 1571 if (!dev->ports) 1572 return -ENOMEM; 1573 for (i = 0; i < dev->port_cnt; i++) { 1574 mutex_init(&dev->ports[i].mib.cnt_mutex); 1575 dev->ports[i].mib.counters = 1576 devm_kzalloc(dev->dev, 1577 sizeof(u64) * 1578 (TOTAL_SWITCH_COUNTER_NUM + 1), 1579 GFP_KERNEL); 1580 if (!dev->ports[i].mib.counters) 1581 return -ENOMEM; 1582 } 1583 1584 /* set the real number of ports */ 1585 dev->ds->num_ports = dev->port_cnt; 1586 1587 return 0; 1588 } 1589 1590 static void ksz9477_switch_exit(struct ksz_device *dev) 1591 { 1592 ksz9477_reset_switch(dev); 1593 } 1594 1595 static const struct ksz_dev_ops ksz9477_dev_ops = { 1596 .get_port_addr = ksz9477_get_port_addr, 1597 .cfg_port_member = ksz9477_cfg_port_member, 1598 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 1599 .port_setup = ksz9477_port_setup, 1600 .r_mib_cnt = ksz9477_r_mib_cnt, 1601 .r_mib_pkt = ksz9477_r_mib_pkt, 1602 .freeze_mib = ksz9477_freeze_mib, 1603 .port_init_cnt = ksz9477_port_init_cnt, 1604 .shutdown = ksz9477_reset_switch, 1605 .detect = ksz9477_switch_detect, 1606 .init = ksz9477_switch_init, 1607 .exit = ksz9477_switch_exit, 1608 }; 1609 1610 int ksz9477_switch_register(struct ksz_device *dev) 1611 { 1612 int ret, i; 1613 struct phy_device *phydev; 1614 1615 ret = ksz_switch_register(dev, &ksz9477_dev_ops); 1616 if (ret) 1617 return ret; 1618 1619 for (i = 0; i < dev->phy_port_cnt; ++i) { 1620 if (!dsa_is_user_port(dev->ds, i)) 1621 continue; 1622 1623 phydev = dsa_to_port(dev->ds, i)->slave->phydev; 1624 1625 /* The MAC actually cannot run in 1000 half-duplex mode. */ 1626 phy_remove_link_mode(phydev, 1627 ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1628 1629 /* PHY does not support gigabit. */ 1630 if (!(dev->features & GBIT_SUPPORT)) 1631 phy_remove_link_mode(phydev, 1632 ETHTOOL_LINK_MODE_1000baseT_Full_BIT); 1633 } 1634 return ret; 1635 } 1636 EXPORT_SYMBOL(ksz9477_switch_register); 1637 1638 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 1639 MODULE_DESCRIPTION("Microchip KSZ9477 Series Switch DSA Driver"); 1640 MODULE_LICENSE("GPL"); 1641