1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip KSZ8XXX series switch driver 4 * 5 * It supports the following switches: 6 * - KSZ8463 7 * - KSZ8863, KSZ8873 aka KSZ88X3 8 * - KSZ8895, KSZ8864 aka KSZ8895 family 9 * - KSZ8794, KSZ8795, KSZ8765 aka KSZ87XX 10 * Note that it does NOT support: 11 * - KSZ8563, KSZ8567 - see KSZ9477 driver 12 * 13 * Copyright (C) 2017 Microchip Technology Inc. 14 * Tristram Ha <Tristram.Ha@microchip.com> 15 */ 16 17 #include <linux/bitfield.h> 18 #include <linux/delay.h> 19 #include <linux/dsa/ksz_common.h> 20 #include <linux/export.h> 21 #include <linux/gpio.h> 22 #include <linux/if_vlan.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/platform_data/microchip-ksz.h> 26 #include <linux/phy.h> 27 #include <linux/etherdevice.h> 28 #include <linux/if_bridge.h> 29 #include <linux/micrel_phy.h> 30 #include <net/dsa.h> 31 #include <net/switchdev.h> 32 #include <linux/phylink.h> 33 34 #include "ksz_common.h" 35 #include "ksz_dcb.h" 36 #include "ksz8_reg.h" 37 #include "ksz8.h" 38 39 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) 40 { 41 ksz_rmw8(dev, addr, bits, set ? bits : 0); 42 } 43 44 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits, 45 bool set) 46 { 47 ksz_rmw8(dev, dev->dev_ops->get_port_addr(port, offset), bits, 48 set ? bits : 0); 49 } 50 51 /** 52 * ksz8_ind_write8 - EEE/ACL/PME indirect register write 53 * @dev: The device structure. 54 * @table: Function & table select, register 110. 55 * @addr: Indirect access control, register 111. 56 * @data: The data to be written. 57 * 58 * This function performs an indirect register write for EEE, ACL or 59 * PME switch functionalities. Both 8-bit registers 110 and 111 are 60 * written at once with ksz_write16, using the serial multiple write 61 * functionality. 62 * 63 * Return: 0 on success, or an error code on failure. 64 */ 65 static int ksz8_ind_write8(struct ksz_device *dev, u8 table, u16 addr, u8 data) 66 { 67 const u16 *regs; 68 u16 ctrl_addr; 69 int ret = 0; 70 71 regs = dev->info->regs; 72 73 mutex_lock(&dev->alu_mutex); 74 75 ctrl_addr = IND_ACC_TABLE(table) | addr; 76 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 77 if (!ret) 78 ret = ksz_write8(dev, regs[REG_IND_BYTE], data); 79 80 mutex_unlock(&dev->alu_mutex); 81 82 return ret; 83 } 84 85 /** 86 * ksz8_ind_read8 - EEE/ACL/PME indirect register read 87 * @dev: The device structure. 88 * @table: Function & table select, register 110. 89 * @addr: Indirect access control, register 111. 90 * @val: The value read. 91 * 92 * This function performs an indirect register read for EEE, ACL or 93 * PME switch functionalities. Both 8-bit registers 110 and 111 are 94 * written at once with ksz_write16, using the serial multiple write 95 * functionality. 96 * 97 * Return: 0 on success, or an error code on failure. 98 */ 99 static int ksz8_ind_read8(struct ksz_device *dev, u8 table, u16 addr, u8 *val) 100 { 101 const u16 *regs; 102 u16 ctrl_addr; 103 int ret = 0; 104 105 regs = dev->info->regs; 106 107 mutex_lock(&dev->alu_mutex); 108 109 ctrl_addr = IND_ACC_TABLE(table | TABLE_READ) | addr; 110 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 111 if (!ret) 112 ret = ksz_read8(dev, regs[REG_IND_BYTE], val); 113 114 mutex_unlock(&dev->alu_mutex); 115 116 return ret; 117 } 118 119 static int ksz8_pme_write8(struct ksz_device *dev, u32 reg, u8 value) 120 { 121 return ksz8_ind_write8(dev, (u8)(reg >> 8), (u8)(reg), value); 122 } 123 124 static int ksz8_pme_pread8(struct ksz_device *dev, int port, int offset, u8 *data) 125 { 126 u8 table = (u8)(offset >> 8 | (port + 1)); 127 128 return ksz8_ind_read8(dev, table, (u8)(offset), data); 129 } 130 131 static int ksz8_pme_pwrite8(struct ksz_device *dev, int port, int offset, u8 data) 132 { 133 u8 table = (u8)(offset >> 8 | (port + 1)); 134 135 return ksz8_ind_write8(dev, table, (u8)(offset), data); 136 } 137 138 static int ksz8_reset_switch(struct ksz_device *dev) 139 { 140 if (ksz_is_ksz88x3(dev)) { 141 /* reset switch */ 142 ksz_cfg(dev, KSZ8863_REG_SW_RESET, 143 KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, true); 144 ksz_cfg(dev, KSZ8863_REG_SW_RESET, 145 KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, false); 146 } else if (ksz_is_ksz8463(dev)) { 147 ksz_cfg(dev, KSZ8463_REG_SW_RESET, 148 KSZ8463_GLOBAL_SOFTWARE_RESET, true); 149 ksz_cfg(dev, KSZ8463_REG_SW_RESET, 150 KSZ8463_GLOBAL_SOFTWARE_RESET, false); 151 } else { 152 /* reset switch */ 153 ksz_write8(dev, REG_POWER_MANAGEMENT_1, 154 SW_SOFTWARE_POWER_DOWN << SW_POWER_MANAGEMENT_MODE_S); 155 ksz_write8(dev, REG_POWER_MANAGEMENT_1, 0); 156 } 157 158 return 0; 159 } 160 161 static int ksz8863_change_mtu(struct ksz_device *dev, int frame_size) 162 { 163 u8 ctrl2 = 0; 164 165 if (frame_size <= KSZ8_LEGAL_PACKET_SIZE) 166 ctrl2 |= KSZ8863_LEGAL_PACKET_ENABLE; 167 else if (frame_size > KSZ8863_NORMAL_PACKET_SIZE) 168 ctrl2 |= KSZ8863_HUGE_PACKET_ENABLE; 169 170 return ksz_rmw8(dev, REG_SW_CTRL_2, KSZ8863_LEGAL_PACKET_ENABLE | 171 KSZ8863_HUGE_PACKET_ENABLE, ctrl2); 172 } 173 174 static int ksz8795_change_mtu(struct ksz_device *dev, int frame_size) 175 { 176 u8 ctrl1 = 0, ctrl2 = 0; 177 int ret; 178 179 if (frame_size > KSZ8_LEGAL_PACKET_SIZE) 180 ctrl2 |= SW_LEGAL_PACKET_DISABLE; 181 if (frame_size > KSZ8863_NORMAL_PACKET_SIZE) 182 ctrl1 |= SW_HUGE_PACKET; 183 184 ret = ksz_rmw8(dev, REG_SW_CTRL_1, SW_HUGE_PACKET, ctrl1); 185 if (ret) 186 return ret; 187 188 return ksz_rmw8(dev, REG_SW_CTRL_2, SW_LEGAL_PACKET_DISABLE, ctrl2); 189 } 190 191 static int ksz8_change_mtu(struct dsa_switch *ds, int port, int mtu) 192 { 193 struct ksz_device *dev = ds->priv; 194 u16 frame_size; 195 196 if (!dsa_is_cpu_port(dev->ds, port)) 197 return 0; 198 199 frame_size = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 200 201 switch (dev->chip_id) { 202 case KSZ8795_CHIP_ID: 203 case KSZ8794_CHIP_ID: 204 case KSZ8765_CHIP_ID: 205 return ksz8795_change_mtu(dev, frame_size); 206 case KSZ8463_CHIP_ID: 207 case KSZ88X3_CHIP_ID: 208 case KSZ8864_CHIP_ID: 209 case KSZ8895_CHIP_ID: 210 return ksz8863_change_mtu(dev, frame_size); 211 } 212 213 return -EOPNOTSUPP; 214 } 215 216 static int ksz8_port_queue_split(struct ksz_device *dev, int port, int queues) 217 { 218 u8 mask_4q, mask_2q; 219 u8 reg_4q, reg_2q; 220 u8 data_4q = 0; 221 u8 data_2q = 0; 222 int ret; 223 224 if (ksz_is_ksz88x3(dev)) { 225 mask_4q = KSZ8873_PORT_4QUEUE_SPLIT_EN; 226 mask_2q = KSZ8873_PORT_2QUEUE_SPLIT_EN; 227 reg_4q = REG_PORT_CTRL_0; 228 reg_2q = REG_PORT_CTRL_2; 229 230 /* KSZ8795 family switches have Weighted Fair Queueing (WFQ) 231 * enabled by default. Enable it for KSZ8873 family switches 232 * too. Default value for KSZ8873 family is strict priority, 233 * which should be enabled by using TC_SETUP_QDISC_ETS, not 234 * by default. 235 */ 236 ret = ksz_rmw8(dev, REG_SW_CTRL_3, WEIGHTED_FAIR_QUEUE_ENABLE, 237 WEIGHTED_FAIR_QUEUE_ENABLE); 238 if (ret) 239 return ret; 240 } else if (ksz_is_ksz8463(dev)) { 241 mask_4q = KSZ8873_PORT_4QUEUE_SPLIT_EN; 242 mask_2q = KSZ8873_PORT_2QUEUE_SPLIT_EN; 243 reg_4q = P1CR1; 244 reg_2q = P1CR1 + 1; 245 } else { 246 mask_4q = KSZ8795_PORT_4QUEUE_SPLIT_EN; 247 mask_2q = KSZ8795_PORT_2QUEUE_SPLIT_EN; 248 reg_4q = REG_PORT_CTRL_13; 249 reg_2q = REG_PORT_CTRL_0; 250 251 /* TODO: this is legacy from initial KSZ8795 driver, should be 252 * moved to appropriate place in the future. 253 */ 254 ret = ksz_rmw8(dev, REG_SW_CTRL_19, 255 SW_OUT_RATE_LIMIT_QUEUE_BASED, 256 SW_OUT_RATE_LIMIT_QUEUE_BASED); 257 if (ret) 258 return ret; 259 } 260 261 if (queues == 4) 262 data_4q = mask_4q; 263 else if (queues == 2) 264 data_2q = mask_2q; 265 266 ret = ksz_prmw8(dev, port, reg_4q, mask_4q, data_4q); 267 if (ret) 268 return ret; 269 270 return ksz_prmw8(dev, port, reg_2q, mask_2q, data_2q); 271 } 272 273 static void ksz8_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, u64 *cnt) 274 { 275 const u32 *masks; 276 const u16 *regs; 277 u16 ctrl_addr; 278 u32 data; 279 u8 check; 280 int loop; 281 282 masks = dev->info->masks; 283 regs = dev->info->regs; 284 285 ctrl_addr = addr + dev->info->reg_mib_cnt * port; 286 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ); 287 288 mutex_lock(&dev->alu_mutex); 289 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 290 291 /* It is almost guaranteed to always read the valid bit because of 292 * slow SPI speed. 293 */ 294 for (loop = 2; loop > 0; loop--) { 295 ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check); 296 297 if (check & masks[MIB_COUNTER_VALID]) { 298 ksz_read32(dev, regs[REG_IND_DATA_LO], &data); 299 if (check & masks[MIB_COUNTER_OVERFLOW]) 300 *cnt += MIB_COUNTER_VALUE + 1; 301 *cnt += data & MIB_COUNTER_VALUE; 302 break; 303 } 304 } 305 mutex_unlock(&dev->alu_mutex); 306 } 307 308 static void ksz8795_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 309 u64 *dropped, u64 *cnt) 310 { 311 const u32 *masks; 312 const u16 *regs; 313 u16 ctrl_addr; 314 u32 data; 315 u8 check; 316 int loop; 317 318 masks = dev->info->masks; 319 regs = dev->info->regs; 320 321 addr -= dev->info->reg_mib_cnt; 322 ctrl_addr = (KSZ8795_MIB_TOTAL_RX_1 - KSZ8795_MIB_TOTAL_RX_0) * port; 323 ctrl_addr += addr + KSZ8795_MIB_TOTAL_RX_0; 324 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ); 325 326 mutex_lock(&dev->alu_mutex); 327 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 328 329 /* It is almost guaranteed to always read the valid bit because of 330 * slow SPI speed. 331 */ 332 for (loop = 2; loop > 0; loop--) { 333 ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check); 334 335 if (check & masks[MIB_COUNTER_VALID]) { 336 ksz_read32(dev, regs[REG_IND_DATA_LO], &data); 337 if (addr < 2) { 338 u64 total; 339 340 total = check & MIB_TOTAL_BYTES_H; 341 total <<= 32; 342 *cnt += total; 343 *cnt += data; 344 if (check & masks[MIB_COUNTER_OVERFLOW]) { 345 total = MIB_TOTAL_BYTES_H + 1; 346 total <<= 32; 347 *cnt += total; 348 } 349 } else { 350 if (check & masks[MIB_COUNTER_OVERFLOW]) 351 *cnt += MIB_PACKET_DROPPED + 1; 352 *cnt += data & MIB_PACKET_DROPPED; 353 } 354 break; 355 } 356 } 357 mutex_unlock(&dev->alu_mutex); 358 } 359 360 static void ksz8863_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 361 u64 *dropped, u64 *cnt) 362 { 363 u32 *last = (u32 *)dropped; 364 const u16 *regs; 365 u16 ctrl_addr; 366 u32 data; 367 u32 cur; 368 369 regs = dev->info->regs; 370 371 addr -= dev->info->reg_mib_cnt; 372 ctrl_addr = addr ? KSZ8863_MIB_PACKET_DROPPED_TX_0 : 373 KSZ8863_MIB_PACKET_DROPPED_RX_0; 374 if (ksz_is_8895_family(dev) && 375 ctrl_addr == KSZ8863_MIB_PACKET_DROPPED_RX_0) 376 ctrl_addr = KSZ8895_MIB_PACKET_DROPPED_RX_0; 377 ctrl_addr += port; 378 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ); 379 380 mutex_lock(&dev->alu_mutex); 381 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 382 ksz_read32(dev, regs[REG_IND_DATA_LO], &data); 383 mutex_unlock(&dev->alu_mutex); 384 385 data &= MIB_PACKET_DROPPED; 386 cur = last[addr]; 387 if (data != cur) { 388 last[addr] = data; 389 if (data < cur) 390 data += MIB_PACKET_DROPPED + 1; 391 data -= cur; 392 *cnt += data; 393 } 394 } 395 396 static void ksz8_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 397 u64 *dropped, u64 *cnt) 398 { 399 if (is_ksz88xx(dev)) 400 ksz8863_r_mib_pkt(dev, port, addr, dropped, cnt); 401 else 402 ksz8795_r_mib_pkt(dev, port, addr, dropped, cnt); 403 } 404 405 static void ksz8_freeze_mib(struct ksz_device *dev, int port, bool freeze) 406 { 407 if (is_ksz88xx(dev)) 408 return; 409 410 /* enable the port for flush/freeze function */ 411 if (freeze) 412 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true); 413 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FREEZE, freeze); 414 415 /* disable the port after freeze is done */ 416 if (!freeze) 417 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false); 418 } 419 420 static void ksz8_port_init_cnt(struct ksz_device *dev, int port) 421 { 422 struct ksz_port_mib *mib = &dev->ports[port].mib; 423 u64 *dropped; 424 425 /* For KSZ8795 family. */ 426 if (ksz_is_ksz87xx(dev)) { 427 /* flush all enabled port MIB counters */ 428 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true); 429 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FLUSH, true); 430 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false); 431 } 432 433 mib->cnt_ptr = 0; 434 435 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 436 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 437 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 438 &mib->counters[mib->cnt_ptr]); 439 ++mib->cnt_ptr; 440 } 441 442 /* last one in storage */ 443 dropped = &mib->counters[dev->info->mib_cnt]; 444 445 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 446 while (mib->cnt_ptr < dev->info->mib_cnt) { 447 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 448 dropped, &mib->counters[mib->cnt_ptr]); 449 ++mib->cnt_ptr; 450 } 451 } 452 453 static int ksz8_r_table(struct ksz_device *dev, int table, u16 addr, u64 *data) 454 { 455 const u16 *regs; 456 u16 ctrl_addr; 457 int ret; 458 459 regs = dev->info->regs; 460 461 ctrl_addr = IND_ACC_TABLE(table | TABLE_READ) | addr; 462 463 mutex_lock(&dev->alu_mutex); 464 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 465 if (ret) 466 goto unlock_alu; 467 468 ret = ksz_read64(dev, regs[REG_IND_DATA_HI], data); 469 unlock_alu: 470 mutex_unlock(&dev->alu_mutex); 471 472 return ret; 473 } 474 475 static int ksz8_w_table(struct ksz_device *dev, int table, u16 addr, u64 data) 476 { 477 const u16 *regs; 478 u16 ctrl_addr; 479 int ret; 480 481 regs = dev->info->regs; 482 483 ctrl_addr = IND_ACC_TABLE(table) | addr; 484 485 mutex_lock(&dev->alu_mutex); 486 ret = ksz_write64(dev, regs[REG_IND_DATA_HI], data); 487 if (ret) 488 goto unlock_alu; 489 490 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 491 unlock_alu: 492 mutex_unlock(&dev->alu_mutex); 493 494 return ret; 495 } 496 497 static int ksz8_valid_dyn_entry(struct ksz_device *dev, u8 *data) 498 { 499 int timeout = 100; 500 const u32 *masks; 501 const u16 *regs; 502 int ret; 503 504 masks = dev->info->masks; 505 regs = dev->info->regs; 506 507 do { 508 ret = ksz_read8(dev, regs[REG_IND_DATA_CHECK], data); 509 if (ret) 510 return ret; 511 512 timeout--; 513 } while ((*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) && timeout); 514 515 /* Entry is not ready for accessing. */ 516 if (*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) 517 return -ETIMEDOUT; 518 519 /* Entry is ready for accessing. */ 520 return ksz_read8(dev, regs[REG_IND_DATA_8], data); 521 } 522 523 static int ksz8_r_dyn_mac_table(struct ksz_device *dev, u16 addr, u8 *mac_addr, 524 u8 *fid, u8 *src_port, u16 *entries) 525 { 526 u32 data_hi, data_lo; 527 const u8 *shifts; 528 const u32 *masks; 529 const u16 *regs; 530 u16 ctrl_addr; 531 u64 buf = 0; 532 u8 data; 533 int cnt; 534 int ret; 535 536 shifts = dev->info->shifts; 537 masks = dev->info->masks; 538 regs = dev->info->regs; 539 540 ctrl_addr = IND_ACC_TABLE(TABLE_DYNAMIC_MAC | TABLE_READ) | addr; 541 542 mutex_lock(&dev->alu_mutex); 543 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 544 if (ret) 545 goto unlock_alu; 546 547 ret = ksz8_valid_dyn_entry(dev, &data); 548 if (ret) 549 goto unlock_alu; 550 551 if (data & masks[DYNAMIC_MAC_TABLE_MAC_EMPTY]) { 552 *entries = 0; 553 goto unlock_alu; 554 } 555 556 ret = ksz_read64(dev, regs[REG_IND_DATA_HI], &buf); 557 if (ret) 558 goto unlock_alu; 559 560 data_hi = (u32)(buf >> 32); 561 data_lo = (u32)buf; 562 563 /* Check out how many valid entry in the table. */ 564 cnt = data & masks[DYNAMIC_MAC_TABLE_ENTRIES_H]; 565 cnt <<= shifts[DYNAMIC_MAC_ENTRIES_H]; 566 cnt |= (data_hi & masks[DYNAMIC_MAC_TABLE_ENTRIES]) >> 567 shifts[DYNAMIC_MAC_ENTRIES]; 568 *entries = cnt + 1; 569 570 *fid = (data_hi & masks[DYNAMIC_MAC_TABLE_FID]) >> 571 shifts[DYNAMIC_MAC_FID]; 572 *src_port = (data_hi & masks[DYNAMIC_MAC_TABLE_SRC_PORT]) >> 573 shifts[DYNAMIC_MAC_SRC_PORT]; 574 575 mac_addr[5] = (u8)data_lo; 576 mac_addr[4] = (u8)(data_lo >> 8); 577 mac_addr[3] = (u8)(data_lo >> 16); 578 mac_addr[2] = (u8)(data_lo >> 24); 579 580 mac_addr[1] = (u8)data_hi; 581 mac_addr[0] = (u8)(data_hi >> 8); 582 583 unlock_alu: 584 mutex_unlock(&dev->alu_mutex); 585 586 return ret; 587 } 588 589 static int ksz8_r_sta_mac_table(struct ksz_device *dev, u16 addr, 590 struct alu_struct *alu, bool *valid) 591 { 592 u32 data_hi, data_lo; 593 const u8 *shifts; 594 const u32 *masks; 595 u64 data; 596 int ret; 597 598 shifts = dev->info->shifts; 599 masks = dev->info->masks; 600 601 ret = ksz8_r_table(dev, TABLE_STATIC_MAC, addr, &data); 602 if (ret) 603 return ret; 604 605 data_hi = data >> 32; 606 data_lo = (u32)data; 607 608 if (!(data_hi & (masks[STATIC_MAC_TABLE_VALID] | 609 masks[STATIC_MAC_TABLE_OVERRIDE]))) { 610 *valid = false; 611 return 0; 612 } 613 614 alu->mac[5] = (u8)data_lo; 615 alu->mac[4] = (u8)(data_lo >> 8); 616 alu->mac[3] = (u8)(data_lo >> 16); 617 alu->mac[2] = (u8)(data_lo >> 24); 618 alu->mac[1] = (u8)data_hi; 619 alu->mac[0] = (u8)(data_hi >> 8); 620 alu->port_forward = 621 (data_hi & masks[STATIC_MAC_TABLE_FWD_PORTS]) >> 622 shifts[STATIC_MAC_FWD_PORTS]; 623 alu->is_override = (data_hi & masks[STATIC_MAC_TABLE_OVERRIDE]) ? 1 : 0; 624 625 /* KSZ8795/KSZ8895 family switches have STATIC_MAC_TABLE_USE_FID and 626 * STATIC_MAC_TABLE_FID definitions off by 1 when doing read on the 627 * static MAC table compared to doing write. 628 */ 629 if (ksz_is_ksz87xx(dev) || ksz_is_8895_family(dev)) 630 data_hi >>= 1; 631 alu->is_static = true; 632 alu->is_use_fid = (data_hi & masks[STATIC_MAC_TABLE_USE_FID]) ? 1 : 0; 633 alu->fid = (data_hi & masks[STATIC_MAC_TABLE_FID]) >> 634 shifts[STATIC_MAC_FID]; 635 636 *valid = true; 637 638 return 0; 639 } 640 641 static int ksz8_w_sta_mac_table(struct ksz_device *dev, u16 addr, 642 struct alu_struct *alu) 643 { 644 u32 data_hi, data_lo; 645 const u8 *shifts; 646 const u32 *masks; 647 u64 data; 648 649 shifts = dev->info->shifts; 650 masks = dev->info->masks; 651 652 data_lo = ((u32)alu->mac[2] << 24) | 653 ((u32)alu->mac[3] << 16) | 654 ((u32)alu->mac[4] << 8) | alu->mac[5]; 655 data_hi = ((u32)alu->mac[0] << 8) | alu->mac[1]; 656 data_hi |= (u32)alu->port_forward << shifts[STATIC_MAC_FWD_PORTS]; 657 658 if (alu->is_override) 659 data_hi |= masks[STATIC_MAC_TABLE_OVERRIDE]; 660 if (alu->is_use_fid) { 661 data_hi |= masks[STATIC_MAC_TABLE_USE_FID]; 662 data_hi |= (u32)alu->fid << shifts[STATIC_MAC_FID]; 663 } 664 if (alu->is_static) 665 data_hi |= masks[STATIC_MAC_TABLE_VALID]; 666 else 667 data_hi &= ~masks[STATIC_MAC_TABLE_OVERRIDE]; 668 669 data = (u64)data_hi << 32 | data_lo; 670 671 return ksz8_w_table(dev, TABLE_STATIC_MAC, addr, data); 672 } 673 674 static void ksz8_from_vlan(struct ksz_device *dev, u32 vlan, u8 *fid, 675 u8 *member, u8 *valid) 676 { 677 const u8 *shifts; 678 const u32 *masks; 679 680 shifts = dev->info->shifts; 681 masks = dev->info->masks; 682 683 *fid = vlan & masks[VLAN_TABLE_FID]; 684 *member = (vlan & masks[VLAN_TABLE_MEMBERSHIP]) >> 685 shifts[VLAN_TABLE_MEMBERSHIP_S]; 686 *valid = !!(vlan & masks[VLAN_TABLE_VALID]); 687 } 688 689 static void ksz8_to_vlan(struct ksz_device *dev, u8 fid, u8 member, u8 valid, 690 u16 *vlan) 691 { 692 const u8 *shifts; 693 const u32 *masks; 694 695 shifts = dev->info->shifts; 696 masks = dev->info->masks; 697 698 *vlan = fid; 699 *vlan |= (u16)member << shifts[VLAN_TABLE_MEMBERSHIP_S]; 700 if (valid) 701 *vlan |= masks[VLAN_TABLE_VALID]; 702 } 703 704 static void ksz8_r_vlan_entries(struct ksz_device *dev, u16 addr) 705 { 706 const u8 *shifts; 707 u64 data; 708 int i; 709 710 shifts = dev->info->shifts; 711 712 ksz8_r_table(dev, TABLE_VLAN, addr, &data); 713 addr *= 4; 714 for (i = 0; i < 4; i++) { 715 dev->vlan_cache[addr + i].table[0] = (u16)data; 716 data >>= shifts[VLAN_TABLE]; 717 } 718 } 719 720 static void ksz8_r_vlan_table(struct ksz_device *dev, u16 vid, u16 *vlan) 721 { 722 int index; 723 u16 *data; 724 u16 addr; 725 u64 buf; 726 727 data = (u16 *)&buf; 728 addr = vid / 4; 729 index = vid & 3; 730 ksz8_r_table(dev, TABLE_VLAN, addr, &buf); 731 *vlan = data[index]; 732 } 733 734 static void ksz8_w_vlan_table(struct ksz_device *dev, u16 vid, u16 vlan) 735 { 736 int index; 737 u16 *data; 738 u16 addr; 739 u64 buf; 740 741 data = (u16 *)&buf; 742 addr = vid / 4; 743 index = vid & 3; 744 ksz8_r_table(dev, TABLE_VLAN, addr, &buf); 745 data[index] = vlan; 746 dev->vlan_cache[vid].table[0] = vlan; 747 ksz8_w_table(dev, TABLE_VLAN, addr, buf); 748 } 749 750 /** 751 * ksz879x_get_loopback - KSZ879x specific function to get loopback 752 * configuration status for a specific port 753 * @dev: Pointer to the device structure 754 * @port: Port number to query 755 * @val: Pointer to store the result 756 * 757 * This function reads the SMI registers to determine whether loopback mode 758 * is enabled for a specific port. 759 * 760 * Return: 0 on success, error code on failure. 761 */ 762 static int ksz879x_get_loopback(struct ksz_device *dev, u16 port, 763 u16 *val) 764 { 765 u8 stat3; 766 int ret; 767 768 ret = ksz_pread8(dev, port, REG_PORT_STATUS_3, &stat3); 769 if (ret) 770 return ret; 771 772 if (stat3 & PORT_PHY_LOOPBACK) 773 *val |= BMCR_LOOPBACK; 774 775 return 0; 776 } 777 778 /** 779 * ksz879x_set_loopback - KSZ879x specific function to set loopback mode for 780 * a specific port 781 * @dev: Pointer to the device structure. 782 * @port: Port number to modify. 783 * @val: Value indicating whether to enable or disable loopback mode. 784 * 785 * This function translates loopback bit of the BMCR register into the 786 * corresponding hardware register bit value and writes it to the SMI interface. 787 * 788 * Return: 0 on success, error code on failure. 789 */ 790 static int ksz879x_set_loopback(struct ksz_device *dev, u16 port, u16 val) 791 { 792 u8 stat3 = 0; 793 794 if (val & BMCR_LOOPBACK) 795 stat3 |= PORT_PHY_LOOPBACK; 796 797 return ksz_prmw8(dev, port, REG_PORT_STATUS_3, PORT_PHY_LOOPBACK, 798 stat3); 799 } 800 801 /** 802 * ksz8_r_phy_ctrl - Translates and reads from the SMI interface to a MIIM PHY 803 * Control register (Reg. 31). 804 * @dev: The KSZ device instance. 805 * @port: The port number to be read. 806 * @val: The value read from the SMI interface. 807 * 808 * This function reads the SMI interface and translates the hardware register 809 * bit values into their corresponding control settings for a MIIM PHY Control 810 * register. 811 * 812 * Return: 0 on success, error code on failure. 813 */ 814 static int ksz8_r_phy_ctrl(struct ksz_device *dev, int port, u16 *val) 815 { 816 const u16 *regs = dev->info->regs; 817 u8 reg_val; 818 int ret; 819 820 *val = 0; 821 822 ret = ksz_pread8(dev, port, regs[P_LINK_STATUS], ®_val); 823 if (ret < 0) 824 return ret; 825 826 if (reg_val & PORT_MDIX_STATUS) 827 *val |= KSZ886X_CTRL_MDIX_STAT; 828 829 ret = ksz_pread8(dev, port, REG_PORT_LINK_MD_CTRL, ®_val); 830 if (ret < 0) 831 return ret; 832 833 if (reg_val & PORT_FORCE_LINK) 834 *val |= KSZ886X_CTRL_FORCE_LINK; 835 836 if (reg_val & PORT_POWER_SAVING) 837 *val |= KSZ886X_CTRL_PWRSAVE; 838 839 if (reg_val & PORT_PHY_REMOTE_LOOPBACK) 840 *val |= KSZ886X_CTRL_REMOTE_LOOPBACK; 841 842 return 0; 843 } 844 845 /** 846 * ksz8_r_phy_bmcr - Translates and reads from the SMI interface to a MIIM PHY 847 * Basic mode control register (Reg. 0). 848 * @dev: The KSZ device instance. 849 * @port: The port number to be read. 850 * @val: The value read from the SMI interface. 851 * 852 * This function reads the SMI interface and translates the hardware register 853 * bit values into their corresponding control settings for a MIIM PHY Basic 854 * mode control register. 855 * 856 * MIIM Bit Mapping Comparison between KSZ8794 and KSZ8873 857 * ------------------------------------------------------------------- 858 * MIIM Bit | KSZ8794 Reg/Bit | KSZ8873 Reg/Bit 859 * ----------------------------+-----------------------------+---------------- 860 * Bit 15 - Soft Reset | 0xF/4 | Not supported 861 * Bit 14 - Loopback | 0xD/0 (MAC), 0xF/7 (PHY) ~ 0xD/0 (PHY) 862 * Bit 13 - Force 100 | 0xC/6 = 0xC/6 863 * Bit 12 - AN Enable | 0xC/7 (reverse logic) ~ 0xC/7 864 * Bit 11 - Power Down | 0xD/3 = 0xD/3 865 * Bit 10 - PHY Isolate | 0xF/5 | Not supported 866 * Bit 9 - Restart AN | 0xD/5 = 0xD/5 867 * Bit 8 - Force Full-Duplex | 0xC/5 = 0xC/5 868 * Bit 7 - Collision Test/Res. | Not supported | Not supported 869 * Bit 6 - Reserved | Not supported | Not supported 870 * Bit 5 - Hp_mdix | 0x9/7 ~ 0xF/7 871 * Bit 4 - Force MDI | 0xD/1 = 0xD/1 872 * Bit 3 - Disable MDIX | 0xD/2 = 0xD/2 873 * Bit 2 - Disable Far-End F. | ???? | 0xD/4 874 * Bit 1 - Disable Transmit | 0xD/6 = 0xD/6 875 * Bit 0 - Disable LED | 0xD/7 = 0xD/7 876 * ------------------------------------------------------------------- 877 * 878 * Return: 0 on success, error code on failure. 879 */ 880 static int ksz8_r_phy_bmcr(struct ksz_device *dev, u16 port, u16 *val) 881 { 882 const u16 *regs = dev->info->regs; 883 u8 restart, speed, ctrl; 884 int ret; 885 886 *val = 0; 887 888 ret = ksz_pread8(dev, port, regs[P_NEG_RESTART_CTRL], &restart); 889 if (ret) 890 return ret; 891 892 ret = ksz_pread8(dev, port, regs[P_SPEED_STATUS], &speed); 893 if (ret) 894 return ret; 895 896 ret = ksz_pread8(dev, port, regs[P_FORCE_CTRL], &ctrl); 897 if (ret) 898 return ret; 899 900 if (ctrl & PORT_FORCE_100_MBIT) 901 *val |= BMCR_SPEED100; 902 903 if (ksz_is_ksz88x3(dev)) { 904 if (restart & KSZ8873_PORT_PHY_LOOPBACK) 905 *val |= BMCR_LOOPBACK; 906 907 if ((ctrl & PORT_AUTO_NEG_ENABLE)) 908 *val |= BMCR_ANENABLE; 909 } else { 910 ret = ksz879x_get_loopback(dev, port, val); 911 if (ret) 912 return ret; 913 914 if (!(ctrl & PORT_AUTO_NEG_DISABLE)) 915 *val |= BMCR_ANENABLE; 916 } 917 918 if (restart & PORT_POWER_DOWN) 919 *val |= BMCR_PDOWN; 920 921 if (restart & PORT_AUTO_NEG_RESTART) 922 *val |= BMCR_ANRESTART; 923 924 if (ctrl & PORT_FORCE_FULL_DUPLEX) 925 *val |= BMCR_FULLDPLX; 926 927 if (speed & PORT_HP_MDIX) 928 *val |= KSZ886X_BMCR_HP_MDIX; 929 930 if (restart & PORT_FORCE_MDIX) 931 *val |= KSZ886X_BMCR_FORCE_MDI; 932 933 if (restart & PORT_AUTO_MDIX_DISABLE) 934 *val |= KSZ886X_BMCR_DISABLE_AUTO_MDIX; 935 936 if (restart & PORT_TX_DISABLE) 937 *val |= KSZ886X_BMCR_DISABLE_TRANSMIT; 938 939 if (restart & PORT_LED_OFF) 940 *val |= KSZ886X_BMCR_DISABLE_LED; 941 942 return 0; 943 } 944 945 static int ksz8_r_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 *val) 946 { 947 u8 ctrl, link, val1, val2; 948 int processed = true; 949 const u16 *regs; 950 u16 data = 0; 951 u16 p = phy; 952 int ret; 953 954 regs = dev->info->regs; 955 956 switch (reg) { 957 case MII_BMCR: 958 ret = ksz8_r_phy_bmcr(dev, p, &data); 959 if (ret) 960 return ret; 961 break; 962 case MII_BMSR: 963 ret = ksz_pread8(dev, p, regs[P_LINK_STATUS], &link); 964 if (ret) 965 return ret; 966 967 data = BMSR_100FULL | 968 BMSR_100HALF | 969 BMSR_10FULL | 970 BMSR_10HALF | 971 BMSR_ANEGCAPABLE; 972 if (link & PORT_AUTO_NEG_COMPLETE) 973 data |= BMSR_ANEGCOMPLETE; 974 if (link & PORT_STAT_LINK_GOOD) 975 data |= BMSR_LSTATUS; 976 break; 977 case MII_PHYSID1: 978 data = KSZ8795_ID_HI; 979 break; 980 case MII_PHYSID2: 981 if (ksz_is_ksz88x3(dev)) 982 data = KSZ8863_ID_LO; 983 else 984 data = KSZ8795_ID_LO; 985 break; 986 case MII_ADVERTISE: 987 ret = ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl); 988 if (ret) 989 return ret; 990 991 data = ADVERTISE_CSMA; 992 if (ctrl & PORT_AUTO_NEG_SYM_PAUSE) 993 data |= ADVERTISE_PAUSE_CAP; 994 if (ctrl & PORT_AUTO_NEG_100BTX_FD) 995 data |= ADVERTISE_100FULL; 996 if (ctrl & PORT_AUTO_NEG_100BTX) 997 data |= ADVERTISE_100HALF; 998 if (ctrl & PORT_AUTO_NEG_10BT_FD) 999 data |= ADVERTISE_10FULL; 1000 if (ctrl & PORT_AUTO_NEG_10BT) 1001 data |= ADVERTISE_10HALF; 1002 break; 1003 case MII_LPA: 1004 ret = ksz_pread8(dev, p, regs[P_REMOTE_STATUS], &link); 1005 if (ret) 1006 return ret; 1007 1008 data = LPA_SLCT; 1009 if (link & PORT_REMOTE_SYM_PAUSE) 1010 data |= LPA_PAUSE_CAP; 1011 if (link & PORT_REMOTE_100BTX_FD) 1012 data |= LPA_100FULL; 1013 if (link & PORT_REMOTE_100BTX) 1014 data |= LPA_100HALF; 1015 if (link & PORT_REMOTE_10BT_FD) 1016 data |= LPA_10FULL; 1017 if (link & PORT_REMOTE_10BT) 1018 data |= LPA_10HALF; 1019 if (data & ~LPA_SLCT) 1020 data |= LPA_LPACK; 1021 break; 1022 case PHY_REG_LINK_MD: 1023 ret = ksz_pread8(dev, p, REG_PORT_LINK_MD_CTRL, &val1); 1024 if (ret) 1025 return ret; 1026 1027 ret = ksz_pread8(dev, p, REG_PORT_LINK_MD_RESULT, &val2); 1028 if (ret) 1029 return ret; 1030 1031 if (val1 & PORT_START_CABLE_DIAG) 1032 data |= PHY_START_CABLE_DIAG; 1033 1034 if (val1 & PORT_CABLE_10M_SHORT) 1035 data |= PHY_CABLE_10M_SHORT; 1036 1037 data |= FIELD_PREP(PHY_CABLE_DIAG_RESULT_M, 1038 FIELD_GET(PORT_CABLE_DIAG_RESULT_M, val1)); 1039 1040 data |= FIELD_PREP(PHY_CABLE_FAULT_COUNTER_M, 1041 (FIELD_GET(PORT_CABLE_FAULT_COUNTER_H, val1) << 8) | 1042 FIELD_GET(PORT_CABLE_FAULT_COUNTER_L, val2)); 1043 break; 1044 case PHY_REG_PHY_CTRL: 1045 ret = ksz8_r_phy_ctrl(dev, p, &data); 1046 if (ret) 1047 return ret; 1048 1049 break; 1050 default: 1051 processed = false; 1052 break; 1053 } 1054 if (processed) 1055 *val = data; 1056 1057 return 0; 1058 } 1059 1060 static int ksz8_phy_read16(struct dsa_switch *ds, int addr, int reg) 1061 { 1062 struct ksz_device *dev = ds->priv; 1063 u16 val = 0xffff; 1064 int ret; 1065 1066 ret = ksz8_r_phy(dev, addr, reg, &val); 1067 if (ret) 1068 return ret; 1069 1070 return val; 1071 } 1072 1073 /** 1074 * ksz8_w_phy_ctrl - Translates and writes to the SMI interface from a MIIM PHY 1075 * Control register (Reg. 31). 1076 * @dev: The KSZ device instance. 1077 * @port: The port number to be configured. 1078 * @val: The register value to be written. 1079 * 1080 * This function translates control settings from a MIIM PHY Control register 1081 * into their corresponding hardware register bit values for the SMI 1082 * interface. 1083 * 1084 * Return: 0 on success, error code on failure. 1085 */ 1086 static int ksz8_w_phy_ctrl(struct ksz_device *dev, int port, u16 val) 1087 { 1088 u8 reg_val = 0; 1089 int ret; 1090 1091 if (val & KSZ886X_CTRL_FORCE_LINK) 1092 reg_val |= PORT_FORCE_LINK; 1093 1094 if (val & KSZ886X_CTRL_PWRSAVE) 1095 reg_val |= PORT_POWER_SAVING; 1096 1097 if (val & KSZ886X_CTRL_REMOTE_LOOPBACK) 1098 reg_val |= PORT_PHY_REMOTE_LOOPBACK; 1099 1100 ret = ksz_prmw8(dev, port, REG_PORT_LINK_MD_CTRL, PORT_FORCE_LINK | 1101 PORT_POWER_SAVING | PORT_PHY_REMOTE_LOOPBACK, reg_val); 1102 return ret; 1103 } 1104 1105 /** 1106 * ksz8_w_phy_bmcr - Translates and writes to the SMI interface from a MIIM PHY 1107 * Basic mode control register (Reg. 0). 1108 * @dev: The KSZ device instance. 1109 * @port: The port number to be configured. 1110 * @val: The register value to be written. 1111 * 1112 * This function translates control settings from a MIIM PHY Basic mode control 1113 * register into their corresponding hardware register bit values for the SMI 1114 * interface. 1115 * 1116 * MIIM Bit Mapping Comparison between KSZ8794 and KSZ8873 1117 * ------------------------------------------------------------------- 1118 * MIIM Bit | KSZ8794 Reg/Bit | KSZ8873 Reg/Bit 1119 * ----------------------------+-----------------------------+---------------- 1120 * Bit 15 - Soft Reset | 0xF/4 | Not supported 1121 * Bit 14 - Loopback | 0xD/0 (MAC), 0xF/7 (PHY) ~ 0xD/0 (PHY) 1122 * Bit 13 - Force 100 | 0xC/6 = 0xC/6 1123 * Bit 12 - AN Enable | 0xC/7 (reverse logic) ~ 0xC/7 1124 * Bit 11 - Power Down | 0xD/3 = 0xD/3 1125 * Bit 10 - PHY Isolate | 0xF/5 | Not supported 1126 * Bit 9 - Restart AN | 0xD/5 = 0xD/5 1127 * Bit 8 - Force Full-Duplex | 0xC/5 = 0xC/5 1128 * Bit 7 - Collision Test/Res. | Not supported | Not supported 1129 * Bit 6 - Reserved | Not supported | Not supported 1130 * Bit 5 - Hp_mdix | 0x9/7 ~ 0xF/7 1131 * Bit 4 - Force MDI | 0xD/1 = 0xD/1 1132 * Bit 3 - Disable MDIX | 0xD/2 = 0xD/2 1133 * Bit 2 - Disable Far-End F. | ???? | 0xD/4 1134 * Bit 1 - Disable Transmit | 0xD/6 = 0xD/6 1135 * Bit 0 - Disable LED | 0xD/7 = 0xD/7 1136 * ------------------------------------------------------------------- 1137 * 1138 * Return: 0 on success, error code on failure. 1139 */ 1140 static int ksz8_w_phy_bmcr(struct ksz_device *dev, u16 port, u16 val) 1141 { 1142 u8 restart, speed, ctrl, restart_mask; 1143 const u16 *regs = dev->info->regs; 1144 int ret; 1145 1146 /* Do not support PHY reset function. */ 1147 if (val & BMCR_RESET) 1148 return 0; 1149 1150 speed = 0; 1151 if (val & KSZ886X_BMCR_HP_MDIX) 1152 speed |= PORT_HP_MDIX; 1153 1154 ret = ksz_prmw8(dev, port, regs[P_SPEED_STATUS], PORT_HP_MDIX, speed); 1155 if (ret) 1156 return ret; 1157 1158 ctrl = 0; 1159 if (ksz_is_ksz88x3(dev)) { 1160 if ((val & BMCR_ANENABLE)) 1161 ctrl |= PORT_AUTO_NEG_ENABLE; 1162 } else { 1163 if (!(val & BMCR_ANENABLE)) 1164 ctrl |= PORT_AUTO_NEG_DISABLE; 1165 1166 /* Fiber port does not support auto-negotiation. */ 1167 if (dev->ports[port].fiber) 1168 ctrl |= PORT_AUTO_NEG_DISABLE; 1169 } 1170 1171 if (val & BMCR_SPEED100) 1172 ctrl |= PORT_FORCE_100_MBIT; 1173 1174 if (val & BMCR_FULLDPLX) 1175 ctrl |= PORT_FORCE_FULL_DUPLEX; 1176 1177 ret = ksz_prmw8(dev, port, regs[P_FORCE_CTRL], PORT_FORCE_100_MBIT | 1178 /* PORT_AUTO_NEG_ENABLE and PORT_AUTO_NEG_DISABLE are the same 1179 * bits 1180 */ 1181 PORT_FORCE_FULL_DUPLEX | PORT_AUTO_NEG_ENABLE, ctrl); 1182 if (ret) 1183 return ret; 1184 1185 restart = 0; 1186 restart_mask = PORT_LED_OFF | PORT_TX_DISABLE | PORT_AUTO_NEG_RESTART | 1187 PORT_POWER_DOWN | PORT_AUTO_MDIX_DISABLE | PORT_FORCE_MDIX; 1188 1189 if (val & KSZ886X_BMCR_DISABLE_LED) 1190 restart |= PORT_LED_OFF; 1191 1192 if (val & KSZ886X_BMCR_DISABLE_TRANSMIT) 1193 restart |= PORT_TX_DISABLE; 1194 1195 if (val & BMCR_ANRESTART) 1196 restart |= PORT_AUTO_NEG_RESTART; 1197 1198 if (val & BMCR_PDOWN) 1199 restart |= PORT_POWER_DOWN; 1200 1201 if (val & KSZ886X_BMCR_DISABLE_AUTO_MDIX) 1202 restart |= PORT_AUTO_MDIX_DISABLE; 1203 1204 if (val & KSZ886X_BMCR_FORCE_MDI) 1205 restart |= PORT_FORCE_MDIX; 1206 1207 if (ksz_is_ksz88x3(dev)) { 1208 restart_mask |= KSZ8873_PORT_PHY_LOOPBACK; 1209 1210 if (val & BMCR_LOOPBACK) 1211 restart |= KSZ8873_PORT_PHY_LOOPBACK; 1212 } else { 1213 ret = ksz879x_set_loopback(dev, port, val); 1214 if (ret) 1215 return ret; 1216 } 1217 1218 return ksz_prmw8(dev, port, regs[P_NEG_RESTART_CTRL], restart_mask, 1219 restart); 1220 } 1221 1222 static int ksz8_w_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 val) 1223 { 1224 const u16 *regs; 1225 u8 ctrl, data; 1226 u16 p = phy; 1227 int ret; 1228 1229 regs = dev->info->regs; 1230 1231 switch (reg) { 1232 case MII_BMCR: 1233 ret = ksz8_w_phy_bmcr(dev, p, val); 1234 if (ret) 1235 return ret; 1236 break; 1237 case MII_ADVERTISE: 1238 ret = ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl); 1239 if (ret) 1240 return ret; 1241 1242 data = ctrl; 1243 data &= ~(PORT_AUTO_NEG_SYM_PAUSE | 1244 PORT_AUTO_NEG_100BTX_FD | 1245 PORT_AUTO_NEG_100BTX | 1246 PORT_AUTO_NEG_10BT_FD | 1247 PORT_AUTO_NEG_10BT); 1248 if (val & ADVERTISE_PAUSE_CAP) 1249 data |= PORT_AUTO_NEG_SYM_PAUSE; 1250 if (val & ADVERTISE_100FULL) 1251 data |= PORT_AUTO_NEG_100BTX_FD; 1252 if (val & ADVERTISE_100HALF) 1253 data |= PORT_AUTO_NEG_100BTX; 1254 if (val & ADVERTISE_10FULL) 1255 data |= PORT_AUTO_NEG_10BT_FD; 1256 if (val & ADVERTISE_10HALF) 1257 data |= PORT_AUTO_NEG_10BT; 1258 1259 if (data != ctrl) { 1260 ret = ksz_pwrite8(dev, p, regs[P_LOCAL_CTRL], data); 1261 if (ret) 1262 return ret; 1263 } 1264 break; 1265 case PHY_REG_LINK_MD: 1266 if (val & PHY_START_CABLE_DIAG) 1267 ksz_port_cfg(dev, p, REG_PORT_LINK_MD_CTRL, PORT_START_CABLE_DIAG, true); 1268 break; 1269 1270 case PHY_REG_PHY_CTRL: 1271 ret = ksz8_w_phy_ctrl(dev, p, val); 1272 if (ret) 1273 return ret; 1274 break; 1275 default: 1276 break; 1277 } 1278 1279 return 0; 1280 } 1281 1282 static int ksz8_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 1283 { 1284 struct ksz_device *dev = ds->priv; 1285 int ret; 1286 1287 ret = ksz8_w_phy(dev, addr, reg, val); 1288 if (ret) 1289 return ret; 1290 1291 return 0; 1292 } 1293 1294 static void ksz8_cfg_port_member(struct ksz_device *dev, int port, u8 member) 1295 { 1296 int offset = P_MIRROR_CTRL; 1297 u8 data; 1298 1299 if (ksz_is_ksz8463(dev)) 1300 offset = P1CR2; 1301 ksz_pread8(dev, port, offset, &data); 1302 data &= ~dev->port_mask; 1303 data |= (member & dev->port_mask); 1304 ksz_pwrite8(dev, port, offset, data); 1305 } 1306 1307 static void ksz8_flush_dyn_mac_table(struct dsa_switch *ds, int port) 1308 { 1309 struct ksz_device *dev = ds->priv; 1310 u8 learn[DSA_MAX_PORTS]; 1311 int first, index, cnt; 1312 const u16 *regs; 1313 int reg = S_FLUSH_TABLE_CTRL; 1314 int mask = SW_FLUSH_DYN_MAC_TABLE; 1315 1316 regs = dev->info->regs; 1317 1318 if ((uint)port < dev->info->port_cnt) { 1319 first = port; 1320 cnt = port + 1; 1321 } else { 1322 /* Flush all ports. */ 1323 first = 0; 1324 cnt = dev->info->port_cnt; 1325 } 1326 for (index = first; index < cnt; index++) { 1327 ksz_pread8(dev, index, regs[P_STP_CTRL], &learn[index]); 1328 if (!(learn[index] & PORT_LEARN_DISABLE)) 1329 ksz_pwrite8(dev, index, regs[P_STP_CTRL], 1330 learn[index] | PORT_LEARN_DISABLE); 1331 } 1332 if (ksz_is_ksz8463(dev)) { 1333 reg = KSZ8463_FLUSH_TABLE_CTRL; 1334 mask = KSZ8463_FLUSH_DYN_MAC_TABLE; 1335 } 1336 ksz_cfg(dev, reg, mask, true); 1337 for (index = first; index < cnt; index++) { 1338 if (!(learn[index] & PORT_LEARN_DISABLE)) 1339 ksz_pwrite8(dev, index, regs[P_STP_CTRL], learn[index]); 1340 } 1341 } 1342 1343 static int ksz8_fdb_dump(struct dsa_switch *ds, int port, 1344 dsa_fdb_dump_cb_t *cb, void *data) 1345 { 1346 struct ksz_device *dev = ds->priv; 1347 u8 mac[ETH_ALEN]; 1348 u8 src_port, fid; 1349 u16 entries = 0; 1350 int ret, i; 1351 1352 for (i = 0; i < KSZ8_DYN_MAC_ENTRIES; i++) { 1353 ret = ksz8_r_dyn_mac_table(dev, i, mac, &fid, &src_port, 1354 &entries); 1355 if (ret) 1356 return ret; 1357 1358 if (i >= entries) 1359 return 0; 1360 1361 if (port == src_port) { 1362 ret = cb(mac, fid, false, data); 1363 if (ret) 1364 return ret; 1365 } 1366 } 1367 1368 return 0; 1369 } 1370 1371 static int ksz8_add_sta_mac(struct ksz_device *dev, int port, 1372 const unsigned char *addr, u16 vid) 1373 { 1374 struct alu_struct alu; 1375 int index, ret; 1376 int empty = 0; 1377 1378 alu.port_forward = 0; 1379 for (index = 0; index < dev->info->num_statics; index++) { 1380 bool valid; 1381 1382 ret = ksz8_r_sta_mac_table(dev, index, &alu, &valid); 1383 if (ret) 1384 return ret; 1385 if (!valid) { 1386 /* Remember the first empty entry. */ 1387 if (!empty) 1388 empty = index + 1; 1389 continue; 1390 } 1391 1392 if (!memcmp(alu.mac, addr, ETH_ALEN) && alu.fid == vid) 1393 break; 1394 } 1395 1396 /* no available entry */ 1397 if (index == dev->info->num_statics && !empty) 1398 return -ENOSPC; 1399 1400 /* add entry */ 1401 if (index == dev->info->num_statics) { 1402 index = empty - 1; 1403 memset(&alu, 0, sizeof(alu)); 1404 memcpy(alu.mac, addr, ETH_ALEN); 1405 alu.is_static = true; 1406 } 1407 alu.port_forward |= BIT(port); 1408 if (vid) { 1409 alu.is_use_fid = true; 1410 1411 /* Need a way to map VID to FID. */ 1412 alu.fid = vid; 1413 } 1414 1415 return ksz8_w_sta_mac_table(dev, index, &alu); 1416 } 1417 1418 static int ksz8_del_sta_mac(struct ksz_device *dev, int port, 1419 const unsigned char *addr, u16 vid) 1420 { 1421 struct alu_struct alu; 1422 int index, ret; 1423 1424 for (index = 0; index < dev->info->num_statics; index++) { 1425 bool valid; 1426 1427 ret = ksz8_r_sta_mac_table(dev, index, &alu, &valid); 1428 if (ret) 1429 return ret; 1430 if (!valid) 1431 continue; 1432 1433 if (!memcmp(alu.mac, addr, ETH_ALEN) && alu.fid == vid) 1434 break; 1435 } 1436 1437 /* no available entry */ 1438 if (index == dev->info->num_statics) 1439 return 0; 1440 1441 /* clear port */ 1442 alu.port_forward &= ~BIT(port); 1443 if (!alu.port_forward) 1444 alu.is_static = false; 1445 1446 return ksz8_w_sta_mac_table(dev, index, &alu); 1447 } 1448 1449 static int ksz8_mdb_add(struct dsa_switch *ds, int port, 1450 const struct switchdev_obj_port_mdb *mdb, 1451 struct dsa_db db) 1452 { 1453 return ksz8_add_sta_mac(ds->priv, port, mdb->addr, mdb->vid); 1454 } 1455 1456 static int ksz8_mdb_del(struct dsa_switch *ds, int port, 1457 const struct switchdev_obj_port_mdb *mdb, 1458 struct dsa_db db) 1459 { 1460 return ksz8_del_sta_mac(ds->priv, port, mdb->addr, mdb->vid); 1461 } 1462 1463 static int ksz8_fdb_add(struct dsa_switch *ds, int port, 1464 const unsigned char *addr, u16 vid, struct dsa_db db) 1465 { 1466 return ksz8_add_sta_mac(ds->priv, port, addr, vid); 1467 } 1468 1469 static int ksz8_fdb_del(struct dsa_switch *ds, int port, 1470 const unsigned char *addr, u16 vid, struct dsa_db db) 1471 { 1472 return ksz8_del_sta_mac(ds->priv, port, addr, vid); 1473 } 1474 1475 static int ksz8_port_vlan_filtering(struct dsa_switch *ds, int port, bool flag, 1476 struct netlink_ext_ack *extack) 1477 { 1478 struct ksz_device *dev = ds->priv; 1479 1480 if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev)) 1481 return -ENOTSUPP; 1482 1483 /* Discard packets with VID not enabled on the switch */ 1484 ksz_cfg(dev, S_MIRROR_CTRL, SW_VLAN_ENABLE, flag); 1485 1486 /* Discard packets with VID not enabled on the ingress port */ 1487 for (port = 0; port < dev->phy_port_cnt; ++port) 1488 ksz_port_cfg(dev, port, REG_PORT_CTRL_2, PORT_INGRESS_FILTER, 1489 flag); 1490 1491 return 0; 1492 } 1493 1494 static void ksz8_port_enable_pvid(struct ksz_device *dev, int port, bool state) 1495 { 1496 if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev)) { 1497 int reg = REG_SW_INSERT_SRC_PVID; 1498 1499 if (ksz_is_ksz8463(dev)) 1500 reg = KSZ8463_REG_SW_CTRL_9; 1501 ksz_cfg(dev, reg, 0x03 << (4 - 2 * port), state); 1502 } else { 1503 ksz_pwrite8(dev, port, REG_PORT_CTRL_12, state ? 0x0f : 0x00); 1504 } 1505 } 1506 1507 static int ksz8_port_vlan_add(struct dsa_switch *ds, int port, 1508 const struct switchdev_obj_port_vlan *vlan, 1509 struct netlink_ext_ack *extack) 1510 { 1511 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1512 struct ksz_device *dev = ds->priv; 1513 struct ksz_port *p = &dev->ports[port]; 1514 u16 data, new_pvid = 0; 1515 u8 fid, member, valid; 1516 1517 if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev)) 1518 return -ENOTSUPP; 1519 1520 /* If a VLAN is added with untagged flag different from the 1521 * port's Remove Tag flag, we need to change the latter. 1522 * Ignore VID 0, which is always untagged. 1523 * Ignore CPU port, which will always be tagged. 1524 */ 1525 if (untagged != p->remove_tag && vlan->vid != 0 && 1526 port != dev->cpu_port) { 1527 unsigned int vid; 1528 1529 /* Reject attempts to add a VLAN that requires the 1530 * Remove Tag flag to be changed, unless there are no 1531 * other VLANs currently configured. 1532 */ 1533 for (vid = 1; vid < dev->info->num_vlans; ++vid) { 1534 /* Skip the VID we are going to add or reconfigure */ 1535 if (vid == vlan->vid) 1536 continue; 1537 1538 ksz8_from_vlan(dev, dev->vlan_cache[vid].table[0], 1539 &fid, &member, &valid); 1540 if (valid && (member & BIT(port))) 1541 return -EINVAL; 1542 } 1543 1544 ksz_port_cfg(dev, port, P_TAG_CTRL, PORT_REMOVE_TAG, untagged); 1545 p->remove_tag = untagged; 1546 } 1547 1548 ksz8_r_vlan_table(dev, vlan->vid, &data); 1549 ksz8_from_vlan(dev, data, &fid, &member, &valid); 1550 1551 /* First time to setup the VLAN entry. */ 1552 if (!valid) { 1553 /* Need to find a way to map VID to FID. */ 1554 fid = 1; 1555 valid = 1; 1556 } 1557 member |= BIT(port); 1558 1559 ksz8_to_vlan(dev, fid, member, valid, &data); 1560 ksz8_w_vlan_table(dev, vlan->vid, data); 1561 1562 /* change PVID */ 1563 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) 1564 new_pvid = vlan->vid; 1565 1566 if (new_pvid) { 1567 u16 vid; 1568 1569 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &vid); 1570 vid &= ~VLAN_VID_MASK; 1571 vid |= new_pvid; 1572 ksz_pwrite16(dev, port, REG_PORT_CTRL_VID, vid); 1573 1574 ksz8_port_enable_pvid(dev, port, true); 1575 } 1576 1577 return 0; 1578 } 1579 1580 static int ksz8_port_vlan_del(struct dsa_switch *ds, int port, 1581 const struct switchdev_obj_port_vlan *vlan) 1582 { 1583 struct ksz_device *dev = ds->priv; 1584 u8 fid, member, valid; 1585 u16 data, pvid; 1586 1587 if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev)) 1588 return -ENOTSUPP; 1589 1590 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &pvid); 1591 pvid = pvid & 0xFFF; 1592 1593 ksz8_r_vlan_table(dev, vlan->vid, &data); 1594 ksz8_from_vlan(dev, data, &fid, &member, &valid); 1595 1596 member &= ~BIT(port); 1597 1598 /* Invalidate the entry if no more member. */ 1599 if (!member) { 1600 fid = 0; 1601 valid = 0; 1602 } 1603 1604 ksz8_to_vlan(dev, fid, member, valid, &data); 1605 ksz8_w_vlan_table(dev, vlan->vid, data); 1606 1607 if (pvid == vlan->vid) 1608 ksz8_port_enable_pvid(dev, port, false); 1609 1610 return 0; 1611 } 1612 1613 static int ksz8_port_mirror_add(struct dsa_switch *ds, int port, 1614 struct dsa_mall_mirror_tc_entry *mirror, 1615 bool ingress, struct netlink_ext_ack *extack) 1616 { 1617 struct ksz_device *dev = ds->priv; 1618 int offset = P_MIRROR_CTRL; 1619 1620 if (ksz_is_ksz8463(dev)) 1621 offset = P1CR2; 1622 if (ingress) { 1623 ksz_port_cfg(dev, port, offset, PORT_MIRROR_RX, true); 1624 dev->mirror_rx |= BIT(port); 1625 } else { 1626 ksz_port_cfg(dev, port, offset, PORT_MIRROR_TX, true); 1627 dev->mirror_tx |= BIT(port); 1628 } 1629 1630 ksz_port_cfg(dev, port, offset, PORT_MIRROR_SNIFFER, false); 1631 1632 /* configure mirror port */ 1633 if (dev->mirror_rx || dev->mirror_tx) 1634 ksz_port_cfg(dev, mirror->to_local_port, offset, 1635 PORT_MIRROR_SNIFFER, true); 1636 1637 return 0; 1638 } 1639 1640 static void ksz8_port_mirror_del(struct dsa_switch *ds, int port, 1641 struct dsa_mall_mirror_tc_entry *mirror) 1642 { 1643 struct ksz_device *dev = ds->priv; 1644 int offset = P_MIRROR_CTRL; 1645 u8 data; 1646 1647 if (ksz_is_ksz8463(dev)) 1648 offset = P1CR2; 1649 if (mirror->ingress) { 1650 ksz_port_cfg(dev, port, offset, PORT_MIRROR_RX, false); 1651 dev->mirror_rx &= ~BIT(port); 1652 } else { 1653 ksz_port_cfg(dev, port, offset, PORT_MIRROR_TX, false); 1654 dev->mirror_tx &= ~BIT(port); 1655 } 1656 1657 ksz_pread8(dev, port, offset, &data); 1658 1659 if (!dev->mirror_rx && !dev->mirror_tx) 1660 ksz_port_cfg(dev, mirror->to_local_port, offset, 1661 PORT_MIRROR_SNIFFER, false); 1662 } 1663 1664 static void ksz8795_cpu_interface_select(struct ksz_device *dev, int port) 1665 { 1666 struct ksz_port *p = &dev->ports[port]; 1667 1668 if (!ksz_is_ksz87xx(dev)) 1669 return; 1670 1671 if (!p->interface && dev->compat_interface) { 1672 dev_warn(dev->dev, 1673 "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. " 1674 "Please update your device tree.\n", 1675 port); 1676 p->interface = dev->compat_interface; 1677 } 1678 } 1679 1680 static void ksz8_port_setup(struct ksz_device *dev, int port, bool cpu_port) 1681 { 1682 const u16 *regs = dev->info->regs; 1683 struct dsa_switch *ds = dev->ds; 1684 const u32 *masks; 1685 int offset; 1686 u8 member; 1687 1688 masks = dev->info->masks; 1689 1690 /* enable broadcast storm limit */ 1691 offset = P_BCAST_STORM_CTRL; 1692 if (ksz_is_ksz8463(dev)) 1693 offset = P1CR1; 1694 ksz_port_cfg(dev, port, offset, PORT_BROADCAST_STORM, true); 1695 1696 ksz8_port_queue_split(dev, port, dev->info->num_tx_queues); 1697 1698 /* replace priority */ 1699 offset = P_802_1P_CTRL; 1700 if (ksz_is_ksz8463(dev)) 1701 offset = P1CR2; 1702 ksz_port_cfg(dev, port, offset, 1703 masks[PORT_802_1P_REMAPPING], false); 1704 1705 if (cpu_port) 1706 member = dsa_user_ports(ds); 1707 else 1708 member = BIT(dsa_upstream_port(ds, port)); 1709 1710 ksz8_cfg_port_member(dev, port, member); 1711 1712 /* Disable all WoL options by default. Otherwise 1713 * ksz_switch_macaddr_get/put logic will not work properly. 1714 * CPU port 4 has no WoL functionality. 1715 */ 1716 if (ksz_is_ksz87xx(dev) && !cpu_port) 1717 ksz8_pme_pwrite8(dev, port, regs[REG_PORT_PME_CTRL], 0); 1718 } 1719 1720 static int ksz8_dsa_port_setup(struct dsa_switch *ds, int port) 1721 { 1722 struct ksz_device *dev = ds->priv; 1723 1724 if (!dsa_is_user_port(ds, port)) 1725 return 0; 1726 1727 ksz8_port_setup(dev, port, false); 1728 return ksz_dcb_init_port(dev, port); 1729 } 1730 1731 static void ksz88x3_config_rmii_clk(struct ksz_device *dev) 1732 { 1733 struct dsa_port *cpu_dp = dsa_to_port(dev->ds, dev->cpu_port); 1734 bool rmii_clk_internal; 1735 1736 if (!ksz_is_ksz88x3(dev)) 1737 return; 1738 1739 rmii_clk_internal = of_property_read_bool(cpu_dp->dn, 1740 "microchip,rmii-clk-internal"); 1741 1742 ksz_cfg(dev, KSZ88X3_REG_FVID_AND_HOST_MODE, 1743 KSZ88X3_PORT3_RMII_CLK_INTERNAL, rmii_clk_internal); 1744 } 1745 1746 static void ksz8_config_cpu_port(struct dsa_switch *ds) 1747 { 1748 struct ksz_device *dev = ds->priv; 1749 struct ksz_port *p; 1750 const u32 *masks; 1751 const u16 *regs; 1752 u8 remote; 1753 u8 fiber_ports = 0; 1754 int i; 1755 1756 masks = dev->info->masks; 1757 regs = dev->info->regs; 1758 1759 ksz_cfg(dev, regs[S_TAIL_TAG_CTRL], masks[SW_TAIL_TAG_ENABLE], true); 1760 1761 ksz8_port_setup(dev, dev->cpu_port, true); 1762 1763 ksz8795_cpu_interface_select(dev, dev->cpu_port); 1764 ksz88x3_config_rmii_clk(dev); 1765 1766 for (i = 0; i < dev->phy_port_cnt; i++) { 1767 ksz_port_stp_state_set(ds, i, BR_STATE_DISABLED); 1768 } 1769 for (i = 0; i < dev->phy_port_cnt; i++) { 1770 p = &dev->ports[i]; 1771 1772 /* For KSZ8795 family. */ 1773 if (ksz_is_ksz87xx(dev)) { 1774 ksz_pread8(dev, i, regs[P_REMOTE_STATUS], &remote); 1775 if (remote & KSZ8_PORT_FIBER_MODE) 1776 p->fiber = 1; 1777 } 1778 if (p->fiber) 1779 ksz_port_cfg(dev, i, regs[P_STP_CTRL], 1780 PORT_FORCE_FLOW_CTRL, true); 1781 else 1782 ksz_port_cfg(dev, i, regs[P_STP_CTRL], 1783 PORT_FORCE_FLOW_CTRL, false); 1784 if (p->fiber) 1785 fiber_ports |= (1 << i); 1786 } 1787 if (ksz_is_ksz8463(dev)) { 1788 /* Setup fiber ports. */ 1789 if (fiber_ports) { 1790 fiber_ports &= 3; 1791 regmap_update_bits(ksz_regmap_16(dev), 1792 KSZ8463_REG_CFG_CTRL, 1793 fiber_ports << PORT_COPPER_MODE_S, 1794 0); 1795 regmap_update_bits(ksz_regmap_16(dev), 1796 KSZ8463_REG_DSP_CTRL_6, 1797 COPPER_RECEIVE_ADJUSTMENT, 0); 1798 } 1799 1800 /* Turn off PTP function as the switch's proprietary way of 1801 * handling timestamp is not supported in current Linux PTP 1802 * stack implementation. 1803 */ 1804 regmap_update_bits(ksz_regmap_16(dev), 1805 KSZ8463_PTP_MSG_CONF1, 1806 PTP_ENABLE, 0); 1807 regmap_update_bits(ksz_regmap_16(dev), 1808 KSZ8463_PTP_CLK_CTRL, 1809 PTP_CLK_ENABLE, 0); 1810 } 1811 } 1812 1813 /** 1814 * ksz8_phy_port_link_up - Configures ports with integrated PHYs 1815 * @dev: The KSZ device instance. 1816 * @port: The port number to configure. 1817 * @duplex: The desired duplex mode. 1818 * @tx_pause: If true, enables transmit pause. 1819 * @rx_pause: If true, enables receive pause. 1820 * 1821 * Description: 1822 * The function configures flow control settings for a given port based on the 1823 * desired settings and current duplex mode. 1824 * 1825 * According to the KSZ8873 datasheet, the PORT_FORCE_FLOW_CTRL bit in the 1826 * Port Control 2 register (0x1A for Port 1, 0x22 for Port 2, 0x32 for Port 3) 1827 * determines how flow control is handled on the port: 1828 * "1 = will always enable full-duplex flow control on the port, regardless 1829 * of AN result. 1830 * 0 = full-duplex flow control is enabled based on AN result." 1831 * 1832 * This means that the flow control behavior depends on the state of this bit: 1833 * - If PORT_FORCE_FLOW_CTRL is set to 1, the switch will ignore AN results and 1834 * force flow control on the port. 1835 * - If PORT_FORCE_FLOW_CTRL is set to 0, the switch will enable or disable 1836 * flow control based on the AN results. 1837 * 1838 * However, there is a potential limitation in this configuration. It is 1839 * currently not possible to force disable flow control on a port if we still 1840 * advertise pause support. While such a configuration is not currently 1841 * supported by Linux, and may not make practical sense, it's important to be 1842 * aware of this limitation when working with the KSZ8873 and similar devices. 1843 */ 1844 static void ksz8_phy_port_link_up(struct ksz_device *dev, int port, int duplex, 1845 bool tx_pause, bool rx_pause) 1846 { 1847 const u16 *regs = dev->info->regs; 1848 u8 sctrl = 0; 1849 1850 /* The KSZ8795 switch differs from the KSZ8873 by supporting 1851 * asymmetric pause control. However, since a single bit is used to 1852 * control both RX and TX pause, we can't enforce asymmetric pause 1853 * control - both TX and RX pause will be either enabled or disabled 1854 * together. 1855 * 1856 * If auto-negotiation is enabled, we usually allow the flow control to 1857 * be determined by the auto-negotiation process based on the 1858 * capabilities of both link partners. However, for KSZ8873, the 1859 * PORT_FORCE_FLOW_CTRL bit may be set by the hardware bootstrap, 1860 * ignoring the auto-negotiation result. Thus, even in auto-negotiation 1861 * mode, we need to ensure that the PORT_FORCE_FLOW_CTRL bit is 1862 * properly cleared. 1863 * 1864 * In the absence of pause auto-negotiation, we will enforce symmetric 1865 * pause control for both variants of switches - KSZ8873 and KSZ8795. 1866 * 1867 * Autoneg Pause Autoneg rx,tx PORT_FORCE_FLOW_CTRL 1868 * 1 1 x 0 1869 * 0 1 x 0 (flow control probably disabled) 1870 * x 0 1 1 (flow control force enabled) 1871 * 1 0 0 0 (flow control still depends on 1872 * aneg result due to hardware) 1873 * 0 0 0 0 (flow control probably disabled) 1874 */ 1875 if (dev->ports[port].manual_flow && tx_pause) 1876 sctrl |= PORT_FORCE_FLOW_CTRL; 1877 1878 ksz_prmw8(dev, port, regs[P_STP_CTRL], PORT_FORCE_FLOW_CTRL, sctrl); 1879 } 1880 1881 /** 1882 * ksz8_cpu_port_link_up - Configures the CPU port of the switch. 1883 * @dev: The KSZ device instance. 1884 * @speed: The desired link speed. 1885 * @duplex: The desired duplex mode. 1886 * @tx_pause: If true, enables transmit pause. 1887 * @rx_pause: If true, enables receive pause. 1888 * 1889 * Description: 1890 * The function configures flow control and speed settings for the CPU 1891 * port of the switch based on the desired settings, current duplex mode, and 1892 * speed. 1893 */ 1894 static void ksz8_cpu_port_link_up(struct ksz_device *dev, int speed, int duplex, 1895 bool tx_pause, bool rx_pause) 1896 { 1897 const u16 *regs = dev->info->regs; 1898 u8 ctrl = 0; 1899 1900 /* SW_FLOW_CTRL, SW_HALF_DUPLEX, and SW_10_MBIT bits are bootstrappable 1901 * at least on KSZ8873. They can have different values depending on your 1902 * board setup. 1903 */ 1904 if (tx_pause || rx_pause) 1905 ctrl |= SW_FLOW_CTRL; 1906 1907 if (duplex == DUPLEX_HALF) 1908 ctrl |= SW_HALF_DUPLEX; 1909 1910 /* This hardware only supports SPEED_10 and SPEED_100. For SPEED_10 1911 * we need to set the SW_10_MBIT bit. Otherwise, we can leave it 0. 1912 */ 1913 if (speed == SPEED_10) 1914 ctrl |= SW_10_MBIT; 1915 1916 ksz_rmw8(dev, regs[S_BROADCAST_CTRL], SW_HALF_DUPLEX | SW_FLOW_CTRL | 1917 SW_10_MBIT, ctrl); 1918 } 1919 1920 static void ksz8_phylink_mac_link_up(struct phylink_config *config, 1921 struct phy_device *phydev, 1922 unsigned int mode, 1923 phy_interface_t interface, 1924 int speed, int duplex, 1925 bool tx_pause, bool rx_pause) 1926 { 1927 struct dsa_port *dp = dsa_phylink_to_port(config); 1928 struct ksz_device *dev = dp->ds->priv; 1929 int port = dp->index; 1930 1931 /* If the port is the CPU port, apply special handling. Only the CPU 1932 * port is configured via global registers. 1933 */ 1934 if (dev->cpu_port == port) 1935 ksz8_cpu_port_link_up(dev, speed, duplex, tx_pause, rx_pause); 1936 else if (dev->info->internal_phy[port]) 1937 ksz8_phy_port_link_up(dev, port, duplex, tx_pause, rx_pause); 1938 } 1939 1940 static int ksz8_handle_global_errata(struct dsa_switch *ds) 1941 { 1942 struct ksz_device *dev = ds->priv; 1943 int ret = 0; 1944 1945 /* KSZ87xx Errata DS80000687C. 1946 * Module 2: Link drops with some EEE link partners. 1947 * An issue with the EEE next page exchange between the 1948 * KSZ879x/KSZ877x/KSZ876x and some EEE link partners may result in 1949 * the link dropping. 1950 */ 1951 if (dev->info->ksz87xx_eee_link_erratum) 1952 ret = ksz8_ind_write8(dev, TABLE_EEE, REG_IND_EEE_GLOB2_HI, 0); 1953 1954 return ret; 1955 } 1956 1957 static int ksz8_enable_stp_addr(struct ksz_device *dev) 1958 { 1959 struct alu_struct alu; 1960 1961 /* Setup STP address for STP operation. */ 1962 memset(&alu, 0, sizeof(alu)); 1963 ether_addr_copy(alu.mac, eth_stp_addr); 1964 alu.is_static = true; 1965 alu.is_override = true; 1966 alu.port_forward = dev->info->cpu_ports; 1967 1968 return ksz8_w_sta_mac_table(dev, 0, &alu); 1969 } 1970 1971 static int ksz8_setup(struct dsa_switch *ds) 1972 { 1973 struct ksz_device *dev = ds->priv; 1974 u16 storm_mask, storm_rate; 1975 struct dsa_port *dp; 1976 struct ksz_port *p; 1977 const u16 *regs; 1978 int i, ret; 1979 1980 regs = dev->info->regs; 1981 1982 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 1983 dev->info->num_vlans, GFP_KERNEL); 1984 if (!dev->vlan_cache) 1985 return -ENOMEM; 1986 1987 ret = ksz8_reset_switch(dev); 1988 if (ret) { 1989 dev_err(ds->dev, "failed to reset switch\n"); 1990 return ret; 1991 } 1992 1993 ret = ksz_parse_drive_strength(dev); 1994 if (ret) 1995 return ret; 1996 1997 /* set broadcast storm protection 10% rate */ 1998 storm_mask = BROADCAST_STORM_RATE; 1999 storm_rate = (BROADCAST_STORM_VALUE * BROADCAST_STORM_PROT_RATE) / 100; 2000 if (ksz_is_ksz8463(dev)) { 2001 storm_mask = swab16(storm_mask); 2002 storm_rate = swab16(storm_rate); 2003 } 2004 regmap_update_bits(ksz_regmap_16(dev), regs[S_BROADCAST_CTRL], 2005 storm_mask, storm_rate); 2006 2007 ksz8_config_cpu_port(ds); 2008 2009 ksz8_enable_stp_addr(dev); 2010 2011 ds->num_tx_queues = dev->info->num_tx_queues; 2012 2013 regmap_update_bits(ksz_regmap_8(dev), regs[S_MULTICAST_CTRL], 2014 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE); 2015 2016 ksz_init_mib_timer(dev); 2017 2018 ds->configure_vlan_while_not_filtering = false; 2019 ds->dscp_prio_mapping_is_global = true; 2020 ds->mtu_enforcement_ingress = true; 2021 2022 /* We rely on software untagging on the CPU port, so that we 2023 * can support both tagged and untagged VLANs 2024 */ 2025 ds->untag_bridge_pvid = true; 2026 2027 /* VLAN filtering is partly controlled by the global VLAN 2028 * Enable flag 2029 */ 2030 ds->vlan_filtering_is_global = true; 2031 2032 /* Enable automatic fast aging when link changed detected. */ 2033 ksz_cfg(dev, S_LINK_AGING_CTRL, SW_LINK_AUTO_AGING, true); 2034 2035 /* Enable aggressive back off algorithm in half duplex mode. */ 2036 ret = ksz_rmw8(dev, REG_SW_CTRL_1, SW_AGGR_BACKOFF, SW_AGGR_BACKOFF); 2037 if (ret) 2038 return ret; 2039 2040 /* 2041 * Make sure unicast VLAN boundary is set as default and 2042 * enable no excessive collision drop. 2043 */ 2044 ret = ksz_rmw8(dev, REG_SW_CTRL_2, 2045 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP, 2046 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP); 2047 if (ret) 2048 return ret; 2049 2050 ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_REPLACE_VID, false); 2051 2052 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false); 2053 2054 if (!ksz_is_ksz88x3(dev) && !ksz_is_ksz8463(dev)) 2055 ksz_cfg(dev, REG_SW_CTRL_19, SW_INS_TAG_ENABLE, true); 2056 2057 for (i = 0; i < (dev->info->num_vlans / 4); i++) 2058 ksz8_r_vlan_entries(dev, i); 2059 2060 /* Make sure PME (WoL) is not enabled. If requested, it will 2061 * be enabled by ksz_wol_pre_shutdown(). Otherwise, some PMICs 2062 * do not like PME events changes before shutdown. PME only 2063 * available on KSZ87xx family. 2064 */ 2065 if (ksz_is_ksz87xx(dev)) { 2066 ret = ksz8_pme_write8(dev, regs[REG_SW_PME_CTRL], 0); 2067 if (!ret) 2068 ret = ksz_rmw8(dev, REG_INT_ENABLE, INT_PME, 0); 2069 if (ret) 2070 return ret; 2071 } 2072 2073 ret = ksz8_handle_global_errata(ds); 2074 if (ret) 2075 return ret; 2076 2077 /* Start with learning disabled on standalone user ports, and enabled 2078 * on the CPU port. In lack of other finer mechanisms, learning on the 2079 * CPU port will avoid flooding bridge local addresses on the network 2080 * in some cases. 2081 */ 2082 p = &dev->ports[dev->cpu_port]; 2083 p->learning = true; 2084 2085 if (dev->irq > 0) { 2086 ret = ksz_girq_setup(dev); 2087 if (ret) 2088 return ret; 2089 2090 dsa_switch_for_each_user_port(dp, dev->ds) { 2091 ret = ksz_pirq_setup(dev, dp->index); 2092 if (ret) 2093 goto port_release; 2094 2095 if (dev->info->ptp_capable) { 2096 ret = ksz_ptp_irq_setup(ds, dp->index); 2097 if (ret) 2098 goto pirq_release; 2099 } 2100 } 2101 } 2102 2103 if (dev->info->ptp_capable) { 2104 ret = ksz_ptp_clock_register(ds); 2105 if (ret) { 2106 dev_err(dev->dev, "Failed to register PTP clock: %d\n", 2107 ret); 2108 goto port_release; 2109 } 2110 } 2111 2112 ret = ksz_mdio_register(dev); 2113 if (ret < 0) { 2114 dev_err(dev->dev, "failed to register the mdio"); 2115 goto out_ptp_clock_unregister; 2116 } 2117 2118 ret = ksz_dcb_init(dev); 2119 if (ret) 2120 goto out_ptp_clock_unregister; 2121 2122 /* start switch */ 2123 regmap_update_bits(ksz_regmap_8(dev), regs[S_START_CTRL], 2124 SW_START, SW_START); 2125 2126 return 0; 2127 2128 out_ptp_clock_unregister: 2129 if (dev->info->ptp_capable) 2130 ksz_ptp_clock_unregister(ds); 2131 port_release: 2132 if (dev->irq > 0) { 2133 dsa_switch_for_each_user_port_continue_reverse(dp, dev->ds) { 2134 if (dev->info->ptp_capable) 2135 ksz_ptp_irq_free(ds, dp->index); 2136 pirq_release: 2137 ksz_irq_free(&dev->ports[dp->index].pirq); 2138 } 2139 ksz_irq_free(&dev->girq); 2140 } 2141 2142 return ret; 2143 } 2144 2145 static void ksz8_phylink_get_caps(struct dsa_switch *ds, int port, 2146 struct phylink_config *config) 2147 { 2148 struct ksz_device *dev = ds->priv; 2149 2150 config->mac_capabilities = MAC_10 | MAC_100; 2151 2152 /* Silicon Errata Sheet (DS80000830A): 2153 * "Port 1 does not respond to received flow control PAUSE frames" 2154 * So, disable Pause support on "Port 1" (port == 0) for all ksz88x3 2155 * switches. 2156 */ 2157 if (!ksz_is_ksz88x3(dev) || port) 2158 config->mac_capabilities |= MAC_SYM_PAUSE; 2159 2160 /* Asym pause is not supported on KSZ8863 and KSZ8873 */ 2161 if (!ksz_is_ksz88x3(dev)) 2162 config->mac_capabilities |= MAC_ASYM_PAUSE; 2163 2164 ksz_phylink_get_caps(ds, port, config); 2165 } 2166 2167 static u32 ksz8_get_port_addr(int port, int offset) 2168 { 2169 return PORT_CTRL_ADDR(port, offset); 2170 } 2171 2172 static u32 ksz8463_get_port_addr(int port, int offset) 2173 { 2174 return offset + 0x18 * port; 2175 } 2176 2177 static u16 ksz8463_get_phy_addr(u16 phy, u16 reg, u16 offset) 2178 { 2179 return offset + reg * 2 + phy * (P2MBCR - P1MBCR); 2180 } 2181 2182 static int ksz8463_r_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 *val) 2183 { 2184 u16 sw_reg = 0; 2185 u16 data = 0; 2186 int ret; 2187 2188 if (phy > 1) 2189 return -ENOSPC; 2190 switch (reg) { 2191 case MII_PHYSID1: 2192 sw_reg = ksz8463_get_phy_addr(phy, 0, PHY1IHR); 2193 break; 2194 case MII_PHYSID2: 2195 sw_reg = ksz8463_get_phy_addr(phy, 0, PHY1ILR); 2196 break; 2197 case MII_BMCR: 2198 case MII_BMSR: 2199 case MII_ADVERTISE: 2200 case MII_LPA: 2201 sw_reg = ksz8463_get_phy_addr(phy, reg, P1MBCR); 2202 break; 2203 case MII_TPISTATUS: 2204 /* This register holds the PHY interrupt status for simulated 2205 * Micrel KSZ PHY. 2206 */ 2207 data = 0x0505; 2208 break; 2209 default: 2210 break; 2211 } 2212 if (sw_reg) { 2213 ret = ksz_read16(dev, sw_reg, &data); 2214 if (ret) 2215 return ret; 2216 } 2217 *val = data; 2218 2219 return 0; 2220 } 2221 2222 static int ksz8463_phy_read16(struct dsa_switch *ds, int addr, int reg) 2223 { 2224 struct ksz_device *dev = ds->priv; 2225 u16 val = 0xffff; 2226 int ret; 2227 2228 ret = ksz8463_r_phy(dev, addr, reg, &val); 2229 if (ret) 2230 return ret; 2231 2232 return val; 2233 } 2234 2235 static int ksz8463_w_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 val) 2236 { 2237 u16 sw_reg = 0; 2238 int ret; 2239 2240 if (phy > 1) 2241 return -ENOSPC; 2242 2243 /* No write to fiber port. */ 2244 if (dev->ports[phy].fiber) 2245 return 0; 2246 switch (reg) { 2247 case MII_BMCR: 2248 case MII_ADVERTISE: 2249 sw_reg = ksz8463_get_phy_addr(phy, reg, P1MBCR); 2250 break; 2251 default: 2252 break; 2253 } 2254 if (sw_reg) { 2255 ret = ksz_write16(dev, sw_reg, val); 2256 if (ret) 2257 return ret; 2258 } 2259 2260 return 0; 2261 } 2262 2263 static int ksz8463_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 2264 { 2265 struct ksz_device *dev = ds->priv; 2266 int ret; 2267 2268 ret = ksz8463_w_phy(dev, addr, reg, val); 2269 if (ret) 2270 return ret; 2271 2272 return 0; 2273 } 2274 2275 static int ksz8_switch_init(struct ksz_device *dev) 2276 { 2277 dev->cpu_port = fls(dev->info->cpu_ports) - 1; 2278 dev->phy_port_cnt = dev->info->port_cnt - 1; 2279 dev->port_mask = (BIT(dev->phy_port_cnt) - 1) | dev->info->cpu_ports; 2280 2281 return 0; 2282 } 2283 2284 static enum dsa_tag_protocol ksz8463_get_tag_protocol(struct dsa_switch *ds, 2285 int port, 2286 enum dsa_tag_protocol mp) 2287 { 2288 return DSA_TAG_PROTO_KSZ9893; 2289 } 2290 2291 static int ksz8463_connect_tag_protocol(struct dsa_switch *ds, 2292 enum dsa_tag_protocol proto) 2293 { 2294 struct ksz_tagger_data *tagger_data; 2295 2296 if (proto != DSA_TAG_PROTO_KSZ9893) 2297 return -EPROTONOSUPPORT; 2298 2299 tagger_data = ksz_tagger_data(ds); 2300 tagger_data->xmit_work_fn = ksz_port_deferred_xmit; 2301 2302 return 0; 2303 } 2304 2305 static enum dsa_tag_protocol ksz87xx_get_tag_protocol(struct dsa_switch *ds, 2306 int port, 2307 enum dsa_tag_protocol mp) 2308 { 2309 return DSA_TAG_PROTO_KSZ8795; 2310 } 2311 2312 static int ksz87xx_connect_tag_protocol(struct dsa_switch *ds, 2313 enum dsa_tag_protocol proto) 2314 { 2315 if (proto != DSA_TAG_PROTO_KSZ8795) 2316 return -EPROTONOSUPPORT; 2317 2318 return 0; 2319 } 2320 2321 static enum dsa_tag_protocol ksz88xx_get_tag_protocol(struct dsa_switch *ds, 2322 int port, 2323 enum dsa_tag_protocol mp) 2324 { 2325 struct ksz_device *dev = ds->priv; 2326 2327 if (ksz_is_8895_family(dev)) /* KSZ8864, KSZ8895 */ 2328 return DSA_TAG_PROTO_KSZ8795; 2329 2330 return DSA_TAG_PROTO_KSZ9893; 2331 } 2332 2333 static int ksz88xx_connect_tag_protocol(struct dsa_switch *ds, 2334 enum dsa_tag_protocol proto) 2335 { 2336 struct ksz_tagger_data *tagger_data; 2337 2338 if (ksz_is_8895_family(ds->priv)) { /* KSZ8864, KSZ8895 */ 2339 if (proto != DSA_TAG_PROTO_KSZ8795) 2340 return -EPROTONOSUPPORT; 2341 2342 return 0; 2343 } 2344 2345 if (proto != DSA_TAG_PROTO_KSZ9893) 2346 return -EPROTONOSUPPORT; 2347 2348 tagger_data = ksz_tagger_data(ds); 2349 tagger_data->xmit_work_fn = ksz_port_deferred_xmit; 2350 2351 return 0; 2352 } 2353 2354 static void ksz88x3_phylink_mac_config(struct phylink_config *config, 2355 unsigned int mode, 2356 const struct phylink_link_state *state) 2357 { 2358 struct dsa_port *dp = dsa_phylink_to_port(config); 2359 struct ksz_device *dev = dp->ds->priv; 2360 2361 dev->ports[dp->index].manual_flow = !(state->pause & MLO_PAUSE_AN); 2362 } 2363 2364 const struct phylink_mac_ops ksz88x3_phylink_mac_ops = { 2365 .mac_config = ksz88x3_phylink_mac_config, 2366 .mac_link_down = ksz_phylink_mac_link_down, 2367 .mac_link_up = ksz8_phylink_mac_link_up, 2368 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi, 2369 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi, 2370 }; 2371 2372 const struct phylink_mac_ops ksz8_phylink_mac_ops = { 2373 .mac_config = ksz_phylink_mac_config, 2374 .mac_link_down = ksz_phylink_mac_link_down, 2375 .mac_link_up = ksz8_phylink_mac_link_up, 2376 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi, 2377 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi, 2378 }; 2379 2380 const struct ksz_dev_ops ksz8463_dev_ops = { 2381 .get_port_addr = ksz8463_get_port_addr, 2382 .cfg_port_member = ksz8_cfg_port_member, 2383 .r_mib_cnt = ksz8_r_mib_cnt, 2384 .r_mib_pkt = ksz8_r_mib_pkt, 2385 .r_mib_stat64 = ksz88xx_r_mib_stats64, 2386 .freeze_mib = ksz8_freeze_mib, 2387 .port_init_cnt = ksz8_port_init_cnt, 2388 .init = ksz8_switch_init, 2389 }; 2390 2391 const struct ksz_dev_ops ksz87xx_dev_ops = { 2392 .get_port_addr = ksz8_get_port_addr, 2393 .cfg_port_member = ksz8_cfg_port_member, 2394 .r_mib_cnt = ksz8_r_mib_cnt, 2395 .r_mib_pkt = ksz8_r_mib_pkt, 2396 .r_mib_stat64 = ksz_r_mib_stats64, 2397 .freeze_mib = ksz8_freeze_mib, 2398 .port_init_cnt = ksz8_port_init_cnt, 2399 .init = ksz8_switch_init, 2400 .pme_write8 = ksz8_pme_write8, 2401 .pme_pread8 = ksz8_pme_pread8, 2402 .pme_pwrite8 = ksz8_pme_pwrite8, 2403 }; 2404 2405 const struct ksz_dev_ops ksz88xx_dev_ops = { 2406 .get_port_addr = ksz8_get_port_addr, 2407 .cfg_port_member = ksz8_cfg_port_member, 2408 .r_mib_cnt = ksz8_r_mib_cnt, 2409 .r_mib_pkt = ksz8_r_mib_pkt, 2410 .r_mib_stat64 = ksz88xx_r_mib_stats64, 2411 .freeze_mib = ksz8_freeze_mib, 2412 .port_init_cnt = ksz8_port_init_cnt, 2413 .init = ksz8_switch_init, 2414 .pme_write8 = ksz8_pme_write8, 2415 .pme_pread8 = ksz8_pme_pread8, 2416 .pme_pwrite8 = ksz8_pme_pwrite8, 2417 }; 2418 2419 const struct dsa_switch_ops ksz8463_switch_ops = { 2420 .get_tag_protocol = ksz8463_get_tag_protocol, 2421 .connect_tag_protocol = ksz8463_connect_tag_protocol, 2422 .get_phy_flags = ksz_get_phy_flags, 2423 .setup = ksz8_setup, 2424 .teardown = ksz_teardown, 2425 .phy_read = ksz8463_phy_read16, 2426 .phy_write = ksz8463_phy_write16, 2427 .phylink_get_caps = ksz8_phylink_get_caps, 2428 .port_setup = ksz8_dsa_port_setup, 2429 .get_strings = ksz_get_strings, 2430 .get_ethtool_stats = ksz_get_ethtool_stats, 2431 .get_sset_count = ksz_sset_count, 2432 .port_bridge_join = ksz_port_bridge_join, 2433 .port_bridge_leave = ksz_port_bridge_leave, 2434 .port_hsr_join = ksz_hsr_join, 2435 .port_hsr_leave = ksz_hsr_leave, 2436 .port_set_mac_address = ksz_port_set_mac_address, 2437 .port_stp_state_set = ksz_port_stp_state_set, 2438 .port_teardown = ksz_port_teardown, 2439 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 2440 .port_bridge_flags = ksz_port_bridge_flags, 2441 .port_fast_age = ksz8_flush_dyn_mac_table, 2442 .port_vlan_filtering = ksz8_port_vlan_filtering, 2443 .port_vlan_add = ksz8_port_vlan_add, 2444 .port_vlan_del = ksz8_port_vlan_del, 2445 .port_fdb_dump = ksz8_fdb_dump, 2446 .port_fdb_add = ksz8_fdb_add, 2447 .port_fdb_del = ksz8_fdb_del, 2448 .port_mdb_add = ksz8_mdb_add, 2449 .port_mdb_del = ksz8_mdb_del, 2450 .port_mirror_add = ksz8_port_mirror_add, 2451 .port_mirror_del = ksz8_port_mirror_del, 2452 .get_stats64 = ksz_get_stats64, 2453 .get_pause_stats = ksz_get_pause_stats, 2454 .port_change_mtu = ksz8_change_mtu, 2455 .port_max_mtu = ksz_max_mtu, 2456 .get_wol = ksz_get_wol, 2457 .set_wol = ksz_set_wol, 2458 .suspend = ksz_suspend, 2459 .resume = ksz_resume, 2460 .get_ts_info = ksz_get_ts_info, 2461 .port_hwtstamp_get = ksz_hwtstamp_get, 2462 .port_hwtstamp_set = ksz_hwtstamp_set, 2463 .port_txtstamp = ksz_port_txtstamp, 2464 .port_rxtstamp = ksz_port_rxtstamp, 2465 .cls_flower_add = ksz_cls_flower_add, 2466 .cls_flower_del = ksz_cls_flower_del, 2467 .port_setup_tc = ksz_setup_tc, 2468 .support_eee = ksz_support_eee, 2469 .set_mac_eee = ksz_set_mac_eee, 2470 .port_get_default_prio = ksz_port_get_default_prio, 2471 .port_set_default_prio = ksz_port_set_default_prio, 2472 .port_get_dscp_prio = ksz_port_get_dscp_prio, 2473 .port_add_dscp_prio = ksz_port_add_dscp_prio, 2474 .port_del_dscp_prio = ksz_port_del_dscp_prio, 2475 .port_get_apptrust = ksz_port_get_apptrust, 2476 .port_set_apptrust = ksz_port_set_apptrust, 2477 }; 2478 2479 const struct dsa_switch_ops ksz87xx_switch_ops = { 2480 .get_tag_protocol = ksz87xx_get_tag_protocol, 2481 .connect_tag_protocol = ksz87xx_connect_tag_protocol, 2482 .get_phy_flags = ksz_get_phy_flags, 2483 .setup = ksz8_setup, 2484 .teardown = ksz_teardown, 2485 .phy_read = ksz8_phy_read16, 2486 .phy_write = ksz8_phy_write16, 2487 .phylink_get_caps = ksz8_phylink_get_caps, 2488 .port_setup = ksz8_dsa_port_setup, 2489 .get_strings = ksz_get_strings, 2490 .get_ethtool_stats = ksz_get_ethtool_stats, 2491 .get_sset_count = ksz_sset_count, 2492 .port_bridge_join = ksz_port_bridge_join, 2493 .port_bridge_leave = ksz_port_bridge_leave, 2494 .port_hsr_join = ksz_hsr_join, 2495 .port_hsr_leave = ksz_hsr_leave, 2496 .port_set_mac_address = ksz_port_set_mac_address, 2497 .port_stp_state_set = ksz_port_stp_state_set, 2498 .port_teardown = ksz_port_teardown, 2499 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 2500 .port_bridge_flags = ksz_port_bridge_flags, 2501 .port_fast_age = ksz8_flush_dyn_mac_table, 2502 .port_vlan_filtering = ksz8_port_vlan_filtering, 2503 .port_vlan_add = ksz8_port_vlan_add, 2504 .port_vlan_del = ksz8_port_vlan_del, 2505 .port_fdb_dump = ksz8_fdb_dump, 2506 .port_fdb_add = ksz8_fdb_add, 2507 .port_fdb_del = ksz8_fdb_del, 2508 .port_mdb_add = ksz8_mdb_add, 2509 .port_mdb_del = ksz8_mdb_del, 2510 .port_mirror_add = ksz8_port_mirror_add, 2511 .port_mirror_del = ksz8_port_mirror_del, 2512 .get_stats64 = ksz_get_stats64, 2513 .get_pause_stats = ksz_get_pause_stats, 2514 .port_change_mtu = ksz8_change_mtu, 2515 .port_max_mtu = ksz_max_mtu, 2516 .get_wol = ksz_get_wol, 2517 .set_wol = ksz_set_wol, 2518 .suspend = ksz_suspend, 2519 .resume = ksz_resume, 2520 .get_ts_info = ksz_get_ts_info, 2521 .port_hwtstamp_get = ksz_hwtstamp_get, 2522 .port_hwtstamp_set = ksz_hwtstamp_set, 2523 .port_txtstamp = ksz_port_txtstamp, 2524 .port_rxtstamp = ksz_port_rxtstamp, 2525 .cls_flower_add = ksz_cls_flower_add, 2526 .cls_flower_del = ksz_cls_flower_del, 2527 .port_setup_tc = ksz_setup_tc, 2528 .support_eee = ksz_support_eee, 2529 .set_mac_eee = ksz_set_mac_eee, 2530 .port_get_default_prio = ksz_port_get_default_prio, 2531 .port_set_default_prio = ksz_port_set_default_prio, 2532 .port_get_dscp_prio = ksz_port_get_dscp_prio, 2533 .port_add_dscp_prio = ksz_port_add_dscp_prio, 2534 .port_del_dscp_prio = ksz_port_del_dscp_prio, 2535 .port_get_apptrust = ksz_port_get_apptrust, 2536 .port_set_apptrust = ksz_port_set_apptrust, 2537 }; 2538 2539 const struct dsa_switch_ops ksz88xx_switch_ops = { 2540 .get_tag_protocol = ksz88xx_get_tag_protocol, 2541 .connect_tag_protocol = ksz88xx_connect_tag_protocol, 2542 .get_phy_flags = ksz_get_phy_flags, 2543 .setup = ksz8_setup, 2544 .teardown = ksz_teardown, 2545 .phy_read = ksz8_phy_read16, 2546 .phy_write = ksz8_phy_write16, 2547 .phylink_get_caps = ksz8_phylink_get_caps, 2548 .port_setup = ksz8_dsa_port_setup, 2549 .get_strings = ksz_get_strings, 2550 .get_ethtool_stats = ksz_get_ethtool_stats, 2551 .get_sset_count = ksz_sset_count, 2552 .port_bridge_join = ksz_port_bridge_join, 2553 .port_bridge_leave = ksz_port_bridge_leave, 2554 .port_hsr_join = ksz_hsr_join, 2555 .port_hsr_leave = ksz_hsr_leave, 2556 .port_set_mac_address = ksz_port_set_mac_address, 2557 .port_stp_state_set = ksz_port_stp_state_set, 2558 .port_teardown = ksz_port_teardown, 2559 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 2560 .port_bridge_flags = ksz_port_bridge_flags, 2561 .port_fast_age = ksz8_flush_dyn_mac_table, 2562 .port_vlan_filtering = ksz8_port_vlan_filtering, 2563 .port_vlan_add = ksz8_port_vlan_add, 2564 .port_vlan_del = ksz8_port_vlan_del, 2565 .port_fdb_dump = ksz8_fdb_dump, 2566 .port_fdb_add = ksz8_fdb_add, 2567 .port_fdb_del = ksz8_fdb_del, 2568 .port_mdb_add = ksz8_mdb_add, 2569 .port_mdb_del = ksz8_mdb_del, 2570 .port_mirror_add = ksz8_port_mirror_add, 2571 .port_mirror_del = ksz8_port_mirror_del, 2572 .get_stats64 = ksz_get_stats64, 2573 .get_pause_stats = ksz_get_pause_stats, 2574 .port_change_mtu = ksz8_change_mtu, 2575 .port_max_mtu = ksz_max_mtu, 2576 .get_wol = ksz_get_wol, 2577 .set_wol = ksz_set_wol, 2578 .suspend = ksz_suspend, 2579 .resume = ksz_resume, 2580 .get_ts_info = ksz_get_ts_info, 2581 .port_hwtstamp_get = ksz_hwtstamp_get, 2582 .port_hwtstamp_set = ksz_hwtstamp_set, 2583 .port_txtstamp = ksz_port_txtstamp, 2584 .port_rxtstamp = ksz_port_rxtstamp, 2585 .cls_flower_add = ksz_cls_flower_add, 2586 .cls_flower_del = ksz_cls_flower_del, 2587 .port_setup_tc = ksz_setup_tc, 2588 .support_eee = ksz_support_eee, 2589 .set_mac_eee = ksz_set_mac_eee, 2590 .port_get_default_prio = ksz_port_get_default_prio, 2591 .port_set_default_prio = ksz_port_set_default_prio, 2592 .port_get_dscp_prio = ksz_port_get_dscp_prio, 2593 .port_add_dscp_prio = ksz_port_add_dscp_prio, 2594 .port_del_dscp_prio = ksz_port_del_dscp_prio, 2595 .port_get_apptrust = ksz_port_get_apptrust, 2596 .port_set_apptrust = ksz_port_set_apptrust, 2597 }; 2598 2599 MODULE_AUTHOR("Tristram Ha <Tristram.Ha@microchip.com>"); 2600 MODULE_DESCRIPTION("Microchip KSZ8795 Series Switch DSA Driver"); 2601 MODULE_LICENSE("GPL"); 2602