1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip KSZ8XXX series switch driver 4 * 5 * It supports the following switches: 6 * - KSZ8463 7 * - KSZ8863, KSZ8873 aka KSZ88X3 8 * - KSZ8895, KSZ8864 aka KSZ8895 family 9 * - KSZ8794, KSZ8795, KSZ8765 aka KSZ87XX 10 * Note that it does NOT support: 11 * - KSZ8563, KSZ8567 - see KSZ9477 driver 12 * 13 * Copyright (C) 2017 Microchip Technology Inc. 14 * Tristram Ha <Tristram.Ha@microchip.com> 15 */ 16 17 #include <linux/bitfield.h> 18 #include <linux/delay.h> 19 #include <linux/export.h> 20 #include <linux/gpio.h> 21 #include <linux/if_vlan.h> 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/platform_data/microchip-ksz.h> 25 #include <linux/phy.h> 26 #include <linux/etherdevice.h> 27 #include <linux/if_bridge.h> 28 #include <linux/micrel_phy.h> 29 #include <net/dsa.h> 30 #include <net/switchdev.h> 31 #include <linux/phylink.h> 32 33 #include "ksz_common.h" 34 #include "ksz8_reg.h" 35 #include "ksz8.h" 36 37 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) 38 { 39 regmap_update_bits(ksz_regmap_8(dev), addr, bits, set ? bits : 0); 40 } 41 42 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits, 43 bool set) 44 { 45 regmap_update_bits(ksz_regmap_8(dev), 46 dev->dev_ops->get_port_addr(port, offset), 47 bits, set ? bits : 0); 48 } 49 50 /** 51 * ksz8_ind_write8 - EEE/ACL/PME indirect register write 52 * @dev: The device structure. 53 * @table: Function & table select, register 110. 54 * @addr: Indirect access control, register 111. 55 * @data: The data to be written. 56 * 57 * This function performs an indirect register write for EEE, ACL or 58 * PME switch functionalities. Both 8-bit registers 110 and 111 are 59 * written at once with ksz_write16, using the serial multiple write 60 * functionality. 61 * 62 * Return: 0 on success, or an error code on failure. 63 */ 64 static int ksz8_ind_write8(struct ksz_device *dev, u8 table, u16 addr, u8 data) 65 { 66 const u16 *regs; 67 u16 ctrl_addr; 68 int ret = 0; 69 70 regs = dev->info->regs; 71 72 mutex_lock(&dev->alu_mutex); 73 74 ctrl_addr = IND_ACC_TABLE(table) | addr; 75 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 76 if (!ret) 77 ret = ksz_write8(dev, regs[REG_IND_BYTE], data); 78 79 mutex_unlock(&dev->alu_mutex); 80 81 return ret; 82 } 83 84 /** 85 * ksz8_ind_read8 - EEE/ACL/PME indirect register read 86 * @dev: The device structure. 87 * @table: Function & table select, register 110. 88 * @addr: Indirect access control, register 111. 89 * @val: The value read. 90 * 91 * This function performs an indirect register read for EEE, ACL or 92 * PME switch functionalities. Both 8-bit registers 110 and 111 are 93 * written at once with ksz_write16, using the serial multiple write 94 * functionality. 95 * 96 * Return: 0 on success, or an error code on failure. 97 */ 98 static int ksz8_ind_read8(struct ksz_device *dev, u8 table, u16 addr, u8 *val) 99 { 100 const u16 *regs; 101 u16 ctrl_addr; 102 int ret = 0; 103 104 regs = dev->info->regs; 105 106 mutex_lock(&dev->alu_mutex); 107 108 ctrl_addr = IND_ACC_TABLE(table | TABLE_READ) | addr; 109 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 110 if (!ret) 111 ret = ksz_read8(dev, regs[REG_IND_BYTE], val); 112 113 mutex_unlock(&dev->alu_mutex); 114 115 return ret; 116 } 117 118 int ksz8_pme_write8(struct ksz_device *dev, u32 reg, u8 value) 119 { 120 return ksz8_ind_write8(dev, (u8)(reg >> 8), (u8)(reg), value); 121 } 122 123 int ksz8_pme_pread8(struct ksz_device *dev, int port, int offset, u8 *data) 124 { 125 u8 table = (u8)(offset >> 8 | (port + 1)); 126 127 return ksz8_ind_read8(dev, table, (u8)(offset), data); 128 } 129 130 int ksz8_pme_pwrite8(struct ksz_device *dev, int port, int offset, u8 data) 131 { 132 u8 table = (u8)(offset >> 8 | (port + 1)); 133 134 return ksz8_ind_write8(dev, table, (u8)(offset), data); 135 } 136 137 int ksz8_reset_switch(struct ksz_device *dev) 138 { 139 if (ksz_is_ksz88x3(dev)) { 140 /* reset switch */ 141 ksz_cfg(dev, KSZ8863_REG_SW_RESET, 142 KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, true); 143 ksz_cfg(dev, KSZ8863_REG_SW_RESET, 144 KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, false); 145 } else if (ksz_is_ksz8463(dev)) { 146 ksz_cfg(dev, KSZ8463_REG_SW_RESET, 147 KSZ8463_GLOBAL_SOFTWARE_RESET, true); 148 ksz_cfg(dev, KSZ8463_REG_SW_RESET, 149 KSZ8463_GLOBAL_SOFTWARE_RESET, false); 150 } else { 151 /* reset switch */ 152 ksz_write8(dev, REG_POWER_MANAGEMENT_1, 153 SW_SOFTWARE_POWER_DOWN << SW_POWER_MANAGEMENT_MODE_S); 154 ksz_write8(dev, REG_POWER_MANAGEMENT_1, 0); 155 } 156 157 return 0; 158 } 159 160 static int ksz8863_change_mtu(struct ksz_device *dev, int frame_size) 161 { 162 u8 ctrl2 = 0; 163 164 if (frame_size <= KSZ8_LEGAL_PACKET_SIZE) 165 ctrl2 |= KSZ8863_LEGAL_PACKET_ENABLE; 166 else if (frame_size > KSZ8863_NORMAL_PACKET_SIZE) 167 ctrl2 |= KSZ8863_HUGE_PACKET_ENABLE; 168 169 return ksz_rmw8(dev, REG_SW_CTRL_2, KSZ8863_LEGAL_PACKET_ENABLE | 170 KSZ8863_HUGE_PACKET_ENABLE, ctrl2); 171 } 172 173 static int ksz8795_change_mtu(struct ksz_device *dev, int frame_size) 174 { 175 u8 ctrl1 = 0, ctrl2 = 0; 176 int ret; 177 178 if (frame_size > KSZ8_LEGAL_PACKET_SIZE) 179 ctrl2 |= SW_LEGAL_PACKET_DISABLE; 180 if (frame_size > KSZ8863_NORMAL_PACKET_SIZE) 181 ctrl1 |= SW_HUGE_PACKET; 182 183 ret = ksz_rmw8(dev, REG_SW_CTRL_1, SW_HUGE_PACKET, ctrl1); 184 if (ret) 185 return ret; 186 187 return ksz_rmw8(dev, REG_SW_CTRL_2, SW_LEGAL_PACKET_DISABLE, ctrl2); 188 } 189 190 int ksz8_change_mtu(struct ksz_device *dev, int port, int mtu) 191 { 192 u16 frame_size; 193 194 if (!dsa_is_cpu_port(dev->ds, port)) 195 return 0; 196 197 frame_size = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 198 199 switch (dev->chip_id) { 200 case KSZ8795_CHIP_ID: 201 case KSZ8794_CHIP_ID: 202 case KSZ8765_CHIP_ID: 203 return ksz8795_change_mtu(dev, frame_size); 204 case KSZ8463_CHIP_ID: 205 case KSZ88X3_CHIP_ID: 206 case KSZ8864_CHIP_ID: 207 case KSZ8895_CHIP_ID: 208 return ksz8863_change_mtu(dev, frame_size); 209 } 210 211 return -EOPNOTSUPP; 212 } 213 214 static int ksz8_port_queue_split(struct ksz_device *dev, int port, int queues) 215 { 216 u8 mask_4q, mask_2q; 217 u8 reg_4q, reg_2q; 218 u8 data_4q = 0; 219 u8 data_2q = 0; 220 int ret; 221 222 if (ksz_is_ksz88x3(dev)) { 223 mask_4q = KSZ8873_PORT_4QUEUE_SPLIT_EN; 224 mask_2q = KSZ8873_PORT_2QUEUE_SPLIT_EN; 225 reg_4q = REG_PORT_CTRL_0; 226 reg_2q = REG_PORT_CTRL_2; 227 228 /* KSZ8795 family switches have Weighted Fair Queueing (WFQ) 229 * enabled by default. Enable it for KSZ8873 family switches 230 * too. Default value for KSZ8873 family is strict priority, 231 * which should be enabled by using TC_SETUP_QDISC_ETS, not 232 * by default. 233 */ 234 ret = ksz_rmw8(dev, REG_SW_CTRL_3, WEIGHTED_FAIR_QUEUE_ENABLE, 235 WEIGHTED_FAIR_QUEUE_ENABLE); 236 if (ret) 237 return ret; 238 } else if (ksz_is_ksz8463(dev)) { 239 mask_4q = KSZ8873_PORT_4QUEUE_SPLIT_EN; 240 mask_2q = KSZ8873_PORT_2QUEUE_SPLIT_EN; 241 reg_4q = P1CR1; 242 reg_2q = P1CR1 + 1; 243 } else { 244 mask_4q = KSZ8795_PORT_4QUEUE_SPLIT_EN; 245 mask_2q = KSZ8795_PORT_2QUEUE_SPLIT_EN; 246 reg_4q = REG_PORT_CTRL_13; 247 reg_2q = REG_PORT_CTRL_0; 248 249 /* TODO: this is legacy from initial KSZ8795 driver, should be 250 * moved to appropriate place in the future. 251 */ 252 ret = ksz_rmw8(dev, REG_SW_CTRL_19, 253 SW_OUT_RATE_LIMIT_QUEUE_BASED, 254 SW_OUT_RATE_LIMIT_QUEUE_BASED); 255 if (ret) 256 return ret; 257 } 258 259 if (queues == 4) 260 data_4q = mask_4q; 261 else if (queues == 2) 262 data_2q = mask_2q; 263 264 ret = ksz_prmw8(dev, port, reg_4q, mask_4q, data_4q); 265 if (ret) 266 return ret; 267 268 return ksz_prmw8(dev, port, reg_2q, mask_2q, data_2q); 269 } 270 271 int ksz8_all_queues_split(struct ksz_device *dev, int queues) 272 { 273 struct dsa_switch *ds = dev->ds; 274 const struct dsa_port *dp; 275 276 dsa_switch_for_each_port(dp, ds) { 277 int ret = ksz8_port_queue_split(dev, dp->index, queues); 278 279 if (ret) 280 return ret; 281 } 282 283 return 0; 284 } 285 286 void ksz8_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, u64 *cnt) 287 { 288 const u32 *masks; 289 const u16 *regs; 290 u16 ctrl_addr; 291 u32 data; 292 u8 check; 293 int loop; 294 295 masks = dev->info->masks; 296 regs = dev->info->regs; 297 298 ctrl_addr = addr + dev->info->reg_mib_cnt * port; 299 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ); 300 301 mutex_lock(&dev->alu_mutex); 302 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 303 304 /* It is almost guaranteed to always read the valid bit because of 305 * slow SPI speed. 306 */ 307 for (loop = 2; loop > 0; loop--) { 308 ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check); 309 310 if (check & masks[MIB_COUNTER_VALID]) { 311 ksz_read32(dev, regs[REG_IND_DATA_LO], &data); 312 if (check & masks[MIB_COUNTER_OVERFLOW]) 313 *cnt += MIB_COUNTER_VALUE + 1; 314 *cnt += data & MIB_COUNTER_VALUE; 315 break; 316 } 317 } 318 mutex_unlock(&dev->alu_mutex); 319 } 320 321 static void ksz8795_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 322 u64 *dropped, u64 *cnt) 323 { 324 const u32 *masks; 325 const u16 *regs; 326 u16 ctrl_addr; 327 u32 data; 328 u8 check; 329 int loop; 330 331 masks = dev->info->masks; 332 regs = dev->info->regs; 333 334 addr -= dev->info->reg_mib_cnt; 335 ctrl_addr = (KSZ8795_MIB_TOTAL_RX_1 - KSZ8795_MIB_TOTAL_RX_0) * port; 336 ctrl_addr += addr + KSZ8795_MIB_TOTAL_RX_0; 337 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ); 338 339 mutex_lock(&dev->alu_mutex); 340 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 341 342 /* It is almost guaranteed to always read the valid bit because of 343 * slow SPI speed. 344 */ 345 for (loop = 2; loop > 0; loop--) { 346 ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check); 347 348 if (check & masks[MIB_COUNTER_VALID]) { 349 ksz_read32(dev, regs[REG_IND_DATA_LO], &data); 350 if (addr < 2) { 351 u64 total; 352 353 total = check & MIB_TOTAL_BYTES_H; 354 total <<= 32; 355 *cnt += total; 356 *cnt += data; 357 if (check & masks[MIB_COUNTER_OVERFLOW]) { 358 total = MIB_TOTAL_BYTES_H + 1; 359 total <<= 32; 360 *cnt += total; 361 } 362 } else { 363 if (check & masks[MIB_COUNTER_OVERFLOW]) 364 *cnt += MIB_PACKET_DROPPED + 1; 365 *cnt += data & MIB_PACKET_DROPPED; 366 } 367 break; 368 } 369 } 370 mutex_unlock(&dev->alu_mutex); 371 } 372 373 static void ksz8863_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 374 u64 *dropped, u64 *cnt) 375 { 376 u32 *last = (u32 *)dropped; 377 const u16 *regs; 378 u16 ctrl_addr; 379 u32 data; 380 u32 cur; 381 382 regs = dev->info->regs; 383 384 addr -= dev->info->reg_mib_cnt; 385 ctrl_addr = addr ? KSZ8863_MIB_PACKET_DROPPED_TX_0 : 386 KSZ8863_MIB_PACKET_DROPPED_RX_0; 387 if (ksz_is_8895_family(dev) && 388 ctrl_addr == KSZ8863_MIB_PACKET_DROPPED_RX_0) 389 ctrl_addr = KSZ8895_MIB_PACKET_DROPPED_RX_0; 390 ctrl_addr += port; 391 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ); 392 393 mutex_lock(&dev->alu_mutex); 394 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 395 ksz_read32(dev, regs[REG_IND_DATA_LO], &data); 396 mutex_unlock(&dev->alu_mutex); 397 398 data &= MIB_PACKET_DROPPED; 399 cur = last[addr]; 400 if (data != cur) { 401 last[addr] = data; 402 if (data < cur) 403 data += MIB_PACKET_DROPPED + 1; 404 data -= cur; 405 *cnt += data; 406 } 407 } 408 409 void ksz8_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 410 u64 *dropped, u64 *cnt) 411 { 412 if (is_ksz88xx(dev)) 413 ksz8863_r_mib_pkt(dev, port, addr, dropped, cnt); 414 else 415 ksz8795_r_mib_pkt(dev, port, addr, dropped, cnt); 416 } 417 418 void ksz8_freeze_mib(struct ksz_device *dev, int port, bool freeze) 419 { 420 if (is_ksz88xx(dev)) 421 return; 422 423 /* enable the port for flush/freeze function */ 424 if (freeze) 425 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true); 426 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FREEZE, freeze); 427 428 /* disable the port after freeze is done */ 429 if (!freeze) 430 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false); 431 } 432 433 void ksz8_port_init_cnt(struct ksz_device *dev, int port) 434 { 435 struct ksz_port_mib *mib = &dev->ports[port].mib; 436 u64 *dropped; 437 438 /* For KSZ8795 family. */ 439 if (ksz_is_ksz87xx(dev)) { 440 /* flush all enabled port MIB counters */ 441 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true); 442 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FLUSH, true); 443 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false); 444 } 445 446 mib->cnt_ptr = 0; 447 448 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 449 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 450 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 451 &mib->counters[mib->cnt_ptr]); 452 ++mib->cnt_ptr; 453 } 454 455 /* last one in storage */ 456 dropped = &mib->counters[dev->info->mib_cnt]; 457 458 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 459 while (mib->cnt_ptr < dev->info->mib_cnt) { 460 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 461 dropped, &mib->counters[mib->cnt_ptr]); 462 ++mib->cnt_ptr; 463 } 464 } 465 466 static int ksz8_r_table(struct ksz_device *dev, int table, u16 addr, u64 *data) 467 { 468 const u16 *regs; 469 u16 ctrl_addr; 470 int ret; 471 472 regs = dev->info->regs; 473 474 ctrl_addr = IND_ACC_TABLE(table | TABLE_READ) | addr; 475 476 mutex_lock(&dev->alu_mutex); 477 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 478 if (ret) 479 goto unlock_alu; 480 481 ret = ksz_read64(dev, regs[REG_IND_DATA_HI], data); 482 unlock_alu: 483 mutex_unlock(&dev->alu_mutex); 484 485 return ret; 486 } 487 488 static int ksz8_w_table(struct ksz_device *dev, int table, u16 addr, u64 data) 489 { 490 const u16 *regs; 491 u16 ctrl_addr; 492 int ret; 493 494 regs = dev->info->regs; 495 496 ctrl_addr = IND_ACC_TABLE(table) | addr; 497 498 mutex_lock(&dev->alu_mutex); 499 ret = ksz_write64(dev, regs[REG_IND_DATA_HI], data); 500 if (ret) 501 goto unlock_alu; 502 503 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 504 unlock_alu: 505 mutex_unlock(&dev->alu_mutex); 506 507 return ret; 508 } 509 510 static int ksz8_valid_dyn_entry(struct ksz_device *dev, u8 *data) 511 { 512 int timeout = 100; 513 const u32 *masks; 514 const u16 *regs; 515 int ret; 516 517 masks = dev->info->masks; 518 regs = dev->info->regs; 519 520 do { 521 ret = ksz_read8(dev, regs[REG_IND_DATA_CHECK], data); 522 if (ret) 523 return ret; 524 525 timeout--; 526 } while ((*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) && timeout); 527 528 /* Entry is not ready for accessing. */ 529 if (*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) 530 return -ETIMEDOUT; 531 532 /* Entry is ready for accessing. */ 533 return ksz_read8(dev, regs[REG_IND_DATA_8], data); 534 } 535 536 static int ksz8_r_dyn_mac_table(struct ksz_device *dev, u16 addr, u8 *mac_addr, 537 u8 *fid, u8 *src_port, u16 *entries) 538 { 539 u32 data_hi, data_lo; 540 const u8 *shifts; 541 const u32 *masks; 542 const u16 *regs; 543 u16 ctrl_addr; 544 u64 buf = 0; 545 u8 data; 546 int cnt; 547 int ret; 548 549 shifts = dev->info->shifts; 550 masks = dev->info->masks; 551 regs = dev->info->regs; 552 553 ctrl_addr = IND_ACC_TABLE(TABLE_DYNAMIC_MAC | TABLE_READ) | addr; 554 555 mutex_lock(&dev->alu_mutex); 556 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 557 if (ret) 558 goto unlock_alu; 559 560 ret = ksz8_valid_dyn_entry(dev, &data); 561 if (ret) 562 goto unlock_alu; 563 564 if (data & masks[DYNAMIC_MAC_TABLE_MAC_EMPTY]) { 565 *entries = 0; 566 goto unlock_alu; 567 } 568 569 ret = ksz_read64(dev, regs[REG_IND_DATA_HI], &buf); 570 if (ret) 571 goto unlock_alu; 572 573 data_hi = (u32)(buf >> 32); 574 data_lo = (u32)buf; 575 576 /* Check out how many valid entry in the table. */ 577 cnt = data & masks[DYNAMIC_MAC_TABLE_ENTRIES_H]; 578 cnt <<= shifts[DYNAMIC_MAC_ENTRIES_H]; 579 cnt |= (data_hi & masks[DYNAMIC_MAC_TABLE_ENTRIES]) >> 580 shifts[DYNAMIC_MAC_ENTRIES]; 581 *entries = cnt + 1; 582 583 *fid = (data_hi & masks[DYNAMIC_MAC_TABLE_FID]) >> 584 shifts[DYNAMIC_MAC_FID]; 585 *src_port = (data_hi & masks[DYNAMIC_MAC_TABLE_SRC_PORT]) >> 586 shifts[DYNAMIC_MAC_SRC_PORT]; 587 588 mac_addr[5] = (u8)data_lo; 589 mac_addr[4] = (u8)(data_lo >> 8); 590 mac_addr[3] = (u8)(data_lo >> 16); 591 mac_addr[2] = (u8)(data_lo >> 24); 592 593 mac_addr[1] = (u8)data_hi; 594 mac_addr[0] = (u8)(data_hi >> 8); 595 596 unlock_alu: 597 mutex_unlock(&dev->alu_mutex); 598 599 return ret; 600 } 601 602 static int ksz8_r_sta_mac_table(struct ksz_device *dev, u16 addr, 603 struct alu_struct *alu, bool *valid) 604 { 605 u32 data_hi, data_lo; 606 const u8 *shifts; 607 const u32 *masks; 608 u64 data; 609 int ret; 610 611 shifts = dev->info->shifts; 612 masks = dev->info->masks; 613 614 ret = ksz8_r_table(dev, TABLE_STATIC_MAC, addr, &data); 615 if (ret) 616 return ret; 617 618 data_hi = data >> 32; 619 data_lo = (u32)data; 620 621 if (!(data_hi & (masks[STATIC_MAC_TABLE_VALID] | 622 masks[STATIC_MAC_TABLE_OVERRIDE]))) { 623 *valid = false; 624 return 0; 625 } 626 627 alu->mac[5] = (u8)data_lo; 628 alu->mac[4] = (u8)(data_lo >> 8); 629 alu->mac[3] = (u8)(data_lo >> 16); 630 alu->mac[2] = (u8)(data_lo >> 24); 631 alu->mac[1] = (u8)data_hi; 632 alu->mac[0] = (u8)(data_hi >> 8); 633 alu->port_forward = 634 (data_hi & masks[STATIC_MAC_TABLE_FWD_PORTS]) >> 635 shifts[STATIC_MAC_FWD_PORTS]; 636 alu->is_override = (data_hi & masks[STATIC_MAC_TABLE_OVERRIDE]) ? 1 : 0; 637 638 /* KSZ8795/KSZ8895 family switches have STATIC_MAC_TABLE_USE_FID and 639 * STATIC_MAC_TABLE_FID definitions off by 1 when doing read on the 640 * static MAC table compared to doing write. 641 */ 642 if (ksz_is_ksz87xx(dev) || ksz_is_8895_family(dev)) 643 data_hi >>= 1; 644 alu->is_static = true; 645 alu->is_use_fid = (data_hi & masks[STATIC_MAC_TABLE_USE_FID]) ? 1 : 0; 646 alu->fid = (data_hi & masks[STATIC_MAC_TABLE_FID]) >> 647 shifts[STATIC_MAC_FID]; 648 649 *valid = true; 650 651 return 0; 652 } 653 654 static int ksz8_w_sta_mac_table(struct ksz_device *dev, u16 addr, 655 struct alu_struct *alu) 656 { 657 u32 data_hi, data_lo; 658 const u8 *shifts; 659 const u32 *masks; 660 u64 data; 661 662 shifts = dev->info->shifts; 663 masks = dev->info->masks; 664 665 data_lo = ((u32)alu->mac[2] << 24) | 666 ((u32)alu->mac[3] << 16) | 667 ((u32)alu->mac[4] << 8) | alu->mac[5]; 668 data_hi = ((u32)alu->mac[0] << 8) | alu->mac[1]; 669 data_hi |= (u32)alu->port_forward << shifts[STATIC_MAC_FWD_PORTS]; 670 671 if (alu->is_override) 672 data_hi |= masks[STATIC_MAC_TABLE_OVERRIDE]; 673 if (alu->is_use_fid) { 674 data_hi |= masks[STATIC_MAC_TABLE_USE_FID]; 675 data_hi |= (u32)alu->fid << shifts[STATIC_MAC_FID]; 676 } 677 if (alu->is_static) 678 data_hi |= masks[STATIC_MAC_TABLE_VALID]; 679 else 680 data_hi &= ~masks[STATIC_MAC_TABLE_OVERRIDE]; 681 682 data = (u64)data_hi << 32 | data_lo; 683 684 return ksz8_w_table(dev, TABLE_STATIC_MAC, addr, data); 685 } 686 687 static void ksz8_from_vlan(struct ksz_device *dev, u32 vlan, u8 *fid, 688 u8 *member, u8 *valid) 689 { 690 const u8 *shifts; 691 const u32 *masks; 692 693 shifts = dev->info->shifts; 694 masks = dev->info->masks; 695 696 *fid = vlan & masks[VLAN_TABLE_FID]; 697 *member = (vlan & masks[VLAN_TABLE_MEMBERSHIP]) >> 698 shifts[VLAN_TABLE_MEMBERSHIP_S]; 699 *valid = !!(vlan & masks[VLAN_TABLE_VALID]); 700 } 701 702 static void ksz8_to_vlan(struct ksz_device *dev, u8 fid, u8 member, u8 valid, 703 u16 *vlan) 704 { 705 const u8 *shifts; 706 const u32 *masks; 707 708 shifts = dev->info->shifts; 709 masks = dev->info->masks; 710 711 *vlan = fid; 712 *vlan |= (u16)member << shifts[VLAN_TABLE_MEMBERSHIP_S]; 713 if (valid) 714 *vlan |= masks[VLAN_TABLE_VALID]; 715 } 716 717 static void ksz8_r_vlan_entries(struct ksz_device *dev, u16 addr) 718 { 719 const u8 *shifts; 720 u64 data; 721 int i; 722 723 shifts = dev->info->shifts; 724 725 ksz8_r_table(dev, TABLE_VLAN, addr, &data); 726 addr *= 4; 727 for (i = 0; i < 4; i++) { 728 dev->vlan_cache[addr + i].table[0] = (u16)data; 729 data >>= shifts[VLAN_TABLE]; 730 } 731 } 732 733 static void ksz8_r_vlan_table(struct ksz_device *dev, u16 vid, u16 *vlan) 734 { 735 int index; 736 u16 *data; 737 u16 addr; 738 u64 buf; 739 740 data = (u16 *)&buf; 741 addr = vid / 4; 742 index = vid & 3; 743 ksz8_r_table(dev, TABLE_VLAN, addr, &buf); 744 *vlan = data[index]; 745 } 746 747 static void ksz8_w_vlan_table(struct ksz_device *dev, u16 vid, u16 vlan) 748 { 749 int index; 750 u16 *data; 751 u16 addr; 752 u64 buf; 753 754 data = (u16 *)&buf; 755 addr = vid / 4; 756 index = vid & 3; 757 ksz8_r_table(dev, TABLE_VLAN, addr, &buf); 758 data[index] = vlan; 759 dev->vlan_cache[vid].table[0] = vlan; 760 ksz8_w_table(dev, TABLE_VLAN, addr, buf); 761 } 762 763 /** 764 * ksz879x_get_loopback - KSZ879x specific function to get loopback 765 * configuration status for a specific port 766 * @dev: Pointer to the device structure 767 * @port: Port number to query 768 * @val: Pointer to store the result 769 * 770 * This function reads the SMI registers to determine whether loopback mode 771 * is enabled for a specific port. 772 * 773 * Return: 0 on success, error code on failure. 774 */ 775 static int ksz879x_get_loopback(struct ksz_device *dev, u16 port, 776 u16 *val) 777 { 778 u8 stat3; 779 int ret; 780 781 ret = ksz_pread8(dev, port, REG_PORT_STATUS_3, &stat3); 782 if (ret) 783 return ret; 784 785 if (stat3 & PORT_PHY_LOOPBACK) 786 *val |= BMCR_LOOPBACK; 787 788 return 0; 789 } 790 791 /** 792 * ksz879x_set_loopback - KSZ879x specific function to set loopback mode for 793 * a specific port 794 * @dev: Pointer to the device structure. 795 * @port: Port number to modify. 796 * @val: Value indicating whether to enable or disable loopback mode. 797 * 798 * This function translates loopback bit of the BMCR register into the 799 * corresponding hardware register bit value and writes it to the SMI interface. 800 * 801 * Return: 0 on success, error code on failure. 802 */ 803 static int ksz879x_set_loopback(struct ksz_device *dev, u16 port, u16 val) 804 { 805 u8 stat3 = 0; 806 807 if (val & BMCR_LOOPBACK) 808 stat3 |= PORT_PHY_LOOPBACK; 809 810 return ksz_prmw8(dev, port, REG_PORT_STATUS_3, PORT_PHY_LOOPBACK, 811 stat3); 812 } 813 814 /** 815 * ksz8_r_phy_ctrl - Translates and reads from the SMI interface to a MIIM PHY 816 * Control register (Reg. 31). 817 * @dev: The KSZ device instance. 818 * @port: The port number to be read. 819 * @val: The value read from the SMI interface. 820 * 821 * This function reads the SMI interface and translates the hardware register 822 * bit values into their corresponding control settings for a MIIM PHY Control 823 * register. 824 * 825 * Return: 0 on success, error code on failure. 826 */ 827 static int ksz8_r_phy_ctrl(struct ksz_device *dev, int port, u16 *val) 828 { 829 const u16 *regs = dev->info->regs; 830 u8 reg_val; 831 int ret; 832 833 *val = 0; 834 835 ret = ksz_pread8(dev, port, regs[P_LINK_STATUS], ®_val); 836 if (ret < 0) 837 return ret; 838 839 if (reg_val & PORT_MDIX_STATUS) 840 *val |= KSZ886X_CTRL_MDIX_STAT; 841 842 ret = ksz_pread8(dev, port, REG_PORT_LINK_MD_CTRL, ®_val); 843 if (ret < 0) 844 return ret; 845 846 if (reg_val & PORT_FORCE_LINK) 847 *val |= KSZ886X_CTRL_FORCE_LINK; 848 849 if (reg_val & PORT_POWER_SAVING) 850 *val |= KSZ886X_CTRL_PWRSAVE; 851 852 if (reg_val & PORT_PHY_REMOTE_LOOPBACK) 853 *val |= KSZ886X_CTRL_REMOTE_LOOPBACK; 854 855 return 0; 856 } 857 858 /** 859 * ksz8_r_phy_bmcr - Translates and reads from the SMI interface to a MIIM PHY 860 * Basic mode control register (Reg. 0). 861 * @dev: The KSZ device instance. 862 * @port: The port number to be read. 863 * @val: The value read from the SMI interface. 864 * 865 * This function reads the SMI interface and translates the hardware register 866 * bit values into their corresponding control settings for a MIIM PHY Basic 867 * mode control register. 868 * 869 * MIIM Bit Mapping Comparison between KSZ8794 and KSZ8873 870 * ------------------------------------------------------------------- 871 * MIIM Bit | KSZ8794 Reg/Bit | KSZ8873 Reg/Bit 872 * ----------------------------+-----------------------------+---------------- 873 * Bit 15 - Soft Reset | 0xF/4 | Not supported 874 * Bit 14 - Loopback | 0xD/0 (MAC), 0xF/7 (PHY) ~ 0xD/0 (PHY) 875 * Bit 13 - Force 100 | 0xC/6 = 0xC/6 876 * Bit 12 - AN Enable | 0xC/7 (reverse logic) ~ 0xC/7 877 * Bit 11 - Power Down | 0xD/3 = 0xD/3 878 * Bit 10 - PHY Isolate | 0xF/5 | Not supported 879 * Bit 9 - Restart AN | 0xD/5 = 0xD/5 880 * Bit 8 - Force Full-Duplex | 0xC/5 = 0xC/5 881 * Bit 7 - Collision Test/Res. | Not supported | Not supported 882 * Bit 6 - Reserved | Not supported | Not supported 883 * Bit 5 - Hp_mdix | 0x9/7 ~ 0xF/7 884 * Bit 4 - Force MDI | 0xD/1 = 0xD/1 885 * Bit 3 - Disable MDIX | 0xD/2 = 0xD/2 886 * Bit 2 - Disable Far-End F. | ???? | 0xD/4 887 * Bit 1 - Disable Transmit | 0xD/6 = 0xD/6 888 * Bit 0 - Disable LED | 0xD/7 = 0xD/7 889 * ------------------------------------------------------------------- 890 * 891 * Return: 0 on success, error code on failure. 892 */ 893 static int ksz8_r_phy_bmcr(struct ksz_device *dev, u16 port, u16 *val) 894 { 895 const u16 *regs = dev->info->regs; 896 u8 restart, speed, ctrl; 897 int ret; 898 899 *val = 0; 900 901 ret = ksz_pread8(dev, port, regs[P_NEG_RESTART_CTRL], &restart); 902 if (ret) 903 return ret; 904 905 ret = ksz_pread8(dev, port, regs[P_SPEED_STATUS], &speed); 906 if (ret) 907 return ret; 908 909 ret = ksz_pread8(dev, port, regs[P_FORCE_CTRL], &ctrl); 910 if (ret) 911 return ret; 912 913 if (ctrl & PORT_FORCE_100_MBIT) 914 *val |= BMCR_SPEED100; 915 916 if (ksz_is_ksz88x3(dev)) { 917 if (restart & KSZ8873_PORT_PHY_LOOPBACK) 918 *val |= BMCR_LOOPBACK; 919 920 if ((ctrl & PORT_AUTO_NEG_ENABLE)) 921 *val |= BMCR_ANENABLE; 922 } else { 923 ret = ksz879x_get_loopback(dev, port, val); 924 if (ret) 925 return ret; 926 927 if (!(ctrl & PORT_AUTO_NEG_DISABLE)) 928 *val |= BMCR_ANENABLE; 929 } 930 931 if (restart & PORT_POWER_DOWN) 932 *val |= BMCR_PDOWN; 933 934 if (restart & PORT_AUTO_NEG_RESTART) 935 *val |= BMCR_ANRESTART; 936 937 if (ctrl & PORT_FORCE_FULL_DUPLEX) 938 *val |= BMCR_FULLDPLX; 939 940 if (speed & PORT_HP_MDIX) 941 *val |= KSZ886X_BMCR_HP_MDIX; 942 943 if (restart & PORT_FORCE_MDIX) 944 *val |= KSZ886X_BMCR_FORCE_MDI; 945 946 if (restart & PORT_AUTO_MDIX_DISABLE) 947 *val |= KSZ886X_BMCR_DISABLE_AUTO_MDIX; 948 949 if (restart & PORT_TX_DISABLE) 950 *val |= KSZ886X_BMCR_DISABLE_TRANSMIT; 951 952 if (restart & PORT_LED_OFF) 953 *val |= KSZ886X_BMCR_DISABLE_LED; 954 955 return 0; 956 } 957 958 int ksz8_r_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 *val) 959 { 960 u8 ctrl, link, val1, val2; 961 int processed = true; 962 const u16 *regs; 963 u16 data = 0; 964 u16 p = phy; 965 int ret; 966 967 regs = dev->info->regs; 968 969 switch (reg) { 970 case MII_BMCR: 971 ret = ksz8_r_phy_bmcr(dev, p, &data); 972 if (ret) 973 return ret; 974 break; 975 case MII_BMSR: 976 ret = ksz_pread8(dev, p, regs[P_LINK_STATUS], &link); 977 if (ret) 978 return ret; 979 980 data = BMSR_100FULL | 981 BMSR_100HALF | 982 BMSR_10FULL | 983 BMSR_10HALF | 984 BMSR_ANEGCAPABLE; 985 if (link & PORT_AUTO_NEG_COMPLETE) 986 data |= BMSR_ANEGCOMPLETE; 987 if (link & PORT_STAT_LINK_GOOD) 988 data |= BMSR_LSTATUS; 989 break; 990 case MII_PHYSID1: 991 data = KSZ8795_ID_HI; 992 break; 993 case MII_PHYSID2: 994 if (ksz_is_ksz88x3(dev)) 995 data = KSZ8863_ID_LO; 996 else 997 data = KSZ8795_ID_LO; 998 break; 999 case MII_ADVERTISE: 1000 ret = ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl); 1001 if (ret) 1002 return ret; 1003 1004 data = ADVERTISE_CSMA; 1005 if (ctrl & PORT_AUTO_NEG_SYM_PAUSE) 1006 data |= ADVERTISE_PAUSE_CAP; 1007 if (ctrl & PORT_AUTO_NEG_100BTX_FD) 1008 data |= ADVERTISE_100FULL; 1009 if (ctrl & PORT_AUTO_NEG_100BTX) 1010 data |= ADVERTISE_100HALF; 1011 if (ctrl & PORT_AUTO_NEG_10BT_FD) 1012 data |= ADVERTISE_10FULL; 1013 if (ctrl & PORT_AUTO_NEG_10BT) 1014 data |= ADVERTISE_10HALF; 1015 break; 1016 case MII_LPA: 1017 ret = ksz_pread8(dev, p, regs[P_REMOTE_STATUS], &link); 1018 if (ret) 1019 return ret; 1020 1021 data = LPA_SLCT; 1022 if (link & PORT_REMOTE_SYM_PAUSE) 1023 data |= LPA_PAUSE_CAP; 1024 if (link & PORT_REMOTE_100BTX_FD) 1025 data |= LPA_100FULL; 1026 if (link & PORT_REMOTE_100BTX) 1027 data |= LPA_100HALF; 1028 if (link & PORT_REMOTE_10BT_FD) 1029 data |= LPA_10FULL; 1030 if (link & PORT_REMOTE_10BT) 1031 data |= LPA_10HALF; 1032 if (data & ~LPA_SLCT) 1033 data |= LPA_LPACK; 1034 break; 1035 case PHY_REG_LINK_MD: 1036 ret = ksz_pread8(dev, p, REG_PORT_LINK_MD_CTRL, &val1); 1037 if (ret) 1038 return ret; 1039 1040 ret = ksz_pread8(dev, p, REG_PORT_LINK_MD_RESULT, &val2); 1041 if (ret) 1042 return ret; 1043 1044 if (val1 & PORT_START_CABLE_DIAG) 1045 data |= PHY_START_CABLE_DIAG; 1046 1047 if (val1 & PORT_CABLE_10M_SHORT) 1048 data |= PHY_CABLE_10M_SHORT; 1049 1050 data |= FIELD_PREP(PHY_CABLE_DIAG_RESULT_M, 1051 FIELD_GET(PORT_CABLE_DIAG_RESULT_M, val1)); 1052 1053 data |= FIELD_PREP(PHY_CABLE_FAULT_COUNTER_M, 1054 (FIELD_GET(PORT_CABLE_FAULT_COUNTER_H, val1) << 8) | 1055 FIELD_GET(PORT_CABLE_FAULT_COUNTER_L, val2)); 1056 break; 1057 case PHY_REG_PHY_CTRL: 1058 ret = ksz8_r_phy_ctrl(dev, p, &data); 1059 if (ret) 1060 return ret; 1061 1062 break; 1063 default: 1064 processed = false; 1065 break; 1066 } 1067 if (processed) 1068 *val = data; 1069 1070 return 0; 1071 } 1072 1073 /** 1074 * ksz8_w_phy_ctrl - Translates and writes to the SMI interface from a MIIM PHY 1075 * Control register (Reg. 31). 1076 * @dev: The KSZ device instance. 1077 * @port: The port number to be configured. 1078 * @val: The register value to be written. 1079 * 1080 * This function translates control settings from a MIIM PHY Control register 1081 * into their corresponding hardware register bit values for the SMI 1082 * interface. 1083 * 1084 * Return: 0 on success, error code on failure. 1085 */ 1086 static int ksz8_w_phy_ctrl(struct ksz_device *dev, int port, u16 val) 1087 { 1088 u8 reg_val = 0; 1089 int ret; 1090 1091 if (val & KSZ886X_CTRL_FORCE_LINK) 1092 reg_val |= PORT_FORCE_LINK; 1093 1094 if (val & KSZ886X_CTRL_PWRSAVE) 1095 reg_val |= PORT_POWER_SAVING; 1096 1097 if (val & KSZ886X_CTRL_REMOTE_LOOPBACK) 1098 reg_val |= PORT_PHY_REMOTE_LOOPBACK; 1099 1100 ret = ksz_prmw8(dev, port, REG_PORT_LINK_MD_CTRL, PORT_FORCE_LINK | 1101 PORT_POWER_SAVING | PORT_PHY_REMOTE_LOOPBACK, reg_val); 1102 return ret; 1103 } 1104 1105 /** 1106 * ksz8_w_phy_bmcr - Translates and writes to the SMI interface from a MIIM PHY 1107 * Basic mode control register (Reg. 0). 1108 * @dev: The KSZ device instance. 1109 * @port: The port number to be configured. 1110 * @val: The register value to be written. 1111 * 1112 * This function translates control settings from a MIIM PHY Basic mode control 1113 * register into their corresponding hardware register bit values for the SMI 1114 * interface. 1115 * 1116 * MIIM Bit Mapping Comparison between KSZ8794 and KSZ8873 1117 * ------------------------------------------------------------------- 1118 * MIIM Bit | KSZ8794 Reg/Bit | KSZ8873 Reg/Bit 1119 * ----------------------------+-----------------------------+---------------- 1120 * Bit 15 - Soft Reset | 0xF/4 | Not supported 1121 * Bit 14 - Loopback | 0xD/0 (MAC), 0xF/7 (PHY) ~ 0xD/0 (PHY) 1122 * Bit 13 - Force 100 | 0xC/6 = 0xC/6 1123 * Bit 12 - AN Enable | 0xC/7 (reverse logic) ~ 0xC/7 1124 * Bit 11 - Power Down | 0xD/3 = 0xD/3 1125 * Bit 10 - PHY Isolate | 0xF/5 | Not supported 1126 * Bit 9 - Restart AN | 0xD/5 = 0xD/5 1127 * Bit 8 - Force Full-Duplex | 0xC/5 = 0xC/5 1128 * Bit 7 - Collision Test/Res. | Not supported | Not supported 1129 * Bit 6 - Reserved | Not supported | Not supported 1130 * Bit 5 - Hp_mdix | 0x9/7 ~ 0xF/7 1131 * Bit 4 - Force MDI | 0xD/1 = 0xD/1 1132 * Bit 3 - Disable MDIX | 0xD/2 = 0xD/2 1133 * Bit 2 - Disable Far-End F. | ???? | 0xD/4 1134 * Bit 1 - Disable Transmit | 0xD/6 = 0xD/6 1135 * Bit 0 - Disable LED | 0xD/7 = 0xD/7 1136 * ------------------------------------------------------------------- 1137 * 1138 * Return: 0 on success, error code on failure. 1139 */ 1140 static int ksz8_w_phy_bmcr(struct ksz_device *dev, u16 port, u16 val) 1141 { 1142 u8 restart, speed, ctrl, restart_mask; 1143 const u16 *regs = dev->info->regs; 1144 int ret; 1145 1146 /* Do not support PHY reset function. */ 1147 if (val & BMCR_RESET) 1148 return 0; 1149 1150 speed = 0; 1151 if (val & KSZ886X_BMCR_HP_MDIX) 1152 speed |= PORT_HP_MDIX; 1153 1154 ret = ksz_prmw8(dev, port, regs[P_SPEED_STATUS], PORT_HP_MDIX, speed); 1155 if (ret) 1156 return ret; 1157 1158 ctrl = 0; 1159 if (ksz_is_ksz88x3(dev)) { 1160 if ((val & BMCR_ANENABLE)) 1161 ctrl |= PORT_AUTO_NEG_ENABLE; 1162 } else { 1163 if (!(val & BMCR_ANENABLE)) 1164 ctrl |= PORT_AUTO_NEG_DISABLE; 1165 1166 /* Fiber port does not support auto-negotiation. */ 1167 if (dev->ports[port].fiber) 1168 ctrl |= PORT_AUTO_NEG_DISABLE; 1169 } 1170 1171 if (val & BMCR_SPEED100) 1172 ctrl |= PORT_FORCE_100_MBIT; 1173 1174 if (val & BMCR_FULLDPLX) 1175 ctrl |= PORT_FORCE_FULL_DUPLEX; 1176 1177 ret = ksz_prmw8(dev, port, regs[P_FORCE_CTRL], PORT_FORCE_100_MBIT | 1178 /* PORT_AUTO_NEG_ENABLE and PORT_AUTO_NEG_DISABLE are the same 1179 * bits 1180 */ 1181 PORT_FORCE_FULL_DUPLEX | PORT_AUTO_NEG_ENABLE, ctrl); 1182 if (ret) 1183 return ret; 1184 1185 restart = 0; 1186 restart_mask = PORT_LED_OFF | PORT_TX_DISABLE | PORT_AUTO_NEG_RESTART | 1187 PORT_POWER_DOWN | PORT_AUTO_MDIX_DISABLE | PORT_FORCE_MDIX; 1188 1189 if (val & KSZ886X_BMCR_DISABLE_LED) 1190 restart |= PORT_LED_OFF; 1191 1192 if (val & KSZ886X_BMCR_DISABLE_TRANSMIT) 1193 restart |= PORT_TX_DISABLE; 1194 1195 if (val & BMCR_ANRESTART) 1196 restart |= PORT_AUTO_NEG_RESTART; 1197 1198 if (val & BMCR_PDOWN) 1199 restart |= PORT_POWER_DOWN; 1200 1201 if (val & KSZ886X_BMCR_DISABLE_AUTO_MDIX) 1202 restart |= PORT_AUTO_MDIX_DISABLE; 1203 1204 if (val & KSZ886X_BMCR_FORCE_MDI) 1205 restart |= PORT_FORCE_MDIX; 1206 1207 if (ksz_is_ksz88x3(dev)) { 1208 restart_mask |= KSZ8873_PORT_PHY_LOOPBACK; 1209 1210 if (val & BMCR_LOOPBACK) 1211 restart |= KSZ8873_PORT_PHY_LOOPBACK; 1212 } else { 1213 ret = ksz879x_set_loopback(dev, port, val); 1214 if (ret) 1215 return ret; 1216 } 1217 1218 return ksz_prmw8(dev, port, regs[P_NEG_RESTART_CTRL], restart_mask, 1219 restart); 1220 } 1221 1222 int ksz8_w_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 val) 1223 { 1224 const u16 *regs; 1225 u8 ctrl, data; 1226 u16 p = phy; 1227 int ret; 1228 1229 regs = dev->info->regs; 1230 1231 switch (reg) { 1232 case MII_BMCR: 1233 ret = ksz8_w_phy_bmcr(dev, p, val); 1234 if (ret) 1235 return ret; 1236 break; 1237 case MII_ADVERTISE: 1238 ret = ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl); 1239 if (ret) 1240 return ret; 1241 1242 data = ctrl; 1243 data &= ~(PORT_AUTO_NEG_SYM_PAUSE | 1244 PORT_AUTO_NEG_100BTX_FD | 1245 PORT_AUTO_NEG_100BTX | 1246 PORT_AUTO_NEG_10BT_FD | 1247 PORT_AUTO_NEG_10BT); 1248 if (val & ADVERTISE_PAUSE_CAP) 1249 data |= PORT_AUTO_NEG_SYM_PAUSE; 1250 if (val & ADVERTISE_100FULL) 1251 data |= PORT_AUTO_NEG_100BTX_FD; 1252 if (val & ADVERTISE_100HALF) 1253 data |= PORT_AUTO_NEG_100BTX; 1254 if (val & ADVERTISE_10FULL) 1255 data |= PORT_AUTO_NEG_10BT_FD; 1256 if (val & ADVERTISE_10HALF) 1257 data |= PORT_AUTO_NEG_10BT; 1258 1259 if (data != ctrl) { 1260 ret = ksz_pwrite8(dev, p, regs[P_LOCAL_CTRL], data); 1261 if (ret) 1262 return ret; 1263 } 1264 break; 1265 case PHY_REG_LINK_MD: 1266 if (val & PHY_START_CABLE_DIAG) 1267 ksz_port_cfg(dev, p, REG_PORT_LINK_MD_CTRL, PORT_START_CABLE_DIAG, true); 1268 break; 1269 1270 case PHY_REG_PHY_CTRL: 1271 ret = ksz8_w_phy_ctrl(dev, p, val); 1272 if (ret) 1273 return ret; 1274 break; 1275 default: 1276 break; 1277 } 1278 1279 return 0; 1280 } 1281 1282 void ksz8_cfg_port_member(struct ksz_device *dev, int port, u8 member) 1283 { 1284 int offset = P_MIRROR_CTRL; 1285 u8 data; 1286 1287 if (ksz_is_ksz8463(dev)) 1288 offset = P1CR2; 1289 ksz_pread8(dev, port, offset, &data); 1290 data &= ~dev->port_mask; 1291 data |= (member & dev->port_mask); 1292 ksz_pwrite8(dev, port, offset, data); 1293 } 1294 1295 void ksz8_flush_dyn_mac_table(struct ksz_device *dev, int port) 1296 { 1297 u8 learn[DSA_MAX_PORTS]; 1298 int first, index, cnt; 1299 const u16 *regs; 1300 int reg = S_FLUSH_TABLE_CTRL; 1301 int mask = SW_FLUSH_DYN_MAC_TABLE; 1302 1303 regs = dev->info->regs; 1304 1305 if ((uint)port < dev->info->port_cnt) { 1306 first = port; 1307 cnt = port + 1; 1308 } else { 1309 /* Flush all ports. */ 1310 first = 0; 1311 cnt = dev->info->port_cnt; 1312 } 1313 for (index = first; index < cnt; index++) { 1314 ksz_pread8(dev, index, regs[P_STP_CTRL], &learn[index]); 1315 if (!(learn[index] & PORT_LEARN_DISABLE)) 1316 ksz_pwrite8(dev, index, regs[P_STP_CTRL], 1317 learn[index] | PORT_LEARN_DISABLE); 1318 } 1319 if (ksz_is_ksz8463(dev)) { 1320 reg = KSZ8463_FLUSH_TABLE_CTRL; 1321 mask = KSZ8463_FLUSH_DYN_MAC_TABLE; 1322 } 1323 ksz_cfg(dev, reg, mask, true); 1324 for (index = first; index < cnt; index++) { 1325 if (!(learn[index] & PORT_LEARN_DISABLE)) 1326 ksz_pwrite8(dev, index, regs[P_STP_CTRL], learn[index]); 1327 } 1328 } 1329 1330 int ksz8_fdb_dump(struct ksz_device *dev, int port, 1331 dsa_fdb_dump_cb_t *cb, void *data) 1332 { 1333 u8 mac[ETH_ALEN]; 1334 u8 src_port, fid; 1335 u16 entries = 0; 1336 int ret, i; 1337 1338 for (i = 0; i < KSZ8_DYN_MAC_ENTRIES; i++) { 1339 ret = ksz8_r_dyn_mac_table(dev, i, mac, &fid, &src_port, 1340 &entries); 1341 if (ret) 1342 return ret; 1343 1344 if (i >= entries) 1345 return 0; 1346 1347 if (port == src_port) { 1348 ret = cb(mac, fid, false, data); 1349 if (ret) 1350 return ret; 1351 } 1352 } 1353 1354 return 0; 1355 } 1356 1357 static int ksz8_add_sta_mac(struct ksz_device *dev, int port, 1358 const unsigned char *addr, u16 vid) 1359 { 1360 struct alu_struct alu; 1361 int index, ret; 1362 int empty = 0; 1363 1364 alu.port_forward = 0; 1365 for (index = 0; index < dev->info->num_statics; index++) { 1366 bool valid; 1367 1368 ret = ksz8_r_sta_mac_table(dev, index, &alu, &valid); 1369 if (ret) 1370 return ret; 1371 if (!valid) { 1372 /* Remember the first empty entry. */ 1373 if (!empty) 1374 empty = index + 1; 1375 continue; 1376 } 1377 1378 if (!memcmp(alu.mac, addr, ETH_ALEN) && alu.fid == vid) 1379 break; 1380 } 1381 1382 /* no available entry */ 1383 if (index == dev->info->num_statics && !empty) 1384 return -ENOSPC; 1385 1386 /* add entry */ 1387 if (index == dev->info->num_statics) { 1388 index = empty - 1; 1389 memset(&alu, 0, sizeof(alu)); 1390 memcpy(alu.mac, addr, ETH_ALEN); 1391 alu.is_static = true; 1392 } 1393 alu.port_forward |= BIT(port); 1394 if (vid) { 1395 alu.is_use_fid = true; 1396 1397 /* Need a way to map VID to FID. */ 1398 alu.fid = vid; 1399 } 1400 1401 return ksz8_w_sta_mac_table(dev, index, &alu); 1402 } 1403 1404 static int ksz8_del_sta_mac(struct ksz_device *dev, int port, 1405 const unsigned char *addr, u16 vid) 1406 { 1407 struct alu_struct alu; 1408 int index, ret; 1409 1410 for (index = 0; index < dev->info->num_statics; index++) { 1411 bool valid; 1412 1413 ret = ksz8_r_sta_mac_table(dev, index, &alu, &valid); 1414 if (ret) 1415 return ret; 1416 if (!valid) 1417 continue; 1418 1419 if (!memcmp(alu.mac, addr, ETH_ALEN) && alu.fid == vid) 1420 break; 1421 } 1422 1423 /* no available entry */ 1424 if (index == dev->info->num_statics) 1425 return 0; 1426 1427 /* clear port */ 1428 alu.port_forward &= ~BIT(port); 1429 if (!alu.port_forward) 1430 alu.is_static = false; 1431 1432 return ksz8_w_sta_mac_table(dev, index, &alu); 1433 } 1434 1435 int ksz8_mdb_add(struct ksz_device *dev, int port, 1436 const struct switchdev_obj_port_mdb *mdb, struct dsa_db db) 1437 { 1438 return ksz8_add_sta_mac(dev, port, mdb->addr, mdb->vid); 1439 } 1440 1441 int ksz8_mdb_del(struct ksz_device *dev, int port, 1442 const struct switchdev_obj_port_mdb *mdb, struct dsa_db db) 1443 { 1444 return ksz8_del_sta_mac(dev, port, mdb->addr, mdb->vid); 1445 } 1446 1447 int ksz8_fdb_add(struct ksz_device *dev, int port, const unsigned char *addr, 1448 u16 vid, struct dsa_db db) 1449 { 1450 return ksz8_add_sta_mac(dev, port, addr, vid); 1451 } 1452 1453 int ksz8_fdb_del(struct ksz_device *dev, int port, const unsigned char *addr, 1454 u16 vid, struct dsa_db db) 1455 { 1456 return ksz8_del_sta_mac(dev, port, addr, vid); 1457 } 1458 1459 int ksz8_port_vlan_filtering(struct ksz_device *dev, int port, bool flag, 1460 struct netlink_ext_ack *extack) 1461 { 1462 if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev)) 1463 return -ENOTSUPP; 1464 1465 /* Discard packets with VID not enabled on the switch */ 1466 ksz_cfg(dev, S_MIRROR_CTRL, SW_VLAN_ENABLE, flag); 1467 1468 /* Discard packets with VID not enabled on the ingress port */ 1469 for (port = 0; port < dev->phy_port_cnt; ++port) 1470 ksz_port_cfg(dev, port, REG_PORT_CTRL_2, PORT_INGRESS_FILTER, 1471 flag); 1472 1473 return 0; 1474 } 1475 1476 static void ksz8_port_enable_pvid(struct ksz_device *dev, int port, bool state) 1477 { 1478 if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev)) { 1479 int reg = REG_SW_INSERT_SRC_PVID; 1480 1481 if (ksz_is_ksz8463(dev)) 1482 reg = KSZ8463_REG_SW_CTRL_9; 1483 ksz_cfg(dev, reg, 0x03 << (4 - 2 * port), state); 1484 } else { 1485 ksz_pwrite8(dev, port, REG_PORT_CTRL_12, state ? 0x0f : 0x00); 1486 } 1487 } 1488 1489 int ksz8_port_vlan_add(struct ksz_device *dev, int port, 1490 const struct switchdev_obj_port_vlan *vlan, 1491 struct netlink_ext_ack *extack) 1492 { 1493 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1494 struct ksz_port *p = &dev->ports[port]; 1495 u16 data, new_pvid = 0; 1496 u8 fid, member, valid; 1497 1498 if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev)) 1499 return -ENOTSUPP; 1500 1501 /* If a VLAN is added with untagged flag different from the 1502 * port's Remove Tag flag, we need to change the latter. 1503 * Ignore VID 0, which is always untagged. 1504 * Ignore CPU port, which will always be tagged. 1505 */ 1506 if (untagged != p->remove_tag && vlan->vid != 0 && 1507 port != dev->cpu_port) { 1508 unsigned int vid; 1509 1510 /* Reject attempts to add a VLAN that requires the 1511 * Remove Tag flag to be changed, unless there are no 1512 * other VLANs currently configured. 1513 */ 1514 for (vid = 1; vid < dev->info->num_vlans; ++vid) { 1515 /* Skip the VID we are going to add or reconfigure */ 1516 if (vid == vlan->vid) 1517 continue; 1518 1519 ksz8_from_vlan(dev, dev->vlan_cache[vid].table[0], 1520 &fid, &member, &valid); 1521 if (valid && (member & BIT(port))) 1522 return -EINVAL; 1523 } 1524 1525 ksz_port_cfg(dev, port, P_TAG_CTRL, PORT_REMOVE_TAG, untagged); 1526 p->remove_tag = untagged; 1527 } 1528 1529 ksz8_r_vlan_table(dev, vlan->vid, &data); 1530 ksz8_from_vlan(dev, data, &fid, &member, &valid); 1531 1532 /* First time to setup the VLAN entry. */ 1533 if (!valid) { 1534 /* Need to find a way to map VID to FID. */ 1535 fid = 1; 1536 valid = 1; 1537 } 1538 member |= BIT(port); 1539 1540 ksz8_to_vlan(dev, fid, member, valid, &data); 1541 ksz8_w_vlan_table(dev, vlan->vid, data); 1542 1543 /* change PVID */ 1544 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) 1545 new_pvid = vlan->vid; 1546 1547 if (new_pvid) { 1548 u16 vid; 1549 1550 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &vid); 1551 vid &= ~VLAN_VID_MASK; 1552 vid |= new_pvid; 1553 ksz_pwrite16(dev, port, REG_PORT_CTRL_VID, vid); 1554 1555 ksz8_port_enable_pvid(dev, port, true); 1556 } 1557 1558 return 0; 1559 } 1560 1561 int ksz8_port_vlan_del(struct ksz_device *dev, int port, 1562 const struct switchdev_obj_port_vlan *vlan) 1563 { 1564 u16 data, pvid; 1565 u8 fid, member, valid; 1566 1567 if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev)) 1568 return -ENOTSUPP; 1569 1570 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &pvid); 1571 pvid = pvid & 0xFFF; 1572 1573 ksz8_r_vlan_table(dev, vlan->vid, &data); 1574 ksz8_from_vlan(dev, data, &fid, &member, &valid); 1575 1576 member &= ~BIT(port); 1577 1578 /* Invalidate the entry if no more member. */ 1579 if (!member) { 1580 fid = 0; 1581 valid = 0; 1582 } 1583 1584 ksz8_to_vlan(dev, fid, member, valid, &data); 1585 ksz8_w_vlan_table(dev, vlan->vid, data); 1586 1587 if (pvid == vlan->vid) 1588 ksz8_port_enable_pvid(dev, port, false); 1589 1590 return 0; 1591 } 1592 1593 int ksz8_port_mirror_add(struct ksz_device *dev, int port, 1594 struct dsa_mall_mirror_tc_entry *mirror, 1595 bool ingress, struct netlink_ext_ack *extack) 1596 { 1597 int offset = P_MIRROR_CTRL; 1598 1599 if (ksz_is_ksz8463(dev)) 1600 offset = P1CR2; 1601 if (ingress) { 1602 ksz_port_cfg(dev, port, offset, PORT_MIRROR_RX, true); 1603 dev->mirror_rx |= BIT(port); 1604 } else { 1605 ksz_port_cfg(dev, port, offset, PORT_MIRROR_TX, true); 1606 dev->mirror_tx |= BIT(port); 1607 } 1608 1609 ksz_port_cfg(dev, port, offset, PORT_MIRROR_SNIFFER, false); 1610 1611 /* configure mirror port */ 1612 if (dev->mirror_rx || dev->mirror_tx) 1613 ksz_port_cfg(dev, mirror->to_local_port, offset, 1614 PORT_MIRROR_SNIFFER, true); 1615 1616 return 0; 1617 } 1618 1619 void ksz8_port_mirror_del(struct ksz_device *dev, int port, 1620 struct dsa_mall_mirror_tc_entry *mirror) 1621 { 1622 int offset = P_MIRROR_CTRL; 1623 u8 data; 1624 1625 if (ksz_is_ksz8463(dev)) 1626 offset = P1CR2; 1627 if (mirror->ingress) { 1628 ksz_port_cfg(dev, port, offset, PORT_MIRROR_RX, false); 1629 dev->mirror_rx &= ~BIT(port); 1630 } else { 1631 ksz_port_cfg(dev, port, offset, PORT_MIRROR_TX, false); 1632 dev->mirror_tx &= ~BIT(port); 1633 } 1634 1635 ksz_pread8(dev, port, offset, &data); 1636 1637 if (!dev->mirror_rx && !dev->mirror_tx) 1638 ksz_port_cfg(dev, mirror->to_local_port, offset, 1639 PORT_MIRROR_SNIFFER, false); 1640 } 1641 1642 static void ksz8795_cpu_interface_select(struct ksz_device *dev, int port) 1643 { 1644 struct ksz_port *p = &dev->ports[port]; 1645 1646 if (!ksz_is_ksz87xx(dev)) 1647 return; 1648 1649 if (!p->interface && dev->compat_interface) { 1650 dev_warn(dev->dev, 1651 "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. " 1652 "Please update your device tree.\n", 1653 port); 1654 p->interface = dev->compat_interface; 1655 } 1656 } 1657 1658 void ksz8_port_setup(struct ksz_device *dev, int port, bool cpu_port) 1659 { 1660 const u16 *regs = dev->info->regs; 1661 struct dsa_switch *ds = dev->ds; 1662 const u32 *masks; 1663 int offset; 1664 u8 member; 1665 1666 masks = dev->info->masks; 1667 1668 /* enable broadcast storm limit */ 1669 offset = P_BCAST_STORM_CTRL; 1670 if (ksz_is_ksz8463(dev)) 1671 offset = P1CR1; 1672 ksz_port_cfg(dev, port, offset, PORT_BROADCAST_STORM, true); 1673 1674 ksz8_port_queue_split(dev, port, dev->info->num_tx_queues); 1675 1676 /* replace priority */ 1677 offset = P_802_1P_CTRL; 1678 if (ksz_is_ksz8463(dev)) 1679 offset = P1CR2; 1680 ksz_port_cfg(dev, port, offset, 1681 masks[PORT_802_1P_REMAPPING], false); 1682 1683 if (cpu_port) 1684 member = dsa_user_ports(ds); 1685 else 1686 member = BIT(dsa_upstream_port(ds, port)); 1687 1688 ksz8_cfg_port_member(dev, port, member); 1689 1690 /* Disable all WoL options by default. Otherwise 1691 * ksz_switch_macaddr_get/put logic will not work properly. 1692 * CPU port 4 has no WoL functionality. 1693 */ 1694 if (ksz_is_ksz87xx(dev) && !cpu_port) 1695 ksz8_pme_pwrite8(dev, port, regs[REG_PORT_PME_CTRL], 0); 1696 } 1697 1698 static void ksz88x3_config_rmii_clk(struct ksz_device *dev) 1699 { 1700 struct dsa_port *cpu_dp = dsa_to_port(dev->ds, dev->cpu_port); 1701 bool rmii_clk_internal; 1702 1703 if (!ksz_is_ksz88x3(dev)) 1704 return; 1705 1706 rmii_clk_internal = of_property_read_bool(cpu_dp->dn, 1707 "microchip,rmii-clk-internal"); 1708 1709 ksz_cfg(dev, KSZ88X3_REG_FVID_AND_HOST_MODE, 1710 KSZ88X3_PORT3_RMII_CLK_INTERNAL, rmii_clk_internal); 1711 } 1712 1713 void ksz8_config_cpu_port(struct dsa_switch *ds) 1714 { 1715 struct ksz_device *dev = ds->priv; 1716 struct ksz_port *p; 1717 const u32 *masks; 1718 const u16 *regs; 1719 u8 remote; 1720 u8 fiber_ports = 0; 1721 int i; 1722 1723 masks = dev->info->masks; 1724 regs = dev->info->regs; 1725 1726 ksz_cfg(dev, regs[S_TAIL_TAG_CTRL], masks[SW_TAIL_TAG_ENABLE], true); 1727 1728 ksz8_port_setup(dev, dev->cpu_port, true); 1729 1730 ksz8795_cpu_interface_select(dev, dev->cpu_port); 1731 ksz88x3_config_rmii_clk(dev); 1732 1733 for (i = 0; i < dev->phy_port_cnt; i++) { 1734 ksz_port_stp_state_set(ds, i, BR_STATE_DISABLED); 1735 } 1736 for (i = 0; i < dev->phy_port_cnt; i++) { 1737 p = &dev->ports[i]; 1738 1739 /* For KSZ8795 family. */ 1740 if (ksz_is_ksz87xx(dev)) { 1741 ksz_pread8(dev, i, regs[P_REMOTE_STATUS], &remote); 1742 if (remote & KSZ8_PORT_FIBER_MODE) 1743 p->fiber = 1; 1744 } 1745 if (p->fiber) 1746 ksz_port_cfg(dev, i, regs[P_STP_CTRL], 1747 PORT_FORCE_FLOW_CTRL, true); 1748 else 1749 ksz_port_cfg(dev, i, regs[P_STP_CTRL], 1750 PORT_FORCE_FLOW_CTRL, false); 1751 if (p->fiber) 1752 fiber_ports |= (1 << i); 1753 } 1754 if (ksz_is_ksz8463(dev)) { 1755 /* Setup fiber ports. */ 1756 if (fiber_ports) { 1757 fiber_ports &= 3; 1758 regmap_update_bits(ksz_regmap_16(dev), 1759 KSZ8463_REG_CFG_CTRL, 1760 fiber_ports << PORT_COPPER_MODE_S, 1761 0); 1762 regmap_update_bits(ksz_regmap_16(dev), 1763 KSZ8463_REG_DSP_CTRL_6, 1764 COPPER_RECEIVE_ADJUSTMENT, 0); 1765 } 1766 1767 /* Turn off PTP function as the switch's proprietary way of 1768 * handling timestamp is not supported in current Linux PTP 1769 * stack implementation. 1770 */ 1771 regmap_update_bits(ksz_regmap_16(dev), 1772 KSZ8463_PTP_MSG_CONF1, 1773 PTP_ENABLE, 0); 1774 regmap_update_bits(ksz_regmap_16(dev), 1775 KSZ8463_PTP_CLK_CTRL, 1776 PTP_CLK_ENABLE, 0); 1777 } 1778 } 1779 1780 /** 1781 * ksz8_phy_port_link_up - Configures ports with integrated PHYs 1782 * @dev: The KSZ device instance. 1783 * @port: The port number to configure. 1784 * @duplex: The desired duplex mode. 1785 * @tx_pause: If true, enables transmit pause. 1786 * @rx_pause: If true, enables receive pause. 1787 * 1788 * Description: 1789 * The function configures flow control settings for a given port based on the 1790 * desired settings and current duplex mode. 1791 * 1792 * According to the KSZ8873 datasheet, the PORT_FORCE_FLOW_CTRL bit in the 1793 * Port Control 2 register (0x1A for Port 1, 0x22 for Port 2, 0x32 for Port 3) 1794 * determines how flow control is handled on the port: 1795 * "1 = will always enable full-duplex flow control on the port, regardless 1796 * of AN result. 1797 * 0 = full-duplex flow control is enabled based on AN result." 1798 * 1799 * This means that the flow control behavior depends on the state of this bit: 1800 * - If PORT_FORCE_FLOW_CTRL is set to 1, the switch will ignore AN results and 1801 * force flow control on the port. 1802 * - If PORT_FORCE_FLOW_CTRL is set to 0, the switch will enable or disable 1803 * flow control based on the AN results. 1804 * 1805 * However, there is a potential limitation in this configuration. It is 1806 * currently not possible to force disable flow control on a port if we still 1807 * advertise pause support. While such a configuration is not currently 1808 * supported by Linux, and may not make practical sense, it's important to be 1809 * aware of this limitation when working with the KSZ8873 and similar devices. 1810 */ 1811 static void ksz8_phy_port_link_up(struct ksz_device *dev, int port, int duplex, 1812 bool tx_pause, bool rx_pause) 1813 { 1814 const u16 *regs = dev->info->regs; 1815 u8 sctrl = 0; 1816 1817 /* The KSZ8795 switch differs from the KSZ8873 by supporting 1818 * asymmetric pause control. However, since a single bit is used to 1819 * control both RX and TX pause, we can't enforce asymmetric pause 1820 * control - both TX and RX pause will be either enabled or disabled 1821 * together. 1822 * 1823 * If auto-negotiation is enabled, we usually allow the flow control to 1824 * be determined by the auto-negotiation process based on the 1825 * capabilities of both link partners. However, for KSZ8873, the 1826 * PORT_FORCE_FLOW_CTRL bit may be set by the hardware bootstrap, 1827 * ignoring the auto-negotiation result. Thus, even in auto-negotiation 1828 * mode, we need to ensure that the PORT_FORCE_FLOW_CTRL bit is 1829 * properly cleared. 1830 * 1831 * In the absence of pause auto-negotiation, we will enforce symmetric 1832 * pause control for both variants of switches - KSZ8873 and KSZ8795. 1833 * 1834 * Autoneg Pause Autoneg rx,tx PORT_FORCE_FLOW_CTRL 1835 * 1 1 x 0 1836 * 0 1 x 0 (flow control probably disabled) 1837 * x 0 1 1 (flow control force enabled) 1838 * 1 0 0 0 (flow control still depends on 1839 * aneg result due to hardware) 1840 * 0 0 0 0 (flow control probably disabled) 1841 */ 1842 if (dev->ports[port].manual_flow && tx_pause) 1843 sctrl |= PORT_FORCE_FLOW_CTRL; 1844 1845 ksz_prmw8(dev, port, regs[P_STP_CTRL], PORT_FORCE_FLOW_CTRL, sctrl); 1846 } 1847 1848 /** 1849 * ksz8_cpu_port_link_up - Configures the CPU port of the switch. 1850 * @dev: The KSZ device instance. 1851 * @speed: The desired link speed. 1852 * @duplex: The desired duplex mode. 1853 * @tx_pause: If true, enables transmit pause. 1854 * @rx_pause: If true, enables receive pause. 1855 * 1856 * Description: 1857 * The function configures flow control and speed settings for the CPU 1858 * port of the switch based on the desired settings, current duplex mode, and 1859 * speed. 1860 */ 1861 static void ksz8_cpu_port_link_up(struct ksz_device *dev, int speed, int duplex, 1862 bool tx_pause, bool rx_pause) 1863 { 1864 const u16 *regs = dev->info->regs; 1865 u8 ctrl = 0; 1866 1867 /* SW_FLOW_CTRL, SW_HALF_DUPLEX, and SW_10_MBIT bits are bootstrappable 1868 * at least on KSZ8873. They can have different values depending on your 1869 * board setup. 1870 */ 1871 if (tx_pause || rx_pause) 1872 ctrl |= SW_FLOW_CTRL; 1873 1874 if (duplex == DUPLEX_HALF) 1875 ctrl |= SW_HALF_DUPLEX; 1876 1877 /* This hardware only supports SPEED_10 and SPEED_100. For SPEED_10 1878 * we need to set the SW_10_MBIT bit. Otherwise, we can leave it 0. 1879 */ 1880 if (speed == SPEED_10) 1881 ctrl |= SW_10_MBIT; 1882 1883 ksz_rmw8(dev, regs[S_BROADCAST_CTRL], SW_HALF_DUPLEX | SW_FLOW_CTRL | 1884 SW_10_MBIT, ctrl); 1885 } 1886 1887 void ksz8_phylink_mac_link_up(struct phylink_config *config, 1888 struct phy_device *phydev, unsigned int mode, 1889 phy_interface_t interface, int speed, int duplex, 1890 bool tx_pause, bool rx_pause) 1891 { 1892 struct dsa_port *dp = dsa_phylink_to_port(config); 1893 struct ksz_device *dev = dp->ds->priv; 1894 int port = dp->index; 1895 1896 /* If the port is the CPU port, apply special handling. Only the CPU 1897 * port is configured via global registers. 1898 */ 1899 if (dev->cpu_port == port) 1900 ksz8_cpu_port_link_up(dev, speed, duplex, tx_pause, rx_pause); 1901 else if (dev->info->internal_phy[port]) 1902 ksz8_phy_port_link_up(dev, port, duplex, tx_pause, rx_pause); 1903 } 1904 1905 static int ksz8_handle_global_errata(struct dsa_switch *ds) 1906 { 1907 struct ksz_device *dev = ds->priv; 1908 int ret = 0; 1909 1910 /* KSZ87xx Errata DS80000687C. 1911 * Module 2: Link drops with some EEE link partners. 1912 * An issue with the EEE next page exchange between the 1913 * KSZ879x/KSZ877x/KSZ876x and some EEE link partners may result in 1914 * the link dropping. 1915 */ 1916 if (dev->info->ksz87xx_eee_link_erratum) 1917 ret = ksz8_ind_write8(dev, TABLE_EEE, REG_IND_EEE_GLOB2_HI, 0); 1918 1919 return ret; 1920 } 1921 1922 int ksz8_enable_stp_addr(struct ksz_device *dev) 1923 { 1924 struct alu_struct alu; 1925 1926 /* Setup STP address for STP operation. */ 1927 memset(&alu, 0, sizeof(alu)); 1928 ether_addr_copy(alu.mac, eth_stp_addr); 1929 alu.is_static = true; 1930 alu.is_override = true; 1931 alu.port_forward = dev->info->cpu_ports; 1932 1933 return ksz8_w_sta_mac_table(dev, 0, &alu); 1934 } 1935 1936 int ksz8_setup(struct dsa_switch *ds) 1937 { 1938 struct ksz_device *dev = ds->priv; 1939 const u16 *regs = dev->info->regs; 1940 int i, ret = 0; 1941 1942 ds->mtu_enforcement_ingress = true; 1943 1944 /* We rely on software untagging on the CPU port, so that we 1945 * can support both tagged and untagged VLANs 1946 */ 1947 ds->untag_bridge_pvid = true; 1948 1949 /* VLAN filtering is partly controlled by the global VLAN 1950 * Enable flag 1951 */ 1952 ds->vlan_filtering_is_global = true; 1953 1954 /* Enable automatic fast aging when link changed detected. */ 1955 ksz_cfg(dev, S_LINK_AGING_CTRL, SW_LINK_AUTO_AGING, true); 1956 1957 /* Enable aggressive back off algorithm in half duplex mode. */ 1958 regmap_update_bits(ksz_regmap_8(dev), REG_SW_CTRL_1, 1959 SW_AGGR_BACKOFF, SW_AGGR_BACKOFF); 1960 1961 /* 1962 * Make sure unicast VLAN boundary is set as default and 1963 * enable no excessive collision drop. 1964 */ 1965 regmap_update_bits(ksz_regmap_8(dev), REG_SW_CTRL_2, 1966 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP, 1967 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP); 1968 1969 ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_REPLACE_VID, false); 1970 1971 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false); 1972 1973 if (!ksz_is_ksz88x3(dev) && !ksz_is_ksz8463(dev)) 1974 ksz_cfg(dev, REG_SW_CTRL_19, SW_INS_TAG_ENABLE, true); 1975 1976 for (i = 0; i < (dev->info->num_vlans / 4); i++) 1977 ksz8_r_vlan_entries(dev, i); 1978 1979 /* Make sure PME (WoL) is not enabled. If requested, it will 1980 * be enabled by ksz_wol_pre_shutdown(). Otherwise, some PMICs 1981 * do not like PME events changes before shutdown. PME only 1982 * available on KSZ87xx family. 1983 */ 1984 if (ksz_is_ksz87xx(dev)) { 1985 ret = ksz8_pme_write8(dev, regs[REG_SW_PME_CTRL], 0); 1986 if (!ret) 1987 ret = ksz_rmw8(dev, REG_INT_ENABLE, INT_PME, 0); 1988 } 1989 1990 if (!ret) 1991 return ksz8_handle_global_errata(ds); 1992 else 1993 return ret; 1994 } 1995 1996 void ksz8_get_caps(struct ksz_device *dev, int port, 1997 struct phylink_config *config) 1998 { 1999 config->mac_capabilities = MAC_10 | MAC_100; 2000 2001 /* Silicon Errata Sheet (DS80000830A): 2002 * "Port 1 does not respond to received flow control PAUSE frames" 2003 * So, disable Pause support on "Port 1" (port == 0) for all ksz88x3 2004 * switches. 2005 */ 2006 if (!ksz_is_ksz88x3(dev) || port) 2007 config->mac_capabilities |= MAC_SYM_PAUSE; 2008 2009 /* Asym pause is not supported on KSZ8863 and KSZ8873 */ 2010 if (!ksz_is_ksz88x3(dev)) 2011 config->mac_capabilities |= MAC_ASYM_PAUSE; 2012 } 2013 2014 u32 ksz8_get_port_addr(int port, int offset) 2015 { 2016 return PORT_CTRL_ADDR(port, offset); 2017 } 2018 2019 u32 ksz8463_get_port_addr(int port, int offset) 2020 { 2021 return offset + 0x18 * port; 2022 } 2023 2024 static u16 ksz8463_get_phy_addr(u16 phy, u16 reg, u16 offset) 2025 { 2026 return offset + reg * 2 + phy * (P2MBCR - P1MBCR); 2027 } 2028 2029 int ksz8463_r_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 *val) 2030 { 2031 u16 sw_reg = 0; 2032 u16 data = 0; 2033 int ret; 2034 2035 if (phy > 1) 2036 return -ENOSPC; 2037 switch (reg) { 2038 case MII_PHYSID1: 2039 sw_reg = ksz8463_get_phy_addr(phy, 0, PHY1IHR); 2040 break; 2041 case MII_PHYSID2: 2042 sw_reg = ksz8463_get_phy_addr(phy, 0, PHY1ILR); 2043 break; 2044 case MII_BMCR: 2045 case MII_BMSR: 2046 case MII_ADVERTISE: 2047 case MII_LPA: 2048 sw_reg = ksz8463_get_phy_addr(phy, reg, P1MBCR); 2049 break; 2050 case MII_TPISTATUS: 2051 /* This register holds the PHY interrupt status for simulated 2052 * Micrel KSZ PHY. 2053 */ 2054 data = 0x0505; 2055 break; 2056 default: 2057 break; 2058 } 2059 if (sw_reg) { 2060 ret = ksz_read16(dev, sw_reg, &data); 2061 if (ret) 2062 return ret; 2063 } 2064 *val = data; 2065 2066 return 0; 2067 } 2068 2069 int ksz8463_w_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 val) 2070 { 2071 u16 sw_reg = 0; 2072 int ret; 2073 2074 if (phy > 1) 2075 return -ENOSPC; 2076 2077 /* No write to fiber port. */ 2078 if (dev->ports[phy].fiber) 2079 return 0; 2080 switch (reg) { 2081 case MII_BMCR: 2082 case MII_ADVERTISE: 2083 sw_reg = ksz8463_get_phy_addr(phy, reg, P1MBCR); 2084 break; 2085 default: 2086 break; 2087 } 2088 if (sw_reg) { 2089 ret = ksz_write16(dev, sw_reg, val); 2090 if (ret) 2091 return ret; 2092 } 2093 2094 return 0; 2095 } 2096 2097 int ksz8_switch_init(struct ksz_device *dev) 2098 { 2099 dev->cpu_port = fls(dev->info->cpu_ports) - 1; 2100 dev->phy_port_cnt = dev->info->port_cnt - 1; 2101 dev->port_mask = (BIT(dev->phy_port_cnt) - 1) | dev->info->cpu_ports; 2102 2103 return 0; 2104 } 2105 2106 void ksz8_switch_exit(struct ksz_device *dev) 2107 { 2108 ksz8_reset_switch(dev); 2109 } 2110 2111 MODULE_AUTHOR("Tristram Ha <Tristram.Ha@microchip.com>"); 2112 MODULE_DESCRIPTION("Microchip KSZ8795 Series Switch DSA Driver"); 2113 MODULE_LICENSE("GPL"); 2114