1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip KSZ8XXX series switch driver 4 * 5 * It supports the following switches: 6 * - KSZ8463 7 * - KSZ8863, KSZ8873 aka KSZ88X3 8 * - KSZ8895, KSZ8864 aka KSZ8895 family 9 * - KSZ8794, KSZ8795, KSZ8765 aka KSZ87XX 10 * Note that it does NOT support: 11 * - KSZ8563, KSZ8567 - see KSZ9477 driver 12 * 13 * Copyright (C) 2017 Microchip Technology Inc. 14 * Tristram Ha <Tristram.Ha@microchip.com> 15 */ 16 17 #include <linux/bitfield.h> 18 #include <linux/delay.h> 19 #include <linux/dsa/ksz_common.h> 20 #include <linux/export.h> 21 #include <linux/gpio.h> 22 #include <linux/if_vlan.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/platform_data/microchip-ksz.h> 26 #include <linux/phy.h> 27 #include <linux/etherdevice.h> 28 #include <linux/if_bridge.h> 29 #include <linux/micrel_phy.h> 30 #include <net/dsa.h> 31 #include <net/switchdev.h> 32 #include <linux/phylink.h> 33 34 #include "ksz_common.h" 35 #include "ksz_dcb.h" 36 #include "ksz8_reg.h" 37 #include "ksz8.h" 38 39 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) 40 { 41 ksz_rmw8(dev, addr, bits, set ? bits : 0); 42 } 43 44 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits, 45 bool set) 46 { 47 ksz_rmw8(dev, dev->dev_ops->get_port_addr(port, offset), bits, 48 set ? bits : 0); 49 } 50 51 /** 52 * ksz8_ind_write8 - EEE/ACL/PME indirect register write 53 * @dev: The device structure. 54 * @table: Function & table select, register 110. 55 * @addr: Indirect access control, register 111. 56 * @data: The data to be written. 57 * 58 * This function performs an indirect register write for EEE, ACL or 59 * PME switch functionalities. Both 8-bit registers 110 and 111 are 60 * written at once with ksz_write16, using the serial multiple write 61 * functionality. 62 * 63 * Return: 0 on success, or an error code on failure. 64 */ 65 static int ksz8_ind_write8(struct ksz_device *dev, u8 table, u16 addr, u8 data) 66 { 67 const u16 *regs; 68 u16 ctrl_addr; 69 int ret = 0; 70 71 regs = dev->info->regs; 72 73 mutex_lock(&dev->alu_mutex); 74 75 ctrl_addr = IND_ACC_TABLE(table) | addr; 76 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 77 if (!ret) 78 ret = ksz_write8(dev, regs[REG_IND_BYTE], data); 79 80 mutex_unlock(&dev->alu_mutex); 81 82 return ret; 83 } 84 85 /** 86 * ksz8_ind_read8 - EEE/ACL/PME indirect register read 87 * @dev: The device structure. 88 * @table: Function & table select, register 110. 89 * @addr: Indirect access control, register 111. 90 * @val: The value read. 91 * 92 * This function performs an indirect register read for EEE, ACL or 93 * PME switch functionalities. Both 8-bit registers 110 and 111 are 94 * written at once with ksz_write16, using the serial multiple write 95 * functionality. 96 * 97 * Return: 0 on success, or an error code on failure. 98 */ 99 static int ksz8_ind_read8(struct ksz_device *dev, u8 table, u16 addr, u8 *val) 100 { 101 const u16 *regs; 102 u16 ctrl_addr; 103 int ret = 0; 104 105 regs = dev->info->regs; 106 107 mutex_lock(&dev->alu_mutex); 108 109 ctrl_addr = IND_ACC_TABLE(table | TABLE_READ) | addr; 110 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 111 if (!ret) 112 ret = ksz_read8(dev, regs[REG_IND_BYTE], val); 113 114 mutex_unlock(&dev->alu_mutex); 115 116 return ret; 117 } 118 119 static int ksz8_pme_write8(struct ksz_device *dev, u32 reg, u8 value) 120 { 121 return ksz8_ind_write8(dev, (u8)(reg >> 8), (u8)(reg), value); 122 } 123 124 static int ksz8_pme_pread8(struct ksz_device *dev, int port, int offset, u8 *data) 125 { 126 u8 table = (u8)(offset >> 8 | (port + 1)); 127 128 return ksz8_ind_read8(dev, table, (u8)(offset), data); 129 } 130 131 static int ksz8_pme_pwrite8(struct ksz_device *dev, int port, int offset, u8 data) 132 { 133 u8 table = (u8)(offset >> 8 | (port + 1)); 134 135 return ksz8_ind_write8(dev, table, (u8)(offset), data); 136 } 137 138 static int ksz8_reset_switch(struct ksz_device *dev) 139 { 140 if (ksz_is_ksz88x3(dev)) { 141 /* reset switch */ 142 ksz_cfg(dev, KSZ8863_REG_SW_RESET, 143 KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, true); 144 ksz_cfg(dev, KSZ8863_REG_SW_RESET, 145 KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, false); 146 } else if (ksz_is_ksz8463(dev)) { 147 ksz_cfg(dev, KSZ8463_REG_SW_RESET, 148 KSZ8463_GLOBAL_SOFTWARE_RESET, true); 149 ksz_cfg(dev, KSZ8463_REG_SW_RESET, 150 KSZ8463_GLOBAL_SOFTWARE_RESET, false); 151 } else { 152 /* reset switch */ 153 ksz_write8(dev, REG_POWER_MANAGEMENT_1, 154 SW_SOFTWARE_POWER_DOWN << SW_POWER_MANAGEMENT_MODE_S); 155 ksz_write8(dev, REG_POWER_MANAGEMENT_1, 0); 156 } 157 158 return 0; 159 } 160 161 static int ksz8863_change_mtu(struct ksz_device *dev, int frame_size) 162 { 163 u8 ctrl2 = 0; 164 165 if (frame_size <= KSZ8_LEGAL_PACKET_SIZE) 166 ctrl2 |= KSZ8863_LEGAL_PACKET_ENABLE; 167 else if (frame_size > KSZ8863_NORMAL_PACKET_SIZE) 168 ctrl2 |= KSZ8863_HUGE_PACKET_ENABLE; 169 170 return ksz_rmw8(dev, REG_SW_CTRL_2, KSZ8863_LEGAL_PACKET_ENABLE | 171 KSZ8863_HUGE_PACKET_ENABLE, ctrl2); 172 } 173 174 static int ksz8795_change_mtu(struct ksz_device *dev, int frame_size) 175 { 176 u8 ctrl1 = 0, ctrl2 = 0; 177 int ret; 178 179 if (frame_size > KSZ8_LEGAL_PACKET_SIZE) 180 ctrl2 |= SW_LEGAL_PACKET_DISABLE; 181 if (frame_size > KSZ8863_NORMAL_PACKET_SIZE) 182 ctrl1 |= SW_HUGE_PACKET; 183 184 ret = ksz_rmw8(dev, REG_SW_CTRL_1, SW_HUGE_PACKET, ctrl1); 185 if (ret) 186 return ret; 187 188 return ksz_rmw8(dev, REG_SW_CTRL_2, SW_LEGAL_PACKET_DISABLE, ctrl2); 189 } 190 191 static int ksz8_change_mtu(struct dsa_switch *ds, int port, int mtu) 192 { 193 struct ksz_device *dev = ds->priv; 194 u16 frame_size; 195 196 if (!dsa_is_cpu_port(dev->ds, port)) 197 return 0; 198 199 frame_size = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 200 201 switch (dev->chip_id) { 202 case KSZ8795_CHIP_ID: 203 case KSZ8794_CHIP_ID: 204 case KSZ8765_CHIP_ID: 205 return ksz8795_change_mtu(dev, frame_size); 206 case KSZ8463_CHIP_ID: 207 case KSZ88X3_CHIP_ID: 208 case KSZ8864_CHIP_ID: 209 case KSZ8895_CHIP_ID: 210 return ksz8863_change_mtu(dev, frame_size); 211 } 212 213 return -EOPNOTSUPP; 214 } 215 216 static int ksz8_port_queue_split(struct ksz_device *dev, int port, int queues) 217 { 218 u8 mask_4q, mask_2q; 219 u8 reg_4q, reg_2q; 220 u8 data_4q = 0; 221 u8 data_2q = 0; 222 int ret; 223 224 if (ksz_is_ksz88x3(dev)) { 225 mask_4q = KSZ8873_PORT_4QUEUE_SPLIT_EN; 226 mask_2q = KSZ8873_PORT_2QUEUE_SPLIT_EN; 227 reg_4q = REG_PORT_CTRL_0; 228 reg_2q = REG_PORT_CTRL_2; 229 230 /* KSZ8795 family switches have Weighted Fair Queueing (WFQ) 231 * enabled by default. Enable it for KSZ8873 family switches 232 * too. Default value for KSZ8873 family is strict priority, 233 * which should be enabled by using TC_SETUP_QDISC_ETS, not 234 * by default. 235 */ 236 ret = ksz_rmw8(dev, REG_SW_CTRL_3, WEIGHTED_FAIR_QUEUE_ENABLE, 237 WEIGHTED_FAIR_QUEUE_ENABLE); 238 if (ret) 239 return ret; 240 } else if (ksz_is_ksz8463(dev)) { 241 mask_4q = KSZ8873_PORT_4QUEUE_SPLIT_EN; 242 mask_2q = KSZ8873_PORT_2QUEUE_SPLIT_EN; 243 reg_4q = P1CR1; 244 reg_2q = P1CR1 + 1; 245 } else { 246 mask_4q = KSZ8795_PORT_4QUEUE_SPLIT_EN; 247 mask_2q = KSZ8795_PORT_2QUEUE_SPLIT_EN; 248 reg_4q = REG_PORT_CTRL_13; 249 reg_2q = REG_PORT_CTRL_0; 250 251 /* TODO: this is legacy from initial KSZ8795 driver, should be 252 * moved to appropriate place in the future. 253 */ 254 ret = ksz_rmw8(dev, REG_SW_CTRL_19, 255 SW_OUT_RATE_LIMIT_QUEUE_BASED, 256 SW_OUT_RATE_LIMIT_QUEUE_BASED); 257 if (ret) 258 return ret; 259 } 260 261 if (queues == 4) 262 data_4q = mask_4q; 263 else if (queues == 2) 264 data_2q = mask_2q; 265 266 ret = ksz_prmw8(dev, port, reg_4q, mask_4q, data_4q); 267 if (ret) 268 return ret; 269 270 return ksz_prmw8(dev, port, reg_2q, mask_2q, data_2q); 271 } 272 273 static void ksz8_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, u64 *cnt) 274 { 275 const u32 *masks; 276 const u16 *regs; 277 u16 ctrl_addr; 278 u32 data; 279 u8 check; 280 int loop; 281 282 masks = dev->info->masks; 283 regs = dev->info->regs; 284 285 ctrl_addr = addr + dev->info->reg_mib_cnt * port; 286 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ); 287 288 mutex_lock(&dev->alu_mutex); 289 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 290 291 /* It is almost guaranteed to always read the valid bit because of 292 * slow SPI speed. 293 */ 294 for (loop = 2; loop > 0; loop--) { 295 ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check); 296 297 if (check & masks[MIB_COUNTER_VALID]) { 298 ksz_read32(dev, regs[REG_IND_DATA_LO], &data); 299 if (check & masks[MIB_COUNTER_OVERFLOW]) 300 *cnt += MIB_COUNTER_VALUE + 1; 301 *cnt += data & MIB_COUNTER_VALUE; 302 break; 303 } 304 } 305 mutex_unlock(&dev->alu_mutex); 306 } 307 308 static void ksz8795_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 309 u64 *dropped, u64 *cnt) 310 { 311 const u32 *masks; 312 const u16 *regs; 313 u16 ctrl_addr; 314 u32 data; 315 u8 check; 316 int loop; 317 318 masks = dev->info->masks; 319 regs = dev->info->regs; 320 321 addr -= dev->info->reg_mib_cnt; 322 ctrl_addr = (KSZ8795_MIB_TOTAL_RX_1 - KSZ8795_MIB_TOTAL_RX_0) * port; 323 ctrl_addr += addr + KSZ8795_MIB_TOTAL_RX_0; 324 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ); 325 326 mutex_lock(&dev->alu_mutex); 327 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 328 329 /* It is almost guaranteed to always read the valid bit because of 330 * slow SPI speed. 331 */ 332 for (loop = 2; loop > 0; loop--) { 333 ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check); 334 335 if (check & masks[MIB_COUNTER_VALID]) { 336 ksz_read32(dev, regs[REG_IND_DATA_LO], &data); 337 if (addr < 2) { 338 u64 total; 339 340 total = check & MIB_TOTAL_BYTES_H; 341 total <<= 32; 342 *cnt += total; 343 *cnt += data; 344 if (check & masks[MIB_COUNTER_OVERFLOW]) { 345 total = MIB_TOTAL_BYTES_H + 1; 346 total <<= 32; 347 *cnt += total; 348 } 349 } else { 350 if (check & masks[MIB_COUNTER_OVERFLOW]) 351 *cnt += MIB_PACKET_DROPPED + 1; 352 *cnt += data & MIB_PACKET_DROPPED; 353 } 354 break; 355 } 356 } 357 mutex_unlock(&dev->alu_mutex); 358 } 359 360 static void ksz8863_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 361 u64 *dropped, u64 *cnt) 362 { 363 u32 *last = (u32 *)dropped; 364 const u16 *regs; 365 u16 ctrl_addr; 366 u32 data; 367 u32 cur; 368 369 regs = dev->info->regs; 370 371 addr -= dev->info->reg_mib_cnt; 372 ctrl_addr = addr ? KSZ8863_MIB_PACKET_DROPPED_TX_0 : 373 KSZ8863_MIB_PACKET_DROPPED_RX_0; 374 if (ksz_is_8895_family(dev) && 375 ctrl_addr == KSZ8863_MIB_PACKET_DROPPED_RX_0) 376 ctrl_addr = KSZ8895_MIB_PACKET_DROPPED_RX_0; 377 ctrl_addr += port; 378 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ); 379 380 mutex_lock(&dev->alu_mutex); 381 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 382 ksz_read32(dev, regs[REG_IND_DATA_LO], &data); 383 mutex_unlock(&dev->alu_mutex); 384 385 data &= MIB_PACKET_DROPPED; 386 cur = last[addr]; 387 if (data != cur) { 388 last[addr] = data; 389 if (data < cur) 390 data += MIB_PACKET_DROPPED + 1; 391 data -= cur; 392 *cnt += data; 393 } 394 } 395 396 static void ksz8_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 397 u64 *dropped, u64 *cnt) 398 { 399 if (is_ksz88xx(dev)) 400 ksz8863_r_mib_pkt(dev, port, addr, dropped, cnt); 401 else 402 ksz8795_r_mib_pkt(dev, port, addr, dropped, cnt); 403 } 404 405 static void ksz8_freeze_mib(struct ksz_device *dev, int port, bool freeze) 406 { 407 if (is_ksz88xx(dev)) 408 return; 409 410 /* enable the port for flush/freeze function */ 411 if (freeze) 412 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true); 413 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FREEZE, freeze); 414 415 /* disable the port after freeze is done */ 416 if (!freeze) 417 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false); 418 } 419 420 static void ksz8_port_init_cnt(struct ksz_device *dev, int port) 421 { 422 struct ksz_port_mib *mib = &dev->ports[port].mib; 423 u64 *dropped; 424 425 /* For KSZ8795 family. */ 426 if (ksz_is_ksz87xx(dev)) { 427 /* flush all enabled port MIB counters */ 428 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true); 429 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FLUSH, true); 430 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false); 431 } 432 433 mib->cnt_ptr = 0; 434 435 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 436 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 437 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 438 &mib->counters[mib->cnt_ptr]); 439 ++mib->cnt_ptr; 440 } 441 442 /* last one in storage */ 443 dropped = &mib->counters[dev->info->mib_cnt]; 444 445 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 446 while (mib->cnt_ptr < dev->info->mib_cnt) { 447 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 448 dropped, &mib->counters[mib->cnt_ptr]); 449 ++mib->cnt_ptr; 450 } 451 } 452 453 static int ksz8_r_table(struct ksz_device *dev, int table, u16 addr, u64 *data) 454 { 455 const u16 *regs; 456 u16 ctrl_addr; 457 int ret; 458 459 regs = dev->info->regs; 460 461 ctrl_addr = IND_ACC_TABLE(table | TABLE_READ) | addr; 462 463 mutex_lock(&dev->alu_mutex); 464 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 465 if (ret) 466 goto unlock_alu; 467 468 ret = ksz_read64(dev, regs[REG_IND_DATA_HI], data); 469 unlock_alu: 470 mutex_unlock(&dev->alu_mutex); 471 472 return ret; 473 } 474 475 static int ksz8_w_table(struct ksz_device *dev, int table, u16 addr, u64 data) 476 { 477 const u16 *regs; 478 u16 ctrl_addr; 479 int ret; 480 481 regs = dev->info->regs; 482 483 ctrl_addr = IND_ACC_TABLE(table) | addr; 484 485 mutex_lock(&dev->alu_mutex); 486 ret = ksz_write64(dev, regs[REG_IND_DATA_HI], data); 487 if (ret) 488 goto unlock_alu; 489 490 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 491 unlock_alu: 492 mutex_unlock(&dev->alu_mutex); 493 494 return ret; 495 } 496 497 static int ksz8_valid_dyn_entry(struct ksz_device *dev, u8 *data) 498 { 499 int timeout = 100; 500 const u32 *masks; 501 const u16 *regs; 502 int ret; 503 504 masks = dev->info->masks; 505 regs = dev->info->regs; 506 507 do { 508 ret = ksz_read8(dev, regs[REG_IND_DATA_CHECK], data); 509 if (ret) 510 return ret; 511 512 timeout--; 513 } while ((*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) && timeout); 514 515 /* Entry is not ready for accessing. */ 516 if (*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) 517 return -ETIMEDOUT; 518 519 /* Entry is ready for accessing. */ 520 return ksz_read8(dev, regs[REG_IND_DATA_8], data); 521 } 522 523 static int ksz8_r_dyn_mac_table(struct ksz_device *dev, u16 addr, u8 *mac_addr, 524 u8 *fid, u8 *src_port, u16 *entries) 525 { 526 u32 data_hi, data_lo; 527 const u8 *shifts; 528 const u32 *masks; 529 const u16 *regs; 530 u16 ctrl_addr; 531 u64 buf = 0; 532 u8 data; 533 int cnt; 534 int ret; 535 536 shifts = dev->info->shifts; 537 masks = dev->info->masks; 538 regs = dev->info->regs; 539 540 ctrl_addr = IND_ACC_TABLE(TABLE_DYNAMIC_MAC | TABLE_READ) | addr; 541 542 mutex_lock(&dev->alu_mutex); 543 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 544 if (ret) 545 goto unlock_alu; 546 547 ret = ksz8_valid_dyn_entry(dev, &data); 548 if (ret) 549 goto unlock_alu; 550 551 if (data & masks[DYNAMIC_MAC_TABLE_MAC_EMPTY]) { 552 *entries = 0; 553 goto unlock_alu; 554 } 555 556 ret = ksz_read64(dev, regs[REG_IND_DATA_HI], &buf); 557 if (ret) 558 goto unlock_alu; 559 560 data_hi = (u32)(buf >> 32); 561 data_lo = (u32)buf; 562 563 /* Check out how many valid entry in the table. */ 564 cnt = data & masks[DYNAMIC_MAC_TABLE_ENTRIES_H]; 565 cnt <<= shifts[DYNAMIC_MAC_ENTRIES_H]; 566 cnt |= (data_hi & masks[DYNAMIC_MAC_TABLE_ENTRIES]) >> 567 shifts[DYNAMIC_MAC_ENTRIES]; 568 *entries = cnt + 1; 569 570 *fid = (data_hi & masks[DYNAMIC_MAC_TABLE_FID]) >> 571 shifts[DYNAMIC_MAC_FID]; 572 *src_port = (data_hi & masks[DYNAMIC_MAC_TABLE_SRC_PORT]) >> 573 shifts[DYNAMIC_MAC_SRC_PORT]; 574 575 mac_addr[5] = (u8)data_lo; 576 mac_addr[4] = (u8)(data_lo >> 8); 577 mac_addr[3] = (u8)(data_lo >> 16); 578 mac_addr[2] = (u8)(data_lo >> 24); 579 580 mac_addr[1] = (u8)data_hi; 581 mac_addr[0] = (u8)(data_hi >> 8); 582 583 unlock_alu: 584 mutex_unlock(&dev->alu_mutex); 585 586 return ret; 587 } 588 589 static int ksz8_r_sta_mac_table(struct ksz_device *dev, u16 addr, 590 struct alu_struct *alu, bool *valid) 591 { 592 u32 data_hi, data_lo; 593 const u8 *shifts; 594 const u32 *masks; 595 u64 data; 596 int ret; 597 598 shifts = dev->info->shifts; 599 masks = dev->info->masks; 600 601 ret = ksz8_r_table(dev, TABLE_STATIC_MAC, addr, &data); 602 if (ret) 603 return ret; 604 605 data_hi = data >> 32; 606 data_lo = (u32)data; 607 608 if (!(data_hi & (masks[STATIC_MAC_TABLE_VALID] | 609 masks[STATIC_MAC_TABLE_OVERRIDE]))) { 610 *valid = false; 611 return 0; 612 } 613 614 alu->mac[5] = (u8)data_lo; 615 alu->mac[4] = (u8)(data_lo >> 8); 616 alu->mac[3] = (u8)(data_lo >> 16); 617 alu->mac[2] = (u8)(data_lo >> 24); 618 alu->mac[1] = (u8)data_hi; 619 alu->mac[0] = (u8)(data_hi >> 8); 620 alu->port_forward = 621 (data_hi & masks[STATIC_MAC_TABLE_FWD_PORTS]) >> 622 shifts[STATIC_MAC_FWD_PORTS]; 623 alu->is_override = (data_hi & masks[STATIC_MAC_TABLE_OVERRIDE]) ? 1 : 0; 624 625 /* KSZ8795/KSZ8895 family switches have STATIC_MAC_TABLE_USE_FID and 626 * STATIC_MAC_TABLE_FID definitions off by 1 when doing read on the 627 * static MAC table compared to doing write. 628 */ 629 if (ksz_is_ksz87xx(dev) || ksz_is_8895_family(dev)) 630 data_hi >>= 1; 631 alu->is_static = true; 632 alu->is_use_fid = (data_hi & masks[STATIC_MAC_TABLE_USE_FID]) ? 1 : 0; 633 alu->fid = (data_hi & masks[STATIC_MAC_TABLE_FID]) >> 634 shifts[STATIC_MAC_FID]; 635 636 *valid = true; 637 638 return 0; 639 } 640 641 static int ksz8_w_sta_mac_table(struct ksz_device *dev, u16 addr, 642 struct alu_struct *alu) 643 { 644 u32 data_hi, data_lo; 645 const u8 *shifts; 646 const u32 *masks; 647 u64 data; 648 649 shifts = dev->info->shifts; 650 masks = dev->info->masks; 651 652 data_lo = ((u32)alu->mac[2] << 24) | 653 ((u32)alu->mac[3] << 16) | 654 ((u32)alu->mac[4] << 8) | alu->mac[5]; 655 data_hi = ((u32)alu->mac[0] << 8) | alu->mac[1]; 656 data_hi |= (u32)alu->port_forward << shifts[STATIC_MAC_FWD_PORTS]; 657 658 if (alu->is_override) 659 data_hi |= masks[STATIC_MAC_TABLE_OVERRIDE]; 660 if (alu->is_use_fid) { 661 data_hi |= masks[STATIC_MAC_TABLE_USE_FID]; 662 data_hi |= (u32)alu->fid << shifts[STATIC_MAC_FID]; 663 } 664 if (alu->is_static) 665 data_hi |= masks[STATIC_MAC_TABLE_VALID]; 666 else 667 data_hi &= ~masks[STATIC_MAC_TABLE_OVERRIDE]; 668 669 data = (u64)data_hi << 32 | data_lo; 670 671 return ksz8_w_table(dev, TABLE_STATIC_MAC, addr, data); 672 } 673 674 static void ksz8_from_vlan(struct ksz_device *dev, u32 vlan, u8 *fid, 675 u8 *member, u8 *valid) 676 { 677 const u8 *shifts; 678 const u32 *masks; 679 680 shifts = dev->info->shifts; 681 masks = dev->info->masks; 682 683 *fid = vlan & masks[VLAN_TABLE_FID]; 684 *member = (vlan & masks[VLAN_TABLE_MEMBERSHIP]) >> 685 shifts[VLAN_TABLE_MEMBERSHIP_S]; 686 *valid = !!(vlan & masks[VLAN_TABLE_VALID]); 687 } 688 689 static void ksz8_to_vlan(struct ksz_device *dev, u8 fid, u8 member, u8 valid, 690 u16 *vlan) 691 { 692 const u8 *shifts; 693 const u32 *masks; 694 695 shifts = dev->info->shifts; 696 masks = dev->info->masks; 697 698 *vlan = fid; 699 *vlan |= (u16)member << shifts[VLAN_TABLE_MEMBERSHIP_S]; 700 if (valid) 701 *vlan |= masks[VLAN_TABLE_VALID]; 702 } 703 704 static void ksz8_r_vlan_entries(struct ksz_device *dev, u16 addr) 705 { 706 const u8 *shifts; 707 u64 data; 708 int i; 709 710 shifts = dev->info->shifts; 711 712 ksz8_r_table(dev, TABLE_VLAN, addr, &data); 713 addr *= 4; 714 for (i = 0; i < 4; i++) { 715 dev->vlan_cache[addr + i].table[0] = (u16)data; 716 data >>= shifts[VLAN_TABLE]; 717 } 718 } 719 720 static void ksz8_r_vlan_table(struct ksz_device *dev, u16 vid, u16 *vlan) 721 { 722 int index; 723 u16 *data; 724 u16 addr; 725 u64 buf; 726 727 data = (u16 *)&buf; 728 addr = vid / 4; 729 index = vid & 3; 730 ksz8_r_table(dev, TABLE_VLAN, addr, &buf); 731 *vlan = data[index]; 732 } 733 734 static void ksz8_w_vlan_table(struct ksz_device *dev, u16 vid, u16 vlan) 735 { 736 int index; 737 u16 *data; 738 u16 addr; 739 u64 buf; 740 741 data = (u16 *)&buf; 742 addr = vid / 4; 743 index = vid & 3; 744 ksz8_r_table(dev, TABLE_VLAN, addr, &buf); 745 data[index] = vlan; 746 dev->vlan_cache[vid].table[0] = vlan; 747 ksz8_w_table(dev, TABLE_VLAN, addr, buf); 748 } 749 750 /** 751 * ksz879x_get_loopback - KSZ879x specific function to get loopback 752 * configuration status for a specific port 753 * @dev: Pointer to the device structure 754 * @port: Port number to query 755 * @val: Pointer to store the result 756 * 757 * This function reads the SMI registers to determine whether loopback mode 758 * is enabled for a specific port. 759 * 760 * Return: 0 on success, error code on failure. 761 */ 762 static int ksz879x_get_loopback(struct ksz_device *dev, u16 port, 763 u16 *val) 764 { 765 u8 stat3; 766 int ret; 767 768 ret = ksz_pread8(dev, port, REG_PORT_STATUS_3, &stat3); 769 if (ret) 770 return ret; 771 772 if (stat3 & PORT_PHY_LOOPBACK) 773 *val |= BMCR_LOOPBACK; 774 775 return 0; 776 } 777 778 /** 779 * ksz879x_set_loopback - KSZ879x specific function to set loopback mode for 780 * a specific port 781 * @dev: Pointer to the device structure. 782 * @port: Port number to modify. 783 * @val: Value indicating whether to enable or disable loopback mode. 784 * 785 * This function translates loopback bit of the BMCR register into the 786 * corresponding hardware register bit value and writes it to the SMI interface. 787 * 788 * Return: 0 on success, error code on failure. 789 */ 790 static int ksz879x_set_loopback(struct ksz_device *dev, u16 port, u16 val) 791 { 792 u8 stat3 = 0; 793 794 if (val & BMCR_LOOPBACK) 795 stat3 |= PORT_PHY_LOOPBACK; 796 797 return ksz_prmw8(dev, port, REG_PORT_STATUS_3, PORT_PHY_LOOPBACK, 798 stat3); 799 } 800 801 /** 802 * ksz8_r_phy_ctrl - Translates and reads from the SMI interface to a MIIM PHY 803 * Control register (Reg. 31). 804 * @dev: The KSZ device instance. 805 * @port: The port number to be read. 806 * @val: The value read from the SMI interface. 807 * 808 * This function reads the SMI interface and translates the hardware register 809 * bit values into their corresponding control settings for a MIIM PHY Control 810 * register. 811 * 812 * Return: 0 on success, error code on failure. 813 */ 814 static int ksz8_r_phy_ctrl(struct ksz_device *dev, int port, u16 *val) 815 { 816 const u16 *regs = dev->info->regs; 817 u8 reg_val; 818 int ret; 819 820 *val = 0; 821 822 ret = ksz_pread8(dev, port, regs[P_LINK_STATUS], ®_val); 823 if (ret < 0) 824 return ret; 825 826 if (reg_val & PORT_MDIX_STATUS) 827 *val |= KSZ886X_CTRL_MDIX_STAT; 828 829 ret = ksz_pread8(dev, port, REG_PORT_LINK_MD_CTRL, ®_val); 830 if (ret < 0) 831 return ret; 832 833 if (reg_val & PORT_FORCE_LINK) 834 *val |= KSZ886X_CTRL_FORCE_LINK; 835 836 if (reg_val & PORT_POWER_SAVING) 837 *val |= KSZ886X_CTRL_PWRSAVE; 838 839 if (reg_val & PORT_PHY_REMOTE_LOOPBACK) 840 *val |= KSZ886X_CTRL_REMOTE_LOOPBACK; 841 842 return 0; 843 } 844 845 /** 846 * ksz8_r_phy_bmcr - Translates and reads from the SMI interface to a MIIM PHY 847 * Basic mode control register (Reg. 0). 848 * @dev: The KSZ device instance. 849 * @port: The port number to be read. 850 * @val: The value read from the SMI interface. 851 * 852 * This function reads the SMI interface and translates the hardware register 853 * bit values into their corresponding control settings for a MIIM PHY Basic 854 * mode control register. 855 * 856 * MIIM Bit Mapping Comparison between KSZ8794 and KSZ8873 857 * ------------------------------------------------------------------- 858 * MIIM Bit | KSZ8794 Reg/Bit | KSZ8873 Reg/Bit 859 * ----------------------------+-----------------------------+---------------- 860 * Bit 15 - Soft Reset | 0xF/4 | Not supported 861 * Bit 14 - Loopback | 0xD/0 (MAC), 0xF/7 (PHY) ~ 0xD/0 (PHY) 862 * Bit 13 - Force 100 | 0xC/6 = 0xC/6 863 * Bit 12 - AN Enable | 0xC/7 (reverse logic) ~ 0xC/7 864 * Bit 11 - Power Down | 0xD/3 = 0xD/3 865 * Bit 10 - PHY Isolate | 0xF/5 | Not supported 866 * Bit 9 - Restart AN | 0xD/5 = 0xD/5 867 * Bit 8 - Force Full-Duplex | 0xC/5 = 0xC/5 868 * Bit 7 - Collision Test/Res. | Not supported | Not supported 869 * Bit 6 - Reserved | Not supported | Not supported 870 * Bit 5 - Hp_mdix | 0x9/7 ~ 0xF/7 871 * Bit 4 - Force MDI | 0xD/1 = 0xD/1 872 * Bit 3 - Disable MDIX | 0xD/2 = 0xD/2 873 * Bit 2 - Disable Far-End F. | ???? | 0xD/4 874 * Bit 1 - Disable Transmit | 0xD/6 = 0xD/6 875 * Bit 0 - Disable LED | 0xD/7 = 0xD/7 876 * ------------------------------------------------------------------- 877 * 878 * Return: 0 on success, error code on failure. 879 */ 880 static int ksz8_r_phy_bmcr(struct ksz_device *dev, u16 port, u16 *val) 881 { 882 const u16 *regs = dev->info->regs; 883 u8 restart, speed, ctrl; 884 int ret; 885 886 *val = 0; 887 888 ret = ksz_pread8(dev, port, regs[P_NEG_RESTART_CTRL], &restart); 889 if (ret) 890 return ret; 891 892 ret = ksz_pread8(dev, port, regs[P_SPEED_STATUS], &speed); 893 if (ret) 894 return ret; 895 896 ret = ksz_pread8(dev, port, regs[P_FORCE_CTRL], &ctrl); 897 if (ret) 898 return ret; 899 900 if (ctrl & PORT_FORCE_100_MBIT) 901 *val |= BMCR_SPEED100; 902 903 if (ksz_is_ksz88x3(dev)) { 904 if (restart & KSZ8873_PORT_PHY_LOOPBACK) 905 *val |= BMCR_LOOPBACK; 906 907 if ((ctrl & PORT_AUTO_NEG_ENABLE)) 908 *val |= BMCR_ANENABLE; 909 } else { 910 ret = ksz879x_get_loopback(dev, port, val); 911 if (ret) 912 return ret; 913 914 if (!(ctrl & PORT_AUTO_NEG_DISABLE)) 915 *val |= BMCR_ANENABLE; 916 } 917 918 if (restart & PORT_POWER_DOWN) 919 *val |= BMCR_PDOWN; 920 921 if (restart & PORT_AUTO_NEG_RESTART) 922 *val |= BMCR_ANRESTART; 923 924 if (ctrl & PORT_FORCE_FULL_DUPLEX) 925 *val |= BMCR_FULLDPLX; 926 927 if (speed & PORT_HP_MDIX) 928 *val |= KSZ886X_BMCR_HP_MDIX; 929 930 if (restart & PORT_FORCE_MDIX) 931 *val |= KSZ886X_BMCR_FORCE_MDI; 932 933 if (restart & PORT_AUTO_MDIX_DISABLE) 934 *val |= KSZ886X_BMCR_DISABLE_AUTO_MDIX; 935 936 if (restart & PORT_TX_DISABLE) 937 *val |= KSZ886X_BMCR_DISABLE_TRANSMIT; 938 939 if (restart & PORT_LED_OFF) 940 *val |= KSZ886X_BMCR_DISABLE_LED; 941 942 return 0; 943 } 944 945 static int ksz8_r_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 *val) 946 { 947 u8 ctrl, link, val1, val2; 948 int processed = true; 949 const u16 *regs; 950 u16 data = 0; 951 u16 p = phy; 952 int ret; 953 954 regs = dev->info->regs; 955 956 switch (reg) { 957 case MII_BMCR: 958 ret = ksz8_r_phy_bmcr(dev, p, &data); 959 if (ret) 960 return ret; 961 break; 962 case MII_BMSR: 963 ret = ksz_pread8(dev, p, regs[P_LINK_STATUS], &link); 964 if (ret) 965 return ret; 966 967 data = BMSR_100FULL | 968 BMSR_100HALF | 969 BMSR_10FULL | 970 BMSR_10HALF | 971 BMSR_ANEGCAPABLE; 972 if (link & PORT_AUTO_NEG_COMPLETE) 973 data |= BMSR_ANEGCOMPLETE; 974 if (link & PORT_STAT_LINK_GOOD) 975 data |= BMSR_LSTATUS; 976 break; 977 case MII_PHYSID1: 978 data = KSZ8795_ID_HI; 979 break; 980 case MII_PHYSID2: 981 if (ksz_is_ksz88x3(dev)) 982 data = KSZ8863_ID_LO; 983 else 984 data = KSZ8795_ID_LO; 985 break; 986 case MII_ADVERTISE: 987 ret = ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl); 988 if (ret) 989 return ret; 990 991 data = ADVERTISE_CSMA; 992 if (ctrl & PORT_AUTO_NEG_SYM_PAUSE) 993 data |= ADVERTISE_PAUSE_CAP; 994 if (ctrl & PORT_AUTO_NEG_100BTX_FD) 995 data |= ADVERTISE_100FULL; 996 if (ctrl & PORT_AUTO_NEG_100BTX) 997 data |= ADVERTISE_100HALF; 998 if (ctrl & PORT_AUTO_NEG_10BT_FD) 999 data |= ADVERTISE_10FULL; 1000 if (ctrl & PORT_AUTO_NEG_10BT) 1001 data |= ADVERTISE_10HALF; 1002 break; 1003 case MII_LPA: 1004 ret = ksz_pread8(dev, p, regs[P_REMOTE_STATUS], &link); 1005 if (ret) 1006 return ret; 1007 1008 data = LPA_SLCT; 1009 if (link & PORT_REMOTE_SYM_PAUSE) 1010 data |= LPA_PAUSE_CAP; 1011 if (link & PORT_REMOTE_100BTX_FD) 1012 data |= LPA_100FULL; 1013 if (link & PORT_REMOTE_100BTX) 1014 data |= LPA_100HALF; 1015 if (link & PORT_REMOTE_10BT_FD) 1016 data |= LPA_10FULL; 1017 if (link & PORT_REMOTE_10BT) 1018 data |= LPA_10HALF; 1019 if (data & ~LPA_SLCT) 1020 data |= LPA_LPACK; 1021 break; 1022 case PHY_REG_LINK_MD: 1023 ret = ksz_pread8(dev, p, REG_PORT_LINK_MD_CTRL, &val1); 1024 if (ret) 1025 return ret; 1026 1027 ret = ksz_pread8(dev, p, REG_PORT_LINK_MD_RESULT, &val2); 1028 if (ret) 1029 return ret; 1030 1031 if (val1 & PORT_START_CABLE_DIAG) 1032 data |= PHY_START_CABLE_DIAG; 1033 1034 if (val1 & PORT_CABLE_10M_SHORT) 1035 data |= PHY_CABLE_10M_SHORT; 1036 1037 data |= FIELD_PREP(PHY_CABLE_DIAG_RESULT_M, 1038 FIELD_GET(PORT_CABLE_DIAG_RESULT_M, val1)); 1039 1040 data |= FIELD_PREP(PHY_CABLE_FAULT_COUNTER_M, 1041 (FIELD_GET(PORT_CABLE_FAULT_COUNTER_H, val1) << 8) | 1042 FIELD_GET(PORT_CABLE_FAULT_COUNTER_L, val2)); 1043 break; 1044 case PHY_REG_PHY_CTRL: 1045 ret = ksz8_r_phy_ctrl(dev, p, &data); 1046 if (ret) 1047 return ret; 1048 1049 break; 1050 default: 1051 processed = false; 1052 break; 1053 } 1054 if (processed) 1055 *val = data; 1056 1057 return 0; 1058 } 1059 1060 /** 1061 * ksz8_w_phy_ctrl - Translates and writes to the SMI interface from a MIIM PHY 1062 * Control register (Reg. 31). 1063 * @dev: The KSZ device instance. 1064 * @port: The port number to be configured. 1065 * @val: The register value to be written. 1066 * 1067 * This function translates control settings from a MIIM PHY Control register 1068 * into their corresponding hardware register bit values for the SMI 1069 * interface. 1070 * 1071 * Return: 0 on success, error code on failure. 1072 */ 1073 static int ksz8_w_phy_ctrl(struct ksz_device *dev, int port, u16 val) 1074 { 1075 u8 reg_val = 0; 1076 int ret; 1077 1078 if (val & KSZ886X_CTRL_FORCE_LINK) 1079 reg_val |= PORT_FORCE_LINK; 1080 1081 if (val & KSZ886X_CTRL_PWRSAVE) 1082 reg_val |= PORT_POWER_SAVING; 1083 1084 if (val & KSZ886X_CTRL_REMOTE_LOOPBACK) 1085 reg_val |= PORT_PHY_REMOTE_LOOPBACK; 1086 1087 ret = ksz_prmw8(dev, port, REG_PORT_LINK_MD_CTRL, PORT_FORCE_LINK | 1088 PORT_POWER_SAVING | PORT_PHY_REMOTE_LOOPBACK, reg_val); 1089 return ret; 1090 } 1091 1092 /** 1093 * ksz8_w_phy_bmcr - Translates and writes to the SMI interface from a MIIM PHY 1094 * Basic mode control register (Reg. 0). 1095 * @dev: The KSZ device instance. 1096 * @port: The port number to be configured. 1097 * @val: The register value to be written. 1098 * 1099 * This function translates control settings from a MIIM PHY Basic mode control 1100 * register into their corresponding hardware register bit values for the SMI 1101 * interface. 1102 * 1103 * MIIM Bit Mapping Comparison between KSZ8794 and KSZ8873 1104 * ------------------------------------------------------------------- 1105 * MIIM Bit | KSZ8794 Reg/Bit | KSZ8873 Reg/Bit 1106 * ----------------------------+-----------------------------+---------------- 1107 * Bit 15 - Soft Reset | 0xF/4 | Not supported 1108 * Bit 14 - Loopback | 0xD/0 (MAC), 0xF/7 (PHY) ~ 0xD/0 (PHY) 1109 * Bit 13 - Force 100 | 0xC/6 = 0xC/6 1110 * Bit 12 - AN Enable | 0xC/7 (reverse logic) ~ 0xC/7 1111 * Bit 11 - Power Down | 0xD/3 = 0xD/3 1112 * Bit 10 - PHY Isolate | 0xF/5 | Not supported 1113 * Bit 9 - Restart AN | 0xD/5 = 0xD/5 1114 * Bit 8 - Force Full-Duplex | 0xC/5 = 0xC/5 1115 * Bit 7 - Collision Test/Res. | Not supported | Not supported 1116 * Bit 6 - Reserved | Not supported | Not supported 1117 * Bit 5 - Hp_mdix | 0x9/7 ~ 0xF/7 1118 * Bit 4 - Force MDI | 0xD/1 = 0xD/1 1119 * Bit 3 - Disable MDIX | 0xD/2 = 0xD/2 1120 * Bit 2 - Disable Far-End F. | ???? | 0xD/4 1121 * Bit 1 - Disable Transmit | 0xD/6 = 0xD/6 1122 * Bit 0 - Disable LED | 0xD/7 = 0xD/7 1123 * ------------------------------------------------------------------- 1124 * 1125 * Return: 0 on success, error code on failure. 1126 */ 1127 static int ksz8_w_phy_bmcr(struct ksz_device *dev, u16 port, u16 val) 1128 { 1129 u8 restart, speed, ctrl, restart_mask; 1130 const u16 *regs = dev->info->regs; 1131 int ret; 1132 1133 /* Do not support PHY reset function. */ 1134 if (val & BMCR_RESET) 1135 return 0; 1136 1137 speed = 0; 1138 if (val & KSZ886X_BMCR_HP_MDIX) 1139 speed |= PORT_HP_MDIX; 1140 1141 ret = ksz_prmw8(dev, port, regs[P_SPEED_STATUS], PORT_HP_MDIX, speed); 1142 if (ret) 1143 return ret; 1144 1145 ctrl = 0; 1146 if (ksz_is_ksz88x3(dev)) { 1147 if ((val & BMCR_ANENABLE)) 1148 ctrl |= PORT_AUTO_NEG_ENABLE; 1149 } else { 1150 if (!(val & BMCR_ANENABLE)) 1151 ctrl |= PORT_AUTO_NEG_DISABLE; 1152 1153 /* Fiber port does not support auto-negotiation. */ 1154 if (dev->ports[port].fiber) 1155 ctrl |= PORT_AUTO_NEG_DISABLE; 1156 } 1157 1158 if (val & BMCR_SPEED100) 1159 ctrl |= PORT_FORCE_100_MBIT; 1160 1161 if (val & BMCR_FULLDPLX) 1162 ctrl |= PORT_FORCE_FULL_DUPLEX; 1163 1164 ret = ksz_prmw8(dev, port, regs[P_FORCE_CTRL], PORT_FORCE_100_MBIT | 1165 /* PORT_AUTO_NEG_ENABLE and PORT_AUTO_NEG_DISABLE are the same 1166 * bits 1167 */ 1168 PORT_FORCE_FULL_DUPLEX | PORT_AUTO_NEG_ENABLE, ctrl); 1169 if (ret) 1170 return ret; 1171 1172 restart = 0; 1173 restart_mask = PORT_LED_OFF | PORT_TX_DISABLE | PORT_AUTO_NEG_RESTART | 1174 PORT_POWER_DOWN | PORT_AUTO_MDIX_DISABLE | PORT_FORCE_MDIX; 1175 1176 if (val & KSZ886X_BMCR_DISABLE_LED) 1177 restart |= PORT_LED_OFF; 1178 1179 if (val & KSZ886X_BMCR_DISABLE_TRANSMIT) 1180 restart |= PORT_TX_DISABLE; 1181 1182 if (val & BMCR_ANRESTART) 1183 restart |= PORT_AUTO_NEG_RESTART; 1184 1185 if (val & BMCR_PDOWN) 1186 restart |= PORT_POWER_DOWN; 1187 1188 if (val & KSZ886X_BMCR_DISABLE_AUTO_MDIX) 1189 restart |= PORT_AUTO_MDIX_DISABLE; 1190 1191 if (val & KSZ886X_BMCR_FORCE_MDI) 1192 restart |= PORT_FORCE_MDIX; 1193 1194 if (ksz_is_ksz88x3(dev)) { 1195 restart_mask |= KSZ8873_PORT_PHY_LOOPBACK; 1196 1197 if (val & BMCR_LOOPBACK) 1198 restart |= KSZ8873_PORT_PHY_LOOPBACK; 1199 } else { 1200 ret = ksz879x_set_loopback(dev, port, val); 1201 if (ret) 1202 return ret; 1203 } 1204 1205 return ksz_prmw8(dev, port, regs[P_NEG_RESTART_CTRL], restart_mask, 1206 restart); 1207 } 1208 1209 static int ksz8_w_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 val) 1210 { 1211 const u16 *regs; 1212 u8 ctrl, data; 1213 u16 p = phy; 1214 int ret; 1215 1216 regs = dev->info->regs; 1217 1218 switch (reg) { 1219 case MII_BMCR: 1220 ret = ksz8_w_phy_bmcr(dev, p, val); 1221 if (ret) 1222 return ret; 1223 break; 1224 case MII_ADVERTISE: 1225 ret = ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl); 1226 if (ret) 1227 return ret; 1228 1229 data = ctrl; 1230 data &= ~(PORT_AUTO_NEG_SYM_PAUSE | 1231 PORT_AUTO_NEG_100BTX_FD | 1232 PORT_AUTO_NEG_100BTX | 1233 PORT_AUTO_NEG_10BT_FD | 1234 PORT_AUTO_NEG_10BT); 1235 if (val & ADVERTISE_PAUSE_CAP) 1236 data |= PORT_AUTO_NEG_SYM_PAUSE; 1237 if (val & ADVERTISE_100FULL) 1238 data |= PORT_AUTO_NEG_100BTX_FD; 1239 if (val & ADVERTISE_100HALF) 1240 data |= PORT_AUTO_NEG_100BTX; 1241 if (val & ADVERTISE_10FULL) 1242 data |= PORT_AUTO_NEG_10BT_FD; 1243 if (val & ADVERTISE_10HALF) 1244 data |= PORT_AUTO_NEG_10BT; 1245 1246 if (data != ctrl) { 1247 ret = ksz_pwrite8(dev, p, regs[P_LOCAL_CTRL], data); 1248 if (ret) 1249 return ret; 1250 } 1251 break; 1252 case PHY_REG_LINK_MD: 1253 if (val & PHY_START_CABLE_DIAG) 1254 ksz_port_cfg(dev, p, REG_PORT_LINK_MD_CTRL, PORT_START_CABLE_DIAG, true); 1255 break; 1256 1257 case PHY_REG_PHY_CTRL: 1258 ret = ksz8_w_phy_ctrl(dev, p, val); 1259 if (ret) 1260 return ret; 1261 break; 1262 default: 1263 break; 1264 } 1265 1266 return 0; 1267 } 1268 1269 static void ksz8_cfg_port_member(struct ksz_device *dev, int port, u8 member) 1270 { 1271 int offset = P_MIRROR_CTRL; 1272 u8 data; 1273 1274 if (ksz_is_ksz8463(dev)) 1275 offset = P1CR2; 1276 ksz_pread8(dev, port, offset, &data); 1277 data &= ~dev->port_mask; 1278 data |= (member & dev->port_mask); 1279 ksz_pwrite8(dev, port, offset, data); 1280 } 1281 1282 static void ksz8_flush_dyn_mac_table(struct dsa_switch *ds, int port) 1283 { 1284 struct ksz_device *dev = ds->priv; 1285 u8 learn[DSA_MAX_PORTS]; 1286 int first, index, cnt; 1287 const u16 *regs; 1288 int reg = S_FLUSH_TABLE_CTRL; 1289 int mask = SW_FLUSH_DYN_MAC_TABLE; 1290 1291 regs = dev->info->regs; 1292 1293 if ((uint)port < dev->info->port_cnt) { 1294 first = port; 1295 cnt = port + 1; 1296 } else { 1297 /* Flush all ports. */ 1298 first = 0; 1299 cnt = dev->info->port_cnt; 1300 } 1301 for (index = first; index < cnt; index++) { 1302 ksz_pread8(dev, index, regs[P_STP_CTRL], &learn[index]); 1303 if (!(learn[index] & PORT_LEARN_DISABLE)) 1304 ksz_pwrite8(dev, index, regs[P_STP_CTRL], 1305 learn[index] | PORT_LEARN_DISABLE); 1306 } 1307 if (ksz_is_ksz8463(dev)) { 1308 reg = KSZ8463_FLUSH_TABLE_CTRL; 1309 mask = KSZ8463_FLUSH_DYN_MAC_TABLE; 1310 } 1311 ksz_cfg(dev, reg, mask, true); 1312 for (index = first; index < cnt; index++) { 1313 if (!(learn[index] & PORT_LEARN_DISABLE)) 1314 ksz_pwrite8(dev, index, regs[P_STP_CTRL], learn[index]); 1315 } 1316 } 1317 1318 static int ksz8_fdb_dump(struct dsa_switch *ds, int port, 1319 dsa_fdb_dump_cb_t *cb, void *data) 1320 { 1321 struct ksz_device *dev = ds->priv; 1322 u8 mac[ETH_ALEN]; 1323 u8 src_port, fid; 1324 u16 entries = 0; 1325 int ret, i; 1326 1327 for (i = 0; i < KSZ8_DYN_MAC_ENTRIES; i++) { 1328 ret = ksz8_r_dyn_mac_table(dev, i, mac, &fid, &src_port, 1329 &entries); 1330 if (ret) 1331 return ret; 1332 1333 if (i >= entries) 1334 return 0; 1335 1336 if (port == src_port) { 1337 ret = cb(mac, fid, false, data); 1338 if (ret) 1339 return ret; 1340 } 1341 } 1342 1343 return 0; 1344 } 1345 1346 static int ksz8_add_sta_mac(struct ksz_device *dev, int port, 1347 const unsigned char *addr, u16 vid) 1348 { 1349 struct alu_struct alu; 1350 int index, ret; 1351 int empty = 0; 1352 1353 alu.port_forward = 0; 1354 for (index = 0; index < dev->info->num_statics; index++) { 1355 bool valid; 1356 1357 ret = ksz8_r_sta_mac_table(dev, index, &alu, &valid); 1358 if (ret) 1359 return ret; 1360 if (!valid) { 1361 /* Remember the first empty entry. */ 1362 if (!empty) 1363 empty = index + 1; 1364 continue; 1365 } 1366 1367 if (!memcmp(alu.mac, addr, ETH_ALEN) && alu.fid == vid) 1368 break; 1369 } 1370 1371 /* no available entry */ 1372 if (index == dev->info->num_statics && !empty) 1373 return -ENOSPC; 1374 1375 /* add entry */ 1376 if (index == dev->info->num_statics) { 1377 index = empty - 1; 1378 memset(&alu, 0, sizeof(alu)); 1379 memcpy(alu.mac, addr, ETH_ALEN); 1380 alu.is_static = true; 1381 } 1382 alu.port_forward |= BIT(port); 1383 if (vid) { 1384 alu.is_use_fid = true; 1385 1386 /* Need a way to map VID to FID. */ 1387 alu.fid = vid; 1388 } 1389 1390 return ksz8_w_sta_mac_table(dev, index, &alu); 1391 } 1392 1393 static int ksz8_del_sta_mac(struct ksz_device *dev, int port, 1394 const unsigned char *addr, u16 vid) 1395 { 1396 struct alu_struct alu; 1397 int index, ret; 1398 1399 for (index = 0; index < dev->info->num_statics; index++) { 1400 bool valid; 1401 1402 ret = ksz8_r_sta_mac_table(dev, index, &alu, &valid); 1403 if (ret) 1404 return ret; 1405 if (!valid) 1406 continue; 1407 1408 if (!memcmp(alu.mac, addr, ETH_ALEN) && alu.fid == vid) 1409 break; 1410 } 1411 1412 /* no available entry */ 1413 if (index == dev->info->num_statics) 1414 return 0; 1415 1416 /* clear port */ 1417 alu.port_forward &= ~BIT(port); 1418 if (!alu.port_forward) 1419 alu.is_static = false; 1420 1421 return ksz8_w_sta_mac_table(dev, index, &alu); 1422 } 1423 1424 static int ksz8_mdb_add(struct dsa_switch *ds, int port, 1425 const struct switchdev_obj_port_mdb *mdb, 1426 struct dsa_db db) 1427 { 1428 return ksz8_add_sta_mac(ds->priv, port, mdb->addr, mdb->vid); 1429 } 1430 1431 static int ksz8_mdb_del(struct dsa_switch *ds, int port, 1432 const struct switchdev_obj_port_mdb *mdb, 1433 struct dsa_db db) 1434 { 1435 return ksz8_del_sta_mac(ds->priv, port, mdb->addr, mdb->vid); 1436 } 1437 1438 static int ksz8_fdb_add(struct dsa_switch *ds, int port, 1439 const unsigned char *addr, u16 vid, struct dsa_db db) 1440 { 1441 return ksz8_add_sta_mac(ds->priv, port, addr, vid); 1442 } 1443 1444 static int ksz8_fdb_del(struct dsa_switch *ds, int port, 1445 const unsigned char *addr, u16 vid, struct dsa_db db) 1446 { 1447 return ksz8_del_sta_mac(ds->priv, port, addr, vid); 1448 } 1449 1450 static int ksz8_port_vlan_filtering(struct dsa_switch *ds, int port, bool flag, 1451 struct netlink_ext_ack *extack) 1452 { 1453 struct ksz_device *dev = ds->priv; 1454 1455 if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev)) 1456 return -ENOTSUPP; 1457 1458 /* Discard packets with VID not enabled on the switch */ 1459 ksz_cfg(dev, S_MIRROR_CTRL, SW_VLAN_ENABLE, flag); 1460 1461 /* Discard packets with VID not enabled on the ingress port */ 1462 for (port = 0; port < dev->phy_port_cnt; ++port) 1463 ksz_port_cfg(dev, port, REG_PORT_CTRL_2, PORT_INGRESS_FILTER, 1464 flag); 1465 1466 return 0; 1467 } 1468 1469 static void ksz8_port_enable_pvid(struct ksz_device *dev, int port, bool state) 1470 { 1471 if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev)) { 1472 int reg = REG_SW_INSERT_SRC_PVID; 1473 1474 if (ksz_is_ksz8463(dev)) 1475 reg = KSZ8463_REG_SW_CTRL_9; 1476 ksz_cfg(dev, reg, 0x03 << (4 - 2 * port), state); 1477 } else { 1478 ksz_pwrite8(dev, port, REG_PORT_CTRL_12, state ? 0x0f : 0x00); 1479 } 1480 } 1481 1482 static int ksz8_port_vlan_add(struct dsa_switch *ds, int port, 1483 const struct switchdev_obj_port_vlan *vlan, 1484 struct netlink_ext_ack *extack) 1485 { 1486 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1487 struct ksz_device *dev = ds->priv; 1488 struct ksz_port *p = &dev->ports[port]; 1489 u16 data, new_pvid = 0; 1490 u8 fid, member, valid; 1491 1492 if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev)) 1493 return -ENOTSUPP; 1494 1495 /* If a VLAN is added with untagged flag different from the 1496 * port's Remove Tag flag, we need to change the latter. 1497 * Ignore VID 0, which is always untagged. 1498 * Ignore CPU port, which will always be tagged. 1499 */ 1500 if (untagged != p->remove_tag && vlan->vid != 0 && 1501 port != dev->cpu_port) { 1502 unsigned int vid; 1503 1504 /* Reject attempts to add a VLAN that requires the 1505 * Remove Tag flag to be changed, unless there are no 1506 * other VLANs currently configured. 1507 */ 1508 for (vid = 1; vid < dev->info->num_vlans; ++vid) { 1509 /* Skip the VID we are going to add or reconfigure */ 1510 if (vid == vlan->vid) 1511 continue; 1512 1513 ksz8_from_vlan(dev, dev->vlan_cache[vid].table[0], 1514 &fid, &member, &valid); 1515 if (valid && (member & BIT(port))) 1516 return -EINVAL; 1517 } 1518 1519 ksz_port_cfg(dev, port, P_TAG_CTRL, PORT_REMOVE_TAG, untagged); 1520 p->remove_tag = untagged; 1521 } 1522 1523 ksz8_r_vlan_table(dev, vlan->vid, &data); 1524 ksz8_from_vlan(dev, data, &fid, &member, &valid); 1525 1526 /* First time to setup the VLAN entry. */ 1527 if (!valid) { 1528 /* Need to find a way to map VID to FID. */ 1529 fid = 1; 1530 valid = 1; 1531 } 1532 member |= BIT(port); 1533 1534 ksz8_to_vlan(dev, fid, member, valid, &data); 1535 ksz8_w_vlan_table(dev, vlan->vid, data); 1536 1537 /* change PVID */ 1538 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) 1539 new_pvid = vlan->vid; 1540 1541 if (new_pvid) { 1542 u16 vid; 1543 1544 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &vid); 1545 vid &= ~VLAN_VID_MASK; 1546 vid |= new_pvid; 1547 ksz_pwrite16(dev, port, REG_PORT_CTRL_VID, vid); 1548 1549 ksz8_port_enable_pvid(dev, port, true); 1550 } 1551 1552 return 0; 1553 } 1554 1555 static int ksz8_port_vlan_del(struct dsa_switch *ds, int port, 1556 const struct switchdev_obj_port_vlan *vlan) 1557 { 1558 struct ksz_device *dev = ds->priv; 1559 u8 fid, member, valid; 1560 u16 data, pvid; 1561 1562 if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev)) 1563 return -ENOTSUPP; 1564 1565 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &pvid); 1566 pvid = pvid & 0xFFF; 1567 1568 ksz8_r_vlan_table(dev, vlan->vid, &data); 1569 ksz8_from_vlan(dev, data, &fid, &member, &valid); 1570 1571 member &= ~BIT(port); 1572 1573 /* Invalidate the entry if no more member. */ 1574 if (!member) { 1575 fid = 0; 1576 valid = 0; 1577 } 1578 1579 ksz8_to_vlan(dev, fid, member, valid, &data); 1580 ksz8_w_vlan_table(dev, vlan->vid, data); 1581 1582 if (pvid == vlan->vid) 1583 ksz8_port_enable_pvid(dev, port, false); 1584 1585 return 0; 1586 } 1587 1588 static int ksz8_port_mirror_add(struct dsa_switch *ds, int port, 1589 struct dsa_mall_mirror_tc_entry *mirror, 1590 bool ingress, struct netlink_ext_ack *extack) 1591 { 1592 struct ksz_device *dev = ds->priv; 1593 int offset = P_MIRROR_CTRL; 1594 1595 if (ksz_is_ksz8463(dev)) 1596 offset = P1CR2; 1597 if (ingress) { 1598 ksz_port_cfg(dev, port, offset, PORT_MIRROR_RX, true); 1599 dev->mirror_rx |= BIT(port); 1600 } else { 1601 ksz_port_cfg(dev, port, offset, PORT_MIRROR_TX, true); 1602 dev->mirror_tx |= BIT(port); 1603 } 1604 1605 ksz_port_cfg(dev, port, offset, PORT_MIRROR_SNIFFER, false); 1606 1607 /* configure mirror port */ 1608 if (dev->mirror_rx || dev->mirror_tx) 1609 ksz_port_cfg(dev, mirror->to_local_port, offset, 1610 PORT_MIRROR_SNIFFER, true); 1611 1612 return 0; 1613 } 1614 1615 static void ksz8_port_mirror_del(struct dsa_switch *ds, int port, 1616 struct dsa_mall_mirror_tc_entry *mirror) 1617 { 1618 struct ksz_device *dev = ds->priv; 1619 int offset = P_MIRROR_CTRL; 1620 u8 data; 1621 1622 if (ksz_is_ksz8463(dev)) 1623 offset = P1CR2; 1624 if (mirror->ingress) { 1625 ksz_port_cfg(dev, port, offset, PORT_MIRROR_RX, false); 1626 dev->mirror_rx &= ~BIT(port); 1627 } else { 1628 ksz_port_cfg(dev, port, offset, PORT_MIRROR_TX, false); 1629 dev->mirror_tx &= ~BIT(port); 1630 } 1631 1632 ksz_pread8(dev, port, offset, &data); 1633 1634 if (!dev->mirror_rx && !dev->mirror_tx) 1635 ksz_port_cfg(dev, mirror->to_local_port, offset, 1636 PORT_MIRROR_SNIFFER, false); 1637 } 1638 1639 static void ksz8795_cpu_interface_select(struct ksz_device *dev, int port) 1640 { 1641 struct ksz_port *p = &dev->ports[port]; 1642 1643 if (!ksz_is_ksz87xx(dev)) 1644 return; 1645 1646 if (!p->interface && dev->compat_interface) { 1647 dev_warn(dev->dev, 1648 "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. " 1649 "Please update your device tree.\n", 1650 port); 1651 p->interface = dev->compat_interface; 1652 } 1653 } 1654 1655 static void ksz8_port_setup(struct ksz_device *dev, int port, bool cpu_port) 1656 { 1657 const u16 *regs = dev->info->regs; 1658 struct dsa_switch *ds = dev->ds; 1659 const u32 *masks; 1660 int offset; 1661 u8 member; 1662 1663 masks = dev->info->masks; 1664 1665 /* enable broadcast storm limit */ 1666 offset = P_BCAST_STORM_CTRL; 1667 if (ksz_is_ksz8463(dev)) 1668 offset = P1CR1; 1669 ksz_port_cfg(dev, port, offset, PORT_BROADCAST_STORM, true); 1670 1671 ksz8_port_queue_split(dev, port, dev->info->num_tx_queues); 1672 1673 /* replace priority */ 1674 offset = P_802_1P_CTRL; 1675 if (ksz_is_ksz8463(dev)) 1676 offset = P1CR2; 1677 ksz_port_cfg(dev, port, offset, 1678 masks[PORT_802_1P_REMAPPING], false); 1679 1680 if (cpu_port) 1681 member = dsa_user_ports(ds); 1682 else 1683 member = BIT(dsa_upstream_port(ds, port)); 1684 1685 ksz8_cfg_port_member(dev, port, member); 1686 1687 /* Disable all WoL options by default. Otherwise 1688 * ksz_switch_macaddr_get/put logic will not work properly. 1689 * CPU port 4 has no WoL functionality. 1690 */ 1691 if (ksz_is_ksz87xx(dev) && !cpu_port) 1692 ksz8_pme_pwrite8(dev, port, regs[REG_PORT_PME_CTRL], 0); 1693 } 1694 1695 static void ksz88x3_config_rmii_clk(struct ksz_device *dev) 1696 { 1697 struct dsa_port *cpu_dp = dsa_to_port(dev->ds, dev->cpu_port); 1698 bool rmii_clk_internal; 1699 1700 if (!ksz_is_ksz88x3(dev)) 1701 return; 1702 1703 rmii_clk_internal = of_property_read_bool(cpu_dp->dn, 1704 "microchip,rmii-clk-internal"); 1705 1706 ksz_cfg(dev, KSZ88X3_REG_FVID_AND_HOST_MODE, 1707 KSZ88X3_PORT3_RMII_CLK_INTERNAL, rmii_clk_internal); 1708 } 1709 1710 static void ksz8_config_cpu_port(struct dsa_switch *ds) 1711 { 1712 struct ksz_device *dev = ds->priv; 1713 struct ksz_port *p; 1714 const u32 *masks; 1715 const u16 *regs; 1716 u8 remote; 1717 u8 fiber_ports = 0; 1718 int i; 1719 1720 masks = dev->info->masks; 1721 regs = dev->info->regs; 1722 1723 ksz_cfg(dev, regs[S_TAIL_TAG_CTRL], masks[SW_TAIL_TAG_ENABLE], true); 1724 1725 ksz8_port_setup(dev, dev->cpu_port, true); 1726 1727 ksz8795_cpu_interface_select(dev, dev->cpu_port); 1728 ksz88x3_config_rmii_clk(dev); 1729 1730 for (i = 0; i < dev->phy_port_cnt; i++) { 1731 ksz_port_stp_state_set(ds, i, BR_STATE_DISABLED); 1732 } 1733 for (i = 0; i < dev->phy_port_cnt; i++) { 1734 p = &dev->ports[i]; 1735 1736 /* For KSZ8795 family. */ 1737 if (ksz_is_ksz87xx(dev)) { 1738 ksz_pread8(dev, i, regs[P_REMOTE_STATUS], &remote); 1739 if (remote & KSZ8_PORT_FIBER_MODE) 1740 p->fiber = 1; 1741 } 1742 if (p->fiber) 1743 ksz_port_cfg(dev, i, regs[P_STP_CTRL], 1744 PORT_FORCE_FLOW_CTRL, true); 1745 else 1746 ksz_port_cfg(dev, i, regs[P_STP_CTRL], 1747 PORT_FORCE_FLOW_CTRL, false); 1748 if (p->fiber) 1749 fiber_ports |= (1 << i); 1750 } 1751 if (ksz_is_ksz8463(dev)) { 1752 /* Setup fiber ports. */ 1753 if (fiber_ports) { 1754 fiber_ports &= 3; 1755 regmap_update_bits(ksz_regmap_16(dev), 1756 KSZ8463_REG_CFG_CTRL, 1757 fiber_ports << PORT_COPPER_MODE_S, 1758 0); 1759 regmap_update_bits(ksz_regmap_16(dev), 1760 KSZ8463_REG_DSP_CTRL_6, 1761 COPPER_RECEIVE_ADJUSTMENT, 0); 1762 } 1763 1764 /* Turn off PTP function as the switch's proprietary way of 1765 * handling timestamp is not supported in current Linux PTP 1766 * stack implementation. 1767 */ 1768 regmap_update_bits(ksz_regmap_16(dev), 1769 KSZ8463_PTP_MSG_CONF1, 1770 PTP_ENABLE, 0); 1771 regmap_update_bits(ksz_regmap_16(dev), 1772 KSZ8463_PTP_CLK_CTRL, 1773 PTP_CLK_ENABLE, 0); 1774 } 1775 } 1776 1777 /** 1778 * ksz8_phy_port_link_up - Configures ports with integrated PHYs 1779 * @dev: The KSZ device instance. 1780 * @port: The port number to configure. 1781 * @duplex: The desired duplex mode. 1782 * @tx_pause: If true, enables transmit pause. 1783 * @rx_pause: If true, enables receive pause. 1784 * 1785 * Description: 1786 * The function configures flow control settings for a given port based on the 1787 * desired settings and current duplex mode. 1788 * 1789 * According to the KSZ8873 datasheet, the PORT_FORCE_FLOW_CTRL bit in the 1790 * Port Control 2 register (0x1A for Port 1, 0x22 for Port 2, 0x32 for Port 3) 1791 * determines how flow control is handled on the port: 1792 * "1 = will always enable full-duplex flow control on the port, regardless 1793 * of AN result. 1794 * 0 = full-duplex flow control is enabled based on AN result." 1795 * 1796 * This means that the flow control behavior depends on the state of this bit: 1797 * - If PORT_FORCE_FLOW_CTRL is set to 1, the switch will ignore AN results and 1798 * force flow control on the port. 1799 * - If PORT_FORCE_FLOW_CTRL is set to 0, the switch will enable or disable 1800 * flow control based on the AN results. 1801 * 1802 * However, there is a potential limitation in this configuration. It is 1803 * currently not possible to force disable flow control on a port if we still 1804 * advertise pause support. While such a configuration is not currently 1805 * supported by Linux, and may not make practical sense, it's important to be 1806 * aware of this limitation when working with the KSZ8873 and similar devices. 1807 */ 1808 static void ksz8_phy_port_link_up(struct ksz_device *dev, int port, int duplex, 1809 bool tx_pause, bool rx_pause) 1810 { 1811 const u16 *regs = dev->info->regs; 1812 u8 sctrl = 0; 1813 1814 /* The KSZ8795 switch differs from the KSZ8873 by supporting 1815 * asymmetric pause control. However, since a single bit is used to 1816 * control both RX and TX pause, we can't enforce asymmetric pause 1817 * control - both TX and RX pause will be either enabled or disabled 1818 * together. 1819 * 1820 * If auto-negotiation is enabled, we usually allow the flow control to 1821 * be determined by the auto-negotiation process based on the 1822 * capabilities of both link partners. However, for KSZ8873, the 1823 * PORT_FORCE_FLOW_CTRL bit may be set by the hardware bootstrap, 1824 * ignoring the auto-negotiation result. Thus, even in auto-negotiation 1825 * mode, we need to ensure that the PORT_FORCE_FLOW_CTRL bit is 1826 * properly cleared. 1827 * 1828 * In the absence of pause auto-negotiation, we will enforce symmetric 1829 * pause control for both variants of switches - KSZ8873 and KSZ8795. 1830 * 1831 * Autoneg Pause Autoneg rx,tx PORT_FORCE_FLOW_CTRL 1832 * 1 1 x 0 1833 * 0 1 x 0 (flow control probably disabled) 1834 * x 0 1 1 (flow control force enabled) 1835 * 1 0 0 0 (flow control still depends on 1836 * aneg result due to hardware) 1837 * 0 0 0 0 (flow control probably disabled) 1838 */ 1839 if (dev->ports[port].manual_flow && tx_pause) 1840 sctrl |= PORT_FORCE_FLOW_CTRL; 1841 1842 ksz_prmw8(dev, port, regs[P_STP_CTRL], PORT_FORCE_FLOW_CTRL, sctrl); 1843 } 1844 1845 /** 1846 * ksz8_cpu_port_link_up - Configures the CPU port of the switch. 1847 * @dev: The KSZ device instance. 1848 * @speed: The desired link speed. 1849 * @duplex: The desired duplex mode. 1850 * @tx_pause: If true, enables transmit pause. 1851 * @rx_pause: If true, enables receive pause. 1852 * 1853 * Description: 1854 * The function configures flow control and speed settings for the CPU 1855 * port of the switch based on the desired settings, current duplex mode, and 1856 * speed. 1857 */ 1858 static void ksz8_cpu_port_link_up(struct ksz_device *dev, int speed, int duplex, 1859 bool tx_pause, bool rx_pause) 1860 { 1861 const u16 *regs = dev->info->regs; 1862 u8 ctrl = 0; 1863 1864 /* SW_FLOW_CTRL, SW_HALF_DUPLEX, and SW_10_MBIT bits are bootstrappable 1865 * at least on KSZ8873. They can have different values depending on your 1866 * board setup. 1867 */ 1868 if (tx_pause || rx_pause) 1869 ctrl |= SW_FLOW_CTRL; 1870 1871 if (duplex == DUPLEX_HALF) 1872 ctrl |= SW_HALF_DUPLEX; 1873 1874 /* This hardware only supports SPEED_10 and SPEED_100. For SPEED_10 1875 * we need to set the SW_10_MBIT bit. Otherwise, we can leave it 0. 1876 */ 1877 if (speed == SPEED_10) 1878 ctrl |= SW_10_MBIT; 1879 1880 ksz_rmw8(dev, regs[S_BROADCAST_CTRL], SW_HALF_DUPLEX | SW_FLOW_CTRL | 1881 SW_10_MBIT, ctrl); 1882 } 1883 1884 static void ksz8_phylink_mac_link_up(struct phylink_config *config, 1885 struct phy_device *phydev, 1886 unsigned int mode, 1887 phy_interface_t interface, 1888 int speed, int duplex, 1889 bool tx_pause, bool rx_pause) 1890 { 1891 struct dsa_port *dp = dsa_phylink_to_port(config); 1892 struct ksz_device *dev = dp->ds->priv; 1893 int port = dp->index; 1894 1895 /* If the port is the CPU port, apply special handling. Only the CPU 1896 * port is configured via global registers. 1897 */ 1898 if (dev->cpu_port == port) 1899 ksz8_cpu_port_link_up(dev, speed, duplex, tx_pause, rx_pause); 1900 else if (dev->info->internal_phy[port]) 1901 ksz8_phy_port_link_up(dev, port, duplex, tx_pause, rx_pause); 1902 } 1903 1904 static int ksz8_handle_global_errata(struct dsa_switch *ds) 1905 { 1906 struct ksz_device *dev = ds->priv; 1907 int ret = 0; 1908 1909 /* KSZ87xx Errata DS80000687C. 1910 * Module 2: Link drops with some EEE link partners. 1911 * An issue with the EEE next page exchange between the 1912 * KSZ879x/KSZ877x/KSZ876x and some EEE link partners may result in 1913 * the link dropping. 1914 */ 1915 if (dev->info->ksz87xx_eee_link_erratum) 1916 ret = ksz8_ind_write8(dev, TABLE_EEE, REG_IND_EEE_GLOB2_HI, 0); 1917 1918 return ret; 1919 } 1920 1921 static int ksz8_enable_stp_addr(struct ksz_device *dev) 1922 { 1923 struct alu_struct alu; 1924 1925 /* Setup STP address for STP operation. */ 1926 memset(&alu, 0, sizeof(alu)); 1927 ether_addr_copy(alu.mac, eth_stp_addr); 1928 alu.is_static = true; 1929 alu.is_override = true; 1930 alu.port_forward = dev->info->cpu_ports; 1931 1932 return ksz8_w_sta_mac_table(dev, 0, &alu); 1933 } 1934 1935 static int ksz8_setup(struct dsa_switch *ds) 1936 { 1937 struct ksz_device *dev = ds->priv; 1938 const u16 *regs = dev->info->regs; 1939 int i, ret = 0; 1940 1941 ds->mtu_enforcement_ingress = true; 1942 1943 /* We rely on software untagging on the CPU port, so that we 1944 * can support both tagged and untagged VLANs 1945 */ 1946 ds->untag_bridge_pvid = true; 1947 1948 /* VLAN filtering is partly controlled by the global VLAN 1949 * Enable flag 1950 */ 1951 ds->vlan_filtering_is_global = true; 1952 1953 /* Enable automatic fast aging when link changed detected. */ 1954 ksz_cfg(dev, S_LINK_AGING_CTRL, SW_LINK_AUTO_AGING, true); 1955 1956 /* Enable aggressive back off algorithm in half duplex mode. */ 1957 ret = ksz_rmw8(dev, REG_SW_CTRL_1, SW_AGGR_BACKOFF, SW_AGGR_BACKOFF); 1958 if (ret) 1959 return ret; 1960 1961 /* 1962 * Make sure unicast VLAN boundary is set as default and 1963 * enable no excessive collision drop. 1964 */ 1965 ret = ksz_rmw8(dev, REG_SW_CTRL_2, 1966 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP, 1967 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP); 1968 if (ret) 1969 return ret; 1970 1971 ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_REPLACE_VID, false); 1972 1973 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false); 1974 1975 if (!ksz_is_ksz88x3(dev) && !ksz_is_ksz8463(dev)) 1976 ksz_cfg(dev, REG_SW_CTRL_19, SW_INS_TAG_ENABLE, true); 1977 1978 for (i = 0; i < (dev->info->num_vlans / 4); i++) 1979 ksz8_r_vlan_entries(dev, i); 1980 1981 /* Make sure PME (WoL) is not enabled. If requested, it will 1982 * be enabled by ksz_wol_pre_shutdown(). Otherwise, some PMICs 1983 * do not like PME events changes before shutdown. PME only 1984 * available on KSZ87xx family. 1985 */ 1986 if (ksz_is_ksz87xx(dev)) { 1987 ret = ksz8_pme_write8(dev, regs[REG_SW_PME_CTRL], 0); 1988 if (!ret) 1989 ret = ksz_rmw8(dev, REG_INT_ENABLE, INT_PME, 0); 1990 } 1991 1992 if (!ret) 1993 return ksz8_handle_global_errata(ds); 1994 else 1995 return ret; 1996 } 1997 1998 static void ksz8_phylink_get_caps(struct dsa_switch *ds, int port, 1999 struct phylink_config *config) 2000 { 2001 struct ksz_device *dev = ds->priv; 2002 2003 config->mac_capabilities = MAC_10 | MAC_100; 2004 2005 /* Silicon Errata Sheet (DS80000830A): 2006 * "Port 1 does not respond to received flow control PAUSE frames" 2007 * So, disable Pause support on "Port 1" (port == 0) for all ksz88x3 2008 * switches. 2009 */ 2010 if (!ksz_is_ksz88x3(dev) || port) 2011 config->mac_capabilities |= MAC_SYM_PAUSE; 2012 2013 /* Asym pause is not supported on KSZ8863 and KSZ8873 */ 2014 if (!ksz_is_ksz88x3(dev)) 2015 config->mac_capabilities |= MAC_ASYM_PAUSE; 2016 2017 ksz_phylink_get_caps(ds, port, config); 2018 } 2019 2020 static u32 ksz8_get_port_addr(int port, int offset) 2021 { 2022 return PORT_CTRL_ADDR(port, offset); 2023 } 2024 2025 static u32 ksz8463_get_port_addr(int port, int offset) 2026 { 2027 return offset + 0x18 * port; 2028 } 2029 2030 static u16 ksz8463_get_phy_addr(u16 phy, u16 reg, u16 offset) 2031 { 2032 return offset + reg * 2 + phy * (P2MBCR - P1MBCR); 2033 } 2034 2035 static int ksz8463_r_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 *val) 2036 { 2037 u16 sw_reg = 0; 2038 u16 data = 0; 2039 int ret; 2040 2041 if (phy > 1) 2042 return -ENOSPC; 2043 switch (reg) { 2044 case MII_PHYSID1: 2045 sw_reg = ksz8463_get_phy_addr(phy, 0, PHY1IHR); 2046 break; 2047 case MII_PHYSID2: 2048 sw_reg = ksz8463_get_phy_addr(phy, 0, PHY1ILR); 2049 break; 2050 case MII_BMCR: 2051 case MII_BMSR: 2052 case MII_ADVERTISE: 2053 case MII_LPA: 2054 sw_reg = ksz8463_get_phy_addr(phy, reg, P1MBCR); 2055 break; 2056 case MII_TPISTATUS: 2057 /* This register holds the PHY interrupt status for simulated 2058 * Micrel KSZ PHY. 2059 */ 2060 data = 0x0505; 2061 break; 2062 default: 2063 break; 2064 } 2065 if (sw_reg) { 2066 ret = ksz_read16(dev, sw_reg, &data); 2067 if (ret) 2068 return ret; 2069 } 2070 *val = data; 2071 2072 return 0; 2073 } 2074 2075 static int ksz8463_w_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 val) 2076 { 2077 u16 sw_reg = 0; 2078 int ret; 2079 2080 if (phy > 1) 2081 return -ENOSPC; 2082 2083 /* No write to fiber port. */ 2084 if (dev->ports[phy].fiber) 2085 return 0; 2086 switch (reg) { 2087 case MII_BMCR: 2088 case MII_ADVERTISE: 2089 sw_reg = ksz8463_get_phy_addr(phy, reg, P1MBCR); 2090 break; 2091 default: 2092 break; 2093 } 2094 if (sw_reg) { 2095 ret = ksz_write16(dev, sw_reg, val); 2096 if (ret) 2097 return ret; 2098 } 2099 2100 return 0; 2101 } 2102 2103 static int ksz8_switch_init(struct ksz_device *dev) 2104 { 2105 dev->cpu_port = fls(dev->info->cpu_ports) - 1; 2106 dev->phy_port_cnt = dev->info->port_cnt - 1; 2107 dev->port_mask = (BIT(dev->phy_port_cnt) - 1) | dev->info->cpu_ports; 2108 2109 return 0; 2110 } 2111 2112 static void ksz8_switch_exit(struct ksz_device *dev) 2113 { 2114 ksz8_reset_switch(dev); 2115 } 2116 2117 static enum dsa_tag_protocol ksz8463_get_tag_protocol(struct dsa_switch *ds, 2118 int port, 2119 enum dsa_tag_protocol mp) 2120 { 2121 return DSA_TAG_PROTO_KSZ9893; 2122 } 2123 2124 static int ksz8463_connect_tag_protocol(struct dsa_switch *ds, 2125 enum dsa_tag_protocol proto) 2126 { 2127 struct ksz_tagger_data *tagger_data; 2128 2129 if (proto != DSA_TAG_PROTO_KSZ9893) 2130 return -EPROTONOSUPPORT; 2131 2132 tagger_data = ksz_tagger_data(ds); 2133 tagger_data->xmit_work_fn = ksz_port_deferred_xmit; 2134 2135 return 0; 2136 } 2137 2138 static enum dsa_tag_protocol ksz87xx_get_tag_protocol(struct dsa_switch *ds, 2139 int port, 2140 enum dsa_tag_protocol mp) 2141 { 2142 return DSA_TAG_PROTO_KSZ8795; 2143 } 2144 2145 static int ksz87xx_connect_tag_protocol(struct dsa_switch *ds, 2146 enum dsa_tag_protocol proto) 2147 { 2148 if (proto != DSA_TAG_PROTO_KSZ8795) 2149 return -EPROTONOSUPPORT; 2150 2151 return 0; 2152 } 2153 2154 static enum dsa_tag_protocol ksz88xx_get_tag_protocol(struct dsa_switch *ds, 2155 int port, 2156 enum dsa_tag_protocol mp) 2157 { 2158 struct ksz_device *dev = ds->priv; 2159 2160 if (ksz_is_8895_family(dev)) /* KSZ8864, KSZ8895 */ 2161 return DSA_TAG_PROTO_KSZ8795; 2162 2163 return DSA_TAG_PROTO_KSZ9893; 2164 } 2165 2166 static int ksz88xx_connect_tag_protocol(struct dsa_switch *ds, 2167 enum dsa_tag_protocol proto) 2168 { 2169 struct ksz_tagger_data *tagger_data; 2170 2171 if (ksz_is_8895_family(ds->priv)) { /* KSZ8864, KSZ8895 */ 2172 if (proto != DSA_TAG_PROTO_KSZ8795) 2173 return -EPROTONOSUPPORT; 2174 2175 return 0; 2176 } 2177 2178 if (proto != DSA_TAG_PROTO_KSZ9893) 2179 return -EPROTONOSUPPORT; 2180 2181 tagger_data = ksz_tagger_data(ds); 2182 tagger_data->xmit_work_fn = ksz_port_deferred_xmit; 2183 2184 return 0; 2185 } 2186 2187 static void ksz88x3_phylink_mac_config(struct phylink_config *config, 2188 unsigned int mode, 2189 const struct phylink_link_state *state) 2190 { 2191 struct dsa_port *dp = dsa_phylink_to_port(config); 2192 struct ksz_device *dev = dp->ds->priv; 2193 2194 dev->ports[dp->index].manual_flow = !(state->pause & MLO_PAUSE_AN); 2195 } 2196 2197 const struct phylink_mac_ops ksz88x3_phylink_mac_ops = { 2198 .mac_config = ksz88x3_phylink_mac_config, 2199 .mac_link_down = ksz_phylink_mac_link_down, 2200 .mac_link_up = ksz8_phylink_mac_link_up, 2201 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi, 2202 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi, 2203 }; 2204 2205 const struct phylink_mac_ops ksz8_phylink_mac_ops = { 2206 .mac_config = ksz_phylink_mac_config, 2207 .mac_link_down = ksz_phylink_mac_link_down, 2208 .mac_link_up = ksz8_phylink_mac_link_up, 2209 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi, 2210 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi, 2211 }; 2212 2213 const struct ksz_dev_ops ksz8463_dev_ops = { 2214 .setup = ksz8_setup, 2215 .get_port_addr = ksz8463_get_port_addr, 2216 .cfg_port_member = ksz8_cfg_port_member, 2217 .port_setup = ksz8_port_setup, 2218 .r_phy = ksz8463_r_phy, 2219 .w_phy = ksz8463_w_phy, 2220 .r_mib_cnt = ksz8_r_mib_cnt, 2221 .r_mib_pkt = ksz8_r_mib_pkt, 2222 .r_mib_stat64 = ksz88xx_r_mib_stats64, 2223 .freeze_mib = ksz8_freeze_mib, 2224 .port_init_cnt = ksz8_port_init_cnt, 2225 .config_cpu_port = ksz8_config_cpu_port, 2226 .enable_stp_addr = ksz8_enable_stp_addr, 2227 .reset = ksz8_reset_switch, 2228 .init = ksz8_switch_init, 2229 .exit = ksz8_switch_exit, 2230 }; 2231 2232 const struct ksz_dev_ops ksz87xx_dev_ops = { 2233 .setup = ksz8_setup, 2234 .get_port_addr = ksz8_get_port_addr, 2235 .cfg_port_member = ksz8_cfg_port_member, 2236 .port_setup = ksz8_port_setup, 2237 .r_phy = ksz8_r_phy, 2238 .w_phy = ksz8_w_phy, 2239 .r_mib_cnt = ksz8_r_mib_cnt, 2240 .r_mib_pkt = ksz8_r_mib_pkt, 2241 .r_mib_stat64 = ksz_r_mib_stats64, 2242 .freeze_mib = ksz8_freeze_mib, 2243 .port_init_cnt = ksz8_port_init_cnt, 2244 .config_cpu_port = ksz8_config_cpu_port, 2245 .enable_stp_addr = ksz8_enable_stp_addr, 2246 .reset = ksz8_reset_switch, 2247 .init = ksz8_switch_init, 2248 .exit = ksz8_switch_exit, 2249 .pme_write8 = ksz8_pme_write8, 2250 .pme_pread8 = ksz8_pme_pread8, 2251 .pme_pwrite8 = ksz8_pme_pwrite8, 2252 }; 2253 2254 const struct ksz_dev_ops ksz88xx_dev_ops = { 2255 .setup = ksz8_setup, 2256 .get_port_addr = ksz8_get_port_addr, 2257 .cfg_port_member = ksz8_cfg_port_member, 2258 .port_setup = ksz8_port_setup, 2259 .r_phy = ksz8_r_phy, 2260 .w_phy = ksz8_w_phy, 2261 .r_mib_cnt = ksz8_r_mib_cnt, 2262 .r_mib_pkt = ksz8_r_mib_pkt, 2263 .r_mib_stat64 = ksz88xx_r_mib_stats64, 2264 .freeze_mib = ksz8_freeze_mib, 2265 .port_init_cnt = ksz8_port_init_cnt, 2266 .config_cpu_port = ksz8_config_cpu_port, 2267 .enable_stp_addr = ksz8_enable_stp_addr, 2268 .reset = ksz8_reset_switch, 2269 .init = ksz8_switch_init, 2270 .exit = ksz8_switch_exit, 2271 .pme_write8 = ksz8_pme_write8, 2272 .pme_pread8 = ksz8_pme_pread8, 2273 .pme_pwrite8 = ksz8_pme_pwrite8, 2274 }; 2275 2276 const struct dsa_switch_ops ksz8463_switch_ops = { 2277 .get_tag_protocol = ksz8463_get_tag_protocol, 2278 .connect_tag_protocol = ksz8463_connect_tag_protocol, 2279 .get_phy_flags = ksz_get_phy_flags, 2280 .setup = ksz_setup, 2281 .teardown = ksz_teardown, 2282 .phy_read = ksz_phy_read16, 2283 .phy_write = ksz_phy_write16, 2284 .phylink_get_caps = ksz8_phylink_get_caps, 2285 .port_setup = ksz_port_setup, 2286 .get_strings = ksz_get_strings, 2287 .get_ethtool_stats = ksz_get_ethtool_stats, 2288 .get_sset_count = ksz_sset_count, 2289 .port_bridge_join = ksz_port_bridge_join, 2290 .port_bridge_leave = ksz_port_bridge_leave, 2291 .port_hsr_join = ksz_hsr_join, 2292 .port_hsr_leave = ksz_hsr_leave, 2293 .port_set_mac_address = ksz_port_set_mac_address, 2294 .port_stp_state_set = ksz_port_stp_state_set, 2295 .port_teardown = ksz_port_teardown, 2296 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 2297 .port_bridge_flags = ksz_port_bridge_flags, 2298 .port_fast_age = ksz8_flush_dyn_mac_table, 2299 .port_vlan_filtering = ksz8_port_vlan_filtering, 2300 .port_vlan_add = ksz8_port_vlan_add, 2301 .port_vlan_del = ksz8_port_vlan_del, 2302 .port_fdb_dump = ksz8_fdb_dump, 2303 .port_fdb_add = ksz8_fdb_add, 2304 .port_fdb_del = ksz8_fdb_del, 2305 .port_mdb_add = ksz8_mdb_add, 2306 .port_mdb_del = ksz8_mdb_del, 2307 .port_mirror_add = ksz8_port_mirror_add, 2308 .port_mirror_del = ksz8_port_mirror_del, 2309 .get_stats64 = ksz_get_stats64, 2310 .get_pause_stats = ksz_get_pause_stats, 2311 .port_change_mtu = ksz8_change_mtu, 2312 .port_max_mtu = ksz_max_mtu, 2313 .get_wol = ksz_get_wol, 2314 .set_wol = ksz_set_wol, 2315 .suspend = ksz_suspend, 2316 .resume = ksz_resume, 2317 .get_ts_info = ksz_get_ts_info, 2318 .port_hwtstamp_get = ksz_hwtstamp_get, 2319 .port_hwtstamp_set = ksz_hwtstamp_set, 2320 .port_txtstamp = ksz_port_txtstamp, 2321 .port_rxtstamp = ksz_port_rxtstamp, 2322 .cls_flower_add = ksz_cls_flower_add, 2323 .cls_flower_del = ksz_cls_flower_del, 2324 .port_setup_tc = ksz_setup_tc, 2325 .support_eee = ksz_support_eee, 2326 .set_mac_eee = ksz_set_mac_eee, 2327 .port_get_default_prio = ksz_port_get_default_prio, 2328 .port_set_default_prio = ksz_port_set_default_prio, 2329 .port_get_dscp_prio = ksz_port_get_dscp_prio, 2330 .port_add_dscp_prio = ksz_port_add_dscp_prio, 2331 .port_del_dscp_prio = ksz_port_del_dscp_prio, 2332 .port_get_apptrust = ksz_port_get_apptrust, 2333 .port_set_apptrust = ksz_port_set_apptrust, 2334 }; 2335 2336 const struct dsa_switch_ops ksz87xx_switch_ops = { 2337 .get_tag_protocol = ksz87xx_get_tag_protocol, 2338 .connect_tag_protocol = ksz87xx_connect_tag_protocol, 2339 .get_phy_flags = ksz_get_phy_flags, 2340 .setup = ksz_setup, 2341 .teardown = ksz_teardown, 2342 .phy_read = ksz_phy_read16, 2343 .phy_write = ksz_phy_write16, 2344 .phylink_get_caps = ksz8_phylink_get_caps, 2345 .port_setup = ksz_port_setup, 2346 .get_strings = ksz_get_strings, 2347 .get_ethtool_stats = ksz_get_ethtool_stats, 2348 .get_sset_count = ksz_sset_count, 2349 .port_bridge_join = ksz_port_bridge_join, 2350 .port_bridge_leave = ksz_port_bridge_leave, 2351 .port_hsr_join = ksz_hsr_join, 2352 .port_hsr_leave = ksz_hsr_leave, 2353 .port_set_mac_address = ksz_port_set_mac_address, 2354 .port_stp_state_set = ksz_port_stp_state_set, 2355 .port_teardown = ksz_port_teardown, 2356 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 2357 .port_bridge_flags = ksz_port_bridge_flags, 2358 .port_fast_age = ksz8_flush_dyn_mac_table, 2359 .port_vlan_filtering = ksz8_port_vlan_filtering, 2360 .port_vlan_add = ksz8_port_vlan_add, 2361 .port_vlan_del = ksz8_port_vlan_del, 2362 .port_fdb_dump = ksz8_fdb_dump, 2363 .port_fdb_add = ksz8_fdb_add, 2364 .port_fdb_del = ksz8_fdb_del, 2365 .port_mdb_add = ksz8_mdb_add, 2366 .port_mdb_del = ksz8_mdb_del, 2367 .port_mirror_add = ksz8_port_mirror_add, 2368 .port_mirror_del = ksz8_port_mirror_del, 2369 .get_stats64 = ksz_get_stats64, 2370 .get_pause_stats = ksz_get_pause_stats, 2371 .port_change_mtu = ksz8_change_mtu, 2372 .port_max_mtu = ksz_max_mtu, 2373 .get_wol = ksz_get_wol, 2374 .set_wol = ksz_set_wol, 2375 .suspend = ksz_suspend, 2376 .resume = ksz_resume, 2377 .get_ts_info = ksz_get_ts_info, 2378 .port_hwtstamp_get = ksz_hwtstamp_get, 2379 .port_hwtstamp_set = ksz_hwtstamp_set, 2380 .port_txtstamp = ksz_port_txtstamp, 2381 .port_rxtstamp = ksz_port_rxtstamp, 2382 .cls_flower_add = ksz_cls_flower_add, 2383 .cls_flower_del = ksz_cls_flower_del, 2384 .port_setup_tc = ksz_setup_tc, 2385 .support_eee = ksz_support_eee, 2386 .set_mac_eee = ksz_set_mac_eee, 2387 .port_get_default_prio = ksz_port_get_default_prio, 2388 .port_set_default_prio = ksz_port_set_default_prio, 2389 .port_get_dscp_prio = ksz_port_get_dscp_prio, 2390 .port_add_dscp_prio = ksz_port_add_dscp_prio, 2391 .port_del_dscp_prio = ksz_port_del_dscp_prio, 2392 .port_get_apptrust = ksz_port_get_apptrust, 2393 .port_set_apptrust = ksz_port_set_apptrust, 2394 }; 2395 2396 const struct dsa_switch_ops ksz88xx_switch_ops = { 2397 .get_tag_protocol = ksz88xx_get_tag_protocol, 2398 .connect_tag_protocol = ksz88xx_connect_tag_protocol, 2399 .get_phy_flags = ksz_get_phy_flags, 2400 .setup = ksz_setup, 2401 .teardown = ksz_teardown, 2402 .phy_read = ksz_phy_read16, 2403 .phy_write = ksz_phy_write16, 2404 .phylink_get_caps = ksz8_phylink_get_caps, 2405 .port_setup = ksz_port_setup, 2406 .get_strings = ksz_get_strings, 2407 .get_ethtool_stats = ksz_get_ethtool_stats, 2408 .get_sset_count = ksz_sset_count, 2409 .port_bridge_join = ksz_port_bridge_join, 2410 .port_bridge_leave = ksz_port_bridge_leave, 2411 .port_hsr_join = ksz_hsr_join, 2412 .port_hsr_leave = ksz_hsr_leave, 2413 .port_set_mac_address = ksz_port_set_mac_address, 2414 .port_stp_state_set = ksz_port_stp_state_set, 2415 .port_teardown = ksz_port_teardown, 2416 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 2417 .port_bridge_flags = ksz_port_bridge_flags, 2418 .port_fast_age = ksz8_flush_dyn_mac_table, 2419 .port_vlan_filtering = ksz8_port_vlan_filtering, 2420 .port_vlan_add = ksz8_port_vlan_add, 2421 .port_vlan_del = ksz8_port_vlan_del, 2422 .port_fdb_dump = ksz8_fdb_dump, 2423 .port_fdb_add = ksz8_fdb_add, 2424 .port_fdb_del = ksz8_fdb_del, 2425 .port_mdb_add = ksz8_mdb_add, 2426 .port_mdb_del = ksz8_mdb_del, 2427 .port_mirror_add = ksz8_port_mirror_add, 2428 .port_mirror_del = ksz8_port_mirror_del, 2429 .get_stats64 = ksz_get_stats64, 2430 .get_pause_stats = ksz_get_pause_stats, 2431 .port_change_mtu = ksz8_change_mtu, 2432 .port_max_mtu = ksz_max_mtu, 2433 .get_wol = ksz_get_wol, 2434 .set_wol = ksz_set_wol, 2435 .suspend = ksz_suspend, 2436 .resume = ksz_resume, 2437 .get_ts_info = ksz_get_ts_info, 2438 .port_hwtstamp_get = ksz_hwtstamp_get, 2439 .port_hwtstamp_set = ksz_hwtstamp_set, 2440 .port_txtstamp = ksz_port_txtstamp, 2441 .port_rxtstamp = ksz_port_rxtstamp, 2442 .cls_flower_add = ksz_cls_flower_add, 2443 .cls_flower_del = ksz_cls_flower_del, 2444 .port_setup_tc = ksz_setup_tc, 2445 .support_eee = ksz_support_eee, 2446 .set_mac_eee = ksz_set_mac_eee, 2447 .port_get_default_prio = ksz_port_get_default_prio, 2448 .port_set_default_prio = ksz_port_set_default_prio, 2449 .port_get_dscp_prio = ksz_port_get_dscp_prio, 2450 .port_add_dscp_prio = ksz_port_add_dscp_prio, 2451 .port_del_dscp_prio = ksz_port_del_dscp_prio, 2452 .port_get_apptrust = ksz_port_get_apptrust, 2453 .port_set_apptrust = ksz_port_set_apptrust, 2454 }; 2455 2456 MODULE_AUTHOR("Tristram Ha <Tristram.Ha@microchip.com>"); 2457 MODULE_DESCRIPTION("Microchip KSZ8795 Series Switch DSA Driver"); 2458 MODULE_LICENSE("GPL"); 2459