1 // SPDX-License-Identifier: GPL-2.0 2 #ifndef __LANTIQ_GSWIP_H 3 #define __LANTIQ_GSWIP_H 4 5 #include <linux/clk.h> 6 #include <linux/mutex.h> 7 #include <linux/phylink.h> 8 #include <linux/platform_device.h> 9 #include <linux/regmap.h> 10 #include <linux/reset.h> 11 #include <linux/swab.h> 12 #include <net/dsa.h> 13 14 /* GSWIP MDIO Registers */ 15 #define GSWIP_MDIO_GLOB 0x00 16 #define GSWIP_MDIO_GLOB_ENABLE BIT(15) 17 #define GSWIP_MDIO_CTRL 0x08 18 #define GSWIP_MDIO_CTRL_BUSY BIT(12) 19 #define GSWIP_MDIO_CTRL_RD BIT(11) 20 #define GSWIP_MDIO_CTRL_WR BIT(10) 21 #define GSWIP_MDIO_CTRL_PHYAD_MASK 0x1f 22 #define GSWIP_MDIO_CTRL_PHYAD_SHIFT 5 23 #define GSWIP_MDIO_CTRL_REGAD_MASK 0x1f 24 #define GSWIP_MDIO_READ 0x09 25 #define GSWIP_MDIO_WRITE 0x0A 26 #define GSWIP_MDIO_MDC_CFG0 0x0B 27 #define GSWIP_MDIO_MDC_CFG1 0x0C 28 #define GSWIP_MDIO_PHYp(p) (0x15 - (p)) 29 #define GSWIP_MDIO_PHY_LINK_MASK 0x6000 30 #define GSWIP_MDIO_PHY_LINK_AUTO 0x0000 31 #define GSWIP_MDIO_PHY_LINK_DOWN 0x4000 32 #define GSWIP_MDIO_PHY_LINK_UP 0x2000 33 #define GSWIP_MDIO_PHY_SPEED_MASK 0x1800 34 #define GSWIP_MDIO_PHY_SPEED_AUTO 0x1800 35 #define GSWIP_MDIO_PHY_SPEED_M10 0x0000 36 #define GSWIP_MDIO_PHY_SPEED_M100 0x0800 37 #define GSWIP_MDIO_PHY_SPEED_G1 0x1000 38 #define GSWIP_MDIO_PHY_FDUP_MASK 0x0600 39 #define GSWIP_MDIO_PHY_FDUP_AUTO 0x0000 40 #define GSWIP_MDIO_PHY_FDUP_EN 0x0200 41 #define GSWIP_MDIO_PHY_FDUP_DIS 0x0600 42 #define GSWIP_MDIO_PHY_FCONTX_MASK 0x0180 43 #define GSWIP_MDIO_PHY_FCONTX_AUTO 0x0000 44 #define GSWIP_MDIO_PHY_FCONTX_EN 0x0100 45 #define GSWIP_MDIO_PHY_FCONTX_DIS 0x0180 46 #define GSWIP_MDIO_PHY_FCONRX_MASK 0x0060 47 #define GSWIP_MDIO_PHY_FCONRX_AUTO 0x0000 48 #define GSWIP_MDIO_PHY_FCONRX_EN 0x0020 49 #define GSWIP_MDIO_PHY_FCONRX_DIS 0x0060 50 #define GSWIP_MDIO_PHY_ADDR_MASK 0x001f 51 #define GSWIP_MDIO_PHY_MASK (GSWIP_MDIO_PHY_ADDR_MASK | \ 52 GSWIP_MDIO_PHY_FCONRX_MASK | \ 53 GSWIP_MDIO_PHY_FCONTX_MASK | \ 54 GSWIP_MDIO_PHY_LINK_MASK | \ 55 GSWIP_MDIO_PHY_SPEED_MASK | \ 56 GSWIP_MDIO_PHY_FDUP_MASK) 57 58 /* GSWIP MII Registers */ 59 #define GSWIP_MII_CFGp(p) (0x2 * (p)) 60 #define GSWIP_MII_CFG_RESET BIT(15) 61 #define GSWIP_MII_CFG_EN BIT(14) 62 #define GSWIP_MII_CFG_ISOLATE BIT(13) 63 #define GSWIP_MII_CFG_LDCLKDIS BIT(12) 64 #define GSWIP_MII_CFG_RGMII_IBS BIT(8) 65 #define GSWIP_MII_CFG_RMII_CLK BIT(7) 66 #define GSWIP_MII_CFG_MODE_MIIP 0x0 67 #define GSWIP_MII_CFG_MODE_MIIM 0x1 68 #define GSWIP_MII_CFG_MODE_RMIIP 0x2 69 #define GSWIP_MII_CFG_MODE_RMIIM 0x3 70 #define GSWIP_MII_CFG_MODE_RGMII 0x4 71 #define GSWIP_MII_CFG_MODE_GMII 0x9 72 #define GSWIP_MII_CFG_MODE_MASK 0xf 73 #define GSWIP_MII_CFG_RATE_M2P5 0x00 74 #define GSWIP_MII_CFG_RATE_M25 0x10 75 #define GSWIP_MII_CFG_RATE_M125 0x20 76 #define GSWIP_MII_CFG_RATE_M50 0x30 77 #define GSWIP_MII_CFG_RATE_AUTO 0x40 78 #define GSWIP_MII_CFG_RATE_MASK 0x70 79 #define GSWIP_MII_PCDU0 0x01 80 #define GSWIP_MII_PCDU1 0x03 81 #define GSWIP_MII_PCDU5 0x05 82 #define GSWIP_MII_PCDU_TXDLY_MASK GENMASK(2, 0) 83 #define GSWIP_MII_PCDU_RXDLY_MASK GENMASK(9, 7) 84 85 /* GSWIP Core Registers */ 86 #define GSWIP_SWRES 0x000 87 #define GSWIP_SWRES_R1 BIT(1) /* GSWIP Software reset */ 88 #define GSWIP_SWRES_R0 BIT(0) /* GSWIP Hardware reset */ 89 #define GSWIP_VERSION 0x013 90 #define GSWIP_VERSION_REV_MASK GENMASK(7, 0) 91 #define GSWIP_VERSION_MOD_MASK GENMASK(15, 8) 92 #define GSWIP_VERSION_REV(v) FIELD_GET(GSWIP_VERSION_REV_MASK, v) 93 #define GSWIP_VERSION_MOD(v) FIELD_GET(GSWIP_VERSION_MOD_MASK, v) 94 #define GSWIP_VERSION_2_0 0x100 95 #define GSWIP_VERSION_2_1 0x021 96 #define GSWIP_VERSION_2_2 0x122 97 #define GSWIP_VERSION_2_2_ETC 0x022 98 /* The hardware has the 'major/minor' version bytes in the wrong order 99 * preventing numerical comparisons. Swap the bytes of the 16-bit value 100 * to end up with REV being the most significant byte and MOD being the 101 * least significant byte, which then allows comparing it with the 102 * value stored in struct gswip_priv. 103 */ 104 #define GSWIP_VERSION_GE(priv, ver) ((priv)->version >= swab16(ver)) 105 106 #define GSWIP_BM_RAM_VAL(x) (0x043 - (x)) 107 #define GSWIP_BM_RAM_ADDR 0x044 108 #define GSWIP_BM_RAM_CTRL 0x045 109 #define GSWIP_BM_RAM_CTRL_BAS BIT(15) 110 #define GSWIP_BM_RAM_CTRL_OPMOD BIT(5) 111 #define GSWIP_BM_RAM_CTRL_ADDR_MASK GENMASK(4, 0) 112 #define GSWIP_BM_QUEUE_GCTRL 0x04A 113 #define GSWIP_BM_QUEUE_GCTRL_GL_MOD BIT(10) 114 /* buffer management Port Configuration Register */ 115 #define GSWIP_BM_PCFGp(p) (0x080 + ((p) * 2)) 116 #define GSWIP_BM_PCFG_CNTEN BIT(0) /* RMON Counter Enable */ 117 #define GSWIP_BM_PCFG_IGCNT BIT(1) /* Ingres Special Tag RMON count */ 118 /* buffer management Port Control Register */ 119 #define GSWIP_BM_RMON_CTRLp(p) (0x81 + ((p) * 2)) 120 #define GSWIP_BM_CTRL_RMON_RAM1_RES BIT(0) /* Software Reset for RMON RAM 1 */ 121 #define GSWIP_BM_CTRL_RMON_RAM2_RES BIT(1) /* Software Reset for RMON RAM 2 */ 122 123 /* PCE */ 124 #define GSWIP_PCE_TBL_KEY(x) (0x447 - (x)) 125 #define GSWIP_PCE_TBL_MASK 0x448 126 #define GSWIP_PCE_TBL_VAL(x) (0x44D - (x)) 127 #define GSWIP_PCE_TBL_ADDR 0x44E 128 #define GSWIP_PCE_TBL_CTRL 0x44F 129 #define GSWIP_PCE_TBL_CTRL_BAS BIT(15) 130 #define GSWIP_PCE_TBL_CTRL_TYPE BIT(13) 131 #define GSWIP_PCE_TBL_CTRL_VLD BIT(12) 132 #define GSWIP_PCE_TBL_CTRL_KEYFORM BIT(11) 133 #define GSWIP_PCE_TBL_CTRL_GMAP_MASK GENMASK(10, 7) 134 #define GSWIP_PCE_TBL_CTRL_OPMOD_MASK GENMASK(6, 5) 135 #define GSWIP_PCE_TBL_CTRL_OPMOD_ADRD 0x00 136 #define GSWIP_PCE_TBL_CTRL_OPMOD_ADWR 0x20 137 #define GSWIP_PCE_TBL_CTRL_OPMOD_KSRD 0x40 138 #define GSWIP_PCE_TBL_CTRL_OPMOD_KSWR 0x60 139 #define GSWIP_PCE_TBL_CTRL_ADDR_MASK GENMASK(4, 0) 140 #define GSWIP_PCE_PMAP1 0x453 /* Monitoring port map */ 141 #define GSWIP_PCE_PMAP2 0x454 /* Default Multicast port map */ 142 #define GSWIP_PCE_PMAP3 0x455 /* Default Unknown Unicast port map */ 143 #define GSWIP_PCE_GCTRL_0 0x456 144 #define GSWIP_PCE_GCTRL_0_MTFL BIT(0) /* MAC Table Flushing */ 145 #define GSWIP_PCE_GCTRL_0_MC_VALID BIT(3) 146 #define GSWIP_PCE_GCTRL_0_VLAN BIT(14) /* VLAN aware Switching */ 147 #define GSWIP_PCE_GCTRL_1 0x457 148 #define GSWIP_PCE_GCTRL_1_MAC_GLOCK BIT(2) /* MAC Address table lock */ 149 #define GSWIP_PCE_GCTRL_1_MAC_GLOCK_MOD BIT(3) /* Mac address table lock forwarding mode */ 150 #define GSWIP_PCE_PCTRL_0p(p) (0x480 + ((p) * 0xA)) 151 #define GSWIP_PCE_PCTRL_0_TVM BIT(5) /* Transparent VLAN mode */ 152 #define GSWIP_PCE_PCTRL_0_VREP BIT(6) /* VLAN Replace Mode */ 153 #define GSWIP_PCE_PCTRL_0_INGRESS BIT(11) /* Accept special tag in ingress */ 154 #define GSWIP_PCE_PCTRL_0_PSTATE_LISTEN 0x0 155 #define GSWIP_PCE_PCTRL_0_PSTATE_RX 0x1 156 #define GSWIP_PCE_PCTRL_0_PSTATE_TX 0x2 157 #define GSWIP_PCE_PCTRL_0_PSTATE_LEARNING 0x3 158 #define GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING 0x7 159 #define GSWIP_PCE_PCTRL_0_PSTATE_MASK GENMASK(2, 0) 160 #define GSWIP_PCE_VCTRL(p) (0x485 + ((p) * 0xA)) 161 #define GSWIP_PCE_VCTRL_UVR BIT(0) /* Unknown VLAN Rule */ 162 #define GSWIP_PCE_VCTRL_VIMR BIT(3) /* VLAN Ingress Member violation rule */ 163 #define GSWIP_PCE_VCTRL_VEMR BIT(4) /* VLAN Egress Member violation rule */ 164 #define GSWIP_PCE_VCTRL_VSR BIT(5) /* VLAN Security */ 165 #define GSWIP_PCE_VCTRL_VID0 BIT(6) /* Priority Tagged Rule */ 166 #define GSWIP_PCE_DEFPVID(p) (0x486 + ((p) * 0xA)) 167 168 #define GSWIP_MAC_FLEN 0x8C5 169 #define GSWIP_MAC_CTRL_0p(p) (0x903 + ((p) * 0xC)) 170 #define GSWIP_MAC_CTRL_0_PADEN BIT(8) 171 #define GSWIP_MAC_CTRL_0_FCS_EN BIT(7) 172 #define GSWIP_MAC_CTRL_0_FCON_MASK 0x0070 173 #define GSWIP_MAC_CTRL_0_FCON_AUTO 0x0000 174 #define GSWIP_MAC_CTRL_0_FCON_RX 0x0010 175 #define GSWIP_MAC_CTRL_0_FCON_TX 0x0020 176 #define GSWIP_MAC_CTRL_0_FCON_RXTX 0x0030 177 #define GSWIP_MAC_CTRL_0_FCON_NONE 0x0040 178 #define GSWIP_MAC_CTRL_0_FDUP_MASK 0x000C 179 #define GSWIP_MAC_CTRL_0_FDUP_AUTO 0x0000 180 #define GSWIP_MAC_CTRL_0_FDUP_EN 0x0004 181 #define GSWIP_MAC_CTRL_0_FDUP_DIS 0x000C 182 #define GSWIP_MAC_CTRL_0_GMII_MASK 0x0003 183 #define GSWIP_MAC_CTRL_0_GMII_AUTO 0x0000 184 #define GSWIP_MAC_CTRL_0_GMII_MII 0x0001 185 #define GSWIP_MAC_CTRL_0_GMII_RGMII 0x0002 186 #define GSWIP_MAC_CTRL_2p(p) (0x905 + ((p) * 0xC)) 187 #define GSWIP_MAC_CTRL_2_LCHKL BIT(2) /* Frame Length Check Long Enable */ 188 #define GSWIP_MAC_CTRL_2_MLEN BIT(3) /* Maximum Untagged Frame Lnegth */ 189 190 /* Ethernet Switch Fetch DMA Port Control Register */ 191 #define GSWIP_FDMA_PCTRLp(p) (0xA80 + ((p) * 0x6)) 192 #define GSWIP_FDMA_PCTRL_EN BIT(0) /* FDMA Port Enable */ 193 #define GSWIP_FDMA_PCTRL_STEN BIT(1) /* Special Tag Insertion Enable */ 194 #define GSWIP_FDMA_PCTRL_VLANMOD_MASK GENMASK(4, 3) /* VLAN Modification Control */ 195 #define GSWIP_FDMA_PCTRL_VLANMOD_SHIFT 3 /* VLAN Modification Control */ 196 #define GSWIP_FDMA_PCTRL_VLANMOD_DIS (0x0 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 197 #define GSWIP_FDMA_PCTRL_VLANMOD_PRIO (0x1 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 198 #define GSWIP_FDMA_PCTRL_VLANMOD_ID (0x2 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 199 #define GSWIP_FDMA_PCTRL_VLANMOD_BOTH (0x3 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 200 201 /* Ethernet Switch Store DMA Port Control Register */ 202 #define GSWIP_SDMA_PCTRLp(p) (0xBC0 + ((p) * 0x6)) 203 #define GSWIP_SDMA_PCTRL_EN BIT(0) /* SDMA Port Enable */ 204 #define GSWIP_SDMA_PCTRL_FCEN BIT(1) /* Flow Control Enable */ 205 #define GSWIP_SDMA_PCTRL_PAUFWD BIT(3) /* Pause Frame Forwarding */ 206 207 #define GSWIP_TABLE_ACTIVE_VLAN 0x01 208 #define GSWIP_TABLE_VLAN_MAPPING 0x02 209 #define GSWIP_TABLE_MAC_BRIDGE 0x0b 210 #define GSWIP_TABLE_MAC_BRIDGE_KEY3_FID GENMASK(5, 0) /* Filtering identifier */ 211 #define GSWIP_TABLE_MAC_BRIDGE_VAL0_PORT GENMASK(7, 4) /* Port on learned entries */ 212 #define GSWIP_TABLE_MAC_BRIDGE_VAL1_STATIC BIT(0) /* Static, non-aging entry */ 213 214 #define XRX200_GPHY_FW_ALIGN (16 * 1024) 215 216 /* Maximum packet size supported by the switch. In theory this should be 10240, 217 * but long packets currently cause lock-ups with an MTU of over 2526. Medium 218 * packets are sometimes dropped (e.g. TCP over 2477, UDP over 2516-2519, ICMP 219 * over 2526), hence an MTU value of 2400 seems safe. This issue only affects 220 * packet reception. This is probably caused by the PPA engine, which is on the 221 * RX part of the device. Packet transmission works properly up to 10240. 222 */ 223 #define GSWIP_MAX_PACKET_LENGTH 2400 224 225 struct gswip_pce_microcode { 226 u16 val_3; 227 u16 val_2; 228 u16 val_1; 229 u16 val_0; 230 }; 231 232 struct gswip_hw_info { 233 int max_ports; 234 unsigned int allowed_cpu_ports; 235 unsigned int mii_ports; 236 int mii_port_reg_offset; 237 const struct gswip_pce_microcode (*pce_microcode)[]; 238 size_t pce_microcode_size; 239 enum dsa_tag_protocol tag_protocol; 240 void (*phylink_get_caps)(struct dsa_switch *ds, int port, 241 struct phylink_config *config); 242 struct phylink_pcs *(*mac_select_pcs)(struct phylink_config *config, 243 phy_interface_t interface); 244 }; 245 246 struct gswip_gphy_fw { 247 struct clk *clk_gate; 248 struct reset_control *reset; 249 u32 fw_addr_offset; 250 char *fw_name; 251 }; 252 253 struct gswip_vlan { 254 struct net_device *bridge; 255 u16 vid; 256 u8 fid; 257 }; 258 259 struct gswip_priv { 260 __iomem void *gswip; 261 __iomem void *mdio; 262 __iomem void *mii; 263 const struct gswip_hw_info *hw_info; 264 const struct xway_gphy_match_data *gphy_fw_name_cfg; 265 struct dsa_switch *ds; 266 struct device *dev; 267 struct regmap *rcu_regmap; 268 struct gswip_vlan vlans[64]; 269 int num_gphy_fw; 270 struct gswip_gphy_fw *gphy_fw; 271 u32 port_vlan_filter; 272 struct mutex pce_table_lock; 273 u16 version; 274 }; 275 276 #endif /* __LANTIQ_GSWIP_H */ 277