1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Lantiq / Intel GSWIP switch driver for VRX200, xRX300 and xRX330 SoCs 4 * 5 * Copyright (C) 2010 Lantiq Deutschland 6 * Copyright (C) 2012 John Crispin <john@phrozen.org> 7 * Copyright (C) 2017 - 2019 Hauke Mehrtens <hauke@hauke-m.de> 8 * 9 * The VLAN and bridge model the GSWIP hardware uses does not directly 10 * matches the model DSA uses. 11 * 12 * The hardware has 64 possible table entries for bridges with one VLAN 13 * ID, one flow id and a list of ports for each bridge. All entries which 14 * match the same flow ID are combined in the mac learning table, they 15 * act as one global bridge. 16 * The hardware does not support VLAN filter on the port, but on the 17 * bridge, this driver converts the DSA model to the hardware. 18 * 19 * The CPU gets all the exception frames which do not match any forwarding 20 * rule and the CPU port is also added to all bridges. This makes it possible 21 * to handle all the special cases easily in software. 22 * At the initialization the driver allocates one bridge table entry for 23 * each switch port which is used when the port is used without an 24 * explicit bridge. This prevents the frames from being forwarded 25 * between all LAN ports by default. 26 */ 27 28 #include "lantiq_gswip.h" 29 #include "lantiq_pce.h" 30 31 #include <linux/delay.h> 32 #include <linux/etherdevice.h> 33 #include <linux/firmware.h> 34 #include <linux/if_bridge.h> 35 #include <linux/if_vlan.h> 36 #include <linux/iopoll.h> 37 #include <linux/mfd/syscon.h> 38 #include <linux/module.h> 39 #include <linux/of_mdio.h> 40 #include <linux/of_net.h> 41 #include <linux/of_platform.h> 42 #include <linux/phy.h> 43 #include <linux/phylink.h> 44 #include <dt-bindings/mips/lantiq_rcu_gphy.h> 45 46 struct xway_gphy_match_data { 47 char *fe_firmware_name; 48 char *ge_firmware_name; 49 }; 50 51 struct gswip_pce_table_entry { 52 u16 index; // PCE_TBL_ADDR.ADDR = pData->table_index 53 u16 table; // PCE_TBL_CTRL.ADDR = pData->table 54 u16 key[8]; 55 u16 val[5]; 56 u16 mask; 57 u8 gmap; 58 bool type; 59 bool valid; 60 bool key_mode; 61 }; 62 63 struct gswip_rmon_cnt_desc { 64 unsigned int size; 65 unsigned int offset; 66 const char *name; 67 }; 68 69 #define MIB_DESC(_size, _offset, _name) {.size = _size, .offset = _offset, .name = _name} 70 71 static const struct gswip_rmon_cnt_desc gswip_rmon_cnt[] = { 72 /** Receive Packet Count (only packets that are accepted and not discarded). */ 73 MIB_DESC(1, 0x1F, "RxGoodPkts"), 74 MIB_DESC(1, 0x23, "RxUnicastPkts"), 75 MIB_DESC(1, 0x22, "RxMulticastPkts"), 76 MIB_DESC(1, 0x21, "RxFCSErrorPkts"), 77 MIB_DESC(1, 0x1D, "RxUnderSizeGoodPkts"), 78 MIB_DESC(1, 0x1E, "RxUnderSizeErrorPkts"), 79 MIB_DESC(1, 0x1B, "RxOversizeGoodPkts"), 80 MIB_DESC(1, 0x1C, "RxOversizeErrorPkts"), 81 MIB_DESC(1, 0x20, "RxGoodPausePkts"), 82 MIB_DESC(1, 0x1A, "RxAlignErrorPkts"), 83 MIB_DESC(1, 0x12, "Rx64BytePkts"), 84 MIB_DESC(1, 0x13, "Rx127BytePkts"), 85 MIB_DESC(1, 0x14, "Rx255BytePkts"), 86 MIB_DESC(1, 0x15, "Rx511BytePkts"), 87 MIB_DESC(1, 0x16, "Rx1023BytePkts"), 88 /** Receive Size 1024-1522 (or more, if configured) Packet Count. */ 89 MIB_DESC(1, 0x17, "RxMaxBytePkts"), 90 MIB_DESC(1, 0x18, "RxDroppedPkts"), 91 MIB_DESC(1, 0x19, "RxFilteredPkts"), 92 MIB_DESC(2, 0x24, "RxGoodBytes"), 93 MIB_DESC(2, 0x26, "RxBadBytes"), 94 MIB_DESC(1, 0x11, "TxAcmDroppedPkts"), 95 MIB_DESC(1, 0x0C, "TxGoodPkts"), 96 MIB_DESC(1, 0x06, "TxUnicastPkts"), 97 MIB_DESC(1, 0x07, "TxMulticastPkts"), 98 MIB_DESC(1, 0x00, "Tx64BytePkts"), 99 MIB_DESC(1, 0x01, "Tx127BytePkts"), 100 MIB_DESC(1, 0x02, "Tx255BytePkts"), 101 MIB_DESC(1, 0x03, "Tx511BytePkts"), 102 MIB_DESC(1, 0x04, "Tx1023BytePkts"), 103 /** Transmit Size 1024-1522 (or more, if configured) Packet Count. */ 104 MIB_DESC(1, 0x05, "TxMaxBytePkts"), 105 MIB_DESC(1, 0x08, "TxSingleCollCount"), 106 MIB_DESC(1, 0x09, "TxMultCollCount"), 107 MIB_DESC(1, 0x0A, "TxLateCollCount"), 108 MIB_DESC(1, 0x0B, "TxExcessCollCount"), 109 MIB_DESC(1, 0x0D, "TxPauseCount"), 110 MIB_DESC(1, 0x10, "TxDroppedPkts"), 111 MIB_DESC(2, 0x0E, "TxGoodBytes"), 112 }; 113 114 static u32 gswip_switch_r(struct gswip_priv *priv, u32 offset) 115 { 116 return __raw_readl(priv->gswip + (offset * 4)); 117 } 118 119 static void gswip_switch_w(struct gswip_priv *priv, u32 val, u32 offset) 120 { 121 __raw_writel(val, priv->gswip + (offset * 4)); 122 } 123 124 static void gswip_switch_mask(struct gswip_priv *priv, u32 clear, u32 set, 125 u32 offset) 126 { 127 u32 val = gswip_switch_r(priv, offset); 128 129 val &= ~(clear); 130 val |= set; 131 gswip_switch_w(priv, val, offset); 132 } 133 134 static u32 gswip_switch_r_timeout(struct gswip_priv *priv, u32 offset, 135 u32 cleared) 136 { 137 u32 val; 138 139 return readx_poll_timeout(__raw_readl, priv->gswip + (offset * 4), val, 140 (val & cleared) == 0, 20, 50000); 141 } 142 143 static u32 gswip_mdio_r(struct gswip_priv *priv, u32 offset) 144 { 145 return __raw_readl(priv->mdio + (offset * 4)); 146 } 147 148 static void gswip_mdio_w(struct gswip_priv *priv, u32 val, u32 offset) 149 { 150 __raw_writel(val, priv->mdio + (offset * 4)); 151 } 152 153 static void gswip_mdio_mask(struct gswip_priv *priv, u32 clear, u32 set, 154 u32 offset) 155 { 156 u32 val = gswip_mdio_r(priv, offset); 157 158 val &= ~(clear); 159 val |= set; 160 gswip_mdio_w(priv, val, offset); 161 } 162 163 static u32 gswip_mii_r(struct gswip_priv *priv, u32 offset) 164 { 165 return __raw_readl(priv->mii + (offset * 4)); 166 } 167 168 static void gswip_mii_w(struct gswip_priv *priv, u32 val, u32 offset) 169 { 170 __raw_writel(val, priv->mii + (offset * 4)); 171 } 172 173 static void gswip_mii_mask(struct gswip_priv *priv, u32 clear, u32 set, 174 u32 offset) 175 { 176 u32 val = gswip_mii_r(priv, offset); 177 178 val &= ~(clear); 179 val |= set; 180 gswip_mii_w(priv, val, offset); 181 } 182 183 static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set, 184 int port) 185 { 186 int reg_port; 187 188 /* MII_CFG register only exists for MII ports */ 189 if (!(priv->hw_info->mii_ports & BIT(port))) 190 return; 191 192 reg_port = port + priv->hw_info->mii_port_reg_offset; 193 194 gswip_mii_mask(priv, clear, set, GSWIP_MII_CFGp(reg_port)); 195 } 196 197 static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 clear, u32 set, 198 int port) 199 { 200 int reg_port; 201 202 /* MII_PCDU register only exists for MII ports */ 203 if (!(priv->hw_info->mii_ports & BIT(port))) 204 return; 205 206 reg_port = port + priv->hw_info->mii_port_reg_offset; 207 208 switch (reg_port) { 209 case 0: 210 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU0); 211 break; 212 case 1: 213 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU1); 214 break; 215 case 5: 216 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU5); 217 break; 218 } 219 } 220 221 static int gswip_mdio_poll(struct gswip_priv *priv) 222 { 223 int cnt = 100; 224 225 while (likely(cnt--)) { 226 u32 ctrl = gswip_mdio_r(priv, GSWIP_MDIO_CTRL); 227 228 if ((ctrl & GSWIP_MDIO_CTRL_BUSY) == 0) 229 return 0; 230 usleep_range(20, 40); 231 } 232 233 return -ETIMEDOUT; 234 } 235 236 static int gswip_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val) 237 { 238 struct gswip_priv *priv = bus->priv; 239 int err; 240 241 err = gswip_mdio_poll(priv); 242 if (err) { 243 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); 244 return err; 245 } 246 247 gswip_mdio_w(priv, val, GSWIP_MDIO_WRITE); 248 gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_WR | 249 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) | 250 (reg & GSWIP_MDIO_CTRL_REGAD_MASK), 251 GSWIP_MDIO_CTRL); 252 253 return 0; 254 } 255 256 static int gswip_mdio_rd(struct mii_bus *bus, int addr, int reg) 257 { 258 struct gswip_priv *priv = bus->priv; 259 int err; 260 261 err = gswip_mdio_poll(priv); 262 if (err) { 263 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); 264 return err; 265 } 266 267 gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_RD | 268 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) | 269 (reg & GSWIP_MDIO_CTRL_REGAD_MASK), 270 GSWIP_MDIO_CTRL); 271 272 err = gswip_mdio_poll(priv); 273 if (err) { 274 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); 275 return err; 276 } 277 278 return gswip_mdio_r(priv, GSWIP_MDIO_READ); 279 } 280 281 static int gswip_mdio(struct gswip_priv *priv) 282 { 283 struct device_node *mdio_np, *switch_np = priv->dev->of_node; 284 struct device *dev = priv->dev; 285 struct mii_bus *bus; 286 int err = 0; 287 288 mdio_np = of_get_compatible_child(switch_np, "lantiq,xrx200-mdio"); 289 if (!mdio_np) 290 mdio_np = of_get_child_by_name(switch_np, "mdio"); 291 292 if (!of_device_is_available(mdio_np)) 293 goto out_put_node; 294 295 bus = devm_mdiobus_alloc(dev); 296 if (!bus) { 297 err = -ENOMEM; 298 goto out_put_node; 299 } 300 301 bus->priv = priv; 302 bus->read = gswip_mdio_rd; 303 bus->write = gswip_mdio_wr; 304 bus->name = "lantiq,xrx200-mdio"; 305 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(priv->dev)); 306 bus->parent = priv->dev; 307 308 err = devm_of_mdiobus_register(dev, bus, mdio_np); 309 310 out_put_node: 311 of_node_put(mdio_np); 312 313 return err; 314 } 315 316 static int gswip_pce_table_entry_read(struct gswip_priv *priv, 317 struct gswip_pce_table_entry *tbl) 318 { 319 int i; 320 int err; 321 u16 crtl; 322 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSRD : 323 GSWIP_PCE_TBL_CTRL_OPMOD_ADRD; 324 325 mutex_lock(&priv->pce_table_lock); 326 327 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 328 GSWIP_PCE_TBL_CTRL_BAS); 329 if (err) { 330 mutex_unlock(&priv->pce_table_lock); 331 return err; 332 } 333 334 gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR); 335 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 336 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 337 tbl->table | addr_mode | GSWIP_PCE_TBL_CTRL_BAS, 338 GSWIP_PCE_TBL_CTRL); 339 340 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 341 GSWIP_PCE_TBL_CTRL_BAS); 342 if (err) { 343 mutex_unlock(&priv->pce_table_lock); 344 return err; 345 } 346 347 for (i = 0; i < ARRAY_SIZE(tbl->key); i++) 348 tbl->key[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_KEY(i)); 349 350 for (i = 0; i < ARRAY_SIZE(tbl->val); i++) 351 tbl->val[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_VAL(i)); 352 353 tbl->mask = gswip_switch_r(priv, GSWIP_PCE_TBL_MASK); 354 355 crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL); 356 357 tbl->type = !!(crtl & GSWIP_PCE_TBL_CTRL_TYPE); 358 tbl->valid = !!(crtl & GSWIP_PCE_TBL_CTRL_VLD); 359 tbl->gmap = (crtl & GSWIP_PCE_TBL_CTRL_GMAP_MASK) >> 7; 360 361 mutex_unlock(&priv->pce_table_lock); 362 363 return 0; 364 } 365 366 static int gswip_pce_table_entry_write(struct gswip_priv *priv, 367 struct gswip_pce_table_entry *tbl) 368 { 369 int i; 370 int err; 371 u16 crtl; 372 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSWR : 373 GSWIP_PCE_TBL_CTRL_OPMOD_ADWR; 374 375 mutex_lock(&priv->pce_table_lock); 376 377 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 378 GSWIP_PCE_TBL_CTRL_BAS); 379 if (err) { 380 mutex_unlock(&priv->pce_table_lock); 381 return err; 382 } 383 384 gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR); 385 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 386 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 387 tbl->table | addr_mode, 388 GSWIP_PCE_TBL_CTRL); 389 390 for (i = 0; i < ARRAY_SIZE(tbl->key); i++) 391 gswip_switch_w(priv, tbl->key[i], GSWIP_PCE_TBL_KEY(i)); 392 393 for (i = 0; i < ARRAY_SIZE(tbl->val); i++) 394 gswip_switch_w(priv, tbl->val[i], GSWIP_PCE_TBL_VAL(i)); 395 396 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 397 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 398 tbl->table | addr_mode, 399 GSWIP_PCE_TBL_CTRL); 400 401 gswip_switch_w(priv, tbl->mask, GSWIP_PCE_TBL_MASK); 402 403 crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL); 404 crtl &= ~(GSWIP_PCE_TBL_CTRL_TYPE | GSWIP_PCE_TBL_CTRL_VLD | 405 GSWIP_PCE_TBL_CTRL_GMAP_MASK); 406 if (tbl->type) 407 crtl |= GSWIP_PCE_TBL_CTRL_TYPE; 408 if (tbl->valid) 409 crtl |= GSWIP_PCE_TBL_CTRL_VLD; 410 crtl |= (tbl->gmap << 7) & GSWIP_PCE_TBL_CTRL_GMAP_MASK; 411 crtl |= GSWIP_PCE_TBL_CTRL_BAS; 412 gswip_switch_w(priv, crtl, GSWIP_PCE_TBL_CTRL); 413 414 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 415 GSWIP_PCE_TBL_CTRL_BAS); 416 417 mutex_unlock(&priv->pce_table_lock); 418 419 return err; 420 } 421 422 /* Add the LAN port into a bridge with the CPU port by 423 * default. This prevents automatic forwarding of 424 * packages between the LAN ports when no explicit 425 * bridge is configured. 426 */ 427 static int gswip_add_single_port_br(struct gswip_priv *priv, int port, bool add) 428 { 429 struct gswip_pce_table_entry vlan_active = {0,}; 430 struct gswip_pce_table_entry vlan_mapping = {0,}; 431 int err; 432 433 vlan_active.index = port + 1; 434 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN; 435 vlan_active.key[0] = 0; /* vid */ 436 vlan_active.val[0] = port + 1 /* fid */; 437 vlan_active.valid = add; 438 err = gswip_pce_table_entry_write(priv, &vlan_active); 439 if (err) { 440 dev_err(priv->dev, "failed to write active VLAN: %d\n", err); 441 return err; 442 } 443 444 if (!add) 445 return 0; 446 447 vlan_mapping.index = port + 1; 448 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 449 vlan_mapping.val[0] = 0 /* vid */; 450 vlan_mapping.val[1] = BIT(port) | dsa_cpu_ports(priv->ds); 451 vlan_mapping.val[2] = 0; 452 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 453 if (err) { 454 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 455 return err; 456 } 457 458 return 0; 459 } 460 461 static int gswip_port_setup(struct dsa_switch *ds, int port) 462 { 463 struct gswip_priv *priv = ds->priv; 464 int err; 465 466 if (!dsa_is_cpu_port(ds, port)) { 467 err = gswip_add_single_port_br(priv, port, true); 468 if (err) 469 return err; 470 } 471 472 return 0; 473 } 474 475 static int gswip_port_enable(struct dsa_switch *ds, int port, 476 struct phy_device *phydev) 477 { 478 struct gswip_priv *priv = ds->priv; 479 480 if (!dsa_is_cpu_port(ds, port)) { 481 u32 mdio_phy = 0; 482 483 if (phydev) 484 mdio_phy = phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK; 485 486 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_ADDR_MASK, mdio_phy, 487 GSWIP_MDIO_PHYp(port)); 488 } 489 490 /* RMON Counter Enable for port */ 491 gswip_switch_w(priv, GSWIP_BM_PCFG_CNTEN, GSWIP_BM_PCFGp(port)); 492 493 /* enable port fetch/store dma & VLAN Modification */ 494 gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_EN | 495 GSWIP_FDMA_PCTRL_VLANMOD_BOTH, 496 GSWIP_FDMA_PCTRLp(port)); 497 gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN, 498 GSWIP_SDMA_PCTRLp(port)); 499 500 return 0; 501 } 502 503 static void gswip_port_disable(struct dsa_switch *ds, int port) 504 { 505 struct gswip_priv *priv = ds->priv; 506 507 gswip_switch_mask(priv, GSWIP_FDMA_PCTRL_EN, 0, 508 GSWIP_FDMA_PCTRLp(port)); 509 gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0, 510 GSWIP_SDMA_PCTRLp(port)); 511 } 512 513 static int gswip_pce_load_microcode(struct gswip_priv *priv) 514 { 515 int i; 516 int err; 517 518 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 519 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 520 GSWIP_PCE_TBL_CTRL_OPMOD_ADWR, GSWIP_PCE_TBL_CTRL); 521 gswip_switch_w(priv, 0, GSWIP_PCE_TBL_MASK); 522 523 for (i = 0; i < priv->hw_info->pce_microcode_size; i++) { 524 gswip_switch_w(priv, i, GSWIP_PCE_TBL_ADDR); 525 gswip_switch_w(priv, (*priv->hw_info->pce_microcode)[i].val_0, 526 GSWIP_PCE_TBL_VAL(0)); 527 gswip_switch_w(priv, (*priv->hw_info->pce_microcode)[i].val_1, 528 GSWIP_PCE_TBL_VAL(1)); 529 gswip_switch_w(priv, (*priv->hw_info->pce_microcode)[i].val_2, 530 GSWIP_PCE_TBL_VAL(2)); 531 gswip_switch_w(priv, (*priv->hw_info->pce_microcode)[i].val_3, 532 GSWIP_PCE_TBL_VAL(3)); 533 534 /* start the table access: */ 535 gswip_switch_mask(priv, 0, GSWIP_PCE_TBL_CTRL_BAS, 536 GSWIP_PCE_TBL_CTRL); 537 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 538 GSWIP_PCE_TBL_CTRL_BAS); 539 if (err) 540 return err; 541 } 542 543 /* tell the switch that the microcode is loaded */ 544 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MC_VALID, 545 GSWIP_PCE_GCTRL_0); 546 547 return 0; 548 } 549 550 static int gswip_port_vlan_filtering(struct dsa_switch *ds, int port, 551 bool vlan_filtering, 552 struct netlink_ext_ack *extack) 553 { 554 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port)); 555 struct gswip_priv *priv = ds->priv; 556 557 /* Do not allow changing the VLAN filtering options while in bridge */ 558 if (bridge && !!(priv->port_vlan_filter & BIT(port)) != vlan_filtering) { 559 NL_SET_ERR_MSG_MOD(extack, 560 "Dynamic toggling of vlan_filtering not supported"); 561 return -EIO; 562 } 563 564 if (vlan_filtering) { 565 /* Use tag based VLAN */ 566 gswip_switch_mask(priv, 567 GSWIP_PCE_VCTRL_VSR, 568 GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR | 569 GSWIP_PCE_VCTRL_VEMR, 570 GSWIP_PCE_VCTRL(port)); 571 gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_TVM, 0, 572 GSWIP_PCE_PCTRL_0p(port)); 573 } else { 574 /* Use port based VLAN */ 575 gswip_switch_mask(priv, 576 GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR | 577 GSWIP_PCE_VCTRL_VEMR, 578 GSWIP_PCE_VCTRL_VSR, 579 GSWIP_PCE_VCTRL(port)); 580 gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_TVM, 581 GSWIP_PCE_PCTRL_0p(port)); 582 } 583 584 return 0; 585 } 586 587 static int gswip_setup(struct dsa_switch *ds) 588 { 589 unsigned int cpu_ports = dsa_cpu_ports(ds); 590 struct gswip_priv *priv = ds->priv; 591 struct dsa_port *cpu_dp; 592 int err, i; 593 594 gswip_switch_w(priv, GSWIP_SWRES_R0, GSWIP_SWRES); 595 usleep_range(5000, 10000); 596 gswip_switch_w(priv, 0, GSWIP_SWRES); 597 598 /* disable port fetch/store dma on all ports */ 599 for (i = 0; i < priv->hw_info->max_ports; i++) { 600 gswip_port_disable(ds, i); 601 gswip_port_vlan_filtering(ds, i, false, NULL); 602 } 603 604 /* enable Switch */ 605 gswip_mdio_mask(priv, 0, GSWIP_MDIO_GLOB_ENABLE, GSWIP_MDIO_GLOB); 606 607 err = gswip_pce_load_microcode(priv); 608 if (err) { 609 dev_err(priv->dev, "writing PCE microcode failed, %i\n", err); 610 return err; 611 } 612 613 /* Default unknown Broadcast/Multicast/Unicast port maps */ 614 gswip_switch_w(priv, cpu_ports, GSWIP_PCE_PMAP1); 615 gswip_switch_w(priv, cpu_ports, GSWIP_PCE_PMAP2); 616 gswip_switch_w(priv, cpu_ports, GSWIP_PCE_PMAP3); 617 618 /* Deactivate MDIO PHY auto polling. Some PHYs as the AR8030 have an 619 * interoperability problem with this auto polling mechanism because 620 * their status registers think that the link is in a different state 621 * than it actually is. For the AR8030 it has the BMSR_ESTATEN bit set 622 * as well as ESTATUS_1000_TFULL and ESTATUS_1000_XFULL. This makes the 623 * auto polling state machine consider the link being negotiated with 624 * 1Gbit/s. Since the PHY itself is a Fast Ethernet RMII PHY this leads 625 * to the switch port being completely dead (RX and TX are both not 626 * working). 627 * Also with various other PHY / port combinations (PHY11G GPHY, PHY22F 628 * GPHY, external RGMII PEF7071/7072) any traffic would stop. Sometimes 629 * it would work fine for a few minutes to hours and then stop, on 630 * other device it would no traffic could be sent or received at all. 631 * Testing shows that when PHY auto polling is disabled these problems 632 * go away. 633 */ 634 gswip_mdio_w(priv, 0x0, GSWIP_MDIO_MDC_CFG0); 635 636 /* Configure the MDIO Clock 2.5 MHz */ 637 gswip_mdio_mask(priv, 0xff, 0x09, GSWIP_MDIO_MDC_CFG1); 638 639 /* bring up the mdio bus */ 640 err = gswip_mdio(priv); 641 if (err) { 642 dev_err(priv->dev, "mdio bus setup failed\n"); 643 return err; 644 } 645 646 /* Disable the xMII interface and clear it's isolation bit */ 647 for (i = 0; i < priv->hw_info->max_ports; i++) 648 gswip_mii_mask_cfg(priv, 649 GSWIP_MII_CFG_EN | GSWIP_MII_CFG_ISOLATE, 650 0, i); 651 652 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 653 /* enable special tag insertion on cpu port */ 654 gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_STEN, 655 GSWIP_FDMA_PCTRLp(cpu_dp->index)); 656 657 /* accept special tag in ingress direction */ 658 gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_INGRESS, 659 GSWIP_PCE_PCTRL_0p(cpu_dp->index)); 660 } 661 662 gswip_switch_mask(priv, 0, GSWIP_BM_QUEUE_GCTRL_GL_MOD, 663 GSWIP_BM_QUEUE_GCTRL); 664 665 /* VLAN aware Switching */ 666 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_VLAN, GSWIP_PCE_GCTRL_0); 667 668 /* Flush MAC Table */ 669 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MTFL, GSWIP_PCE_GCTRL_0); 670 671 err = gswip_switch_r_timeout(priv, GSWIP_PCE_GCTRL_0, 672 GSWIP_PCE_GCTRL_0_MTFL); 673 if (err) { 674 dev_err(priv->dev, "MAC flushing didn't finish\n"); 675 return err; 676 } 677 678 ds->mtu_enforcement_ingress = true; 679 680 ds->configure_vlan_while_not_filtering = false; 681 682 return 0; 683 } 684 685 static enum dsa_tag_protocol gswip_get_tag_protocol(struct dsa_switch *ds, 686 int port, 687 enum dsa_tag_protocol mp) 688 { 689 struct gswip_priv *priv = ds->priv; 690 691 return priv->hw_info->tag_protocol; 692 } 693 694 static int gswip_vlan_active_create(struct gswip_priv *priv, 695 struct net_device *bridge, 696 int fid, u16 vid) 697 { 698 struct gswip_pce_table_entry vlan_active = {0,}; 699 unsigned int max_ports = priv->hw_info->max_ports; 700 int idx = -1; 701 int err; 702 int i; 703 704 /* Look for a free slot */ 705 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 706 if (!priv->vlans[i].bridge) { 707 idx = i; 708 break; 709 } 710 } 711 712 if (idx == -1) 713 return -ENOSPC; 714 715 if (fid == -1) 716 fid = idx; 717 718 vlan_active.index = idx; 719 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN; 720 vlan_active.key[0] = vid; 721 vlan_active.val[0] = fid; 722 vlan_active.valid = true; 723 724 err = gswip_pce_table_entry_write(priv, &vlan_active); 725 if (err) { 726 dev_err(priv->dev, "failed to write active VLAN: %d\n", err); 727 return err; 728 } 729 730 priv->vlans[idx].bridge = bridge; 731 priv->vlans[idx].vid = vid; 732 priv->vlans[idx].fid = fid; 733 734 return idx; 735 } 736 737 static int gswip_vlan_active_remove(struct gswip_priv *priv, int idx) 738 { 739 struct gswip_pce_table_entry vlan_active = {0,}; 740 int err; 741 742 vlan_active.index = idx; 743 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN; 744 vlan_active.valid = false; 745 err = gswip_pce_table_entry_write(priv, &vlan_active); 746 if (err) 747 dev_err(priv->dev, "failed to delete active VLAN: %d\n", err); 748 priv->vlans[idx].bridge = NULL; 749 750 return err; 751 } 752 753 static int gswip_vlan_add_unaware(struct gswip_priv *priv, 754 struct net_device *bridge, int port) 755 { 756 struct gswip_pce_table_entry vlan_mapping = {0,}; 757 unsigned int max_ports = priv->hw_info->max_ports; 758 bool active_vlan_created = false; 759 int idx = -1; 760 int i; 761 int err; 762 763 /* Check if there is already a page for this bridge */ 764 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 765 if (priv->vlans[i].bridge == bridge) { 766 idx = i; 767 break; 768 } 769 } 770 771 /* If this bridge is not programmed yet, add a Active VLAN table 772 * entry in a free slot and prepare the VLAN mapping table entry. 773 */ 774 if (idx == -1) { 775 idx = gswip_vlan_active_create(priv, bridge, -1, 0); 776 if (idx < 0) 777 return idx; 778 active_vlan_created = true; 779 780 vlan_mapping.index = idx; 781 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 782 /* VLAN ID byte, maps to the VLAN ID of vlan active table */ 783 vlan_mapping.val[0] = 0; 784 } else { 785 /* Read the existing VLAN mapping entry from the switch */ 786 vlan_mapping.index = idx; 787 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 788 err = gswip_pce_table_entry_read(priv, &vlan_mapping); 789 if (err) { 790 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", 791 err); 792 return err; 793 } 794 } 795 796 /* Update the VLAN mapping entry and write it to the switch */ 797 vlan_mapping.val[1] |= dsa_cpu_ports(priv->ds); 798 vlan_mapping.val[1] |= BIT(port); 799 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 800 if (err) { 801 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 802 /* In case an Active VLAN was creaetd delete it again */ 803 if (active_vlan_created) 804 gswip_vlan_active_remove(priv, idx); 805 return err; 806 } 807 808 gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port)); 809 return 0; 810 } 811 812 static int gswip_vlan_add_aware(struct gswip_priv *priv, 813 struct net_device *bridge, int port, 814 u16 vid, bool untagged, 815 bool pvid) 816 { 817 struct gswip_pce_table_entry vlan_mapping = {0,}; 818 unsigned int max_ports = priv->hw_info->max_ports; 819 unsigned int cpu_ports = dsa_cpu_ports(priv->ds); 820 bool active_vlan_created = false; 821 int idx = -1; 822 int fid = -1; 823 int i; 824 int err; 825 826 /* Check if there is already a page for this bridge */ 827 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 828 if (priv->vlans[i].bridge == bridge) { 829 if (fid != -1 && fid != priv->vlans[i].fid) 830 dev_err(priv->dev, "one bridge with multiple flow ids\n"); 831 fid = priv->vlans[i].fid; 832 if (priv->vlans[i].vid == vid) { 833 idx = i; 834 break; 835 } 836 } 837 } 838 839 /* If this bridge is not programmed yet, add a Active VLAN table 840 * entry in a free slot and prepare the VLAN mapping table entry. 841 */ 842 if (idx == -1) { 843 idx = gswip_vlan_active_create(priv, bridge, fid, vid); 844 if (idx < 0) 845 return idx; 846 active_vlan_created = true; 847 848 vlan_mapping.index = idx; 849 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 850 /* VLAN ID byte, maps to the VLAN ID of vlan active table */ 851 vlan_mapping.val[0] = vid; 852 } else { 853 /* Read the existing VLAN mapping entry from the switch */ 854 vlan_mapping.index = idx; 855 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 856 err = gswip_pce_table_entry_read(priv, &vlan_mapping); 857 if (err) { 858 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", 859 err); 860 return err; 861 } 862 } 863 864 vlan_mapping.val[0] = vid; 865 /* Update the VLAN mapping entry and write it to the switch */ 866 vlan_mapping.val[1] |= cpu_ports; 867 vlan_mapping.val[2] |= cpu_ports; 868 vlan_mapping.val[1] |= BIT(port); 869 if (untagged) 870 vlan_mapping.val[2] &= ~BIT(port); 871 else 872 vlan_mapping.val[2] |= BIT(port); 873 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 874 if (err) { 875 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 876 /* In case an Active VLAN was creaetd delete it again */ 877 if (active_vlan_created) 878 gswip_vlan_active_remove(priv, idx); 879 return err; 880 } 881 882 if (pvid) 883 gswip_switch_w(priv, idx, GSWIP_PCE_DEFPVID(port)); 884 885 return 0; 886 } 887 888 static int gswip_vlan_remove(struct gswip_priv *priv, 889 struct net_device *bridge, int port, 890 u16 vid, bool pvid, bool vlan_aware) 891 { 892 struct gswip_pce_table_entry vlan_mapping = {0,}; 893 unsigned int max_ports = priv->hw_info->max_ports; 894 int idx = -1; 895 int i; 896 int err; 897 898 /* Check if there is already a page for this bridge */ 899 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 900 if (priv->vlans[i].bridge == bridge && 901 (!vlan_aware || priv->vlans[i].vid == vid)) { 902 idx = i; 903 break; 904 } 905 } 906 907 if (idx == -1) { 908 dev_err(priv->dev, "bridge to leave does not exists\n"); 909 return -ENOENT; 910 } 911 912 vlan_mapping.index = idx; 913 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 914 err = gswip_pce_table_entry_read(priv, &vlan_mapping); 915 if (err) { 916 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", err); 917 return err; 918 } 919 920 vlan_mapping.val[1] &= ~BIT(port); 921 vlan_mapping.val[2] &= ~BIT(port); 922 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 923 if (err) { 924 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 925 return err; 926 } 927 928 /* In case all ports are removed from the bridge, remove the VLAN */ 929 if (!(vlan_mapping.val[1] & ~dsa_cpu_ports(priv->ds))) { 930 err = gswip_vlan_active_remove(priv, idx); 931 if (err) { 932 dev_err(priv->dev, "failed to write active VLAN: %d\n", 933 err); 934 return err; 935 } 936 } 937 938 /* GSWIP 2.2 (GRX300) and later program here the VID directly. */ 939 if (pvid) 940 gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port)); 941 942 return 0; 943 } 944 945 static int gswip_port_bridge_join(struct dsa_switch *ds, int port, 946 struct dsa_bridge bridge, 947 bool *tx_fwd_offload, 948 struct netlink_ext_ack *extack) 949 { 950 struct net_device *br = bridge.dev; 951 struct gswip_priv *priv = ds->priv; 952 int err; 953 954 /* When the bridge uses VLAN filtering we have to configure VLAN 955 * specific bridges. No bridge is configured here. 956 */ 957 if (!br_vlan_enabled(br)) { 958 err = gswip_vlan_add_unaware(priv, br, port); 959 if (err) 960 return err; 961 priv->port_vlan_filter &= ~BIT(port); 962 } else { 963 priv->port_vlan_filter |= BIT(port); 964 } 965 return gswip_add_single_port_br(priv, port, false); 966 } 967 968 static void gswip_port_bridge_leave(struct dsa_switch *ds, int port, 969 struct dsa_bridge bridge) 970 { 971 struct net_device *br = bridge.dev; 972 struct gswip_priv *priv = ds->priv; 973 974 gswip_add_single_port_br(priv, port, true); 975 976 /* When the bridge uses VLAN filtering we have to configure VLAN 977 * specific bridges. No bridge is configured here. 978 */ 979 if (!br_vlan_enabled(br)) 980 gswip_vlan_remove(priv, br, port, 0, true, false); 981 } 982 983 static int gswip_port_vlan_prepare(struct dsa_switch *ds, int port, 984 const struct switchdev_obj_port_vlan *vlan, 985 struct netlink_ext_ack *extack) 986 { 987 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port)); 988 struct gswip_priv *priv = ds->priv; 989 unsigned int max_ports = priv->hw_info->max_ports; 990 int pos = max_ports; 991 int i, idx = -1; 992 993 /* We only support VLAN filtering on bridges */ 994 if (!dsa_is_cpu_port(ds, port) && !bridge) 995 return -EOPNOTSUPP; 996 997 /* Check if there is already a page for this VLAN */ 998 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 999 if (priv->vlans[i].bridge == bridge && 1000 priv->vlans[i].vid == vlan->vid) { 1001 idx = i; 1002 break; 1003 } 1004 } 1005 1006 /* If this VLAN is not programmed yet, we have to reserve 1007 * one entry in the VLAN table. Make sure we start at the 1008 * next position round. 1009 */ 1010 if (idx == -1) { 1011 /* Look for a free slot */ 1012 for (; pos < ARRAY_SIZE(priv->vlans); pos++) { 1013 if (!priv->vlans[pos].bridge) { 1014 idx = pos; 1015 pos++; 1016 break; 1017 } 1018 } 1019 1020 if (idx == -1) { 1021 NL_SET_ERR_MSG_MOD(extack, "No slot in VLAN table"); 1022 return -ENOSPC; 1023 } 1024 } 1025 1026 return 0; 1027 } 1028 1029 static int gswip_port_vlan_add(struct dsa_switch *ds, int port, 1030 const struct switchdev_obj_port_vlan *vlan, 1031 struct netlink_ext_ack *extack) 1032 { 1033 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port)); 1034 struct gswip_priv *priv = ds->priv; 1035 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1036 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1037 int err; 1038 1039 err = gswip_port_vlan_prepare(ds, port, vlan, extack); 1040 if (err) 1041 return err; 1042 1043 /* We have to receive all packets on the CPU port and should not 1044 * do any VLAN filtering here. This is also called with bridge 1045 * NULL and then we do not know for which bridge to configure 1046 * this. 1047 */ 1048 if (dsa_is_cpu_port(ds, port)) 1049 return 0; 1050 1051 return gswip_vlan_add_aware(priv, bridge, port, vlan->vid, 1052 untagged, pvid); 1053 } 1054 1055 static int gswip_port_vlan_del(struct dsa_switch *ds, int port, 1056 const struct switchdev_obj_port_vlan *vlan) 1057 { 1058 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port)); 1059 struct gswip_priv *priv = ds->priv; 1060 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1061 1062 /* We have to receive all packets on the CPU port and should not 1063 * do any VLAN filtering here. This is also called with bridge 1064 * NULL and then we do not know for which bridge to configure 1065 * this. 1066 */ 1067 if (dsa_is_cpu_port(ds, port)) 1068 return 0; 1069 1070 return gswip_vlan_remove(priv, bridge, port, vlan->vid, pvid, true); 1071 } 1072 1073 static void gswip_port_fast_age(struct dsa_switch *ds, int port) 1074 { 1075 struct gswip_priv *priv = ds->priv; 1076 struct gswip_pce_table_entry mac_bridge = {0,}; 1077 int i; 1078 int err; 1079 1080 for (i = 0; i < 2048; i++) { 1081 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE; 1082 mac_bridge.index = i; 1083 1084 err = gswip_pce_table_entry_read(priv, &mac_bridge); 1085 if (err) { 1086 dev_err(priv->dev, "failed to read mac bridge: %d\n", 1087 err); 1088 return; 1089 } 1090 1091 if (!mac_bridge.valid) 1092 continue; 1093 1094 if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_VAL1_STATIC) 1095 continue; 1096 1097 if (port != FIELD_GET(GSWIP_TABLE_MAC_BRIDGE_VAL0_PORT, 1098 mac_bridge.val[0])) 1099 continue; 1100 1101 mac_bridge.valid = false; 1102 err = gswip_pce_table_entry_write(priv, &mac_bridge); 1103 if (err) { 1104 dev_err(priv->dev, "failed to write mac bridge: %d\n", 1105 err); 1106 return; 1107 } 1108 } 1109 } 1110 1111 static void gswip_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1112 { 1113 struct gswip_priv *priv = ds->priv; 1114 u32 stp_state; 1115 1116 switch (state) { 1117 case BR_STATE_DISABLED: 1118 gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0, 1119 GSWIP_SDMA_PCTRLp(port)); 1120 return; 1121 case BR_STATE_BLOCKING: 1122 case BR_STATE_LISTENING: 1123 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LISTEN; 1124 break; 1125 case BR_STATE_LEARNING: 1126 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LEARNING; 1127 break; 1128 case BR_STATE_FORWARDING: 1129 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING; 1130 break; 1131 default: 1132 dev_err(priv->dev, "invalid STP state: %d\n", state); 1133 return; 1134 } 1135 1136 gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN, 1137 GSWIP_SDMA_PCTRLp(port)); 1138 gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_PSTATE_MASK, stp_state, 1139 GSWIP_PCE_PCTRL_0p(port)); 1140 } 1141 1142 static int gswip_port_fdb(struct dsa_switch *ds, int port, 1143 const unsigned char *addr, u16 vid, bool add) 1144 { 1145 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port)); 1146 struct gswip_priv *priv = ds->priv; 1147 struct gswip_pce_table_entry mac_bridge = {0,}; 1148 unsigned int max_ports = priv->hw_info->max_ports; 1149 int fid = -1; 1150 int i; 1151 int err; 1152 1153 /* Operation not supported on the CPU port, don't throw errors */ 1154 if (!bridge) 1155 return 0; 1156 1157 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 1158 if (priv->vlans[i].bridge == bridge) { 1159 fid = priv->vlans[i].fid; 1160 break; 1161 } 1162 } 1163 1164 if (fid == -1) { 1165 dev_err(priv->dev, "no FID found for bridge %s\n", 1166 bridge->name); 1167 return -EINVAL; 1168 } 1169 1170 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE; 1171 mac_bridge.key_mode = true; 1172 mac_bridge.key[0] = addr[5] | (addr[4] << 8); 1173 mac_bridge.key[1] = addr[3] | (addr[2] << 8); 1174 mac_bridge.key[2] = addr[1] | (addr[0] << 8); 1175 mac_bridge.key[3] = FIELD_PREP(GSWIP_TABLE_MAC_BRIDGE_KEY3_FID, fid); 1176 mac_bridge.val[0] = add ? BIT(port) : 0; /* port map */ 1177 mac_bridge.val[1] = GSWIP_TABLE_MAC_BRIDGE_VAL1_STATIC; 1178 mac_bridge.valid = add; 1179 1180 err = gswip_pce_table_entry_write(priv, &mac_bridge); 1181 if (err) 1182 dev_err(priv->dev, "failed to write mac bridge: %d\n", err); 1183 1184 return err; 1185 } 1186 1187 static int gswip_port_fdb_add(struct dsa_switch *ds, int port, 1188 const unsigned char *addr, u16 vid, 1189 struct dsa_db db) 1190 { 1191 return gswip_port_fdb(ds, port, addr, vid, true); 1192 } 1193 1194 static int gswip_port_fdb_del(struct dsa_switch *ds, int port, 1195 const unsigned char *addr, u16 vid, 1196 struct dsa_db db) 1197 { 1198 return gswip_port_fdb(ds, port, addr, vid, false); 1199 } 1200 1201 static int gswip_port_fdb_dump(struct dsa_switch *ds, int port, 1202 dsa_fdb_dump_cb_t *cb, void *data) 1203 { 1204 struct gswip_priv *priv = ds->priv; 1205 struct gswip_pce_table_entry mac_bridge = {0,}; 1206 unsigned char addr[ETH_ALEN]; 1207 int i; 1208 int err; 1209 1210 for (i = 0; i < 2048; i++) { 1211 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE; 1212 mac_bridge.index = i; 1213 1214 err = gswip_pce_table_entry_read(priv, &mac_bridge); 1215 if (err) { 1216 dev_err(priv->dev, 1217 "failed to read mac bridge entry %d: %d\n", 1218 i, err); 1219 return err; 1220 } 1221 1222 if (!mac_bridge.valid) 1223 continue; 1224 1225 addr[5] = mac_bridge.key[0] & 0xff; 1226 addr[4] = (mac_bridge.key[0] >> 8) & 0xff; 1227 addr[3] = mac_bridge.key[1] & 0xff; 1228 addr[2] = (mac_bridge.key[1] >> 8) & 0xff; 1229 addr[1] = mac_bridge.key[2] & 0xff; 1230 addr[0] = (mac_bridge.key[2] >> 8) & 0xff; 1231 if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_VAL1_STATIC) { 1232 if (mac_bridge.val[0] & BIT(port)) { 1233 err = cb(addr, 0, true, data); 1234 if (err) 1235 return err; 1236 } 1237 } else { 1238 if (port == FIELD_GET(GSWIP_TABLE_MAC_BRIDGE_VAL0_PORT, 1239 mac_bridge.val[0])) { 1240 err = cb(addr, 0, false, data); 1241 if (err) 1242 return err; 1243 } 1244 } 1245 } 1246 return 0; 1247 } 1248 1249 static int gswip_port_max_mtu(struct dsa_switch *ds, int port) 1250 { 1251 /* Includes 8 bytes for special header. */ 1252 return GSWIP_MAX_PACKET_LENGTH - VLAN_ETH_HLEN - ETH_FCS_LEN; 1253 } 1254 1255 static int gswip_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1256 { 1257 struct gswip_priv *priv = ds->priv; 1258 1259 /* CPU port always has maximum mtu of user ports, so use it to set 1260 * switch frame size, including 8 byte special header. 1261 */ 1262 if (dsa_is_cpu_port(ds, port)) { 1263 new_mtu += 8; 1264 gswip_switch_w(priv, VLAN_ETH_HLEN + new_mtu + ETH_FCS_LEN, 1265 GSWIP_MAC_FLEN); 1266 } 1267 1268 /* Enable MLEN for ports with non-standard MTUs, including the special 1269 * header on the CPU port added above. 1270 */ 1271 if (new_mtu != ETH_DATA_LEN) 1272 gswip_switch_mask(priv, 0, GSWIP_MAC_CTRL_2_MLEN, 1273 GSWIP_MAC_CTRL_2p(port)); 1274 else 1275 gswip_switch_mask(priv, GSWIP_MAC_CTRL_2_MLEN, 0, 1276 GSWIP_MAC_CTRL_2p(port)); 1277 1278 return 0; 1279 } 1280 1281 static void gswip_xrx200_phylink_get_caps(struct dsa_switch *ds, int port, 1282 struct phylink_config *config) 1283 { 1284 switch (port) { 1285 case 0: 1286 case 1: 1287 phy_interface_set_rgmii(config->supported_interfaces); 1288 __set_bit(PHY_INTERFACE_MODE_MII, 1289 config->supported_interfaces); 1290 __set_bit(PHY_INTERFACE_MODE_REVMII, 1291 config->supported_interfaces); 1292 __set_bit(PHY_INTERFACE_MODE_RMII, 1293 config->supported_interfaces); 1294 break; 1295 1296 case 2: 1297 case 3: 1298 case 4: 1299 case 6: 1300 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1301 config->supported_interfaces); 1302 break; 1303 1304 case 5: 1305 phy_interface_set_rgmii(config->supported_interfaces); 1306 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1307 config->supported_interfaces); 1308 break; 1309 } 1310 1311 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 1312 MAC_10 | MAC_100 | MAC_1000; 1313 } 1314 1315 static void gswip_xrx300_phylink_get_caps(struct dsa_switch *ds, int port, 1316 struct phylink_config *config) 1317 { 1318 switch (port) { 1319 case 0: 1320 phy_interface_set_rgmii(config->supported_interfaces); 1321 __set_bit(PHY_INTERFACE_MODE_GMII, 1322 config->supported_interfaces); 1323 __set_bit(PHY_INTERFACE_MODE_RMII, 1324 config->supported_interfaces); 1325 break; 1326 1327 case 1: 1328 case 2: 1329 case 3: 1330 case 4: 1331 case 6: 1332 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1333 config->supported_interfaces); 1334 break; 1335 1336 case 5: 1337 phy_interface_set_rgmii(config->supported_interfaces); 1338 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1339 config->supported_interfaces); 1340 __set_bit(PHY_INTERFACE_MODE_RMII, 1341 config->supported_interfaces); 1342 break; 1343 } 1344 1345 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 1346 MAC_10 | MAC_100 | MAC_1000; 1347 } 1348 1349 static void gswip_phylink_get_caps(struct dsa_switch *ds, int port, 1350 struct phylink_config *config) 1351 { 1352 struct gswip_priv *priv = ds->priv; 1353 1354 priv->hw_info->phylink_get_caps(ds, port, config); 1355 } 1356 1357 static void gswip_port_set_link(struct gswip_priv *priv, int port, bool link) 1358 { 1359 u32 mdio_phy; 1360 1361 if (link) 1362 mdio_phy = GSWIP_MDIO_PHY_LINK_UP; 1363 else 1364 mdio_phy = GSWIP_MDIO_PHY_LINK_DOWN; 1365 1366 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_LINK_MASK, mdio_phy, 1367 GSWIP_MDIO_PHYp(port)); 1368 } 1369 1370 static void gswip_port_set_speed(struct gswip_priv *priv, int port, int speed, 1371 phy_interface_t interface) 1372 { 1373 u32 mdio_phy = 0, mii_cfg = 0, mac_ctrl_0 = 0; 1374 1375 switch (speed) { 1376 case SPEED_10: 1377 mdio_phy = GSWIP_MDIO_PHY_SPEED_M10; 1378 1379 if (interface == PHY_INTERFACE_MODE_RMII) 1380 mii_cfg = GSWIP_MII_CFG_RATE_M50; 1381 else 1382 mii_cfg = GSWIP_MII_CFG_RATE_M2P5; 1383 1384 mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_MII; 1385 break; 1386 1387 case SPEED_100: 1388 mdio_phy = GSWIP_MDIO_PHY_SPEED_M100; 1389 1390 if (interface == PHY_INTERFACE_MODE_RMII) 1391 mii_cfg = GSWIP_MII_CFG_RATE_M50; 1392 else 1393 mii_cfg = GSWIP_MII_CFG_RATE_M25; 1394 1395 mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_MII; 1396 break; 1397 1398 case SPEED_1000: 1399 mdio_phy = GSWIP_MDIO_PHY_SPEED_G1; 1400 1401 mii_cfg = GSWIP_MII_CFG_RATE_M125; 1402 1403 mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_RGMII; 1404 break; 1405 } 1406 1407 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_SPEED_MASK, mdio_phy, 1408 GSWIP_MDIO_PHYp(port)); 1409 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_RATE_MASK, mii_cfg, port); 1410 gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_GMII_MASK, mac_ctrl_0, 1411 GSWIP_MAC_CTRL_0p(port)); 1412 } 1413 1414 static void gswip_port_set_duplex(struct gswip_priv *priv, int port, int duplex) 1415 { 1416 u32 mac_ctrl_0, mdio_phy; 1417 1418 if (duplex == DUPLEX_FULL) { 1419 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FDUP_EN; 1420 mdio_phy = GSWIP_MDIO_PHY_FDUP_EN; 1421 } else { 1422 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FDUP_DIS; 1423 mdio_phy = GSWIP_MDIO_PHY_FDUP_DIS; 1424 } 1425 1426 gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_FDUP_MASK, mac_ctrl_0, 1427 GSWIP_MAC_CTRL_0p(port)); 1428 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_FDUP_MASK, mdio_phy, 1429 GSWIP_MDIO_PHYp(port)); 1430 } 1431 1432 static void gswip_port_set_pause(struct gswip_priv *priv, int port, 1433 bool tx_pause, bool rx_pause) 1434 { 1435 u32 mac_ctrl_0, mdio_phy; 1436 1437 if (tx_pause && rx_pause) { 1438 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_RXTX; 1439 mdio_phy = GSWIP_MDIO_PHY_FCONTX_EN | 1440 GSWIP_MDIO_PHY_FCONRX_EN; 1441 } else if (tx_pause) { 1442 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_TX; 1443 mdio_phy = GSWIP_MDIO_PHY_FCONTX_EN | 1444 GSWIP_MDIO_PHY_FCONRX_DIS; 1445 } else if (rx_pause) { 1446 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_RX; 1447 mdio_phy = GSWIP_MDIO_PHY_FCONTX_DIS | 1448 GSWIP_MDIO_PHY_FCONRX_EN; 1449 } else { 1450 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_NONE; 1451 mdio_phy = GSWIP_MDIO_PHY_FCONTX_DIS | 1452 GSWIP_MDIO_PHY_FCONRX_DIS; 1453 } 1454 1455 gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_FCON_MASK, 1456 mac_ctrl_0, GSWIP_MAC_CTRL_0p(port)); 1457 gswip_mdio_mask(priv, 1458 GSWIP_MDIO_PHY_FCONTX_MASK | 1459 GSWIP_MDIO_PHY_FCONRX_MASK, 1460 mdio_phy, GSWIP_MDIO_PHYp(port)); 1461 } 1462 1463 static void gswip_phylink_mac_config(struct phylink_config *config, 1464 unsigned int mode, 1465 const struct phylink_link_state *state) 1466 { 1467 struct dsa_port *dp = dsa_phylink_to_port(config); 1468 struct gswip_priv *priv = dp->ds->priv; 1469 int port = dp->index; 1470 u32 miicfg = 0; 1471 1472 miicfg |= GSWIP_MII_CFG_LDCLKDIS; 1473 1474 switch (state->interface) { 1475 case PHY_INTERFACE_MODE_SGMII: 1476 case PHY_INTERFACE_MODE_1000BASEX: 1477 case PHY_INTERFACE_MODE_2500BASEX: 1478 return; 1479 case PHY_INTERFACE_MODE_MII: 1480 case PHY_INTERFACE_MODE_INTERNAL: 1481 miicfg |= GSWIP_MII_CFG_MODE_MIIM; 1482 break; 1483 case PHY_INTERFACE_MODE_REVMII: 1484 miicfg |= GSWIP_MII_CFG_MODE_MIIP; 1485 break; 1486 case PHY_INTERFACE_MODE_RMII: 1487 miicfg |= GSWIP_MII_CFG_MODE_RMIIM; 1488 break; 1489 case PHY_INTERFACE_MODE_RGMII: 1490 case PHY_INTERFACE_MODE_RGMII_ID: 1491 case PHY_INTERFACE_MODE_RGMII_RXID: 1492 case PHY_INTERFACE_MODE_RGMII_TXID: 1493 miicfg |= GSWIP_MII_CFG_MODE_RGMII; 1494 break; 1495 case PHY_INTERFACE_MODE_GMII: 1496 miicfg |= GSWIP_MII_CFG_MODE_GMII; 1497 break; 1498 default: 1499 dev_err(dp->ds->dev, 1500 "Unsupported interface: %d\n", state->interface); 1501 return; 1502 } 1503 1504 gswip_mii_mask_cfg(priv, 1505 GSWIP_MII_CFG_MODE_MASK | GSWIP_MII_CFG_RMII_CLK | 1506 GSWIP_MII_CFG_RGMII_IBS | GSWIP_MII_CFG_LDCLKDIS, 1507 miicfg, port); 1508 1509 switch (state->interface) { 1510 case PHY_INTERFACE_MODE_RGMII_ID: 1511 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK | 1512 GSWIP_MII_PCDU_RXDLY_MASK, 0, port); 1513 break; 1514 case PHY_INTERFACE_MODE_RGMII_RXID: 1515 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_RXDLY_MASK, 0, port); 1516 break; 1517 case PHY_INTERFACE_MODE_RGMII_TXID: 1518 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK, 0, port); 1519 break; 1520 default: 1521 break; 1522 } 1523 } 1524 1525 static void gswip_phylink_mac_link_down(struct phylink_config *config, 1526 unsigned int mode, 1527 phy_interface_t interface) 1528 { 1529 struct dsa_port *dp = dsa_phylink_to_port(config); 1530 struct gswip_priv *priv = dp->ds->priv; 1531 int port = dp->index; 1532 1533 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, port); 1534 1535 if (!dsa_port_is_cpu(dp)) 1536 gswip_port_set_link(priv, port, false); 1537 } 1538 1539 static void gswip_phylink_mac_link_up(struct phylink_config *config, 1540 struct phy_device *phydev, 1541 unsigned int mode, 1542 phy_interface_t interface, 1543 int speed, int duplex, 1544 bool tx_pause, bool rx_pause) 1545 { 1546 struct dsa_port *dp = dsa_phylink_to_port(config); 1547 struct gswip_priv *priv = dp->ds->priv; 1548 int port = dp->index; 1549 1550 if (!dsa_port_is_cpu(dp)) { 1551 gswip_port_set_link(priv, port, true); 1552 gswip_port_set_speed(priv, port, speed, interface); 1553 gswip_port_set_duplex(priv, port, duplex); 1554 gswip_port_set_pause(priv, port, tx_pause, rx_pause); 1555 } 1556 1557 gswip_mii_mask_cfg(priv, 0, GSWIP_MII_CFG_EN, port); 1558 } 1559 1560 static void gswip_get_strings(struct dsa_switch *ds, int port, u32 stringset, 1561 uint8_t *data) 1562 { 1563 int i; 1564 1565 if (stringset != ETH_SS_STATS) 1566 return; 1567 1568 for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++) 1569 ethtool_puts(&data, gswip_rmon_cnt[i].name); 1570 } 1571 1572 static u32 gswip_bcm_ram_entry_read(struct gswip_priv *priv, u32 table, 1573 u32 index) 1574 { 1575 u32 result; 1576 int err; 1577 1578 gswip_switch_w(priv, index, GSWIP_BM_RAM_ADDR); 1579 gswip_switch_mask(priv, GSWIP_BM_RAM_CTRL_ADDR_MASK | 1580 GSWIP_BM_RAM_CTRL_OPMOD, 1581 table | GSWIP_BM_RAM_CTRL_BAS, 1582 GSWIP_BM_RAM_CTRL); 1583 1584 err = gswip_switch_r_timeout(priv, GSWIP_BM_RAM_CTRL, 1585 GSWIP_BM_RAM_CTRL_BAS); 1586 if (err) { 1587 dev_err(priv->dev, "timeout while reading table: %u, index: %u\n", 1588 table, index); 1589 return 0; 1590 } 1591 1592 result = gswip_switch_r(priv, GSWIP_BM_RAM_VAL(0)); 1593 result |= gswip_switch_r(priv, GSWIP_BM_RAM_VAL(1)) << 16; 1594 1595 return result; 1596 } 1597 1598 static void gswip_get_ethtool_stats(struct dsa_switch *ds, int port, 1599 uint64_t *data) 1600 { 1601 struct gswip_priv *priv = ds->priv; 1602 const struct gswip_rmon_cnt_desc *rmon_cnt; 1603 int i; 1604 u64 high; 1605 1606 for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++) { 1607 rmon_cnt = &gswip_rmon_cnt[i]; 1608 1609 data[i] = gswip_bcm_ram_entry_read(priv, port, 1610 rmon_cnt->offset); 1611 if (rmon_cnt->size == 2) { 1612 high = gswip_bcm_ram_entry_read(priv, port, 1613 rmon_cnt->offset + 1); 1614 data[i] |= high << 32; 1615 } 1616 } 1617 } 1618 1619 static int gswip_get_sset_count(struct dsa_switch *ds, int port, int sset) 1620 { 1621 if (sset != ETH_SS_STATS) 1622 return 0; 1623 1624 return ARRAY_SIZE(gswip_rmon_cnt); 1625 } 1626 1627 static struct phylink_pcs *gswip_phylink_mac_select_pcs(struct phylink_config *config, 1628 phy_interface_t interface) 1629 { 1630 struct dsa_port *dp = dsa_phylink_to_port(config); 1631 struct gswip_priv *priv = dp->ds->priv; 1632 1633 if (priv->hw_info->mac_select_pcs) 1634 return priv->hw_info->mac_select_pcs(config, interface); 1635 1636 return NULL; 1637 } 1638 1639 static const struct phylink_mac_ops gswip_phylink_mac_ops = { 1640 .mac_config = gswip_phylink_mac_config, 1641 .mac_link_down = gswip_phylink_mac_link_down, 1642 .mac_link_up = gswip_phylink_mac_link_up, 1643 .mac_select_pcs = gswip_phylink_mac_select_pcs, 1644 }; 1645 1646 static const struct dsa_switch_ops gswip_switch_ops = { 1647 .get_tag_protocol = gswip_get_tag_protocol, 1648 .setup = gswip_setup, 1649 .port_setup = gswip_port_setup, 1650 .port_enable = gswip_port_enable, 1651 .port_disable = gswip_port_disable, 1652 .port_bridge_join = gswip_port_bridge_join, 1653 .port_bridge_leave = gswip_port_bridge_leave, 1654 .port_fast_age = gswip_port_fast_age, 1655 .port_vlan_filtering = gswip_port_vlan_filtering, 1656 .port_vlan_add = gswip_port_vlan_add, 1657 .port_vlan_del = gswip_port_vlan_del, 1658 .port_stp_state_set = gswip_port_stp_state_set, 1659 .port_fdb_add = gswip_port_fdb_add, 1660 .port_fdb_del = gswip_port_fdb_del, 1661 .port_fdb_dump = gswip_port_fdb_dump, 1662 .port_change_mtu = gswip_port_change_mtu, 1663 .port_max_mtu = gswip_port_max_mtu, 1664 .phylink_get_caps = gswip_phylink_get_caps, 1665 .get_strings = gswip_get_strings, 1666 .get_ethtool_stats = gswip_get_ethtool_stats, 1667 .get_sset_count = gswip_get_sset_count, 1668 }; 1669 1670 static const struct xway_gphy_match_data xrx200a1x_gphy_data = { 1671 .fe_firmware_name = "lantiq/xrx200_phy22f_a14.bin", 1672 .ge_firmware_name = "lantiq/xrx200_phy11g_a14.bin", 1673 }; 1674 1675 static const struct xway_gphy_match_data xrx200a2x_gphy_data = { 1676 .fe_firmware_name = "lantiq/xrx200_phy22f_a22.bin", 1677 .ge_firmware_name = "lantiq/xrx200_phy11g_a22.bin", 1678 }; 1679 1680 static const struct xway_gphy_match_data xrx300_gphy_data = { 1681 .fe_firmware_name = "lantiq/xrx300_phy22f_a21.bin", 1682 .ge_firmware_name = "lantiq/xrx300_phy11g_a21.bin", 1683 }; 1684 1685 static const struct of_device_id xway_gphy_match[] __maybe_unused = { 1686 { .compatible = "lantiq,xrx200-gphy-fw", .data = NULL }, 1687 { .compatible = "lantiq,xrx200a1x-gphy-fw", .data = &xrx200a1x_gphy_data }, 1688 { .compatible = "lantiq,xrx200a2x-gphy-fw", .data = &xrx200a2x_gphy_data }, 1689 { .compatible = "lantiq,xrx300-gphy-fw", .data = &xrx300_gphy_data }, 1690 { .compatible = "lantiq,xrx330-gphy-fw", .data = &xrx300_gphy_data }, 1691 {}, 1692 }; 1693 1694 static int gswip_gphy_fw_load(struct gswip_priv *priv, struct gswip_gphy_fw *gphy_fw) 1695 { 1696 struct device *dev = priv->dev; 1697 const struct firmware *fw; 1698 void *fw_addr; 1699 dma_addr_t dma_addr; 1700 dma_addr_t dev_addr; 1701 size_t size; 1702 int ret; 1703 1704 ret = clk_prepare_enable(gphy_fw->clk_gate); 1705 if (ret) 1706 return ret; 1707 1708 reset_control_assert(gphy_fw->reset); 1709 1710 /* The vendor BSP uses a 200ms delay after asserting the reset line. 1711 * Without this some users are observing that the PHY is not coming up 1712 * on the MDIO bus. 1713 */ 1714 msleep(200); 1715 1716 ret = request_firmware(&fw, gphy_fw->fw_name, dev); 1717 if (ret) 1718 return dev_err_probe(dev, ret, "failed to load firmware: %s\n", 1719 gphy_fw->fw_name); 1720 1721 /* GPHY cores need the firmware code in a persistent and contiguous 1722 * memory area with a 16 kB boundary aligned start address. 1723 */ 1724 size = fw->size + XRX200_GPHY_FW_ALIGN; 1725 1726 fw_addr = dmam_alloc_coherent(dev, size, &dma_addr, GFP_KERNEL); 1727 if (fw_addr) { 1728 fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN); 1729 dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN); 1730 memcpy(fw_addr, fw->data, fw->size); 1731 } else { 1732 release_firmware(fw); 1733 return -ENOMEM; 1734 } 1735 1736 release_firmware(fw); 1737 1738 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, dev_addr); 1739 if (ret) 1740 return ret; 1741 1742 reset_control_deassert(gphy_fw->reset); 1743 1744 return ret; 1745 } 1746 1747 static int gswip_gphy_fw_probe(struct gswip_priv *priv, 1748 struct gswip_gphy_fw *gphy_fw, 1749 struct device_node *gphy_fw_np, int i) 1750 { 1751 struct device *dev = priv->dev; 1752 u32 gphy_mode; 1753 int ret; 1754 char gphyname[10]; 1755 1756 snprintf(gphyname, sizeof(gphyname), "gphy%d", i); 1757 1758 gphy_fw->clk_gate = devm_clk_get(dev, gphyname); 1759 if (IS_ERR(gphy_fw->clk_gate)) { 1760 return dev_err_probe(dev, PTR_ERR(gphy_fw->clk_gate), 1761 "Failed to lookup gate clock\n"); 1762 } 1763 1764 ret = of_property_read_u32(gphy_fw_np, "reg", &gphy_fw->fw_addr_offset); 1765 if (ret) 1766 return ret; 1767 1768 ret = of_property_read_u32(gphy_fw_np, "lantiq,gphy-mode", &gphy_mode); 1769 /* Default to GE mode */ 1770 if (ret) 1771 gphy_mode = GPHY_MODE_GE; 1772 1773 switch (gphy_mode) { 1774 case GPHY_MODE_FE: 1775 gphy_fw->fw_name = priv->gphy_fw_name_cfg->fe_firmware_name; 1776 break; 1777 case GPHY_MODE_GE: 1778 gphy_fw->fw_name = priv->gphy_fw_name_cfg->ge_firmware_name; 1779 break; 1780 default: 1781 return dev_err_probe(dev, -EINVAL, "Unknown GPHY mode %d\n", 1782 gphy_mode); 1783 } 1784 1785 gphy_fw->reset = of_reset_control_array_get_exclusive(gphy_fw_np); 1786 if (IS_ERR(gphy_fw->reset)) 1787 return dev_err_probe(dev, PTR_ERR(gphy_fw->reset), 1788 "Failed to lookup gphy reset\n"); 1789 1790 return gswip_gphy_fw_load(priv, gphy_fw); 1791 } 1792 1793 static void gswip_gphy_fw_remove(struct gswip_priv *priv, 1794 struct gswip_gphy_fw *gphy_fw) 1795 { 1796 int ret; 1797 1798 /* check if the device was fully probed */ 1799 if (!gphy_fw->fw_name) 1800 return; 1801 1802 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, 0); 1803 if (ret) 1804 dev_err(priv->dev, "can not reset GPHY FW pointer\n"); 1805 1806 clk_disable_unprepare(gphy_fw->clk_gate); 1807 1808 reset_control_put(gphy_fw->reset); 1809 } 1810 1811 static int gswip_gphy_fw_list(struct gswip_priv *priv, 1812 struct device_node *gphy_fw_list_np, u32 version) 1813 { 1814 struct device *dev = priv->dev; 1815 struct device_node *gphy_fw_np; 1816 const struct of_device_id *match; 1817 int err; 1818 int i = 0; 1819 1820 /* The VRX200 rev 1.1 uses the GSWIP 2.0 and needs the older 1821 * GPHY firmware. The VRX200 rev 1.2 uses the GSWIP 2.1 and also 1822 * needs a different GPHY firmware. 1823 */ 1824 if (of_device_is_compatible(gphy_fw_list_np, "lantiq,xrx200-gphy-fw")) { 1825 switch (version) { 1826 case GSWIP_VERSION_2_0: 1827 priv->gphy_fw_name_cfg = &xrx200a1x_gphy_data; 1828 break; 1829 case GSWIP_VERSION_2_1: 1830 priv->gphy_fw_name_cfg = &xrx200a2x_gphy_data; 1831 break; 1832 default: 1833 return dev_err_probe(dev, -ENOENT, 1834 "unknown GSWIP version: 0x%x\n", 1835 version); 1836 } 1837 } 1838 1839 match = of_match_node(xway_gphy_match, gphy_fw_list_np); 1840 if (match && match->data) 1841 priv->gphy_fw_name_cfg = match->data; 1842 1843 if (!priv->gphy_fw_name_cfg) 1844 return dev_err_probe(dev, -ENOENT, 1845 "GPHY compatible type not supported\n"); 1846 1847 priv->num_gphy_fw = of_get_available_child_count(gphy_fw_list_np); 1848 if (!priv->num_gphy_fw) 1849 return -ENOENT; 1850 1851 priv->rcu_regmap = syscon_regmap_lookup_by_phandle(gphy_fw_list_np, 1852 "lantiq,rcu"); 1853 if (IS_ERR(priv->rcu_regmap)) 1854 return PTR_ERR(priv->rcu_regmap); 1855 1856 priv->gphy_fw = devm_kmalloc_array(dev, priv->num_gphy_fw, 1857 sizeof(*priv->gphy_fw), 1858 GFP_KERNEL | __GFP_ZERO); 1859 if (!priv->gphy_fw) 1860 return -ENOMEM; 1861 1862 for_each_available_child_of_node(gphy_fw_list_np, gphy_fw_np) { 1863 err = gswip_gphy_fw_probe(priv, &priv->gphy_fw[i], 1864 gphy_fw_np, i); 1865 if (err) { 1866 of_node_put(gphy_fw_np); 1867 goto remove_gphy; 1868 } 1869 i++; 1870 } 1871 1872 /* The standalone PHY11G requires 300ms to be fully 1873 * initialized and ready for any MDIO communication after being 1874 * taken out of reset. For the SoC-internal GPHY variant there 1875 * is no (known) documentation for the minimum time after a 1876 * reset. Use the same value as for the standalone variant as 1877 * some users have reported internal PHYs not being detected 1878 * without any delay. 1879 */ 1880 msleep(300); 1881 1882 return 0; 1883 1884 remove_gphy: 1885 for (i = 0; i < priv->num_gphy_fw; i++) 1886 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); 1887 return err; 1888 } 1889 1890 static int gswip_validate_cpu_port(struct dsa_switch *ds) 1891 { 1892 struct gswip_priv *priv = ds->priv; 1893 struct dsa_port *cpu_dp; 1894 int cpu_port = -1; 1895 1896 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 1897 if (cpu_port != -1) 1898 return dev_err_probe(ds->dev, -EINVAL, 1899 "only a single CPU port is supported\n"); 1900 1901 cpu_port = cpu_dp->index; 1902 } 1903 1904 if (cpu_port == -1) 1905 return dev_err_probe(ds->dev, -EINVAL, "no CPU port defined\n"); 1906 1907 if (BIT(cpu_port) & ~priv->hw_info->allowed_cpu_ports) 1908 return dev_err_probe(ds->dev, -EINVAL, 1909 "unsupported CPU port defined\n"); 1910 1911 return 0; 1912 } 1913 1914 static int gswip_probe(struct platform_device *pdev) 1915 { 1916 struct device_node *np, *gphy_fw_np; 1917 struct device *dev = &pdev->dev; 1918 struct gswip_priv *priv; 1919 int err; 1920 int i; 1921 u32 version; 1922 1923 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1924 if (!priv) 1925 return -ENOMEM; 1926 1927 priv->gswip = devm_platform_ioremap_resource(pdev, 0); 1928 if (IS_ERR(priv->gswip)) 1929 return PTR_ERR(priv->gswip); 1930 1931 priv->mdio = devm_platform_ioremap_resource(pdev, 1); 1932 if (IS_ERR(priv->mdio)) 1933 return PTR_ERR(priv->mdio); 1934 1935 priv->mii = devm_platform_ioremap_resource(pdev, 2); 1936 if (IS_ERR(priv->mii)) 1937 return PTR_ERR(priv->mii); 1938 1939 priv->hw_info = of_device_get_match_data(dev); 1940 if (!priv->hw_info) 1941 return -EINVAL; 1942 1943 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); 1944 if (!priv->ds) 1945 return -ENOMEM; 1946 1947 priv->ds->dev = dev; 1948 priv->ds->num_ports = priv->hw_info->max_ports; 1949 priv->ds->priv = priv; 1950 priv->ds->ops = &gswip_switch_ops; 1951 priv->ds->phylink_mac_ops = &gswip_phylink_mac_ops; 1952 priv->dev = dev; 1953 mutex_init(&priv->pce_table_lock); 1954 version = gswip_switch_r(priv, GSWIP_VERSION); 1955 1956 /* The hardware has the 'major/minor' version bytes in the wrong order 1957 * preventing numerical comparisons. Construct a 16-bit unsigned integer 1958 * having the REV field as most significant byte and the MOD field as 1959 * least significant byte. This is effectively swapping the two bytes of 1960 * the version variable, but other than using swab16 it doesn't affect 1961 * the source variable. 1962 */ 1963 priv->version = GSWIP_VERSION_REV(version) << 8 | 1964 GSWIP_VERSION_MOD(version); 1965 1966 np = dev->of_node; 1967 switch (version) { 1968 case GSWIP_VERSION_2_0: 1969 case GSWIP_VERSION_2_1: 1970 if (!of_device_is_compatible(np, "lantiq,xrx200-gswip")) 1971 return -EINVAL; 1972 break; 1973 case GSWIP_VERSION_2_2: 1974 case GSWIP_VERSION_2_2_ETC: 1975 if (!of_device_is_compatible(np, "lantiq,xrx300-gswip") && 1976 !of_device_is_compatible(np, "lantiq,xrx330-gswip")) 1977 return -EINVAL; 1978 break; 1979 default: 1980 return dev_err_probe(dev, -ENOENT, 1981 "unknown GSWIP version: 0x%x\n", version); 1982 } 1983 1984 /* bring up the mdio bus */ 1985 gphy_fw_np = of_get_compatible_child(dev->of_node, "lantiq,gphy-fw"); 1986 if (gphy_fw_np) { 1987 err = gswip_gphy_fw_list(priv, gphy_fw_np, version); 1988 of_node_put(gphy_fw_np); 1989 if (err) 1990 return dev_err_probe(dev, err, 1991 "gphy fw probe failed\n"); 1992 } 1993 1994 err = dsa_register_switch(priv->ds); 1995 if (err) { 1996 dev_err_probe(dev, err, "dsa switch registration failed\n"); 1997 goto gphy_fw_remove; 1998 } 1999 2000 err = gswip_validate_cpu_port(priv->ds); 2001 if (err) 2002 goto disable_switch; 2003 2004 platform_set_drvdata(pdev, priv); 2005 2006 dev_info(dev, "probed GSWIP version %lx mod %lx\n", 2007 GSWIP_VERSION_REV(version), GSWIP_VERSION_MOD(version)); 2008 return 0; 2009 2010 disable_switch: 2011 gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB); 2012 dsa_unregister_switch(priv->ds); 2013 gphy_fw_remove: 2014 for (i = 0; i < priv->num_gphy_fw; i++) 2015 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); 2016 return err; 2017 } 2018 2019 static void gswip_remove(struct platform_device *pdev) 2020 { 2021 struct gswip_priv *priv = platform_get_drvdata(pdev); 2022 int i; 2023 2024 if (!priv) 2025 return; 2026 2027 /* disable the switch */ 2028 gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB); 2029 2030 dsa_unregister_switch(priv->ds); 2031 2032 for (i = 0; i < priv->num_gphy_fw; i++) 2033 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); 2034 } 2035 2036 static void gswip_shutdown(struct platform_device *pdev) 2037 { 2038 struct gswip_priv *priv = platform_get_drvdata(pdev); 2039 2040 if (!priv) 2041 return; 2042 2043 dsa_switch_shutdown(priv->ds); 2044 2045 platform_set_drvdata(pdev, NULL); 2046 } 2047 2048 static const struct gswip_hw_info gswip_xrx200 = { 2049 .max_ports = 7, 2050 .allowed_cpu_ports = BIT(6), 2051 .mii_ports = BIT(0) | BIT(1) | BIT(5), 2052 .mii_port_reg_offset = 0, 2053 .phylink_get_caps = gswip_xrx200_phylink_get_caps, 2054 .pce_microcode = &gswip_pce_microcode, 2055 .pce_microcode_size = ARRAY_SIZE(gswip_pce_microcode), 2056 .tag_protocol = DSA_TAG_PROTO_GSWIP, 2057 }; 2058 2059 static const struct gswip_hw_info gswip_xrx300 = { 2060 .max_ports = 7, 2061 .allowed_cpu_ports = BIT(6), 2062 .mii_ports = BIT(0) | BIT(5), 2063 .mii_port_reg_offset = 0, 2064 .phylink_get_caps = gswip_xrx300_phylink_get_caps, 2065 .pce_microcode = &gswip_pce_microcode, 2066 .pce_microcode_size = ARRAY_SIZE(gswip_pce_microcode), 2067 .tag_protocol = DSA_TAG_PROTO_GSWIP, 2068 }; 2069 2070 static const struct of_device_id gswip_of_match[] = { 2071 { .compatible = "lantiq,xrx200-gswip", .data = &gswip_xrx200 }, 2072 { .compatible = "lantiq,xrx300-gswip", .data = &gswip_xrx300 }, 2073 { .compatible = "lantiq,xrx330-gswip", .data = &gswip_xrx300 }, 2074 {}, 2075 }; 2076 MODULE_DEVICE_TABLE(of, gswip_of_match); 2077 2078 static struct platform_driver gswip_driver = { 2079 .probe = gswip_probe, 2080 .remove = gswip_remove, 2081 .shutdown = gswip_shutdown, 2082 .driver = { 2083 .name = "gswip", 2084 .of_match_table = gswip_of_match, 2085 }, 2086 }; 2087 2088 module_platform_driver(gswip_driver); 2089 2090 MODULE_FIRMWARE("lantiq/xrx300_phy11g_a21.bin"); 2091 MODULE_FIRMWARE("lantiq/xrx300_phy22f_a21.bin"); 2092 MODULE_FIRMWARE("lantiq/xrx200_phy11g_a14.bin"); 2093 MODULE_FIRMWARE("lantiq/xrx200_phy11g_a22.bin"); 2094 MODULE_FIRMWARE("lantiq/xrx200_phy22f_a14.bin"); 2095 MODULE_FIRMWARE("lantiq/xrx200_phy22f_a22.bin"); 2096 MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>"); 2097 MODULE_DESCRIPTION("Lantiq / Intel GSWIP driver"); 2098 MODULE_LICENSE("GPL v2"); 2099