1 /* 2 * Copyright (C) 2017 Pengutronix, Juergen Borleis <kernel@pengutronix.de> 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/regmap.h> 18 #include <linux/mutex.h> 19 #include <linux/mii.h> 20 #include <linux/phy.h> 21 #include <linux/if_bridge.h> 22 #include <linux/etherdevice.h> 23 24 #include "lan9303.h" 25 26 #define LAN9303_NUM_PORTS 3 27 28 /* 13.2 System Control and Status Registers 29 * Multiply register number by 4 to get address offset. 30 */ 31 #define LAN9303_CHIP_REV 0x14 32 # define LAN9303_CHIP_ID 0x9303 33 #define LAN9303_IRQ_CFG 0x15 34 # define LAN9303_IRQ_CFG_IRQ_ENABLE BIT(8) 35 # define LAN9303_IRQ_CFG_IRQ_POL BIT(4) 36 # define LAN9303_IRQ_CFG_IRQ_TYPE BIT(0) 37 #define LAN9303_INT_STS 0x16 38 # define LAN9303_INT_STS_PHY_INT2 BIT(27) 39 # define LAN9303_INT_STS_PHY_INT1 BIT(26) 40 #define LAN9303_INT_EN 0x17 41 # define LAN9303_INT_EN_PHY_INT2_EN BIT(27) 42 # define LAN9303_INT_EN_PHY_INT1_EN BIT(26) 43 #define LAN9303_HW_CFG 0x1D 44 # define LAN9303_HW_CFG_READY BIT(27) 45 # define LAN9303_HW_CFG_AMDX_EN_PORT2 BIT(26) 46 # define LAN9303_HW_CFG_AMDX_EN_PORT1 BIT(25) 47 #define LAN9303_PMI_DATA 0x29 48 #define LAN9303_PMI_ACCESS 0x2A 49 # define LAN9303_PMI_ACCESS_PHY_ADDR(x) (((x) & 0x1f) << 11) 50 # define LAN9303_PMI_ACCESS_MIIRINDA(x) (((x) & 0x1f) << 6) 51 # define LAN9303_PMI_ACCESS_MII_BUSY BIT(0) 52 # define LAN9303_PMI_ACCESS_MII_WRITE BIT(1) 53 #define LAN9303_MANUAL_FC_1 0x68 54 #define LAN9303_MANUAL_FC_2 0x69 55 #define LAN9303_MANUAL_FC_0 0x6a 56 #define LAN9303_SWITCH_CSR_DATA 0x6b 57 #define LAN9303_SWITCH_CSR_CMD 0x6c 58 #define LAN9303_SWITCH_CSR_CMD_BUSY BIT(31) 59 #define LAN9303_SWITCH_CSR_CMD_RW BIT(30) 60 #define LAN9303_SWITCH_CSR_CMD_LANES (BIT(19) | BIT(18) | BIT(17) | BIT(16)) 61 #define LAN9303_VIRT_PHY_BASE 0x70 62 #define LAN9303_VIRT_SPECIAL_CTRL 0x77 63 #define LAN9303_VIRT_SPECIAL_TURBO BIT(10) /*Turbo MII Enable*/ 64 65 /*13.4 Switch Fabric Control and Status Registers 66 * Accessed indirectly via SWITCH_CSR_CMD, SWITCH_CSR_DATA. 67 */ 68 #define LAN9303_SW_DEV_ID 0x0000 69 #define LAN9303_SW_RESET 0x0001 70 #define LAN9303_SW_RESET_RESET BIT(0) 71 #define LAN9303_SW_IMR 0x0004 72 #define LAN9303_SW_IPR 0x0005 73 #define LAN9303_MAC_VER_ID_0 0x0400 74 #define LAN9303_MAC_RX_CFG_0 0x0401 75 # define LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES BIT(1) 76 # define LAN9303_MAC_RX_CFG_X_RX_ENABLE BIT(0) 77 #define LAN9303_MAC_RX_UNDSZE_CNT_0 0x0410 78 #define LAN9303_MAC_RX_64_CNT_0 0x0411 79 #define LAN9303_MAC_RX_127_CNT_0 0x0412 80 #define LAN9303_MAC_RX_255_CNT_0 0x413 81 #define LAN9303_MAC_RX_511_CNT_0 0x0414 82 #define LAN9303_MAC_RX_1023_CNT_0 0x0415 83 #define LAN9303_MAC_RX_MAX_CNT_0 0x0416 84 #define LAN9303_MAC_RX_OVRSZE_CNT_0 0x0417 85 #define LAN9303_MAC_RX_PKTOK_CNT_0 0x0418 86 #define LAN9303_MAC_RX_CRCERR_CNT_0 0x0419 87 #define LAN9303_MAC_RX_MULCST_CNT_0 0x041a 88 #define LAN9303_MAC_RX_BRDCST_CNT_0 0x041b 89 #define LAN9303_MAC_RX_PAUSE_CNT_0 0x041c 90 #define LAN9303_MAC_RX_FRAG_CNT_0 0x041d 91 #define LAN9303_MAC_RX_JABB_CNT_0 0x041e 92 #define LAN9303_MAC_RX_ALIGN_CNT_0 0x041f 93 #define LAN9303_MAC_RX_PKTLEN_CNT_0 0x0420 94 #define LAN9303_MAC_RX_GOODPKTLEN_CNT_0 0x0421 95 #define LAN9303_MAC_RX_SYMBL_CNT_0 0x0422 96 #define LAN9303_MAC_RX_CTLFRM_CNT_0 0x0423 97 98 #define LAN9303_MAC_TX_CFG_0 0x0440 99 # define LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT (21 << 2) 100 # define LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE BIT(1) 101 # define LAN9303_MAC_TX_CFG_X_TX_ENABLE BIT(0) 102 #define LAN9303_MAC_TX_DEFER_CNT_0 0x0451 103 #define LAN9303_MAC_TX_PAUSE_CNT_0 0x0452 104 #define LAN9303_MAC_TX_PKTOK_CNT_0 0x0453 105 #define LAN9303_MAC_TX_64_CNT_0 0x0454 106 #define LAN9303_MAC_TX_127_CNT_0 0x0455 107 #define LAN9303_MAC_TX_255_CNT_0 0x0456 108 #define LAN9303_MAC_TX_511_CNT_0 0x0457 109 #define LAN9303_MAC_TX_1023_CNT_0 0x0458 110 #define LAN9303_MAC_TX_MAX_CNT_0 0x0459 111 #define LAN9303_MAC_TX_UNDSZE_CNT_0 0x045a 112 #define LAN9303_MAC_TX_PKTLEN_CNT_0 0x045c 113 #define LAN9303_MAC_TX_BRDCST_CNT_0 0x045d 114 #define LAN9303_MAC_TX_MULCST_CNT_0 0x045e 115 #define LAN9303_MAC_TX_LATECOL_0 0x045f 116 #define LAN9303_MAC_TX_EXCOL_CNT_0 0x0460 117 #define LAN9303_MAC_TX_SNGLECOL_CNT_0 0x0461 118 #define LAN9303_MAC_TX_MULTICOL_CNT_0 0x0462 119 #define LAN9303_MAC_TX_TOTALCOL_CNT_0 0x0463 120 121 #define LAN9303_MAC_VER_ID_1 0x0800 122 #define LAN9303_MAC_RX_CFG_1 0x0801 123 #define LAN9303_MAC_TX_CFG_1 0x0840 124 #define LAN9303_MAC_VER_ID_2 0x0c00 125 #define LAN9303_MAC_RX_CFG_2 0x0c01 126 #define LAN9303_MAC_TX_CFG_2 0x0c40 127 #define LAN9303_SWE_ALR_CMD 0x1800 128 # define LAN9303_ALR_CMD_MAKE_ENTRY BIT(2) 129 # define LAN9303_ALR_CMD_GET_FIRST BIT(1) 130 # define LAN9303_ALR_CMD_GET_NEXT BIT(0) 131 #define LAN9303_SWE_ALR_WR_DAT_0 0x1801 132 #define LAN9303_SWE_ALR_WR_DAT_1 0x1802 133 # define LAN9303_ALR_DAT1_VALID BIT(26) 134 # define LAN9303_ALR_DAT1_END_OF_TABL BIT(25) 135 # define LAN9303_ALR_DAT1_AGE_OVERRID BIT(25) 136 # define LAN9303_ALR_DAT1_STATIC BIT(24) 137 # define LAN9303_ALR_DAT1_PORT_BITOFFS 16 138 # define LAN9303_ALR_DAT1_PORT_MASK (7 << LAN9303_ALR_DAT1_PORT_BITOFFS) 139 #define LAN9303_SWE_ALR_RD_DAT_0 0x1805 140 #define LAN9303_SWE_ALR_RD_DAT_1 0x1806 141 #define LAN9303_SWE_ALR_CMD_STS 0x1808 142 # define ALR_STS_MAKE_PEND BIT(0) 143 #define LAN9303_SWE_VLAN_CMD 0x180b 144 # define LAN9303_SWE_VLAN_CMD_RNW BIT(5) 145 # define LAN9303_SWE_VLAN_CMD_PVIDNVLAN BIT(4) 146 #define LAN9303_SWE_VLAN_WR_DATA 0x180c 147 #define LAN9303_SWE_VLAN_RD_DATA 0x180e 148 # define LAN9303_SWE_VLAN_MEMBER_PORT2 BIT(17) 149 # define LAN9303_SWE_VLAN_UNTAG_PORT2 BIT(16) 150 # define LAN9303_SWE_VLAN_MEMBER_PORT1 BIT(15) 151 # define LAN9303_SWE_VLAN_UNTAG_PORT1 BIT(14) 152 # define LAN9303_SWE_VLAN_MEMBER_PORT0 BIT(13) 153 # define LAN9303_SWE_VLAN_UNTAG_PORT0 BIT(12) 154 #define LAN9303_SWE_VLAN_CMD_STS 0x1810 155 #define LAN9303_SWE_GLB_INGRESS_CFG 0x1840 156 # define LAN9303_SWE_GLB_INGR_IGMP_TRAP BIT(7) 157 # define LAN9303_SWE_GLB_INGR_IGMP_PORT(p) BIT(10 + p) 158 #define LAN9303_SWE_PORT_STATE 0x1843 159 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT2 (0) 160 # define LAN9303_SWE_PORT_STATE_LEARNING_PORT2 BIT(5) 161 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT2 BIT(4) 162 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT1 (0) 163 # define LAN9303_SWE_PORT_STATE_LEARNING_PORT1 BIT(3) 164 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT1 BIT(2) 165 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT0 (0) 166 # define LAN9303_SWE_PORT_STATE_LEARNING_PORT0 BIT(1) 167 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT0 BIT(0) 168 # define LAN9303_SWE_PORT_STATE_DISABLED_PORT0 (3) 169 #define LAN9303_SWE_PORT_MIRROR 0x1846 170 # define LAN9303_SWE_PORT_MIRROR_SNIFF_ALL BIT(8) 171 # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT2 BIT(7) 172 # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT1 BIT(6) 173 # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT0 BIT(5) 174 # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT2 BIT(4) 175 # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT1 BIT(3) 176 # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT0 BIT(2) 177 # define LAN9303_SWE_PORT_MIRROR_ENABLE_RX_MIRRORING BIT(1) 178 # define LAN9303_SWE_PORT_MIRROR_ENABLE_TX_MIRRORING BIT(0) 179 # define LAN9303_SWE_PORT_MIRROR_DISABLED 0 180 #define LAN9303_SWE_INGRESS_PORT_TYPE 0x1847 181 #define LAN9303_SWE_INGRESS_PORT_TYPE_VLAN 3 182 #define LAN9303_BM_CFG 0x1c00 183 #define LAN9303_BM_EGRSS_PORT_TYPE 0x1c0c 184 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT2 (BIT(17) | BIT(16)) 185 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT1 (BIT(9) | BIT(8)) 186 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0 (BIT(1) | BIT(0)) 187 188 #define LAN9303_SWITCH_PORT_REG(port, reg0) (0x400 * (port) + (reg0)) 189 190 /* the built-in PHYs are of type LAN911X */ 191 #define MII_LAN911X_SPECIAL_MODES 0x12 192 #define MII_LAN911X_SPECIAL_CONTROL_STATUS 0x1f 193 194 static const struct regmap_range lan9303_valid_regs[] = { 195 regmap_reg_range(0x14, 0x17), /* misc, interrupt */ 196 regmap_reg_range(0x19, 0x19), /* endian test */ 197 regmap_reg_range(0x1d, 0x1d), /* hardware config */ 198 regmap_reg_range(0x23, 0x24), /* general purpose timer */ 199 regmap_reg_range(0x27, 0x27), /* counter */ 200 regmap_reg_range(0x29, 0x2a), /* PMI index regs */ 201 regmap_reg_range(0x68, 0x6a), /* flow control */ 202 regmap_reg_range(0x6b, 0x6c), /* switch fabric indirect regs */ 203 regmap_reg_range(0x6d, 0x6f), /* misc */ 204 regmap_reg_range(0x70, 0x77), /* virtual phy */ 205 regmap_reg_range(0x78, 0x7a), /* GPIO */ 206 regmap_reg_range(0x7c, 0x7e), /* MAC & reset */ 207 regmap_reg_range(0x80, 0xb7), /* switch fabric direct regs (wr only) */ 208 }; 209 210 static const struct regmap_range lan9303_reserved_ranges[] = { 211 regmap_reg_range(0x00, 0x13), 212 regmap_reg_range(0x18, 0x18), 213 regmap_reg_range(0x1a, 0x1c), 214 regmap_reg_range(0x1e, 0x22), 215 regmap_reg_range(0x25, 0x26), 216 regmap_reg_range(0x28, 0x28), 217 regmap_reg_range(0x2b, 0x67), 218 regmap_reg_range(0x7b, 0x7b), 219 regmap_reg_range(0x7f, 0x7f), 220 regmap_reg_range(0xb8, 0xff), 221 }; 222 223 const struct regmap_access_table lan9303_register_set = { 224 .yes_ranges = lan9303_valid_regs, 225 .n_yes_ranges = ARRAY_SIZE(lan9303_valid_regs), 226 .no_ranges = lan9303_reserved_ranges, 227 .n_no_ranges = ARRAY_SIZE(lan9303_reserved_ranges), 228 }; 229 EXPORT_SYMBOL(lan9303_register_set); 230 231 static int lan9303_read(struct regmap *regmap, unsigned int offset, u32 *reg) 232 { 233 int ret, i; 234 235 /* we can lose arbitration for the I2C case, because the device 236 * tries to detect and read an external EEPROM after reset and acts as 237 * a master on the shared I2C bus itself. This conflicts with our 238 * attempts to access the device as a slave at the same moment. 239 */ 240 for (i = 0; i < 5; i++) { 241 ret = regmap_read(regmap, offset, reg); 242 if (!ret) 243 return 0; 244 if (ret != -EAGAIN) 245 break; 246 msleep(500); 247 } 248 249 return -EIO; 250 } 251 252 static int lan9303_read_wait(struct lan9303 *chip, int offset, u32 mask) 253 { 254 int i; 255 256 for (i = 0; i < 25; i++) { 257 u32 reg; 258 int ret; 259 260 ret = lan9303_read(chip->regmap, offset, ®); 261 if (ret) { 262 dev_err(chip->dev, "%s failed to read offset %d: %d\n", 263 __func__, offset, ret); 264 return ret; 265 } 266 if (!(reg & mask)) 267 return 0; 268 usleep_range(1000, 2000); 269 } 270 271 return -ETIMEDOUT; 272 } 273 274 static int lan9303_virt_phy_reg_read(struct lan9303 *chip, int regnum) 275 { 276 int ret; 277 u32 val; 278 279 if (regnum > MII_EXPANSION) 280 return -EINVAL; 281 282 ret = lan9303_read(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, &val); 283 if (ret) 284 return ret; 285 286 return val & 0xffff; 287 } 288 289 static int lan9303_virt_phy_reg_write(struct lan9303 *chip, int regnum, u16 val) 290 { 291 if (regnum > MII_EXPANSION) 292 return -EINVAL; 293 294 return regmap_write(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, val); 295 } 296 297 static int lan9303_indirect_phy_wait_for_completion(struct lan9303 *chip) 298 { 299 return lan9303_read_wait(chip, LAN9303_PMI_ACCESS, 300 LAN9303_PMI_ACCESS_MII_BUSY); 301 } 302 303 static int lan9303_indirect_phy_read(struct lan9303 *chip, int addr, int regnum) 304 { 305 int ret; 306 u32 val; 307 308 val = LAN9303_PMI_ACCESS_PHY_ADDR(addr); 309 val |= LAN9303_PMI_ACCESS_MIIRINDA(regnum); 310 311 mutex_lock(&chip->indirect_mutex); 312 313 ret = lan9303_indirect_phy_wait_for_completion(chip); 314 if (ret) 315 goto on_error; 316 317 /* start the MII read cycle */ 318 ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, val); 319 if (ret) 320 goto on_error; 321 322 ret = lan9303_indirect_phy_wait_for_completion(chip); 323 if (ret) 324 goto on_error; 325 326 /* read the result of this operation */ 327 ret = lan9303_read(chip->regmap, LAN9303_PMI_DATA, &val); 328 if (ret) 329 goto on_error; 330 331 mutex_unlock(&chip->indirect_mutex); 332 333 return val & 0xffff; 334 335 on_error: 336 mutex_unlock(&chip->indirect_mutex); 337 return ret; 338 } 339 340 static int lan9303_indirect_phy_write(struct lan9303 *chip, int addr, 341 int regnum, u16 val) 342 { 343 int ret; 344 u32 reg; 345 346 reg = LAN9303_PMI_ACCESS_PHY_ADDR(addr); 347 reg |= LAN9303_PMI_ACCESS_MIIRINDA(regnum); 348 reg |= LAN9303_PMI_ACCESS_MII_WRITE; 349 350 mutex_lock(&chip->indirect_mutex); 351 352 ret = lan9303_indirect_phy_wait_for_completion(chip); 353 if (ret) 354 goto on_error; 355 356 /* write the data first... */ 357 ret = regmap_write(chip->regmap, LAN9303_PMI_DATA, val); 358 if (ret) 359 goto on_error; 360 361 /* ...then start the MII write cycle */ 362 ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, reg); 363 364 on_error: 365 mutex_unlock(&chip->indirect_mutex); 366 return ret; 367 } 368 369 const struct lan9303_phy_ops lan9303_indirect_phy_ops = { 370 .phy_read = lan9303_indirect_phy_read, 371 .phy_write = lan9303_indirect_phy_write, 372 }; 373 EXPORT_SYMBOL_GPL(lan9303_indirect_phy_ops); 374 375 static int lan9303_switch_wait_for_completion(struct lan9303 *chip) 376 { 377 return lan9303_read_wait(chip, LAN9303_SWITCH_CSR_CMD, 378 LAN9303_SWITCH_CSR_CMD_BUSY); 379 } 380 381 static int lan9303_write_switch_reg(struct lan9303 *chip, u16 regnum, u32 val) 382 { 383 u32 reg; 384 int ret; 385 386 reg = regnum; 387 reg |= LAN9303_SWITCH_CSR_CMD_LANES; 388 reg |= LAN9303_SWITCH_CSR_CMD_BUSY; 389 390 mutex_lock(&chip->indirect_mutex); 391 392 ret = lan9303_switch_wait_for_completion(chip); 393 if (ret) 394 goto on_error; 395 396 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_DATA, val); 397 if (ret) { 398 dev_err(chip->dev, "Failed to write csr data reg: %d\n", ret); 399 goto on_error; 400 } 401 402 /* trigger write */ 403 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg); 404 if (ret) 405 dev_err(chip->dev, "Failed to write csr command reg: %d\n", 406 ret); 407 408 on_error: 409 mutex_unlock(&chip->indirect_mutex); 410 return ret; 411 } 412 413 static int lan9303_read_switch_reg(struct lan9303 *chip, u16 regnum, u32 *val) 414 { 415 u32 reg; 416 int ret; 417 418 reg = regnum; 419 reg |= LAN9303_SWITCH_CSR_CMD_LANES; 420 reg |= LAN9303_SWITCH_CSR_CMD_RW; 421 reg |= LAN9303_SWITCH_CSR_CMD_BUSY; 422 423 mutex_lock(&chip->indirect_mutex); 424 425 ret = lan9303_switch_wait_for_completion(chip); 426 if (ret) 427 goto on_error; 428 429 /* trigger read */ 430 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg); 431 if (ret) { 432 dev_err(chip->dev, "Failed to write csr command reg: %d\n", 433 ret); 434 goto on_error; 435 } 436 437 ret = lan9303_switch_wait_for_completion(chip); 438 if (ret) 439 goto on_error; 440 441 ret = lan9303_read(chip->regmap, LAN9303_SWITCH_CSR_DATA, val); 442 if (ret) 443 dev_err(chip->dev, "Failed to read csr data reg: %d\n", ret); 444 on_error: 445 mutex_unlock(&chip->indirect_mutex); 446 return ret; 447 } 448 449 static int lan9303_write_switch_reg_mask(struct lan9303 *chip, u16 regnum, 450 u32 val, u32 mask) 451 { 452 int ret; 453 u32 reg; 454 455 ret = lan9303_read_switch_reg(chip, regnum, ®); 456 if (ret) 457 return ret; 458 459 reg = (reg & ~mask) | val; 460 461 return lan9303_write_switch_reg(chip, regnum, reg); 462 } 463 464 static int lan9303_write_switch_port(struct lan9303 *chip, int port, 465 u16 regnum, u32 val) 466 { 467 return lan9303_write_switch_reg( 468 chip, LAN9303_SWITCH_PORT_REG(port, regnum), val); 469 } 470 471 static int lan9303_read_switch_port(struct lan9303 *chip, int port, 472 u16 regnum, u32 *val) 473 { 474 return lan9303_read_switch_reg( 475 chip, LAN9303_SWITCH_PORT_REG(port, regnum), val); 476 } 477 478 static int lan9303_detect_phy_setup(struct lan9303 *chip) 479 { 480 int reg; 481 482 /* depending on the 'phy_addr_sel_strap' setting, the three phys are 483 * using IDs 0-1-2 or IDs 1-2-3. We cannot read back the 484 * 'phy_addr_sel_strap' setting directly, so we need a test, which 485 * configuration is active: 486 * Special reg 18 of phy 3 reads as 0x0000, if 'phy_addr_sel_strap' is 0 487 * and the IDs are 0-1-2, else it contains something different from 488 * 0x0000, which means 'phy_addr_sel_strap' is 1 and the IDs are 1-2-3. 489 * 0xffff is returned on MDIO read with no response. 490 */ 491 reg = chip->ops->phy_read(chip, 3, MII_LAN911X_SPECIAL_MODES); 492 if (reg < 0) { 493 dev_err(chip->dev, "Failed to detect phy config: %d\n", reg); 494 return reg; 495 } 496 497 if ((reg != 0) && (reg != 0xffff)) 498 chip->phy_addr_sel_strap = 1; 499 else 500 chip->phy_addr_sel_strap = 0; 501 502 dev_dbg(chip->dev, "Phy setup '%s' detected\n", 503 chip->phy_addr_sel_strap ? "1-2-3" : "0-1-2"); 504 505 return 0; 506 } 507 508 /* Map ALR-port bits to port bitmap, and back */ 509 static const int alrport_2_portmap[] = {1, 2, 4, 0, 3, 5, 6, 7 }; 510 static const int portmap_2_alrport[] = {3, 0, 1, 4, 2, 5, 6, 7 }; 511 512 /* Return pointer to first free ALR cache entry, return NULL if none */ 513 static struct lan9303_alr_cache_entry * 514 lan9303_alr_cache_find_free(struct lan9303 *chip) 515 { 516 int i; 517 struct lan9303_alr_cache_entry *entr = chip->alr_cache; 518 519 for (i = 0; i < LAN9303_NUM_ALR_RECORDS; i++, entr++) 520 if (entr->port_map == 0) 521 return entr; 522 523 return NULL; 524 } 525 526 /* Return pointer to ALR cache entry matching MAC address */ 527 static struct lan9303_alr_cache_entry * 528 lan9303_alr_cache_find_mac(struct lan9303 *chip, const u8 *mac_addr) 529 { 530 int i; 531 struct lan9303_alr_cache_entry *entr = chip->alr_cache; 532 533 BUILD_BUG_ON_MSG(sizeof(struct lan9303_alr_cache_entry) & 1, 534 "ether_addr_equal require u16 alignment"); 535 536 for (i = 0; i < LAN9303_NUM_ALR_RECORDS; i++, entr++) 537 if (ether_addr_equal(entr->mac_addr, mac_addr)) 538 return entr; 539 540 return NULL; 541 } 542 543 static int lan9303_csr_reg_wait(struct lan9303 *chip, int regno, u32 mask) 544 { 545 int i; 546 547 for (i = 0; i < 25; i++) { 548 u32 reg; 549 550 lan9303_read_switch_reg(chip, regno, ®); 551 if (!(reg & mask)) 552 return 0; 553 usleep_range(1000, 2000); 554 } 555 556 return -ETIMEDOUT; 557 } 558 559 static int lan9303_alr_make_entry_raw(struct lan9303 *chip, u32 dat0, u32 dat1) 560 { 561 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_WR_DAT_0, dat0); 562 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_WR_DAT_1, dat1); 563 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 564 LAN9303_ALR_CMD_MAKE_ENTRY); 565 lan9303_csr_reg_wait(chip, LAN9303_SWE_ALR_CMD_STS, ALR_STS_MAKE_PEND); 566 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0); 567 568 return 0; 569 } 570 571 typedef void alr_loop_cb_t(struct lan9303 *chip, u32 dat0, u32 dat1, 572 int portmap, void *ctx); 573 574 static void lan9303_alr_loop(struct lan9303 *chip, alr_loop_cb_t *cb, void *ctx) 575 { 576 int i; 577 578 mutex_lock(&chip->alr_mutex); 579 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 580 LAN9303_ALR_CMD_GET_FIRST); 581 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0); 582 583 for (i = 1; i < LAN9303_NUM_ALR_RECORDS; i++) { 584 u32 dat0, dat1; 585 int alrport, portmap; 586 587 lan9303_read_switch_reg(chip, LAN9303_SWE_ALR_RD_DAT_0, &dat0); 588 lan9303_read_switch_reg(chip, LAN9303_SWE_ALR_RD_DAT_1, &dat1); 589 if (dat1 & LAN9303_ALR_DAT1_END_OF_TABL) 590 break; 591 592 alrport = (dat1 & LAN9303_ALR_DAT1_PORT_MASK) >> 593 LAN9303_ALR_DAT1_PORT_BITOFFS; 594 portmap = alrport_2_portmap[alrport]; 595 596 cb(chip, dat0, dat1, portmap, ctx); 597 598 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 599 LAN9303_ALR_CMD_GET_NEXT); 600 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0); 601 } 602 mutex_unlock(&chip->alr_mutex); 603 } 604 605 static void alr_reg_to_mac(u32 dat0, u32 dat1, u8 mac[6]) 606 { 607 mac[0] = (dat0 >> 0) & 0xff; 608 mac[1] = (dat0 >> 8) & 0xff; 609 mac[2] = (dat0 >> 16) & 0xff; 610 mac[3] = (dat0 >> 24) & 0xff; 611 mac[4] = (dat1 >> 0) & 0xff; 612 mac[5] = (dat1 >> 8) & 0xff; 613 } 614 615 struct del_port_learned_ctx { 616 int port; 617 }; 618 619 /* Clear learned (non-static) entry on given port */ 620 static void alr_loop_cb_del_port_learned(struct lan9303 *chip, u32 dat0, 621 u32 dat1, int portmap, void *ctx) 622 { 623 struct del_port_learned_ctx *del_ctx = ctx; 624 int port = del_ctx->port; 625 626 if (((BIT(port) & portmap) == 0) || (dat1 & LAN9303_ALR_DAT1_STATIC)) 627 return; 628 629 /* learned entries has only one port, we can just delete */ 630 dat1 &= ~LAN9303_ALR_DAT1_VALID; /* delete entry */ 631 lan9303_alr_make_entry_raw(chip, dat0, dat1); 632 } 633 634 struct port_fdb_dump_ctx { 635 int port; 636 void *data; 637 dsa_fdb_dump_cb_t *cb; 638 }; 639 640 static void alr_loop_cb_fdb_port_dump(struct lan9303 *chip, u32 dat0, 641 u32 dat1, int portmap, void *ctx) 642 { 643 struct port_fdb_dump_ctx *dump_ctx = ctx; 644 u8 mac[ETH_ALEN]; 645 bool is_static; 646 647 if ((BIT(dump_ctx->port) & portmap) == 0) 648 return; 649 650 alr_reg_to_mac(dat0, dat1, mac); 651 is_static = !!(dat1 & LAN9303_ALR_DAT1_STATIC); 652 dump_ctx->cb(mac, 0, is_static, dump_ctx->data); 653 } 654 655 /* Set a static ALR entry. Delete entry if port_map is zero */ 656 static void lan9303_alr_set_entry(struct lan9303 *chip, const u8 *mac, 657 u8 port_map, bool stp_override) 658 { 659 u32 dat0, dat1, alr_port; 660 661 dev_dbg(chip->dev, "%s(%pM, %d)\n", __func__, mac, port_map); 662 dat1 = LAN9303_ALR_DAT1_STATIC; 663 if (port_map) 664 dat1 |= LAN9303_ALR_DAT1_VALID; 665 /* otherwise no ports: delete entry */ 666 if (stp_override) 667 dat1 |= LAN9303_ALR_DAT1_AGE_OVERRID; 668 669 alr_port = portmap_2_alrport[port_map & 7]; 670 dat1 &= ~LAN9303_ALR_DAT1_PORT_MASK; 671 dat1 |= alr_port << LAN9303_ALR_DAT1_PORT_BITOFFS; 672 673 dat0 = 0; 674 dat0 |= (mac[0] << 0); 675 dat0 |= (mac[1] << 8); 676 dat0 |= (mac[2] << 16); 677 dat0 |= (mac[3] << 24); 678 679 dat1 |= (mac[4] << 0); 680 dat1 |= (mac[5] << 8); 681 682 lan9303_alr_make_entry_raw(chip, dat0, dat1); 683 } 684 685 /* Add port to static ALR entry, create new static entry if needed */ 686 static int lan9303_alr_add_port(struct lan9303 *chip, const u8 *mac, int port, 687 bool stp_override) 688 { 689 struct lan9303_alr_cache_entry *entr; 690 691 mutex_lock(&chip->alr_mutex); 692 entr = lan9303_alr_cache_find_mac(chip, mac); 693 if (!entr) { /*New entry */ 694 entr = lan9303_alr_cache_find_free(chip); 695 if (!entr) { 696 mutex_unlock(&chip->alr_mutex); 697 return -ENOSPC; 698 } 699 ether_addr_copy(entr->mac_addr, mac); 700 } 701 entr->port_map |= BIT(port); 702 entr->stp_override = stp_override; 703 lan9303_alr_set_entry(chip, mac, entr->port_map, stp_override); 704 mutex_unlock(&chip->alr_mutex); 705 706 return 0; 707 } 708 709 /* Delete static port from ALR entry, delete entry if last port */ 710 static int lan9303_alr_del_port(struct lan9303 *chip, const u8 *mac, int port) 711 { 712 struct lan9303_alr_cache_entry *entr; 713 714 mutex_lock(&chip->alr_mutex); 715 entr = lan9303_alr_cache_find_mac(chip, mac); 716 if (!entr) 717 goto out; /* no static entry found */ 718 719 entr->port_map &= ~BIT(port); 720 if (entr->port_map == 0) /* zero means its free again */ 721 eth_zero_addr(entr->mac_addr); 722 lan9303_alr_set_entry(chip, mac, entr->port_map, entr->stp_override); 723 724 out: 725 mutex_unlock(&chip->alr_mutex); 726 return 0; 727 } 728 729 static int lan9303_disable_processing_port(struct lan9303 *chip, 730 unsigned int port) 731 { 732 int ret; 733 734 /* disable RX, but keep register reset default values else */ 735 ret = lan9303_write_switch_port(chip, port, LAN9303_MAC_RX_CFG_0, 736 LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES); 737 if (ret) 738 return ret; 739 740 /* disable TX, but keep register reset default values else */ 741 return lan9303_write_switch_port(chip, port, LAN9303_MAC_TX_CFG_0, 742 LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT | 743 LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE); 744 } 745 746 static int lan9303_enable_processing_port(struct lan9303 *chip, 747 unsigned int port) 748 { 749 int ret; 750 751 /* enable RX and keep register reset default values else */ 752 ret = lan9303_write_switch_port(chip, port, LAN9303_MAC_RX_CFG_0, 753 LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES | 754 LAN9303_MAC_RX_CFG_X_RX_ENABLE); 755 if (ret) 756 return ret; 757 758 /* enable TX and keep register reset default values else */ 759 return lan9303_write_switch_port(chip, port, LAN9303_MAC_TX_CFG_0, 760 LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT | 761 LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE | 762 LAN9303_MAC_TX_CFG_X_TX_ENABLE); 763 } 764 765 /* forward special tagged packets from port 0 to port 1 *or* port 2 */ 766 static int lan9303_setup_tagging(struct lan9303 *chip) 767 { 768 int ret; 769 u32 val; 770 /* enable defining the destination port via special VLAN tagging 771 * for port 0 772 */ 773 ret = lan9303_write_switch_reg(chip, LAN9303_SWE_INGRESS_PORT_TYPE, 774 LAN9303_SWE_INGRESS_PORT_TYPE_VLAN); 775 if (ret) 776 return ret; 777 778 /* tag incoming packets at port 1 and 2 on their way to port 0 to be 779 * able to discover their source port 780 */ 781 val = LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0; 782 return lan9303_write_switch_reg(chip, LAN9303_BM_EGRSS_PORT_TYPE, val); 783 } 784 785 /* We want a special working switch: 786 * - do not forward packets between port 1 and 2 787 * - forward everything from port 1 to port 0 788 * - forward everything from port 2 to port 0 789 */ 790 static int lan9303_separate_ports(struct lan9303 *chip) 791 { 792 int ret; 793 794 lan9303_alr_del_port(chip, eth_stp_addr, 0); 795 ret = lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_MIRROR, 796 LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT0 | 797 LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT1 | 798 LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT2 | 799 LAN9303_SWE_PORT_MIRROR_ENABLE_RX_MIRRORING | 800 LAN9303_SWE_PORT_MIRROR_SNIFF_ALL); 801 if (ret) 802 return ret; 803 804 /* prevent port 1 and 2 from forwarding packets by their own */ 805 return lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE, 806 LAN9303_SWE_PORT_STATE_FORWARDING_PORT0 | 807 LAN9303_SWE_PORT_STATE_BLOCKING_PORT1 | 808 LAN9303_SWE_PORT_STATE_BLOCKING_PORT2); 809 } 810 811 static void lan9303_bridge_ports(struct lan9303 *chip) 812 { 813 /* ports bridged: remove mirroring */ 814 lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_MIRROR, 815 LAN9303_SWE_PORT_MIRROR_DISABLED); 816 817 lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE, 818 chip->swe_port_state); 819 lan9303_alr_add_port(chip, eth_stp_addr, 0, true); 820 } 821 822 static int lan9303_handle_reset(struct lan9303 *chip) 823 { 824 if (!chip->reset_gpio) 825 return 0; 826 827 if (chip->reset_duration != 0) 828 msleep(chip->reset_duration); 829 830 /* release (deassert) reset and activate the device */ 831 gpiod_set_value_cansleep(chip->reset_gpio, 0); 832 833 return 0; 834 } 835 836 /* stop processing packets for all ports */ 837 static int lan9303_disable_processing(struct lan9303 *chip) 838 { 839 int p; 840 841 for (p = 1; p < LAN9303_NUM_PORTS; p++) { 842 int ret = lan9303_disable_processing_port(chip, p); 843 844 if (ret) 845 return ret; 846 } 847 848 return 0; 849 } 850 851 static int lan9303_check_device(struct lan9303 *chip) 852 { 853 int ret; 854 u32 reg; 855 856 ret = lan9303_read(chip->regmap, LAN9303_CHIP_REV, ®); 857 if (ret) { 858 dev_err(chip->dev, "failed to read chip revision register: %d\n", 859 ret); 860 if (!chip->reset_gpio) { 861 dev_dbg(chip->dev, 862 "hint: maybe failed due to missing reset GPIO\n"); 863 } 864 return ret; 865 } 866 867 if ((reg >> 16) != LAN9303_CHIP_ID) { 868 dev_err(chip->dev, "expecting LAN9303 chip, but found: %X\n", 869 reg >> 16); 870 return ret; 871 } 872 873 /* The default state of the LAN9303 device is to forward packets between 874 * all ports (if not configured differently by an external EEPROM). 875 * The initial state of a DSA device must be forwarding packets only 876 * between the external and the internal ports and no forwarding 877 * between the external ports. In preparation we stop packet handling 878 * at all for now until the LAN9303 device is re-programmed accordingly. 879 */ 880 ret = lan9303_disable_processing(chip); 881 if (ret) 882 dev_warn(chip->dev, "failed to disable switching %d\n", ret); 883 884 dev_info(chip->dev, "Found LAN9303 rev. %u\n", reg & 0xffff); 885 886 ret = lan9303_detect_phy_setup(chip); 887 if (ret) { 888 dev_err(chip->dev, 889 "failed to discover phy bootstrap setup: %d\n", ret); 890 return ret; 891 } 892 893 return 0; 894 } 895 896 /* ---------------------------- DSA -----------------------------------*/ 897 898 static enum dsa_tag_protocol lan9303_get_tag_protocol(struct dsa_switch *ds, 899 int port) 900 { 901 return DSA_TAG_PROTO_LAN9303; 902 } 903 904 static int lan9303_setup(struct dsa_switch *ds) 905 { 906 struct lan9303 *chip = ds->priv; 907 int ret; 908 909 /* Make sure that port 0 is the cpu port */ 910 if (!dsa_is_cpu_port(ds, 0)) { 911 dev_err(chip->dev, "port 0 is not the CPU port\n"); 912 return -EINVAL; 913 } 914 915 ret = lan9303_setup_tagging(chip); 916 if (ret) 917 dev_err(chip->dev, "failed to setup port tagging %d\n", ret); 918 919 ret = lan9303_separate_ports(chip); 920 if (ret) 921 dev_err(chip->dev, "failed to separate ports %d\n", ret); 922 923 ret = lan9303_enable_processing_port(chip, 0); 924 if (ret) 925 dev_err(chip->dev, "failed to re-enable switching %d\n", ret); 926 927 /* Trap IGMP to port 0 */ 928 ret = lan9303_write_switch_reg_mask(chip, LAN9303_SWE_GLB_INGRESS_CFG, 929 LAN9303_SWE_GLB_INGR_IGMP_TRAP | 930 LAN9303_SWE_GLB_INGR_IGMP_PORT(0), 931 LAN9303_SWE_GLB_INGR_IGMP_PORT(1) | 932 LAN9303_SWE_GLB_INGR_IGMP_PORT(2)); 933 if (ret) 934 dev_err(chip->dev, "failed to setup IGMP trap %d\n", ret); 935 936 return 0; 937 } 938 939 struct lan9303_mib_desc { 940 unsigned int offset; /* offset of first MAC */ 941 const char *name; 942 }; 943 944 static const struct lan9303_mib_desc lan9303_mib[] = { 945 { .offset = LAN9303_MAC_RX_BRDCST_CNT_0, .name = "RxBroad", }, 946 { .offset = LAN9303_MAC_RX_PAUSE_CNT_0, .name = "RxPause", }, 947 { .offset = LAN9303_MAC_RX_MULCST_CNT_0, .name = "RxMulti", }, 948 { .offset = LAN9303_MAC_RX_PKTOK_CNT_0, .name = "RxOk", }, 949 { .offset = LAN9303_MAC_RX_CRCERR_CNT_0, .name = "RxCrcErr", }, 950 { .offset = LAN9303_MAC_RX_ALIGN_CNT_0, .name = "RxAlignErr", }, 951 { .offset = LAN9303_MAC_RX_JABB_CNT_0, .name = "RxJabber", }, 952 { .offset = LAN9303_MAC_RX_FRAG_CNT_0, .name = "RxFragment", }, 953 { .offset = LAN9303_MAC_RX_64_CNT_0, .name = "Rx64Byte", }, 954 { .offset = LAN9303_MAC_RX_127_CNT_0, .name = "Rx128Byte", }, 955 { .offset = LAN9303_MAC_RX_255_CNT_0, .name = "Rx256Byte", }, 956 { .offset = LAN9303_MAC_RX_511_CNT_0, .name = "Rx512Byte", }, 957 { .offset = LAN9303_MAC_RX_1023_CNT_0, .name = "Rx1024Byte", }, 958 { .offset = LAN9303_MAC_RX_MAX_CNT_0, .name = "RxMaxByte", }, 959 { .offset = LAN9303_MAC_RX_PKTLEN_CNT_0, .name = "RxByteCnt", }, 960 { .offset = LAN9303_MAC_RX_SYMBL_CNT_0, .name = "RxSymbolCnt", }, 961 { .offset = LAN9303_MAC_RX_CTLFRM_CNT_0, .name = "RxCfs", }, 962 { .offset = LAN9303_MAC_RX_OVRSZE_CNT_0, .name = "RxOverFlow", }, 963 { .offset = LAN9303_MAC_TX_UNDSZE_CNT_0, .name = "TxShort", }, 964 { .offset = LAN9303_MAC_TX_BRDCST_CNT_0, .name = "TxBroad", }, 965 { .offset = LAN9303_MAC_TX_PAUSE_CNT_0, .name = "TxPause", }, 966 { .offset = LAN9303_MAC_TX_MULCST_CNT_0, .name = "TxMulti", }, 967 { .offset = LAN9303_MAC_RX_UNDSZE_CNT_0, .name = "TxUnderRun", }, 968 { .offset = LAN9303_MAC_TX_64_CNT_0, .name = "Tx64Byte", }, 969 { .offset = LAN9303_MAC_TX_127_CNT_0, .name = "Tx128Byte", }, 970 { .offset = LAN9303_MAC_TX_255_CNT_0, .name = "Tx256Byte", }, 971 { .offset = LAN9303_MAC_TX_511_CNT_0, .name = "Tx512Byte", }, 972 { .offset = LAN9303_MAC_TX_1023_CNT_0, .name = "Tx1024Byte", }, 973 { .offset = LAN9303_MAC_TX_MAX_CNT_0, .name = "TxMaxByte", }, 974 { .offset = LAN9303_MAC_TX_PKTLEN_CNT_0, .name = "TxByteCnt", }, 975 { .offset = LAN9303_MAC_TX_PKTOK_CNT_0, .name = "TxOk", }, 976 { .offset = LAN9303_MAC_TX_TOTALCOL_CNT_0, .name = "TxCollision", }, 977 { .offset = LAN9303_MAC_TX_MULTICOL_CNT_0, .name = "TxMultiCol", }, 978 { .offset = LAN9303_MAC_TX_SNGLECOL_CNT_0, .name = "TxSingleCol", }, 979 { .offset = LAN9303_MAC_TX_EXCOL_CNT_0, .name = "TxExcCol", }, 980 { .offset = LAN9303_MAC_TX_DEFER_CNT_0, .name = "TxDefer", }, 981 { .offset = LAN9303_MAC_TX_LATECOL_0, .name = "TxLateCol", }, 982 }; 983 984 static void lan9303_get_strings(struct dsa_switch *ds, int port, uint8_t *data) 985 { 986 unsigned int u; 987 988 for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++) { 989 strncpy(data + u * ETH_GSTRING_LEN, lan9303_mib[u].name, 990 ETH_GSTRING_LEN); 991 } 992 } 993 994 static void lan9303_get_ethtool_stats(struct dsa_switch *ds, int port, 995 uint64_t *data) 996 { 997 struct lan9303 *chip = ds->priv; 998 unsigned int u; 999 1000 for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++) { 1001 u32 reg; 1002 int ret; 1003 1004 ret = lan9303_read_switch_port( 1005 chip, port, lan9303_mib[u].offset, ®); 1006 1007 if (ret) 1008 dev_warn(chip->dev, "Reading status port %d reg %u failed\n", 1009 port, lan9303_mib[u].offset); 1010 data[u] = reg; 1011 } 1012 } 1013 1014 static int lan9303_get_sset_count(struct dsa_switch *ds) 1015 { 1016 return ARRAY_SIZE(lan9303_mib); 1017 } 1018 1019 static int lan9303_phy_read(struct dsa_switch *ds, int phy, int regnum) 1020 { 1021 struct lan9303 *chip = ds->priv; 1022 int phy_base = chip->phy_addr_sel_strap; 1023 1024 if (phy == phy_base) 1025 return lan9303_virt_phy_reg_read(chip, regnum); 1026 if (phy > phy_base + 2) 1027 return -ENODEV; 1028 1029 return chip->ops->phy_read(chip, phy, regnum); 1030 } 1031 1032 static int lan9303_phy_write(struct dsa_switch *ds, int phy, int regnum, 1033 u16 val) 1034 { 1035 struct lan9303 *chip = ds->priv; 1036 int phy_base = chip->phy_addr_sel_strap; 1037 1038 if (phy == phy_base) 1039 return lan9303_virt_phy_reg_write(chip, regnum, val); 1040 if (phy > phy_base + 2) 1041 return -ENODEV; 1042 1043 return chip->ops->phy_write(chip, phy, regnum, val); 1044 } 1045 1046 static void lan9303_adjust_link(struct dsa_switch *ds, int port, 1047 struct phy_device *phydev) 1048 { 1049 struct lan9303 *chip = ds->priv; 1050 int ctl, res; 1051 1052 if (!phy_is_pseudo_fixed_link(phydev)) 1053 return; 1054 1055 ctl = lan9303_phy_read(ds, port, MII_BMCR); 1056 1057 ctl &= ~BMCR_ANENABLE; 1058 1059 if (phydev->speed == SPEED_100) 1060 ctl |= BMCR_SPEED100; 1061 else if (phydev->speed == SPEED_10) 1062 ctl &= ~BMCR_SPEED100; 1063 else 1064 dev_err(ds->dev, "unsupported speed: %d\n", phydev->speed); 1065 1066 if (phydev->duplex == DUPLEX_FULL) 1067 ctl |= BMCR_FULLDPLX; 1068 else 1069 ctl &= ~BMCR_FULLDPLX; 1070 1071 res = lan9303_phy_write(ds, port, MII_BMCR, ctl); 1072 1073 if (port == chip->phy_addr_sel_strap) { 1074 /* Virtual Phy: Remove Turbo 200Mbit mode */ 1075 lan9303_read(chip->regmap, LAN9303_VIRT_SPECIAL_CTRL, &ctl); 1076 1077 ctl &= ~LAN9303_VIRT_SPECIAL_TURBO; 1078 res = regmap_write(chip->regmap, 1079 LAN9303_VIRT_SPECIAL_CTRL, ctl); 1080 } 1081 } 1082 1083 static int lan9303_port_enable(struct dsa_switch *ds, int port, 1084 struct phy_device *phy) 1085 { 1086 struct lan9303 *chip = ds->priv; 1087 1088 return lan9303_enable_processing_port(chip, port); 1089 } 1090 1091 static void lan9303_port_disable(struct dsa_switch *ds, int port, 1092 struct phy_device *phy) 1093 { 1094 struct lan9303 *chip = ds->priv; 1095 1096 lan9303_disable_processing_port(chip, port); 1097 lan9303_phy_write(ds, chip->phy_addr_sel_strap + port, 1098 MII_BMCR, BMCR_PDOWN); 1099 } 1100 1101 static int lan9303_port_bridge_join(struct dsa_switch *ds, int port, 1102 struct net_device *br) 1103 { 1104 struct lan9303 *chip = ds->priv; 1105 1106 dev_dbg(chip->dev, "%s(port %d)\n", __func__, port); 1107 if (dsa_to_port(ds, 1)->bridge_dev == dsa_to_port(ds, 2)->bridge_dev) { 1108 lan9303_bridge_ports(chip); 1109 chip->is_bridged = true; /* unleash stp_state_set() */ 1110 } 1111 1112 return 0; 1113 } 1114 1115 static void lan9303_port_bridge_leave(struct dsa_switch *ds, int port, 1116 struct net_device *br) 1117 { 1118 struct lan9303 *chip = ds->priv; 1119 1120 dev_dbg(chip->dev, "%s(port %d)\n", __func__, port); 1121 if (chip->is_bridged) { 1122 lan9303_separate_ports(chip); 1123 chip->is_bridged = false; 1124 } 1125 } 1126 1127 static void lan9303_port_stp_state_set(struct dsa_switch *ds, int port, 1128 u8 state) 1129 { 1130 int portmask, portstate; 1131 struct lan9303 *chip = ds->priv; 1132 1133 dev_dbg(chip->dev, "%s(port %d, state %d)\n", 1134 __func__, port, state); 1135 1136 switch (state) { 1137 case BR_STATE_DISABLED: 1138 portstate = LAN9303_SWE_PORT_STATE_DISABLED_PORT0; 1139 break; 1140 case BR_STATE_BLOCKING: 1141 case BR_STATE_LISTENING: 1142 portstate = LAN9303_SWE_PORT_STATE_BLOCKING_PORT0; 1143 break; 1144 case BR_STATE_LEARNING: 1145 portstate = LAN9303_SWE_PORT_STATE_LEARNING_PORT0; 1146 break; 1147 case BR_STATE_FORWARDING: 1148 portstate = LAN9303_SWE_PORT_STATE_FORWARDING_PORT0; 1149 break; 1150 default: 1151 portstate = LAN9303_SWE_PORT_STATE_DISABLED_PORT0; 1152 dev_err(chip->dev, "unknown stp state: port %d, state %d\n", 1153 port, state); 1154 } 1155 1156 portmask = 0x3 << (port * 2); 1157 portstate <<= (port * 2); 1158 1159 chip->swe_port_state = (chip->swe_port_state & ~portmask) | portstate; 1160 1161 if (chip->is_bridged) 1162 lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE, 1163 chip->swe_port_state); 1164 /* else: touching SWE_PORT_STATE would break port separation */ 1165 } 1166 1167 static void lan9303_port_fast_age(struct dsa_switch *ds, int port) 1168 { 1169 struct lan9303 *chip = ds->priv; 1170 struct del_port_learned_ctx del_ctx = { 1171 .port = port, 1172 }; 1173 1174 dev_dbg(chip->dev, "%s(%d)\n", __func__, port); 1175 lan9303_alr_loop(chip, alr_loop_cb_del_port_learned, &del_ctx); 1176 } 1177 1178 static int lan9303_port_fdb_add(struct dsa_switch *ds, int port, 1179 const unsigned char *addr, u16 vid) 1180 { 1181 struct lan9303 *chip = ds->priv; 1182 1183 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, addr, vid); 1184 if (vid) 1185 return -EOPNOTSUPP; 1186 1187 return lan9303_alr_add_port(chip, addr, port, false); 1188 } 1189 1190 static int lan9303_port_fdb_del(struct dsa_switch *ds, int port, 1191 const unsigned char *addr, u16 vid) 1192 1193 { 1194 struct lan9303 *chip = ds->priv; 1195 1196 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, addr, vid); 1197 if (vid) 1198 return -EOPNOTSUPP; 1199 lan9303_alr_del_port(chip, addr, port); 1200 1201 return 0; 1202 } 1203 1204 static int lan9303_port_fdb_dump(struct dsa_switch *ds, int port, 1205 dsa_fdb_dump_cb_t *cb, void *data) 1206 { 1207 struct lan9303 *chip = ds->priv; 1208 struct port_fdb_dump_ctx dump_ctx = { 1209 .port = port, 1210 .data = data, 1211 .cb = cb, 1212 }; 1213 1214 dev_dbg(chip->dev, "%s(%d)\n", __func__, port); 1215 lan9303_alr_loop(chip, alr_loop_cb_fdb_port_dump, &dump_ctx); 1216 1217 return 0; 1218 } 1219 1220 static int lan9303_port_mdb_prepare(struct dsa_switch *ds, int port, 1221 const struct switchdev_obj_port_mdb *mdb) 1222 { 1223 struct lan9303 *chip = ds->priv; 1224 1225 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr, 1226 mdb->vid); 1227 if (mdb->vid) 1228 return -EOPNOTSUPP; 1229 if (lan9303_alr_cache_find_mac(chip, mdb->addr)) 1230 return 0; 1231 if (!lan9303_alr_cache_find_free(chip)) 1232 return -ENOSPC; 1233 1234 return 0; 1235 } 1236 1237 static void lan9303_port_mdb_add(struct dsa_switch *ds, int port, 1238 const struct switchdev_obj_port_mdb *mdb) 1239 { 1240 struct lan9303 *chip = ds->priv; 1241 1242 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr, 1243 mdb->vid); 1244 lan9303_alr_add_port(chip, mdb->addr, port, false); 1245 } 1246 1247 static int lan9303_port_mdb_del(struct dsa_switch *ds, int port, 1248 const struct switchdev_obj_port_mdb *mdb) 1249 { 1250 struct lan9303 *chip = ds->priv; 1251 1252 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr, 1253 mdb->vid); 1254 if (mdb->vid) 1255 return -EOPNOTSUPP; 1256 lan9303_alr_del_port(chip, mdb->addr, port); 1257 1258 return 0; 1259 } 1260 1261 static const struct dsa_switch_ops lan9303_switch_ops = { 1262 .get_tag_protocol = lan9303_get_tag_protocol, 1263 .setup = lan9303_setup, 1264 .get_strings = lan9303_get_strings, 1265 .phy_read = lan9303_phy_read, 1266 .phy_write = lan9303_phy_write, 1267 .adjust_link = lan9303_adjust_link, 1268 .get_ethtool_stats = lan9303_get_ethtool_stats, 1269 .get_sset_count = lan9303_get_sset_count, 1270 .port_enable = lan9303_port_enable, 1271 .port_disable = lan9303_port_disable, 1272 .port_bridge_join = lan9303_port_bridge_join, 1273 .port_bridge_leave = lan9303_port_bridge_leave, 1274 .port_stp_state_set = lan9303_port_stp_state_set, 1275 .port_fast_age = lan9303_port_fast_age, 1276 .port_fdb_add = lan9303_port_fdb_add, 1277 .port_fdb_del = lan9303_port_fdb_del, 1278 .port_fdb_dump = lan9303_port_fdb_dump, 1279 .port_mdb_prepare = lan9303_port_mdb_prepare, 1280 .port_mdb_add = lan9303_port_mdb_add, 1281 .port_mdb_del = lan9303_port_mdb_del, 1282 }; 1283 1284 static int lan9303_register_switch(struct lan9303 *chip) 1285 { 1286 chip->ds = dsa_switch_alloc(chip->dev, LAN9303_NUM_PORTS); 1287 if (!chip->ds) 1288 return -ENOMEM; 1289 1290 chip->ds->priv = chip; 1291 chip->ds->ops = &lan9303_switch_ops; 1292 chip->ds->phys_mii_mask = chip->phy_addr_sel_strap ? 0xe : 0x7; 1293 1294 return dsa_register_switch(chip->ds); 1295 } 1296 1297 static void lan9303_probe_reset_gpio(struct lan9303 *chip, 1298 struct device_node *np) 1299 { 1300 chip->reset_gpio = devm_gpiod_get_optional(chip->dev, "reset", 1301 GPIOD_OUT_LOW); 1302 1303 if (IS_ERR(chip->reset_gpio)) { 1304 dev_dbg(chip->dev, "No reset GPIO defined\n"); 1305 return; 1306 } 1307 1308 chip->reset_duration = 200; 1309 1310 if (np) { 1311 of_property_read_u32(np, "reset-duration", 1312 &chip->reset_duration); 1313 } else { 1314 dev_dbg(chip->dev, "reset duration defaults to 200 ms\n"); 1315 } 1316 1317 /* A sane reset duration should not be longer than 1s */ 1318 if (chip->reset_duration > 1000) 1319 chip->reset_duration = 1000; 1320 } 1321 1322 int lan9303_probe(struct lan9303 *chip, struct device_node *np) 1323 { 1324 int ret; 1325 1326 mutex_init(&chip->indirect_mutex); 1327 mutex_init(&chip->alr_mutex); 1328 1329 lan9303_probe_reset_gpio(chip, np); 1330 1331 ret = lan9303_handle_reset(chip); 1332 if (ret) 1333 return ret; 1334 1335 ret = lan9303_check_device(chip); 1336 if (ret) 1337 return ret; 1338 1339 ret = lan9303_register_switch(chip); 1340 if (ret) { 1341 dev_dbg(chip->dev, "Failed to register switch: %d\n", ret); 1342 return ret; 1343 } 1344 1345 return 0; 1346 } 1347 EXPORT_SYMBOL(lan9303_probe); 1348 1349 int lan9303_remove(struct lan9303 *chip) 1350 { 1351 int rc; 1352 1353 rc = lan9303_disable_processing(chip); 1354 if (rc != 0) 1355 dev_warn(chip->dev, "shutting down failed\n"); 1356 1357 dsa_unregister_switch(chip->ds); 1358 1359 /* assert reset to the whole device to prevent it from doing anything */ 1360 gpiod_set_value_cansleep(chip->reset_gpio, 1); 1361 gpiod_unexport(chip->reset_gpio); 1362 1363 return 0; 1364 } 1365 EXPORT_SYMBOL(lan9303_remove); 1366 1367 MODULE_AUTHOR("Juergen Borleis <kernel@pengutronix.de>"); 1368 MODULE_DESCRIPTION("Core driver for SMSC/Microchip LAN9303 three port ethernet switch"); 1369 MODULE_LICENSE("GPL v2"); 1370