1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2017 Pengutronix, Juergen Borleis <kernel@pengutronix.de> 4 */ 5 #include <linux/kernel.h> 6 #include <linux/module.h> 7 #include <linux/gpio/consumer.h> 8 #include <linux/regmap.h> 9 #include <linux/iopoll.h> 10 #include <linux/mutex.h> 11 #include <linux/mii.h> 12 #include <linux/of.h> 13 #include <linux/phy.h> 14 #include <linux/if_bridge.h> 15 #include <linux/if_vlan.h> 16 #include <linux/etherdevice.h> 17 18 #include "lan9303.h" 19 20 /* For the LAN9303 and LAN9354, only port 0 is an XMII port. */ 21 #define IS_PORT_XMII(port) ((port) == 0) 22 23 #define LAN9303_NUM_PORTS 3 24 25 /* 13.2 System Control and Status Registers 26 * Multiply register number by 4 to get address offset. 27 */ 28 #define LAN9303_CHIP_REV 0x14 29 # define LAN9303_CHIP_ID 0x9303 30 # define LAN9352_CHIP_ID 0x9352 31 # define LAN9353_CHIP_ID 0x9353 32 # define LAN9354_CHIP_ID 0x9354 33 # define LAN9355_CHIP_ID 0x9355 34 #define LAN9303_IRQ_CFG 0x15 35 # define LAN9303_IRQ_CFG_IRQ_ENABLE BIT(8) 36 # define LAN9303_IRQ_CFG_IRQ_POL BIT(4) 37 # define LAN9303_IRQ_CFG_IRQ_TYPE BIT(0) 38 #define LAN9303_INT_STS 0x16 39 # define LAN9303_INT_STS_PHY_INT2 BIT(27) 40 # define LAN9303_INT_STS_PHY_INT1 BIT(26) 41 #define LAN9303_INT_EN 0x17 42 # define LAN9303_INT_EN_PHY_INT2_EN BIT(27) 43 # define LAN9303_INT_EN_PHY_INT1_EN BIT(26) 44 #define LAN9303_BYTE_ORDER 0x19 45 #define LAN9303_HW_CFG 0x1D 46 # define LAN9303_HW_CFG_READY BIT(27) 47 # define LAN9303_HW_CFG_AMDX_EN_PORT2 BIT(26) 48 # define LAN9303_HW_CFG_AMDX_EN_PORT1 BIT(25) 49 #define LAN9303_PMI_DATA 0x29 50 #define LAN9303_PMI_ACCESS 0x2A 51 # define LAN9303_PMI_ACCESS_PHY_ADDR(x) (((x) & 0x1f) << 11) 52 # define LAN9303_PMI_ACCESS_MIIRINDA(x) (((x) & 0x1f) << 6) 53 # define LAN9303_PMI_ACCESS_MII_BUSY BIT(0) 54 # define LAN9303_PMI_ACCESS_MII_WRITE BIT(1) 55 #define LAN9303_MANUAL_FC_1 0x68 56 #define LAN9303_MANUAL_FC_2 0x69 57 #define LAN9303_MANUAL_FC_0 0x6a 58 # define LAN9303_BP_EN BIT(6) 59 # define LAN9303_RX_FC_EN BIT(2) 60 # define LAN9303_TX_FC_EN BIT(1) 61 #define LAN9303_SWITCH_CSR_DATA 0x6b 62 #define LAN9303_SWITCH_CSR_CMD 0x6c 63 #define LAN9303_SWITCH_CSR_CMD_BUSY BIT(31) 64 #define LAN9303_SWITCH_CSR_CMD_RW BIT(30) 65 #define LAN9303_SWITCH_CSR_CMD_LANES (BIT(19) | BIT(18) | BIT(17) | BIT(16)) 66 #define LAN9303_VIRT_PHY_BASE 0x70 67 #define LAN9303_VIRT_SPECIAL_CTRL 0x77 68 #define LAN9303_VIRT_SPECIAL_TURBO BIT(10) /*Turbo MII Enable*/ 69 70 /*13.4 Switch Fabric Control and Status Registers 71 * Accessed indirectly via SWITCH_CSR_CMD, SWITCH_CSR_DATA. 72 */ 73 #define LAN9303_SW_DEV_ID 0x0000 74 #define LAN9303_SW_RESET 0x0001 75 #define LAN9303_SW_RESET_RESET BIT(0) 76 #define LAN9303_SW_IMR 0x0004 77 #define LAN9303_SW_IPR 0x0005 78 #define LAN9303_MAC_VER_ID_0 0x0400 79 #define LAN9303_MAC_RX_CFG_0 0x0401 80 # define LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES BIT(1) 81 # define LAN9303_MAC_RX_CFG_X_RX_ENABLE BIT(0) 82 #define LAN9303_MAC_RX_UNDSZE_CNT_0 0x0410 83 #define LAN9303_MAC_RX_64_CNT_0 0x0411 84 #define LAN9303_MAC_RX_127_CNT_0 0x0412 85 #define LAN9303_MAC_RX_255_CNT_0 0x413 86 #define LAN9303_MAC_RX_511_CNT_0 0x0414 87 #define LAN9303_MAC_RX_1023_CNT_0 0x0415 88 #define LAN9303_MAC_RX_MAX_CNT_0 0x0416 89 #define LAN9303_MAC_RX_OVRSZE_CNT_0 0x0417 90 #define LAN9303_MAC_RX_PKTOK_CNT_0 0x0418 91 #define LAN9303_MAC_RX_CRCERR_CNT_0 0x0419 92 #define LAN9303_MAC_RX_MULCST_CNT_0 0x041a 93 #define LAN9303_MAC_RX_BRDCST_CNT_0 0x041b 94 #define LAN9303_MAC_RX_PAUSE_CNT_0 0x041c 95 #define LAN9303_MAC_RX_FRAG_CNT_0 0x041d 96 #define LAN9303_MAC_RX_JABB_CNT_0 0x041e 97 #define LAN9303_MAC_RX_ALIGN_CNT_0 0x041f 98 #define LAN9303_MAC_RX_PKTLEN_CNT_0 0x0420 99 #define LAN9303_MAC_RX_GOODPKTLEN_CNT_0 0x0421 100 #define LAN9303_MAC_RX_SYMBL_CNT_0 0x0422 101 #define LAN9303_MAC_RX_CTLFRM_CNT_0 0x0423 102 103 #define LAN9303_MAC_TX_CFG_0 0x0440 104 # define LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT (21 << 2) 105 # define LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE BIT(1) 106 # define LAN9303_MAC_TX_CFG_X_TX_ENABLE BIT(0) 107 #define LAN9303_MAC_TX_DEFER_CNT_0 0x0451 108 #define LAN9303_MAC_TX_PAUSE_CNT_0 0x0452 109 #define LAN9303_MAC_TX_PKTOK_CNT_0 0x0453 110 #define LAN9303_MAC_TX_64_CNT_0 0x0454 111 #define LAN9303_MAC_TX_127_CNT_0 0x0455 112 #define LAN9303_MAC_TX_255_CNT_0 0x0456 113 #define LAN9303_MAC_TX_511_CNT_0 0x0457 114 #define LAN9303_MAC_TX_1023_CNT_0 0x0458 115 #define LAN9303_MAC_TX_MAX_CNT_0 0x0459 116 #define LAN9303_MAC_TX_UNDSZE_CNT_0 0x045a 117 #define LAN9303_MAC_TX_PKTLEN_CNT_0 0x045c 118 #define LAN9303_MAC_TX_BRDCST_CNT_0 0x045d 119 #define LAN9303_MAC_TX_MULCST_CNT_0 0x045e 120 #define LAN9303_MAC_TX_LATECOL_0 0x045f 121 #define LAN9303_MAC_TX_EXCOL_CNT_0 0x0460 122 #define LAN9303_MAC_TX_SNGLECOL_CNT_0 0x0461 123 #define LAN9303_MAC_TX_MULTICOL_CNT_0 0x0462 124 #define LAN9303_MAC_TX_TOTALCOL_CNT_0 0x0463 125 126 #define LAN9303_MAC_VER_ID_1 0x0800 127 #define LAN9303_MAC_RX_CFG_1 0x0801 128 #define LAN9303_MAC_TX_CFG_1 0x0840 129 #define LAN9303_MAC_VER_ID_2 0x0c00 130 #define LAN9303_MAC_RX_CFG_2 0x0c01 131 #define LAN9303_MAC_TX_CFG_2 0x0c40 132 #define LAN9303_SWE_ALR_CMD 0x1800 133 # define LAN9303_ALR_CMD_MAKE_ENTRY BIT(2) 134 # define LAN9303_ALR_CMD_GET_FIRST BIT(1) 135 # define LAN9303_ALR_CMD_GET_NEXT BIT(0) 136 #define LAN9303_SWE_ALR_WR_DAT_0 0x1801 137 #define LAN9303_SWE_ALR_WR_DAT_1 0x1802 138 # define LAN9303_ALR_DAT1_VALID BIT(26) 139 # define LAN9303_ALR_DAT1_END_OF_TABL BIT(25) 140 # define LAN9303_ALR_DAT1_AGE_OVERRID BIT(25) 141 # define LAN9303_ALR_DAT1_STATIC BIT(24) 142 # define LAN9303_ALR_DAT1_PORT_BITOFFS 16 143 # define LAN9303_ALR_DAT1_PORT_MASK (7 << LAN9303_ALR_DAT1_PORT_BITOFFS) 144 #define LAN9303_SWE_ALR_RD_DAT_0 0x1805 145 #define LAN9303_SWE_ALR_RD_DAT_1 0x1806 146 #define LAN9303_SWE_ALR_CMD_STS 0x1808 147 # define ALR_STS_MAKE_PEND BIT(0) 148 #define LAN9303_SWE_VLAN_CMD 0x180b 149 # define LAN9303_SWE_VLAN_CMD_RNW BIT(5) 150 # define LAN9303_SWE_VLAN_CMD_PVIDNVLAN BIT(4) 151 #define LAN9303_SWE_VLAN_WR_DATA 0x180c 152 #define LAN9303_SWE_VLAN_RD_DATA 0x180e 153 # define LAN9303_SWE_VLAN_MEMBER_PORT2 BIT(17) 154 # define LAN9303_SWE_VLAN_UNTAG_PORT2 BIT(16) 155 # define LAN9303_SWE_VLAN_MEMBER_PORT1 BIT(15) 156 # define LAN9303_SWE_VLAN_UNTAG_PORT1 BIT(14) 157 # define LAN9303_SWE_VLAN_MEMBER_PORT0 BIT(13) 158 # define LAN9303_SWE_VLAN_UNTAG_PORT0 BIT(12) 159 #define LAN9303_SWE_VLAN_CMD_STS 0x1810 160 #define LAN9303_SWE_GLB_INGRESS_CFG 0x1840 161 # define LAN9303_SWE_GLB_INGR_IGMP_TRAP BIT(7) 162 # define LAN9303_SWE_GLB_INGR_IGMP_PORT(p) BIT(10 + p) 163 #define LAN9303_SWE_PORT_STATE 0x1843 164 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT2 (0) 165 # define LAN9303_SWE_PORT_STATE_LEARNING_PORT2 BIT(5) 166 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT2 BIT(4) 167 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT1 (0) 168 # define LAN9303_SWE_PORT_STATE_LEARNING_PORT1 BIT(3) 169 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT1 BIT(2) 170 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT0 (0) 171 # define LAN9303_SWE_PORT_STATE_LEARNING_PORT0 BIT(1) 172 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT0 BIT(0) 173 # define LAN9303_SWE_PORT_STATE_DISABLED_PORT0 (3) 174 #define LAN9303_SWE_PORT_MIRROR 0x1846 175 # define LAN9303_SWE_PORT_MIRROR_SNIFF_ALL BIT(8) 176 # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT2 BIT(7) 177 # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT1 BIT(6) 178 # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT0 BIT(5) 179 # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT2 BIT(4) 180 # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT1 BIT(3) 181 # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT0 BIT(2) 182 # define LAN9303_SWE_PORT_MIRROR_ENABLE_RX_MIRRORING BIT(1) 183 # define LAN9303_SWE_PORT_MIRROR_ENABLE_TX_MIRRORING BIT(0) 184 # define LAN9303_SWE_PORT_MIRROR_DISABLED 0 185 #define LAN9303_SWE_INGRESS_PORT_TYPE 0x1847 186 #define LAN9303_SWE_INGRESS_PORT_TYPE_VLAN 3 187 #define LAN9303_BM_CFG 0x1c00 188 #define LAN9303_BM_EGRSS_PORT_TYPE 0x1c0c 189 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT2 (BIT(17) | BIT(16)) 190 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT1 (BIT(9) | BIT(8)) 191 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0 (BIT(1) | BIT(0)) 192 193 #define LAN9303_SWITCH_PORT_REG(port, reg0) (0x400 * (port) + (reg0)) 194 195 /* the built-in PHYs are of type LAN911X */ 196 #define MII_LAN911X_SPECIAL_MODES 0x12 197 #define MII_LAN911X_SPECIAL_CONTROL_STATUS 0x1f 198 199 static const struct regmap_range lan9303_valid_regs[] = { 200 regmap_reg_range(0x14, 0x17), /* misc, interrupt */ 201 regmap_reg_range(0x19, 0x19), /* endian test */ 202 regmap_reg_range(0x1d, 0x1d), /* hardware config */ 203 regmap_reg_range(0x23, 0x24), /* general purpose timer */ 204 regmap_reg_range(0x27, 0x27), /* counter */ 205 regmap_reg_range(0x29, 0x2a), /* PMI index regs */ 206 regmap_reg_range(0x68, 0x6a), /* flow control */ 207 regmap_reg_range(0x6b, 0x6c), /* switch fabric indirect regs */ 208 regmap_reg_range(0x6d, 0x6f), /* misc */ 209 regmap_reg_range(0x70, 0x77), /* virtual phy */ 210 regmap_reg_range(0x78, 0x7a), /* GPIO */ 211 regmap_reg_range(0x7c, 0x7e), /* MAC & reset */ 212 regmap_reg_range(0x80, 0xb7), /* switch fabric direct regs (wr only) */ 213 }; 214 215 static const struct regmap_range lan9303_reserved_ranges[] = { 216 regmap_reg_range(0x00, 0x13), 217 regmap_reg_range(0x18, 0x18), 218 regmap_reg_range(0x1a, 0x1c), 219 regmap_reg_range(0x1e, 0x22), 220 regmap_reg_range(0x25, 0x26), 221 regmap_reg_range(0x28, 0x28), 222 regmap_reg_range(0x2b, 0x67), 223 regmap_reg_range(0x7b, 0x7b), 224 regmap_reg_range(0x7f, 0x7f), 225 regmap_reg_range(0xb8, 0xff), 226 }; 227 228 const struct regmap_access_table lan9303_register_set = { 229 .yes_ranges = lan9303_valid_regs, 230 .n_yes_ranges = ARRAY_SIZE(lan9303_valid_regs), 231 .no_ranges = lan9303_reserved_ranges, 232 .n_no_ranges = ARRAY_SIZE(lan9303_reserved_ranges), 233 }; 234 EXPORT_SYMBOL(lan9303_register_set); 235 236 /* Flow Control registers indexed by port number */ 237 static unsigned int flow_ctl_reg[] = { 238 LAN9303_MANUAL_FC_0, 239 LAN9303_MANUAL_FC_1, 240 LAN9303_MANUAL_FC_2 241 }; 242 243 static int lan9303_read(struct regmap *regmap, unsigned int offset, u32 *reg) 244 { 245 int ret, i; 246 247 /* we can lose arbitration for the I2C case, because the device 248 * tries to detect and read an external EEPROM after reset and acts as 249 * a master on the shared I2C bus itself. This conflicts with our 250 * attempts to access the device as a slave at the same moment. 251 */ 252 for (i = 0; i < 5; i++) { 253 ret = regmap_read(regmap, offset, reg); 254 if (!ret) 255 return 0; 256 if (ret != -EAGAIN) 257 break; 258 msleep(500); 259 } 260 261 return -EIO; 262 } 263 264 static int lan9303_read_wait(struct lan9303 *chip, int offset, u32 mask) 265 { 266 int i; 267 268 for (i = 0; i < 25; i++) { 269 u32 reg; 270 int ret; 271 272 ret = lan9303_read(chip->regmap, offset, ®); 273 if (ret) { 274 dev_err(chip->dev, "%s failed to read offset %d: %d\n", 275 __func__, offset, ret); 276 return ret; 277 } 278 if (!(reg & mask)) 279 return 0; 280 usleep_range(1000, 2000); 281 } 282 283 return -ETIMEDOUT; 284 } 285 286 static int lan9303_virt_phy_reg_read(struct lan9303 *chip, int regnum) 287 { 288 int ret; 289 u32 val; 290 291 if (regnum > MII_EXPANSION) 292 return -EINVAL; 293 294 ret = lan9303_read(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, &val); 295 if (ret) 296 return ret; 297 298 return val & 0xffff; 299 } 300 301 static int lan9303_virt_phy_reg_write(struct lan9303 *chip, int regnum, u16 val) 302 { 303 if (regnum > MII_EXPANSION) 304 return -EINVAL; 305 306 return regmap_write(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, val); 307 } 308 309 static int lan9303_indirect_phy_wait_for_completion(struct lan9303 *chip) 310 { 311 return lan9303_read_wait(chip, LAN9303_PMI_ACCESS, 312 LAN9303_PMI_ACCESS_MII_BUSY); 313 } 314 315 static int lan9303_indirect_phy_read(struct lan9303 *chip, int addr, int regnum) 316 { 317 int ret; 318 u32 val; 319 320 val = LAN9303_PMI_ACCESS_PHY_ADDR(addr); 321 val |= LAN9303_PMI_ACCESS_MIIRINDA(regnum); 322 323 mutex_lock(&chip->indirect_mutex); 324 325 ret = lan9303_indirect_phy_wait_for_completion(chip); 326 if (ret) 327 goto on_error; 328 329 /* start the MII read cycle */ 330 ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, val); 331 if (ret) 332 goto on_error; 333 334 ret = lan9303_indirect_phy_wait_for_completion(chip); 335 if (ret) 336 goto on_error; 337 338 /* read the result of this operation */ 339 ret = lan9303_read(chip->regmap, LAN9303_PMI_DATA, &val); 340 if (ret) 341 goto on_error; 342 343 mutex_unlock(&chip->indirect_mutex); 344 345 return val & 0xffff; 346 347 on_error: 348 mutex_unlock(&chip->indirect_mutex); 349 return ret; 350 } 351 352 static int lan9303_indirect_phy_write(struct lan9303 *chip, int addr, 353 int regnum, u16 val) 354 { 355 int ret; 356 u32 reg; 357 358 reg = LAN9303_PMI_ACCESS_PHY_ADDR(addr); 359 reg |= LAN9303_PMI_ACCESS_MIIRINDA(regnum); 360 reg |= LAN9303_PMI_ACCESS_MII_WRITE; 361 362 mutex_lock(&chip->indirect_mutex); 363 364 ret = lan9303_indirect_phy_wait_for_completion(chip); 365 if (ret) 366 goto on_error; 367 368 /* write the data first... */ 369 ret = regmap_write(chip->regmap, LAN9303_PMI_DATA, val); 370 if (ret) 371 goto on_error; 372 373 /* ...then start the MII write cycle */ 374 ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, reg); 375 376 on_error: 377 mutex_unlock(&chip->indirect_mutex); 378 return ret; 379 } 380 381 const struct lan9303_phy_ops lan9303_indirect_phy_ops = { 382 .phy_read = lan9303_indirect_phy_read, 383 .phy_write = lan9303_indirect_phy_write, 384 }; 385 EXPORT_SYMBOL_GPL(lan9303_indirect_phy_ops); 386 387 static int lan9303_switch_wait_for_completion(struct lan9303 *chip) 388 { 389 return lan9303_read_wait(chip, LAN9303_SWITCH_CSR_CMD, 390 LAN9303_SWITCH_CSR_CMD_BUSY); 391 } 392 393 static int lan9303_write_switch_reg(struct lan9303 *chip, u16 regnum, u32 val) 394 { 395 u32 reg; 396 int ret; 397 398 reg = regnum; 399 reg |= LAN9303_SWITCH_CSR_CMD_LANES; 400 reg |= LAN9303_SWITCH_CSR_CMD_BUSY; 401 402 mutex_lock(&chip->indirect_mutex); 403 404 ret = lan9303_switch_wait_for_completion(chip); 405 if (ret) 406 goto on_error; 407 408 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_DATA, val); 409 if (ret) { 410 dev_err(chip->dev, "Failed to write csr data reg: %d\n", ret); 411 goto on_error; 412 } 413 414 /* trigger write */ 415 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg); 416 if (ret) 417 dev_err(chip->dev, "Failed to write csr command reg: %d\n", 418 ret); 419 420 on_error: 421 mutex_unlock(&chip->indirect_mutex); 422 return ret; 423 } 424 425 static int lan9303_read_switch_reg(struct lan9303 *chip, u16 regnum, u32 *val) 426 { 427 u32 reg; 428 int ret; 429 430 reg = regnum; 431 reg |= LAN9303_SWITCH_CSR_CMD_LANES; 432 reg |= LAN9303_SWITCH_CSR_CMD_RW; 433 reg |= LAN9303_SWITCH_CSR_CMD_BUSY; 434 435 mutex_lock(&chip->indirect_mutex); 436 437 ret = lan9303_switch_wait_for_completion(chip); 438 if (ret) 439 goto on_error; 440 441 /* trigger read */ 442 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg); 443 if (ret) { 444 dev_err(chip->dev, "Failed to write csr command reg: %d\n", 445 ret); 446 goto on_error; 447 } 448 449 ret = lan9303_switch_wait_for_completion(chip); 450 if (ret) 451 goto on_error; 452 453 ret = lan9303_read(chip->regmap, LAN9303_SWITCH_CSR_DATA, val); 454 if (ret) 455 dev_err(chip->dev, "Failed to read csr data reg: %d\n", ret); 456 on_error: 457 mutex_unlock(&chip->indirect_mutex); 458 return ret; 459 } 460 461 static int lan9303_write_switch_reg_mask(struct lan9303 *chip, u16 regnum, 462 u32 val, u32 mask) 463 { 464 int ret; 465 u32 reg; 466 467 ret = lan9303_read_switch_reg(chip, regnum, ®); 468 if (ret) 469 return ret; 470 471 reg = (reg & ~mask) | val; 472 473 return lan9303_write_switch_reg(chip, regnum, reg); 474 } 475 476 static int lan9303_write_switch_port(struct lan9303 *chip, int port, 477 u16 regnum, u32 val) 478 { 479 return lan9303_write_switch_reg( 480 chip, LAN9303_SWITCH_PORT_REG(port, regnum), val); 481 } 482 483 static int lan9303_read_switch_port(struct lan9303 *chip, int port, 484 u16 regnum, u32 *val) 485 { 486 return lan9303_read_switch_reg( 487 chip, LAN9303_SWITCH_PORT_REG(port, regnum), val); 488 } 489 490 static int lan9303_detect_phy_setup(struct lan9303 *chip) 491 { 492 int reg; 493 494 /* Calculate chip->phy_addr_base: 495 * Depending on the 'phy_addr_sel_strap' setting, the three phys are 496 * using IDs 0-1-2 or IDs 1-2-3. We cannot read back the 497 * 'phy_addr_sel_strap' setting directly, so we need a test, which 498 * configuration is active: 499 * Special reg 18 of phy 3 reads as 0x0000, if 'phy_addr_sel_strap' is 0 500 * and the IDs are 0-1-2, else it contains something different from 501 * 0x0000, which means 'phy_addr_sel_strap' is 1 and the IDs are 1-2-3. 502 * 0xffff is returned on MDIO read with no response. 503 */ 504 reg = chip->ops->phy_read(chip, 3, MII_LAN911X_SPECIAL_MODES); 505 if (reg < 0) { 506 dev_err(chip->dev, "Failed to detect phy config: %d\n", reg); 507 return reg; 508 } 509 510 chip->phy_addr_base = reg != 0 && reg != 0xffff; 511 512 dev_dbg(chip->dev, "Phy setup '%s' detected\n", 513 chip->phy_addr_base ? "1-2-3" : "0-1-2"); 514 515 return 0; 516 } 517 518 /* Map ALR-port bits to port bitmap, and back */ 519 static const int alrport_2_portmap[] = {1, 2, 4, 0, 3, 5, 6, 7 }; 520 static const int portmap_2_alrport[] = {3, 0, 1, 4, 2, 5, 6, 7 }; 521 522 /* Return pointer to first free ALR cache entry, return NULL if none */ 523 static struct lan9303_alr_cache_entry * 524 lan9303_alr_cache_find_free(struct lan9303 *chip) 525 { 526 int i; 527 struct lan9303_alr_cache_entry *entr = chip->alr_cache; 528 529 for (i = 0; i < LAN9303_NUM_ALR_RECORDS; i++, entr++) 530 if (entr->port_map == 0) 531 return entr; 532 533 return NULL; 534 } 535 536 /* Return pointer to ALR cache entry matching MAC address */ 537 static struct lan9303_alr_cache_entry * 538 lan9303_alr_cache_find_mac(struct lan9303 *chip, const u8 *mac_addr) 539 { 540 int i; 541 struct lan9303_alr_cache_entry *entr = chip->alr_cache; 542 543 BUILD_BUG_ON_MSG(sizeof(struct lan9303_alr_cache_entry) & 1, 544 "ether_addr_equal require u16 alignment"); 545 546 for (i = 0; i < LAN9303_NUM_ALR_RECORDS; i++, entr++) 547 if (ether_addr_equal(entr->mac_addr, mac_addr)) 548 return entr; 549 550 return NULL; 551 } 552 553 static int lan9303_csr_reg_wait(struct lan9303 *chip, int regno, u32 mask) 554 { 555 int i; 556 557 for (i = 0; i < 25; i++) { 558 u32 reg; 559 560 lan9303_read_switch_reg(chip, regno, ®); 561 if (!(reg & mask)) 562 return 0; 563 usleep_range(1000, 2000); 564 } 565 566 return -ETIMEDOUT; 567 } 568 569 static int lan9303_alr_make_entry_raw(struct lan9303 *chip, u32 dat0, u32 dat1) 570 { 571 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_WR_DAT_0, dat0); 572 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_WR_DAT_1, dat1); 573 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 574 LAN9303_ALR_CMD_MAKE_ENTRY); 575 lan9303_csr_reg_wait(chip, LAN9303_SWE_ALR_CMD_STS, ALR_STS_MAKE_PEND); 576 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0); 577 578 return 0; 579 } 580 581 typedef int alr_loop_cb_t(struct lan9303 *chip, u32 dat0, u32 dat1, 582 int portmap, void *ctx); 583 584 static int lan9303_alr_loop(struct lan9303 *chip, alr_loop_cb_t *cb, void *ctx) 585 { 586 int ret = 0, i; 587 588 mutex_lock(&chip->alr_mutex); 589 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 590 LAN9303_ALR_CMD_GET_FIRST); 591 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0); 592 593 for (i = 1; i < LAN9303_NUM_ALR_RECORDS; i++) { 594 u32 dat0, dat1; 595 int alrport, portmap; 596 597 lan9303_read_switch_reg(chip, LAN9303_SWE_ALR_RD_DAT_0, &dat0); 598 lan9303_read_switch_reg(chip, LAN9303_SWE_ALR_RD_DAT_1, &dat1); 599 if (dat1 & LAN9303_ALR_DAT1_END_OF_TABL) 600 break; 601 602 alrport = (dat1 & LAN9303_ALR_DAT1_PORT_MASK) >> 603 LAN9303_ALR_DAT1_PORT_BITOFFS; 604 portmap = alrport_2_portmap[alrport]; 605 606 ret = cb(chip, dat0, dat1, portmap, ctx); 607 if (ret) 608 break; 609 610 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 611 LAN9303_ALR_CMD_GET_NEXT); 612 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0); 613 } 614 mutex_unlock(&chip->alr_mutex); 615 616 return ret; 617 } 618 619 static void alr_reg_to_mac(u32 dat0, u32 dat1, u8 mac[6]) 620 { 621 mac[0] = (dat0 >> 0) & 0xff; 622 mac[1] = (dat0 >> 8) & 0xff; 623 mac[2] = (dat0 >> 16) & 0xff; 624 mac[3] = (dat0 >> 24) & 0xff; 625 mac[4] = (dat1 >> 0) & 0xff; 626 mac[5] = (dat1 >> 8) & 0xff; 627 } 628 629 struct del_port_learned_ctx { 630 int port; 631 }; 632 633 /* Clear learned (non-static) entry on given port */ 634 static int alr_loop_cb_del_port_learned(struct lan9303 *chip, u32 dat0, 635 u32 dat1, int portmap, void *ctx) 636 { 637 struct del_port_learned_ctx *del_ctx = ctx; 638 int port = del_ctx->port; 639 640 if (((BIT(port) & portmap) == 0) || (dat1 & LAN9303_ALR_DAT1_STATIC)) 641 return 0; 642 643 /* learned entries has only one port, we can just delete */ 644 dat1 &= ~LAN9303_ALR_DAT1_VALID; /* delete entry */ 645 lan9303_alr_make_entry_raw(chip, dat0, dat1); 646 647 return 0; 648 } 649 650 struct port_fdb_dump_ctx { 651 int port; 652 void *data; 653 dsa_fdb_dump_cb_t *cb; 654 }; 655 656 static int alr_loop_cb_fdb_port_dump(struct lan9303 *chip, u32 dat0, 657 u32 dat1, int portmap, void *ctx) 658 { 659 struct port_fdb_dump_ctx *dump_ctx = ctx; 660 u8 mac[ETH_ALEN]; 661 bool is_static; 662 663 if ((BIT(dump_ctx->port) & portmap) == 0) 664 return 0; 665 666 alr_reg_to_mac(dat0, dat1, mac); 667 is_static = !!(dat1 & LAN9303_ALR_DAT1_STATIC); 668 return dump_ctx->cb(mac, 0, is_static, dump_ctx->data); 669 } 670 671 /* Set a static ALR entry. Delete entry if port_map is zero */ 672 static void lan9303_alr_set_entry(struct lan9303 *chip, const u8 *mac, 673 u8 port_map, bool stp_override) 674 { 675 u32 dat0, dat1, alr_port; 676 677 dev_dbg(chip->dev, "%s(%pM, %d)\n", __func__, mac, port_map); 678 dat1 = LAN9303_ALR_DAT1_STATIC; 679 if (port_map) 680 dat1 |= LAN9303_ALR_DAT1_VALID; 681 /* otherwise no ports: delete entry */ 682 if (stp_override) 683 dat1 |= LAN9303_ALR_DAT1_AGE_OVERRID; 684 685 alr_port = portmap_2_alrport[port_map & 7]; 686 dat1 &= ~LAN9303_ALR_DAT1_PORT_MASK; 687 dat1 |= alr_port << LAN9303_ALR_DAT1_PORT_BITOFFS; 688 689 dat0 = 0; 690 dat0 |= (mac[0] << 0); 691 dat0 |= (mac[1] << 8); 692 dat0 |= (mac[2] << 16); 693 dat0 |= (mac[3] << 24); 694 695 dat1 |= (mac[4] << 0); 696 dat1 |= (mac[5] << 8); 697 698 lan9303_alr_make_entry_raw(chip, dat0, dat1); 699 } 700 701 /* Add port to static ALR entry, create new static entry if needed */ 702 static int lan9303_alr_add_port(struct lan9303 *chip, const u8 *mac, int port, 703 bool stp_override) 704 { 705 struct lan9303_alr_cache_entry *entr; 706 707 mutex_lock(&chip->alr_mutex); 708 entr = lan9303_alr_cache_find_mac(chip, mac); 709 if (!entr) { /*New entry */ 710 entr = lan9303_alr_cache_find_free(chip); 711 if (!entr) { 712 mutex_unlock(&chip->alr_mutex); 713 return -ENOSPC; 714 } 715 ether_addr_copy(entr->mac_addr, mac); 716 } 717 entr->port_map |= BIT(port); 718 entr->stp_override = stp_override; 719 lan9303_alr_set_entry(chip, mac, entr->port_map, stp_override); 720 mutex_unlock(&chip->alr_mutex); 721 722 return 0; 723 } 724 725 /* Delete static port from ALR entry, delete entry if last port */ 726 static int lan9303_alr_del_port(struct lan9303 *chip, const u8 *mac, int port) 727 { 728 struct lan9303_alr_cache_entry *entr; 729 730 mutex_lock(&chip->alr_mutex); 731 entr = lan9303_alr_cache_find_mac(chip, mac); 732 if (!entr) 733 goto out; /* no static entry found */ 734 735 entr->port_map &= ~BIT(port); 736 if (entr->port_map == 0) /* zero means its free again */ 737 eth_zero_addr(entr->mac_addr); 738 lan9303_alr_set_entry(chip, mac, entr->port_map, entr->stp_override); 739 740 out: 741 mutex_unlock(&chip->alr_mutex); 742 return 0; 743 } 744 745 static int lan9303_disable_processing_port(struct lan9303 *chip, 746 unsigned int port) 747 { 748 int ret; 749 750 /* disable RX, but keep register reset default values else */ 751 ret = lan9303_write_switch_port(chip, port, LAN9303_MAC_RX_CFG_0, 752 LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES); 753 if (ret) 754 return ret; 755 756 /* disable TX, but keep register reset default values else */ 757 return lan9303_write_switch_port(chip, port, LAN9303_MAC_TX_CFG_0, 758 LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT | 759 LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE); 760 } 761 762 static int lan9303_enable_processing_port(struct lan9303 *chip, 763 unsigned int port) 764 { 765 int ret; 766 767 /* enable RX and keep register reset default values else */ 768 ret = lan9303_write_switch_port(chip, port, LAN9303_MAC_RX_CFG_0, 769 LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES | 770 LAN9303_MAC_RX_CFG_X_RX_ENABLE); 771 if (ret) 772 return ret; 773 774 /* enable TX and keep register reset default values else */ 775 return lan9303_write_switch_port(chip, port, LAN9303_MAC_TX_CFG_0, 776 LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT | 777 LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE | 778 LAN9303_MAC_TX_CFG_X_TX_ENABLE); 779 } 780 781 /* forward special tagged packets from port 0 to port 1 *or* port 2 */ 782 static int lan9303_setup_tagging(struct lan9303 *chip) 783 { 784 int ret; 785 u32 val; 786 /* enable defining the destination port via special VLAN tagging 787 * for port 0 788 */ 789 ret = lan9303_write_switch_reg(chip, LAN9303_SWE_INGRESS_PORT_TYPE, 790 LAN9303_SWE_INGRESS_PORT_TYPE_VLAN); 791 if (ret) 792 return ret; 793 794 /* tag incoming packets at port 1 and 2 on their way to port 0 to be 795 * able to discover their source port 796 */ 797 val = LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0; 798 return lan9303_write_switch_reg(chip, LAN9303_BM_EGRSS_PORT_TYPE, val); 799 } 800 801 /* We want a special working switch: 802 * - do not forward packets between port 1 and 2 803 * - forward everything from port 1 to port 0 804 * - forward everything from port 2 to port 0 805 */ 806 static int lan9303_separate_ports(struct lan9303 *chip) 807 { 808 int ret; 809 810 lan9303_alr_del_port(chip, eth_stp_addr, 0); 811 ret = lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_MIRROR, 812 LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT0 | 813 LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT1 | 814 LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT2 | 815 LAN9303_SWE_PORT_MIRROR_ENABLE_RX_MIRRORING | 816 LAN9303_SWE_PORT_MIRROR_SNIFF_ALL); 817 if (ret) 818 return ret; 819 820 /* prevent port 1 and 2 from forwarding packets by their own */ 821 return lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE, 822 LAN9303_SWE_PORT_STATE_FORWARDING_PORT0 | 823 LAN9303_SWE_PORT_STATE_BLOCKING_PORT1 | 824 LAN9303_SWE_PORT_STATE_BLOCKING_PORT2); 825 } 826 827 static void lan9303_bridge_ports(struct lan9303 *chip) 828 { 829 /* ports bridged: remove mirroring */ 830 lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_MIRROR, 831 LAN9303_SWE_PORT_MIRROR_DISABLED); 832 833 lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE, 834 chip->swe_port_state); 835 lan9303_alr_add_port(chip, eth_stp_addr, 0, true); 836 } 837 838 static void lan9303_handle_reset(struct lan9303 *chip) 839 { 840 if (!chip->reset_gpio) 841 return; 842 843 gpiod_set_value_cansleep(chip->reset_gpio, 1); 844 845 if (chip->reset_duration != 0) 846 msleep(chip->reset_duration); 847 848 /* release (deassert) reset and activate the device */ 849 gpiod_set_value_cansleep(chip->reset_gpio, 0); 850 } 851 852 /* stop processing packets for all ports */ 853 static int lan9303_disable_processing(struct lan9303 *chip) 854 { 855 int p; 856 857 for (p = 1; p < LAN9303_NUM_PORTS; p++) { 858 int ret = lan9303_disable_processing_port(chip, p); 859 860 if (ret) 861 return ret; 862 } 863 864 return 0; 865 } 866 867 static int lan9303_check_device(struct lan9303 *chip) 868 { 869 int ret; 870 int err; 871 u32 reg; 872 873 /* In I2C-managed configurations this polling loop will clash with 874 * switch's reading of EEPROM right after reset and this behaviour is 875 * not configurable. While lan9303_read() already has quite long retry 876 * timeout, seems not all cases are being detected as arbitration error. 877 * 878 * According to datasheet, EEPROM loader has 30ms timeout (in case of 879 * missing EEPROM). 880 * 881 * Loading of the largest supported EEPROM is expected to take at least 882 * 5.9s. 883 */ 884 err = read_poll_timeout(lan9303_read, ret, 885 !ret && reg & LAN9303_HW_CFG_READY, 886 20000, 6000000, false, 887 chip->regmap, LAN9303_HW_CFG, ®); 888 if (ret) { 889 dev_err(chip->dev, "failed to read HW_CFG reg: %pe\n", 890 ERR_PTR(ret)); 891 return ret; 892 } 893 if (err) { 894 dev_err(chip->dev, "HW_CFG not ready: 0x%08x\n", reg); 895 return err; 896 } 897 898 ret = lan9303_read(chip->regmap, LAN9303_CHIP_REV, ®); 899 if (ret) { 900 dev_err(chip->dev, "failed to read chip revision register: %d\n", 901 ret); 902 return ret; 903 } 904 905 if (((reg >> 16) != LAN9303_CHIP_ID) && 906 ((reg >> 16) != LAN9354_CHIP_ID)) { 907 dev_err(chip->dev, "unexpected device found: LAN%4.4X\n", 908 reg >> 16); 909 return -ENODEV; 910 } 911 912 /* The default state of the LAN9303 device is to forward packets between 913 * all ports (if not configured differently by an external EEPROM). 914 * The initial state of a DSA device must be forwarding packets only 915 * between the external and the internal ports and no forwarding 916 * between the external ports. In preparation we stop packet handling 917 * at all for now until the LAN9303 device is re-programmed accordingly. 918 */ 919 ret = lan9303_disable_processing(chip); 920 if (ret) 921 dev_warn(chip->dev, "failed to disable switching %d\n", ret); 922 923 dev_info(chip->dev, "Found LAN%4.4X rev. %u\n", (reg >> 16), reg & 0xffff); 924 925 ret = lan9303_detect_phy_setup(chip); 926 if (ret) { 927 dev_err(chip->dev, 928 "failed to discover phy bootstrap setup: %d\n", ret); 929 return ret; 930 } 931 932 return 0; 933 } 934 935 /* ---------------------------- DSA -----------------------------------*/ 936 937 static enum dsa_tag_protocol lan9303_get_tag_protocol(struct dsa_switch *ds, 938 int port, 939 enum dsa_tag_protocol mp) 940 { 941 return DSA_TAG_PROTO_LAN9303; 942 } 943 944 static int lan9303_setup(struct dsa_switch *ds) 945 { 946 struct lan9303 *chip = ds->priv; 947 int ret; 948 u32 reg; 949 950 /* Make sure that port 0 is the cpu port */ 951 if (!dsa_is_cpu_port(ds, 0)) { 952 dev_err(chip->dev, "port 0 is not the CPU port\n"); 953 return -EINVAL; 954 } 955 956 /* Virtual Phy: Remove Turbo 200Mbit mode */ 957 ret = lan9303_read(chip->regmap, LAN9303_VIRT_SPECIAL_CTRL, ®); 958 if (ret) 959 return (ret); 960 961 /* Clear the TURBO Mode bit if it was set. */ 962 if (reg & LAN9303_VIRT_SPECIAL_TURBO) { 963 reg &= ~LAN9303_VIRT_SPECIAL_TURBO; 964 regmap_write(chip->regmap, LAN9303_VIRT_SPECIAL_CTRL, reg); 965 } 966 967 ret = lan9303_setup_tagging(chip); 968 if (ret) 969 dev_err(chip->dev, "failed to setup port tagging %d\n", ret); 970 971 ret = lan9303_separate_ports(chip); 972 if (ret) 973 dev_err(chip->dev, "failed to separate ports %d\n", ret); 974 975 ret = lan9303_enable_processing_port(chip, 0); 976 if (ret) 977 dev_err(chip->dev, "failed to re-enable switching %d\n", ret); 978 979 /* Trap IGMP to port 0 */ 980 ret = lan9303_write_switch_reg_mask(chip, LAN9303_SWE_GLB_INGRESS_CFG, 981 LAN9303_SWE_GLB_INGR_IGMP_TRAP | 982 LAN9303_SWE_GLB_INGR_IGMP_PORT(0), 983 LAN9303_SWE_GLB_INGR_IGMP_PORT(1) | 984 LAN9303_SWE_GLB_INGR_IGMP_PORT(2)); 985 if (ret) 986 dev_err(chip->dev, "failed to setup IGMP trap %d\n", ret); 987 988 return 0; 989 } 990 991 struct lan9303_mib_desc { 992 unsigned int offset; /* offset of first MAC */ 993 const char *name; 994 }; 995 996 static const struct lan9303_mib_desc lan9303_mib[] = { 997 { .offset = LAN9303_MAC_RX_BRDCST_CNT_0, .name = "RxBroad", }, 998 { .offset = LAN9303_MAC_RX_PAUSE_CNT_0, .name = "RxPause", }, 999 { .offset = LAN9303_MAC_RX_MULCST_CNT_0, .name = "RxMulti", }, 1000 { .offset = LAN9303_MAC_RX_PKTOK_CNT_0, .name = "RxOk", }, 1001 { .offset = LAN9303_MAC_RX_CRCERR_CNT_0, .name = "RxCrcErr", }, 1002 { .offset = LAN9303_MAC_RX_ALIGN_CNT_0, .name = "RxAlignErr", }, 1003 { .offset = LAN9303_MAC_RX_JABB_CNT_0, .name = "RxJabber", }, 1004 { .offset = LAN9303_MAC_RX_FRAG_CNT_0, .name = "RxFragment", }, 1005 { .offset = LAN9303_MAC_RX_64_CNT_0, .name = "Rx64Byte", }, 1006 { .offset = LAN9303_MAC_RX_127_CNT_0, .name = "Rx128Byte", }, 1007 { .offset = LAN9303_MAC_RX_255_CNT_0, .name = "Rx256Byte", }, 1008 { .offset = LAN9303_MAC_RX_511_CNT_0, .name = "Rx512Byte", }, 1009 { .offset = LAN9303_MAC_RX_1023_CNT_0, .name = "Rx1024Byte", }, 1010 { .offset = LAN9303_MAC_RX_MAX_CNT_0, .name = "RxMaxByte", }, 1011 { .offset = LAN9303_MAC_RX_PKTLEN_CNT_0, .name = "RxByteCnt", }, 1012 { .offset = LAN9303_MAC_RX_SYMBL_CNT_0, .name = "RxSymbolCnt", }, 1013 { .offset = LAN9303_MAC_RX_CTLFRM_CNT_0, .name = "RxCfs", }, 1014 { .offset = LAN9303_MAC_RX_OVRSZE_CNT_0, .name = "RxOverFlow", }, 1015 { .offset = LAN9303_MAC_TX_UNDSZE_CNT_0, .name = "TxShort", }, 1016 { .offset = LAN9303_MAC_TX_BRDCST_CNT_0, .name = "TxBroad", }, 1017 { .offset = LAN9303_MAC_TX_PAUSE_CNT_0, .name = "TxPause", }, 1018 { .offset = LAN9303_MAC_TX_MULCST_CNT_0, .name = "TxMulti", }, 1019 { .offset = LAN9303_MAC_RX_UNDSZE_CNT_0, .name = "RxShort", }, 1020 { .offset = LAN9303_MAC_TX_64_CNT_0, .name = "Tx64Byte", }, 1021 { .offset = LAN9303_MAC_TX_127_CNT_0, .name = "Tx128Byte", }, 1022 { .offset = LAN9303_MAC_TX_255_CNT_0, .name = "Tx256Byte", }, 1023 { .offset = LAN9303_MAC_TX_511_CNT_0, .name = "Tx512Byte", }, 1024 { .offset = LAN9303_MAC_TX_1023_CNT_0, .name = "Tx1024Byte", }, 1025 { .offset = LAN9303_MAC_TX_MAX_CNT_0, .name = "TxMaxByte", }, 1026 { .offset = LAN9303_MAC_TX_PKTLEN_CNT_0, .name = "TxByteCnt", }, 1027 { .offset = LAN9303_MAC_TX_PKTOK_CNT_0, .name = "TxOk", }, 1028 { .offset = LAN9303_MAC_TX_TOTALCOL_CNT_0, .name = "TxCollision", }, 1029 { .offset = LAN9303_MAC_TX_MULTICOL_CNT_0, .name = "TxMultiCol", }, 1030 { .offset = LAN9303_MAC_TX_SNGLECOL_CNT_0, .name = "TxSingleCol", }, 1031 { .offset = LAN9303_MAC_TX_EXCOL_CNT_0, .name = "TxExcCol", }, 1032 { .offset = LAN9303_MAC_TX_DEFER_CNT_0, .name = "TxDefer", }, 1033 { .offset = LAN9303_MAC_TX_LATECOL_0, .name = "TxLateCol", }, 1034 }; 1035 1036 static void lan9303_get_strings(struct dsa_switch *ds, int port, 1037 u32 stringset, uint8_t *data) 1038 { 1039 u8 *buf = data; 1040 unsigned int u; 1041 1042 if (stringset != ETH_SS_STATS) 1043 return; 1044 1045 for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++) 1046 ethtool_puts(&buf, lan9303_mib[u].name); 1047 } 1048 1049 static void lan9303_get_ethtool_stats(struct dsa_switch *ds, int port, 1050 uint64_t *data) 1051 { 1052 struct lan9303 *chip = ds->priv; 1053 unsigned int u; 1054 1055 for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++) { 1056 u32 reg; 1057 int ret; 1058 1059 ret = lan9303_read_switch_port( 1060 chip, port, lan9303_mib[u].offset, ®); 1061 1062 if (ret) { 1063 dev_warn(chip->dev, "Reading status port %d reg %u failed\n", 1064 port, lan9303_mib[u].offset); 1065 reg = 0; 1066 } 1067 data[u] = reg; 1068 } 1069 } 1070 1071 static int lan9303_get_sset_count(struct dsa_switch *ds, int port, int sset) 1072 { 1073 if (sset != ETH_SS_STATS) 1074 return 0; 1075 1076 return ARRAY_SIZE(lan9303_mib); 1077 } 1078 1079 static int lan9303_phy_read(struct dsa_switch *ds, int port, int regnum) 1080 { 1081 struct lan9303 *chip = ds->priv; 1082 int phy_base = chip->phy_addr_base; 1083 1084 if (port == 0) 1085 return lan9303_virt_phy_reg_read(chip, regnum); 1086 if (port > 2) 1087 return -ENODEV; 1088 1089 return chip->ops->phy_read(chip, phy_base + port, regnum); 1090 } 1091 1092 static int lan9303_phy_write(struct dsa_switch *ds, int port, int regnum, 1093 u16 val) 1094 { 1095 struct lan9303 *chip = ds->priv; 1096 int phy_base = chip->phy_addr_base; 1097 1098 if (port == 0) 1099 return lan9303_virt_phy_reg_write(chip, regnum, val); 1100 if (port > 2) 1101 return -ENODEV; 1102 1103 return chip->ops->phy_write(chip, phy_base + port, regnum, val); 1104 } 1105 1106 static int lan9303_port_enable(struct dsa_switch *ds, int port, 1107 struct phy_device *phy) 1108 { 1109 struct dsa_port *dp = dsa_to_port(ds, port); 1110 struct lan9303 *chip = ds->priv; 1111 1112 if (!dsa_port_is_user(dp)) 1113 return 0; 1114 1115 vlan_vid_add(dsa_port_to_conduit(dp), htons(ETH_P_8021Q), port); 1116 1117 return lan9303_enable_processing_port(chip, port); 1118 } 1119 1120 static void lan9303_port_disable(struct dsa_switch *ds, int port) 1121 { 1122 struct dsa_port *dp = dsa_to_port(ds, port); 1123 struct lan9303 *chip = ds->priv; 1124 1125 if (!dsa_port_is_user(dp)) 1126 return; 1127 1128 vlan_vid_del(dsa_port_to_conduit(dp), htons(ETH_P_8021Q), port); 1129 1130 lan9303_disable_processing_port(chip, port); 1131 lan9303_phy_write(ds, port, MII_BMCR, BMCR_PDOWN); 1132 } 1133 1134 static int lan9303_port_bridge_join(struct dsa_switch *ds, int port, 1135 struct dsa_bridge bridge, 1136 bool *tx_fwd_offload, 1137 struct netlink_ext_ack *extack) 1138 { 1139 struct lan9303 *chip = ds->priv; 1140 1141 dev_dbg(chip->dev, "%s(port %d)\n", __func__, port); 1142 if (dsa_port_bridge_same(dsa_to_port(ds, 1), dsa_to_port(ds, 2))) { 1143 lan9303_bridge_ports(chip); 1144 chip->is_bridged = true; /* unleash stp_state_set() */ 1145 } 1146 1147 return 0; 1148 } 1149 1150 static void lan9303_port_bridge_leave(struct dsa_switch *ds, int port, 1151 struct dsa_bridge bridge) 1152 { 1153 struct lan9303 *chip = ds->priv; 1154 1155 dev_dbg(chip->dev, "%s(port %d)\n", __func__, port); 1156 if (chip->is_bridged) { 1157 lan9303_separate_ports(chip); 1158 chip->is_bridged = false; 1159 } 1160 } 1161 1162 static void lan9303_port_stp_state_set(struct dsa_switch *ds, int port, 1163 u8 state) 1164 { 1165 int portmask, portstate; 1166 struct lan9303 *chip = ds->priv; 1167 1168 dev_dbg(chip->dev, "%s(port %d, state %d)\n", 1169 __func__, port, state); 1170 1171 switch (state) { 1172 case BR_STATE_DISABLED: 1173 portstate = LAN9303_SWE_PORT_STATE_DISABLED_PORT0; 1174 break; 1175 case BR_STATE_BLOCKING: 1176 case BR_STATE_LISTENING: 1177 portstate = LAN9303_SWE_PORT_STATE_BLOCKING_PORT0; 1178 break; 1179 case BR_STATE_LEARNING: 1180 portstate = LAN9303_SWE_PORT_STATE_LEARNING_PORT0; 1181 break; 1182 case BR_STATE_FORWARDING: 1183 portstate = LAN9303_SWE_PORT_STATE_FORWARDING_PORT0; 1184 break; 1185 default: 1186 portstate = LAN9303_SWE_PORT_STATE_DISABLED_PORT0; 1187 dev_err(chip->dev, "unknown stp state: port %d, state %d\n", 1188 port, state); 1189 } 1190 1191 portmask = 0x3 << (port * 2); 1192 portstate <<= (port * 2); 1193 1194 chip->swe_port_state = (chip->swe_port_state & ~portmask) | portstate; 1195 1196 if (chip->is_bridged) 1197 lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE, 1198 chip->swe_port_state); 1199 /* else: touching SWE_PORT_STATE would break port separation */ 1200 } 1201 1202 static void lan9303_port_fast_age(struct dsa_switch *ds, int port) 1203 { 1204 struct lan9303 *chip = ds->priv; 1205 struct del_port_learned_ctx del_ctx = { 1206 .port = port, 1207 }; 1208 1209 dev_dbg(chip->dev, "%s(%d)\n", __func__, port); 1210 lan9303_alr_loop(chip, alr_loop_cb_del_port_learned, &del_ctx); 1211 } 1212 1213 static int lan9303_port_fdb_add(struct dsa_switch *ds, int port, 1214 const unsigned char *addr, u16 vid, 1215 struct dsa_db db) 1216 { 1217 struct lan9303 *chip = ds->priv; 1218 1219 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, addr, vid); 1220 1221 return lan9303_alr_add_port(chip, addr, port, false); 1222 } 1223 1224 static int lan9303_port_fdb_del(struct dsa_switch *ds, int port, 1225 const unsigned char *addr, u16 vid, 1226 struct dsa_db db) 1227 { 1228 struct lan9303 *chip = ds->priv; 1229 1230 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, addr, vid); 1231 lan9303_alr_del_port(chip, addr, port); 1232 1233 return 0; 1234 } 1235 1236 static int lan9303_port_fdb_dump(struct dsa_switch *ds, int port, 1237 dsa_fdb_dump_cb_t *cb, void *data) 1238 { 1239 struct lan9303 *chip = ds->priv; 1240 struct port_fdb_dump_ctx dump_ctx = { 1241 .port = port, 1242 .data = data, 1243 .cb = cb, 1244 }; 1245 1246 dev_dbg(chip->dev, "%s(%d)\n", __func__, port); 1247 return lan9303_alr_loop(chip, alr_loop_cb_fdb_port_dump, &dump_ctx); 1248 } 1249 1250 static int lan9303_port_mdb_prepare(struct dsa_switch *ds, int port, 1251 const struct switchdev_obj_port_mdb *mdb) 1252 { 1253 struct lan9303 *chip = ds->priv; 1254 1255 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr, 1256 mdb->vid); 1257 if (mdb->vid) 1258 return -EOPNOTSUPP; 1259 if (lan9303_alr_cache_find_mac(chip, mdb->addr)) 1260 return 0; 1261 if (!lan9303_alr_cache_find_free(chip)) 1262 return -ENOSPC; 1263 1264 return 0; 1265 } 1266 1267 static int lan9303_port_mdb_add(struct dsa_switch *ds, int port, 1268 const struct switchdev_obj_port_mdb *mdb, 1269 struct dsa_db db) 1270 { 1271 struct lan9303 *chip = ds->priv; 1272 int err; 1273 1274 err = lan9303_port_mdb_prepare(ds, port, mdb); 1275 if (err) 1276 return err; 1277 1278 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr, 1279 mdb->vid); 1280 return lan9303_alr_add_port(chip, mdb->addr, port, false); 1281 } 1282 1283 static int lan9303_port_mdb_del(struct dsa_switch *ds, int port, 1284 const struct switchdev_obj_port_mdb *mdb, 1285 struct dsa_db db) 1286 { 1287 struct lan9303 *chip = ds->priv; 1288 1289 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr, 1290 mdb->vid); 1291 if (mdb->vid) 1292 return -EOPNOTSUPP; 1293 lan9303_alr_del_port(chip, mdb->addr, port); 1294 1295 return 0; 1296 } 1297 1298 static void lan9303_phylink_get_caps(struct dsa_switch *ds, int port, 1299 struct phylink_config *config) 1300 { 1301 struct lan9303 *chip = ds->priv; 1302 1303 dev_dbg(chip->dev, "%s(%d) entered.", __func__, port); 1304 1305 config->mac_capabilities = MAC_10 | MAC_100 | MAC_ASYM_PAUSE | 1306 MAC_SYM_PAUSE; 1307 1308 if (port == 0) { 1309 __set_bit(PHY_INTERFACE_MODE_RMII, 1310 config->supported_interfaces); 1311 __set_bit(PHY_INTERFACE_MODE_MII, 1312 config->supported_interfaces); 1313 } else { 1314 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1315 config->supported_interfaces); 1316 /* Compatibility for phylib's default interface type when the 1317 * phy-mode property is absent 1318 */ 1319 __set_bit(PHY_INTERFACE_MODE_GMII, 1320 config->supported_interfaces); 1321 } 1322 } 1323 1324 static void lan9303_phylink_mac_config(struct phylink_config *config, 1325 unsigned int mode, 1326 const struct phylink_link_state *state) 1327 { 1328 } 1329 1330 static void lan9303_phylink_mac_link_down(struct phylink_config *config, 1331 unsigned int mode, 1332 phy_interface_t interface) 1333 { 1334 } 1335 1336 static void lan9303_phylink_mac_link_up(struct phylink_config *config, 1337 struct phy_device *phydev, 1338 unsigned int mode, 1339 phy_interface_t interface, 1340 int speed, int duplex, bool tx_pause, 1341 bool rx_pause) 1342 { 1343 struct dsa_port *dp = dsa_phylink_to_port(config); 1344 struct lan9303 *chip = dp->ds->priv; 1345 struct dsa_switch *ds = dp->ds; 1346 int port = dp->index; 1347 u32 ctl; 1348 u32 reg; 1349 1350 /* On this device, we are only interested in doing something here if 1351 * this is the xMII port. All other ports are 10/100 phys using MDIO 1352 * to control there link settings. 1353 */ 1354 if (!IS_PORT_XMII(port)) 1355 return; 1356 1357 /* Disable auto-negotiation and force the speed/duplex settings. */ 1358 ctl = lan9303_phy_read(ds, port, MII_BMCR); 1359 ctl &= ~(BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX); 1360 if (speed == SPEED_100) 1361 ctl |= BMCR_SPEED100; 1362 if (duplex == DUPLEX_FULL) 1363 ctl |= BMCR_FULLDPLX; 1364 lan9303_phy_write(ds, port, MII_BMCR, ctl); 1365 1366 /* Force the flow control settings. */ 1367 lan9303_read(chip->regmap, flow_ctl_reg[port], ®); 1368 reg &= ~(LAN9303_BP_EN | LAN9303_RX_FC_EN | LAN9303_TX_FC_EN); 1369 if (rx_pause) 1370 reg |= (LAN9303_RX_FC_EN | LAN9303_BP_EN); 1371 if (tx_pause) 1372 reg |= LAN9303_TX_FC_EN; 1373 regmap_write(chip->regmap, flow_ctl_reg[port], reg); 1374 } 1375 1376 static const struct phylink_mac_ops lan9303_phylink_mac_ops = { 1377 .mac_config = lan9303_phylink_mac_config, 1378 .mac_link_down = lan9303_phylink_mac_link_down, 1379 .mac_link_up = lan9303_phylink_mac_link_up, 1380 }; 1381 1382 static const struct dsa_switch_ops lan9303_switch_ops = { 1383 .get_tag_protocol = lan9303_get_tag_protocol, 1384 .setup = lan9303_setup, 1385 .get_strings = lan9303_get_strings, 1386 .phy_read = lan9303_phy_read, 1387 .phy_write = lan9303_phy_write, 1388 .phylink_get_caps = lan9303_phylink_get_caps, 1389 .get_ethtool_stats = lan9303_get_ethtool_stats, 1390 .get_sset_count = lan9303_get_sset_count, 1391 .port_enable = lan9303_port_enable, 1392 .port_disable = lan9303_port_disable, 1393 .port_bridge_join = lan9303_port_bridge_join, 1394 .port_bridge_leave = lan9303_port_bridge_leave, 1395 .port_stp_state_set = lan9303_port_stp_state_set, 1396 .port_fast_age = lan9303_port_fast_age, 1397 .port_fdb_add = lan9303_port_fdb_add, 1398 .port_fdb_del = lan9303_port_fdb_del, 1399 .port_fdb_dump = lan9303_port_fdb_dump, 1400 .port_mdb_add = lan9303_port_mdb_add, 1401 .port_mdb_del = lan9303_port_mdb_del, 1402 }; 1403 1404 static int lan9303_register_switch(struct lan9303 *chip) 1405 { 1406 chip->ds = devm_kzalloc(chip->dev, sizeof(*chip->ds), GFP_KERNEL); 1407 if (!chip->ds) 1408 return -ENOMEM; 1409 1410 chip->ds->dev = chip->dev; 1411 chip->ds->num_ports = LAN9303_NUM_PORTS; 1412 chip->ds->priv = chip; 1413 chip->ds->ops = &lan9303_switch_ops; 1414 chip->ds->phylink_mac_ops = &lan9303_phylink_mac_ops; 1415 chip->ds->phys_mii_mask = GENMASK(LAN9303_NUM_PORTS - 1, 0); 1416 1417 return dsa_register_switch(chip->ds); 1418 } 1419 1420 static int lan9303_probe_reset_gpio(struct lan9303 *chip, 1421 struct device_node *np) 1422 { 1423 chip->reset_gpio = devm_gpiod_get_optional(chip->dev, "reset", 1424 GPIOD_OUT_HIGH); 1425 if (IS_ERR(chip->reset_gpio)) 1426 return PTR_ERR(chip->reset_gpio); 1427 1428 if (!chip->reset_gpio) { 1429 dev_dbg(chip->dev, "No reset GPIO defined\n"); 1430 return 0; 1431 } 1432 1433 chip->reset_duration = 200; 1434 1435 if (np) { 1436 of_property_read_u32(np, "reset-duration", 1437 &chip->reset_duration); 1438 } else { 1439 dev_dbg(chip->dev, "reset duration defaults to 200 ms\n"); 1440 } 1441 1442 /* A sane reset duration should not be longer than 1s */ 1443 if (chip->reset_duration > 1000) 1444 chip->reset_duration = 1000; 1445 1446 return 0; 1447 } 1448 1449 int lan9303_probe(struct lan9303 *chip, struct device_node *np) 1450 { 1451 int ret; 1452 u32 reg; 1453 1454 mutex_init(&chip->indirect_mutex); 1455 mutex_init(&chip->alr_mutex); 1456 1457 ret = lan9303_probe_reset_gpio(chip, np); 1458 if (ret) 1459 return ret; 1460 1461 lan9303_handle_reset(chip); 1462 1463 /* First read to the device. This is a Dummy read to ensure MDIO */ 1464 /* access is in 32-bit sync. */ 1465 ret = lan9303_read(chip->regmap, LAN9303_BYTE_ORDER, ®); 1466 if (ret) { 1467 dev_err(chip->dev, "failed to access the device: %d\n", 1468 ret); 1469 if (!chip->reset_gpio) { 1470 dev_dbg(chip->dev, 1471 "hint: maybe failed due to missing reset GPIO\n"); 1472 } 1473 return ret; 1474 } 1475 1476 ret = lan9303_check_device(chip); 1477 if (ret) 1478 return ret; 1479 1480 ret = lan9303_register_switch(chip); 1481 if (ret) { 1482 dev_dbg(chip->dev, "Failed to register switch: %d\n", ret); 1483 return ret; 1484 } 1485 1486 return 0; 1487 } 1488 EXPORT_SYMBOL(lan9303_probe); 1489 1490 int lan9303_remove(struct lan9303 *chip) 1491 { 1492 int rc; 1493 1494 rc = lan9303_disable_processing(chip); 1495 if (rc != 0) 1496 dev_warn(chip->dev, "shutting down failed\n"); 1497 1498 dsa_unregister_switch(chip->ds); 1499 1500 /* assert reset to the whole device to prevent it from doing anything */ 1501 gpiod_set_value_cansleep(chip->reset_gpio, 1); 1502 1503 return 0; 1504 } 1505 EXPORT_SYMBOL(lan9303_remove); 1506 1507 void lan9303_shutdown(struct lan9303 *chip) 1508 { 1509 dsa_switch_shutdown(chip->ds); 1510 } 1511 EXPORT_SYMBOL(lan9303_shutdown); 1512 1513 MODULE_AUTHOR("Juergen Borleis <kernel@pengutronix.de>"); 1514 MODULE_DESCRIPTION("Core driver for SMSC/Microchip LAN9303 three port ethernet switch"); 1515 MODULE_LICENSE("GPL v2"); 1516