1 /* 2 * Broadcom Starfighter2 private context 3 * 4 * Copyright (C) 2014, Broadcom Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #ifndef __BCM_SF2_H 13 #define __BCM_SF2_H 14 15 #include <linux/platform_device.h> 16 #include <linux/kernel.h> 17 #include <linux/io.h> 18 #include <linux/spinlock.h> 19 #include <linux/mutex.h> 20 #include <linux/mii.h> 21 #include <linux/ethtool.h> 22 #include <linux/types.h> 23 #include <linux/bitops.h> 24 #include <linux/if_vlan.h> 25 26 #include <net/dsa.h> 27 28 #include "bcm_sf2_regs.h" 29 #include "b53/b53_priv.h" 30 31 struct bcm_sf2_hw_params { 32 u16 top_rev; 33 u16 core_rev; 34 u16 gphy_rev; 35 u32 num_gphy; 36 u8 num_acb_queue; 37 u8 num_rgmii; 38 u8 num_ports; 39 u8 fcb_pause_override:1; 40 u8 acb_packets_inflight:1; 41 }; 42 43 #define BCM_SF2_REGS_NAME {\ 44 "core", "reg", "intrl2_0", "intrl2_1", "fcb", "acb" \ 45 } 46 47 #define BCM_SF2_REGS_NUM 6 48 49 struct bcm_sf2_port_status { 50 unsigned int link; 51 52 struct ethtool_eee eee; 53 54 u16 vlan_ctl_mask; 55 }; 56 57 struct bcm_sf2_priv { 58 /* Base registers, keep those in order with BCM_SF2_REGS_NAME */ 59 void __iomem *core; 60 void __iomem *reg; 61 void __iomem *intrl2_0; 62 void __iomem *intrl2_1; 63 void __iomem *fcb; 64 void __iomem *acb; 65 66 /* spinlock protecting access to the indirect registers */ 67 spinlock_t indir_lock; 68 69 int irq0; 70 int irq1; 71 u32 irq0_stat; 72 u32 irq0_mask; 73 u32 irq1_stat; 74 u32 irq1_mask; 75 76 /* Backing b53_device */ 77 struct b53_device *dev; 78 79 /* Mutex protecting access to the MIB counters */ 80 struct mutex stats_mutex; 81 82 struct bcm_sf2_hw_params hw_params; 83 84 struct bcm_sf2_port_status port_sts[DSA_MAX_PORTS]; 85 86 /* Mask of ports enabled for Wake-on-LAN */ 87 u32 wol_ports_mask; 88 89 /* MoCA port location */ 90 int moca_port; 91 92 /* Bitmask of ports having an integrated PHY */ 93 unsigned int int_phy_mask; 94 95 /* Master and slave MDIO bus controller */ 96 unsigned int indir_phy_mask; 97 struct device_node *master_mii_dn; 98 struct mii_bus *slave_mii_bus; 99 struct mii_bus *master_mii_bus; 100 }; 101 102 static inline struct bcm_sf2_priv *bcm_sf2_to_priv(struct dsa_switch *ds) 103 { 104 struct b53_device *dev = ds->priv; 105 106 return dev->priv; 107 } 108 109 #define SF2_IO_MACRO(name) \ 110 static inline u32 name##_readl(struct bcm_sf2_priv *priv, u32 off) \ 111 { \ 112 return __raw_readl(priv->name + off); \ 113 } \ 114 static inline void name##_writel(struct bcm_sf2_priv *priv, \ 115 u32 val, u32 off) \ 116 { \ 117 __raw_writel(val, priv->name + off); \ 118 } \ 119 120 /* Accesses to 64-bits register requires us to latch the hi/lo pairs 121 * using the REG_DIR_DATA_{READ,WRITE} ancillary registers. The 'indir_lock' 122 * spinlock is automatically grabbed and released to provide relative 123 * atomiticy with latched reads/writes. 124 */ 125 #define SF2_IO64_MACRO(name) \ 126 static inline u64 name##_readq(struct bcm_sf2_priv *priv, u32 off) \ 127 { \ 128 u32 indir, dir; \ 129 spin_lock(&priv->indir_lock); \ 130 dir = __raw_readl(priv->name + off); \ 131 indir = reg_readl(priv, REG_DIR_DATA_READ); \ 132 spin_unlock(&priv->indir_lock); \ 133 return (u64)indir << 32 | dir; \ 134 } \ 135 static inline void name##_writeq(struct bcm_sf2_priv *priv, u64 val, \ 136 u32 off) \ 137 { \ 138 spin_lock(&priv->indir_lock); \ 139 reg_writel(priv, upper_32_bits(val), REG_DIR_DATA_WRITE); \ 140 __raw_writel(lower_32_bits(val), priv->name + off); \ 141 spin_unlock(&priv->indir_lock); \ 142 } 143 144 #define SWITCH_INTR_L2(which) \ 145 static inline void intrl2_##which##_mask_clear(struct bcm_sf2_priv *priv, \ 146 u32 mask) \ 147 { \ 148 priv->irq##which##_mask &= ~(mask); \ 149 intrl2_##which##_writel(priv, mask, INTRL2_CPU_MASK_CLEAR); \ 150 } \ 151 static inline void intrl2_##which##_mask_set(struct bcm_sf2_priv *priv, \ 152 u32 mask) \ 153 { \ 154 intrl2_## which##_writel(priv, mask, INTRL2_CPU_MASK_SET); \ 155 priv->irq##which##_mask |= (mask); \ 156 } \ 157 158 SF2_IO_MACRO(core); 159 SF2_IO_MACRO(reg); 160 SF2_IO64_MACRO(core); 161 SF2_IO_MACRO(intrl2_0); 162 SF2_IO_MACRO(intrl2_1); 163 SF2_IO_MACRO(fcb); 164 SF2_IO_MACRO(acb); 165 166 SWITCH_INTR_L2(0); 167 SWITCH_INTR_L2(1); 168 169 #endif /* __BCM_SF2_H */ 170