1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Broadcom Starfighter 2 DSA switch driver 4 * 5 * Copyright (C) 2014, Broadcom Corporation 6 */ 7 8 #include <linux/list.h> 9 #include <linux/module.h> 10 #include <linux/netdevice.h> 11 #include <linux/interrupt.h> 12 #include <linux/platform_device.h> 13 #include <linux/phy.h> 14 #include <linux/phy_fixed.h> 15 #include <linux/phylink.h> 16 #include <linux/mii.h> 17 #include <linux/clk.h> 18 #include <linux/of.h> 19 #include <linux/of_irq.h> 20 #include <linux/of_address.h> 21 #include <linux/of_net.h> 22 #include <linux/of_mdio.h> 23 #include <net/dsa.h> 24 #include <linux/ethtool.h> 25 #include <linux/if_bridge.h> 26 #include <linux/brcmphy.h> 27 #include <linux/etherdevice.h> 28 #include <linux/platform_data/b53.h> 29 30 #include "bcm_sf2.h" 31 #include "bcm_sf2_regs.h" 32 #include "b53/b53_priv.h" 33 #include "b53/b53_regs.h" 34 35 static u16 bcm_sf2_reg_rgmii_cntrl(struct bcm_sf2_priv *priv, int port) 36 { 37 switch (priv->type) { 38 case BCM4908_DEVICE_ID: 39 switch (port) { 40 case 7: 41 return REG_RGMII_11_CNTRL; 42 default: 43 break; 44 } 45 break; 46 default: 47 switch (port) { 48 case 0: 49 return REG_RGMII_0_CNTRL; 50 case 1: 51 return REG_RGMII_1_CNTRL; 52 case 2: 53 return REG_RGMII_2_CNTRL; 54 default: 55 break; 56 } 57 } 58 59 WARN_ONCE(1, "Unsupported port %d\n", port); 60 61 /* RO fallback reg */ 62 return REG_SWITCH_STATUS; 63 } 64 65 static u16 bcm_sf2_reg_led_base(struct bcm_sf2_priv *priv, int port) 66 { 67 switch (port) { 68 case 0: 69 return REG_LED_0_CNTRL; 70 case 1: 71 return REG_LED_1_CNTRL; 72 case 2: 73 return REG_LED_2_CNTRL; 74 } 75 76 switch (priv->type) { 77 case BCM4908_DEVICE_ID: 78 switch (port) { 79 case 3: 80 return REG_LED_3_CNTRL; 81 case 7: 82 return REG_LED_4_CNTRL; 83 default: 84 break; 85 } 86 break; 87 default: 88 break; 89 } 90 91 WARN_ONCE(1, "Unsupported port %d\n", port); 92 93 /* RO fallback reg */ 94 return REG_SWITCH_STATUS; 95 } 96 97 static u32 bcm_sf2_port_override_offset(struct bcm_sf2_priv *priv, int port) 98 { 99 switch (priv->type) { 100 case BCM4908_DEVICE_ID: 101 case BCM7445_DEVICE_ID: 102 return port == 8 ? CORE_STS_OVERRIDE_IMP : 103 CORE_STS_OVERRIDE_GMIIP_PORT(port); 104 case BCM7278_DEVICE_ID: 105 return port == 8 ? CORE_STS_OVERRIDE_IMP2 : 106 CORE_STS_OVERRIDE_GMIIP2_PORT(port); 107 default: 108 WARN_ONCE(1, "Unsupported device: %d\n", priv->type); 109 } 110 111 /* RO fallback register */ 112 return REG_SWITCH_STATUS; 113 } 114 115 /* Return the number of active ports, not counting the IMP (CPU) port */ 116 static unsigned int bcm_sf2_num_active_ports(struct dsa_switch *ds) 117 { 118 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 119 unsigned int port, count = 0; 120 121 for (port = 0; port < ds->num_ports; port++) { 122 if (dsa_is_cpu_port(ds, port)) 123 continue; 124 if (priv->port_sts[port].enabled) 125 count++; 126 } 127 128 return count; 129 } 130 131 static void bcm_sf2_recalc_clock(struct dsa_switch *ds) 132 { 133 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 134 unsigned long new_rate; 135 unsigned int ports_active; 136 /* Frequenty in Mhz */ 137 static const unsigned long rate_table[] = { 138 59220000, 139 60820000, 140 62500000, 141 62500000, 142 }; 143 144 ports_active = bcm_sf2_num_active_ports(ds); 145 if (ports_active == 0 || !priv->clk_mdiv) 146 return; 147 148 /* If we overflow our table, just use the recommended operational 149 * frequency 150 */ 151 if (ports_active > ARRAY_SIZE(rate_table)) 152 new_rate = 90000000; 153 else 154 new_rate = rate_table[ports_active - 1]; 155 clk_set_rate(priv->clk_mdiv, new_rate); 156 } 157 158 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port) 159 { 160 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 161 unsigned int i; 162 u32 reg; 163 164 /* Enable the port memories */ 165 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 166 reg &= ~P_TXQ_PSM_VDD(port); 167 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 168 169 /* Enable forwarding */ 170 core_writel(priv, SW_FWDG_EN, CORE_SWMODE); 171 172 /* Enable IMP port in dumb mode */ 173 reg = core_readl(priv, CORE_SWITCH_CTRL); 174 reg |= MII_DUMB_FWDG_EN; 175 core_writel(priv, reg, CORE_SWITCH_CTRL); 176 177 /* Configure Traffic Class to QoS mapping, allow each priority to map 178 * to a different queue number 179 */ 180 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); 181 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) 182 reg |= i << (PRT_TO_QID_SHIFT * i); 183 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); 184 185 b53_brcm_hdr_setup(ds, port); 186 187 if (port == 8) { 188 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */ 189 reg = core_readl(priv, CORE_IMP_CTL); 190 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN); 191 reg &= ~(RX_DIS | TX_DIS); 192 core_writel(priv, reg, CORE_IMP_CTL); 193 } else { 194 reg = core_readl(priv, CORE_G_PCTL_PORT(port)); 195 reg &= ~(RX_DIS | TX_DIS); 196 core_writel(priv, reg, CORE_G_PCTL_PORT(port)); 197 } 198 199 priv->port_sts[port].enabled = true; 200 } 201 202 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable) 203 { 204 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 205 u32 reg; 206 207 reg = reg_readl(priv, REG_SPHY_CNTRL); 208 if (enable) { 209 reg |= PHY_RESET; 210 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS); 211 reg_writel(priv, reg, REG_SPHY_CNTRL); 212 udelay(21); 213 reg = reg_readl(priv, REG_SPHY_CNTRL); 214 reg &= ~PHY_RESET; 215 } else { 216 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET; 217 reg_writel(priv, reg, REG_SPHY_CNTRL); 218 mdelay(1); 219 reg |= CK25_DIS; 220 } 221 reg_writel(priv, reg, REG_SPHY_CNTRL); 222 223 /* Use PHY-driven LED signaling */ 224 if (!enable) { 225 u16 led_ctrl = bcm_sf2_reg_led_base(priv, 0); 226 227 if (priv->type == BCM7278_DEVICE_ID || 228 priv->type == BCM7445_DEVICE_ID) { 229 reg = reg_led_readl(priv, led_ctrl, 0); 230 reg |= LED_CNTRL_SPDLNK_SRC_SEL; 231 reg_led_writel(priv, reg, led_ctrl, 0); 232 } 233 } 234 } 235 236 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv, 237 int port) 238 { 239 unsigned int off; 240 241 switch (port) { 242 case 7: 243 off = P7_IRQ_OFF; 244 break; 245 case 0: 246 /* Port 0 interrupts are located on the first bank */ 247 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF)); 248 return; 249 default: 250 off = P_IRQ_OFF(port); 251 break; 252 } 253 254 intrl2_1_mask_clear(priv, P_IRQ_MASK(off)); 255 } 256 257 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv, 258 int port) 259 { 260 unsigned int off; 261 262 switch (port) { 263 case 7: 264 off = P7_IRQ_OFF; 265 break; 266 case 0: 267 /* Port 0 interrupts are located on the first bank */ 268 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF)); 269 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR); 270 return; 271 default: 272 off = P_IRQ_OFF(port); 273 break; 274 } 275 276 intrl2_1_mask_set(priv, P_IRQ_MASK(off)); 277 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR); 278 } 279 280 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port, 281 struct phy_device *phy) 282 { 283 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 284 unsigned int i; 285 u32 reg; 286 287 if (!dsa_is_user_port(ds, port)) 288 return 0; 289 290 priv->port_sts[port].enabled = true; 291 292 bcm_sf2_recalc_clock(ds); 293 294 /* Clear the memory power down */ 295 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 296 reg &= ~P_TXQ_PSM_VDD(port); 297 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 298 299 /* Enable Broadcom tags for that port if requested */ 300 if (priv->brcm_tag_mask & BIT(port)) 301 b53_brcm_hdr_setup(ds, port); 302 303 /* Configure Traffic Class to QoS mapping, allow each priority to map 304 * to a different queue number 305 */ 306 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); 307 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) 308 reg |= i << (PRT_TO_QID_SHIFT * i); 309 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); 310 311 /* Re-enable the GPHY and re-apply workarounds */ 312 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) { 313 bcm_sf2_gphy_enable_set(ds, true); 314 if (phy) { 315 /* if phy_stop() has been called before, phy 316 * will be in halted state, and phy_start() 317 * will call resume. 318 * 319 * the resume path does not configure back 320 * autoneg settings, and since we hard reset 321 * the phy manually here, we need to reset the 322 * state machine also. 323 */ 324 phy->state = PHY_READY; 325 phy_init_hw(phy); 326 } 327 } 328 329 /* Enable MoCA port interrupts to get notified */ 330 if (port == priv->moca_port) 331 bcm_sf2_port_intr_enable(priv, port); 332 333 /* Set per-queue pause threshold to 32 */ 334 core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port)); 335 336 /* Set ACB threshold to 24 */ 337 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) { 338 reg = acb_readl(priv, ACB_QUEUE_CFG(port * 339 SF2_NUM_EGRESS_QUEUES + i)); 340 reg &= ~XOFF_THRESHOLD_MASK; 341 reg |= 24; 342 acb_writel(priv, reg, ACB_QUEUE_CFG(port * 343 SF2_NUM_EGRESS_QUEUES + i)); 344 } 345 346 return b53_enable_port(ds, port, phy); 347 } 348 349 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port) 350 { 351 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 352 u32 reg; 353 354 /* Disable learning while in WoL mode */ 355 if (priv->wol_ports_mask & (1 << port)) { 356 reg = core_readl(priv, CORE_DIS_LEARN); 357 reg |= BIT(port); 358 core_writel(priv, reg, CORE_DIS_LEARN); 359 return; 360 } 361 362 if (port == priv->moca_port) 363 bcm_sf2_port_intr_disable(priv, port); 364 365 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) 366 bcm_sf2_gphy_enable_set(ds, false); 367 368 b53_disable_port(ds, port); 369 370 /* Power down the port memory */ 371 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 372 reg |= P_TXQ_PSM_VDD(port); 373 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 374 375 priv->port_sts[port].enabled = false; 376 377 bcm_sf2_recalc_clock(ds); 378 } 379 380 381 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr, 382 int regnum, u16 val) 383 { 384 int ret = 0; 385 u32 reg; 386 387 reg = reg_readl(priv, REG_SWITCH_CNTRL); 388 reg |= MDIO_MASTER_SEL; 389 reg_writel(priv, reg, REG_SWITCH_CNTRL); 390 391 /* Page << 8 | offset */ 392 reg = 0x70; 393 reg <<= 2; 394 core_writel(priv, addr, reg); 395 396 /* Page << 8 | offset */ 397 reg = 0x80 << 8 | regnum << 1; 398 reg <<= 2; 399 400 if (op) 401 ret = core_readl(priv, reg); 402 else 403 core_writel(priv, val, reg); 404 405 reg = reg_readl(priv, REG_SWITCH_CNTRL); 406 reg &= ~MDIO_MASTER_SEL; 407 reg_writel(priv, reg, REG_SWITCH_CNTRL); 408 409 return ret & 0xffff; 410 } 411 412 static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 413 { 414 struct bcm_sf2_priv *priv = bus->priv; 415 416 /* Intercept reads from Broadcom pseudo-PHY address, else, send 417 * them to our master MDIO bus controller 418 */ 419 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) 420 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0); 421 else 422 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum); 423 } 424 425 static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 426 u16 val) 427 { 428 struct bcm_sf2_priv *priv = bus->priv; 429 430 /* Intercept writes to the Broadcom pseudo-PHY address, else, 431 * send them to our master MDIO bus controller 432 */ 433 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) 434 return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val); 435 else 436 return mdiobus_write_nested(priv->master_mii_bus, addr, 437 regnum, val); 438 } 439 440 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id) 441 { 442 struct dsa_switch *ds = dev_id; 443 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 444 445 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) & 446 ~priv->irq0_mask; 447 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR); 448 449 return IRQ_HANDLED; 450 } 451 452 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id) 453 { 454 struct dsa_switch *ds = dev_id; 455 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 456 457 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) & 458 ~priv->irq1_mask; 459 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR); 460 461 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) { 462 priv->port_sts[7].link = true; 463 dsa_port_phylink_mac_change(ds, 7, true); 464 } 465 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) { 466 priv->port_sts[7].link = false; 467 dsa_port_phylink_mac_change(ds, 7, false); 468 } 469 470 return IRQ_HANDLED; 471 } 472 473 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv) 474 { 475 unsigned int timeout = 1000; 476 u32 reg; 477 int ret; 478 479 /* The watchdog reset does not work on 7278, we need to hit the 480 * "external" reset line through the reset controller. 481 */ 482 if (priv->type == BCM7278_DEVICE_ID) { 483 ret = reset_control_assert(priv->rcdev); 484 if (ret) 485 return ret; 486 487 return reset_control_deassert(priv->rcdev); 488 } 489 490 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 491 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET; 492 core_writel(priv, reg, CORE_WATCHDOG_CTRL); 493 494 do { 495 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 496 if (!(reg & SOFTWARE_RESET)) 497 break; 498 499 usleep_range(1000, 2000); 500 } while (timeout-- > 0); 501 502 if (timeout == 0) 503 return -ETIMEDOUT; 504 505 return 0; 506 } 507 508 static void bcm_sf2_crossbar_setup(struct bcm_sf2_priv *priv) 509 { 510 struct device *dev = priv->dev->ds->dev; 511 int shift; 512 u32 mask; 513 u32 reg; 514 int i; 515 516 mask = BIT(priv->num_crossbar_int_ports) - 1; 517 518 reg = reg_readl(priv, REG_CROSSBAR); 519 switch (priv->type) { 520 case BCM4908_DEVICE_ID: 521 shift = CROSSBAR_BCM4908_INT_P7 * priv->num_crossbar_int_ports; 522 reg &= ~(mask << shift); 523 if (0) /* FIXME */ 524 reg |= CROSSBAR_BCM4908_EXT_SERDES << shift; 525 else if (priv->int_phy_mask & BIT(7)) 526 reg |= CROSSBAR_BCM4908_EXT_GPHY4 << shift; 527 else if (phy_interface_mode_is_rgmii(priv->port_sts[7].mode)) 528 reg |= CROSSBAR_BCM4908_EXT_RGMII << shift; 529 else if (WARN(1, "Invalid port mode\n")) 530 return; 531 break; 532 default: 533 return; 534 } 535 reg_writel(priv, reg, REG_CROSSBAR); 536 537 reg = reg_readl(priv, REG_CROSSBAR); 538 for (i = 0; i < priv->num_crossbar_int_ports; i++) { 539 shift = i * priv->num_crossbar_int_ports; 540 541 dev_dbg(dev, "crossbar int port #%d - ext port #%d\n", i, 542 (reg >> shift) & mask); 543 } 544 } 545 546 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv) 547 { 548 intrl2_0_mask_set(priv, 0xffffffff); 549 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 550 intrl2_1_mask_set(priv, 0xffffffff); 551 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 552 } 553 554 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv, 555 struct device_node *dn) 556 { 557 struct device *dev = priv->dev->ds->dev; 558 struct bcm_sf2_port_status *port_st; 559 struct device_node *port; 560 unsigned int port_num; 561 struct property *prop; 562 int err; 563 564 priv->moca_port = -1; 565 566 for_each_available_child_of_node(dn, port) { 567 if (of_property_read_u32(port, "reg", &port_num)) 568 continue; 569 570 if (port_num >= DSA_MAX_PORTS) { 571 dev_err(dev, "Invalid port number %d\n", port_num); 572 continue; 573 } 574 575 port_st = &priv->port_sts[port_num]; 576 577 /* Internal PHYs get assigned a specific 'phy-mode' property 578 * value: "internal" to help flag them before MDIO probing 579 * has completed, since they might be turned off at that 580 * time 581 */ 582 err = of_get_phy_mode(port, &port_st->mode); 583 if (err) 584 continue; 585 586 if (port_st->mode == PHY_INTERFACE_MODE_INTERNAL) 587 priv->int_phy_mask |= 1 << port_num; 588 589 if (port_st->mode == PHY_INTERFACE_MODE_MOCA) 590 priv->moca_port = port_num; 591 592 if (of_property_read_bool(port, "brcm,use-bcm-hdr")) 593 priv->brcm_tag_mask |= 1 << port_num; 594 595 /* Ensure that port 5 is not picked up as a DSA CPU port 596 * flavour but a regular port instead. We should be using 597 * devlink to be able to set the port flavour. 598 */ 599 if (port_num == 5 && priv->type == BCM7278_DEVICE_ID) { 600 prop = of_find_property(port, "ethernet", NULL); 601 if (prop) 602 of_remove_property(port, prop); 603 } 604 } 605 } 606 607 static int bcm_sf2_mdio_register(struct dsa_switch *ds) 608 { 609 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 610 struct device_node *dn, *child; 611 struct phy_device *phydev; 612 struct property *prop; 613 static int index; 614 int err, reg; 615 616 /* Find our integrated MDIO bus node */ 617 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio"); 618 priv->master_mii_bus = of_mdio_find_bus(dn); 619 if (!priv->master_mii_bus) { 620 err = -EPROBE_DEFER; 621 goto err_of_node_put; 622 } 623 624 priv->user_mii_bus = mdiobus_alloc(); 625 if (!priv->user_mii_bus) { 626 err = -ENOMEM; 627 goto err_put_master_mii_bus_dev; 628 } 629 630 priv->user_mii_bus->priv = priv; 631 priv->user_mii_bus->name = "sf2 user mii"; 632 priv->user_mii_bus->read = bcm_sf2_sw_mdio_read; 633 priv->user_mii_bus->write = bcm_sf2_sw_mdio_write; 634 snprintf(priv->user_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d", 635 index++); 636 637 /* Include the pseudo-PHY address to divert reads towards our 638 * workaround. This is only required for 7445D0, since 7445E0 639 * disconnects the internal switch pseudo-PHY such that we can use the 640 * regular SWITCH_MDIO master controller instead. 641 * 642 * Here we flag the pseudo PHY as needing special treatment and would 643 * otherwise make all other PHY read/writes go to the master MDIO bus 644 * controller that comes with this switch backed by the "mdio-unimac" 645 * driver. 646 */ 647 if (of_machine_is_compatible("brcm,bcm7445d0")) 648 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR) | (1 << 0); 649 else 650 priv->indir_phy_mask = 0; 651 652 ds->phys_mii_mask = priv->indir_phy_mask; 653 ds->user_mii_bus = priv->user_mii_bus; 654 priv->user_mii_bus->parent = ds->dev->parent; 655 priv->user_mii_bus->phy_mask = ~priv->indir_phy_mask; 656 657 /* We need to make sure that of_phy_connect() will not work by 658 * removing the 'phandle' and 'linux,phandle' properties and 659 * unregister the existing PHY device that was already registered. 660 */ 661 for_each_available_child_of_node(dn, child) { 662 if (of_property_read_u32(child, "reg", ®) || 663 reg >= PHY_MAX_ADDR) 664 continue; 665 666 if (!(priv->indir_phy_mask & BIT(reg))) 667 continue; 668 669 prop = of_find_property(child, "phandle", NULL); 670 if (prop) 671 of_remove_property(child, prop); 672 673 prop = of_find_property(child, "linux,phandle", NULL); 674 if (prop) 675 of_remove_property(child, prop); 676 677 phydev = of_phy_find_device(child); 678 if (phydev) 679 phy_device_remove(phydev); 680 } 681 682 err = mdiobus_register(priv->user_mii_bus); 683 if (err) 684 goto err_free_user_mii_bus; 685 686 of_node_put(dn); 687 688 return 0; 689 690 err_free_user_mii_bus: 691 mdiobus_free(priv->user_mii_bus); 692 err_put_master_mii_bus_dev: 693 put_device(&priv->master_mii_bus->dev); 694 err_of_node_put: 695 of_node_put(dn); 696 return err; 697 } 698 699 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv) 700 { 701 mdiobus_unregister(priv->user_mii_bus); 702 mdiobus_free(priv->user_mii_bus); 703 put_device(&priv->master_mii_bus->dev); 704 } 705 706 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port) 707 { 708 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 709 710 /* The BCM7xxx PHY driver expects to find the integrated PHY revision 711 * in bits 15:8 and the patch level in bits 7:0 which is exactly what 712 * the REG_PHY_REVISION register layout is. 713 */ 714 if (priv->int_phy_mask & BIT(port)) 715 return priv->hw_params.gphy_rev; 716 else 717 return PHY_BRCM_AUTO_PWRDWN_ENABLE | 718 PHY_BRCM_DIS_TXCRXC_NOENRGY | 719 PHY_BRCM_IDDQ_SUSPEND; 720 } 721 722 static void bcm_sf2_sw_get_caps(struct dsa_switch *ds, int port, 723 struct phylink_config *config) 724 { 725 unsigned long *interfaces = config->supported_interfaces; 726 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 727 728 if (priv->int_phy_mask & BIT(port)) { 729 __set_bit(PHY_INTERFACE_MODE_INTERNAL, interfaces); 730 } else if (priv->moca_port == port) { 731 __set_bit(PHY_INTERFACE_MODE_MOCA, interfaces); 732 } else { 733 __set_bit(PHY_INTERFACE_MODE_MII, interfaces); 734 __set_bit(PHY_INTERFACE_MODE_REVMII, interfaces); 735 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces); 736 phy_interface_set_rgmii(interfaces); 737 } 738 739 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 740 MAC_10 | MAC_100 | MAC_1000; 741 } 742 743 static void bcm_sf2_sw_mac_config(struct phylink_config *config, 744 unsigned int mode, 745 const struct phylink_link_state *state) 746 { 747 struct dsa_port *dp = dsa_phylink_to_port(config); 748 u32 id_mode_dis = 0, port_mode; 749 struct bcm_sf2_priv *priv; 750 u32 reg_rgmii_ctrl; 751 u32 reg; 752 753 priv = bcm_sf2_to_priv(dp->ds); 754 755 if (dp->index == core_readl(priv, CORE_IMP0_PRT_ID)) 756 return; 757 758 switch (state->interface) { 759 case PHY_INTERFACE_MODE_RGMII: 760 id_mode_dis = 1; 761 fallthrough; 762 case PHY_INTERFACE_MODE_RGMII_TXID: 763 port_mode = EXT_GPHY; 764 break; 765 case PHY_INTERFACE_MODE_MII: 766 port_mode = EXT_EPHY; 767 break; 768 case PHY_INTERFACE_MODE_REVMII: 769 port_mode = EXT_REVMII; 770 break; 771 default: 772 /* Nothing required for all other PHYs: internal and MoCA */ 773 return; 774 } 775 776 reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, dp->index); 777 778 /* Clear id_mode_dis bit, and the existing port mode, let 779 * RGMII_MODE_EN bet set by mac_link_{up,down} 780 */ 781 reg = reg_readl(priv, reg_rgmii_ctrl); 782 reg &= ~ID_MODE_DIS; 783 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT); 784 785 reg |= port_mode; 786 if (id_mode_dis) 787 reg |= ID_MODE_DIS; 788 789 reg_writel(priv, reg, reg_rgmii_ctrl); 790 } 791 792 static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port, 793 phy_interface_t interface, bool link) 794 { 795 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 796 u32 reg_rgmii_ctrl; 797 u32 reg; 798 799 if (!phy_interface_mode_is_rgmii(interface) && 800 interface != PHY_INTERFACE_MODE_MII && 801 interface != PHY_INTERFACE_MODE_REVMII) 802 return; 803 804 reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port); 805 806 /* If the link is down, just disable the interface to conserve power */ 807 reg = reg_readl(priv, reg_rgmii_ctrl); 808 if (link) 809 reg |= RGMII_MODE_EN; 810 else 811 reg &= ~RGMII_MODE_EN; 812 reg_writel(priv, reg, reg_rgmii_ctrl); 813 } 814 815 static void bcm_sf2_sw_mac_link_down(struct phylink_config *config, 816 unsigned int mode, 817 phy_interface_t interface) 818 { 819 struct dsa_port *dp = dsa_phylink_to_port(config); 820 struct bcm_sf2_priv *priv; 821 int port = dp->index; 822 u32 reg, offset; 823 824 priv = bcm_sf2_to_priv(dp->ds); 825 if (priv->wol_ports_mask & BIT(port)) 826 return; 827 828 offset = bcm_sf2_port_override_offset(priv, port); 829 reg = core_readl(priv, offset); 830 reg &= ~LINK_STS; 831 core_writel(priv, reg, offset); 832 833 bcm_sf2_sw_mac_link_set(dp->ds, port, interface, false); 834 } 835 836 static void bcm_sf2_sw_mac_link_up(struct phylink_config *config, 837 struct phy_device *phydev, 838 unsigned int mode, 839 phy_interface_t interface, 840 int speed, int duplex, 841 bool tx_pause, bool rx_pause) 842 { 843 struct dsa_port *dp = dsa_phylink_to_port(config); 844 struct bcm_sf2_priv *priv; 845 u32 reg_rgmii_ctrl = 0; 846 struct ethtool_keee *p; 847 int port = dp->index; 848 u32 reg, offset; 849 850 bcm_sf2_sw_mac_link_set(dp->ds, port, interface, true); 851 852 priv = bcm_sf2_to_priv(dp->ds); 853 offset = bcm_sf2_port_override_offset(priv, port); 854 855 if (phy_interface_mode_is_rgmii(interface) || 856 interface == PHY_INTERFACE_MODE_MII || 857 interface == PHY_INTERFACE_MODE_REVMII) { 858 reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port); 859 reg = reg_readl(priv, reg_rgmii_ctrl); 860 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN); 861 862 if (tx_pause) 863 reg |= TX_PAUSE_EN; 864 if (rx_pause) 865 reg |= RX_PAUSE_EN; 866 867 reg_writel(priv, reg, reg_rgmii_ctrl); 868 } 869 870 reg = LINK_STS; 871 if (port == 8) { 872 if (priv->type == BCM4908_DEVICE_ID) 873 reg |= GMII_SPEED_UP_2G; 874 reg |= MII_SW_OR; 875 } else { 876 reg |= SW_OVERRIDE; 877 } 878 879 switch (speed) { 880 case SPEED_1000: 881 reg |= SPDSTS_1000 << SPEED_SHIFT; 882 break; 883 case SPEED_100: 884 reg |= SPDSTS_100 << SPEED_SHIFT; 885 break; 886 } 887 888 if (duplex == DUPLEX_FULL) 889 reg |= DUPLX_MODE; 890 891 if (tx_pause) 892 reg |= TXFLOW_CNTL; 893 if (rx_pause) 894 reg |= RXFLOW_CNTL; 895 896 core_writel(priv, reg, offset); 897 898 if (mode == MLO_AN_PHY && phydev) { 899 p = &priv->dev->ports[port].eee; 900 p->eee_enabled = b53_eee_init(dp->ds, port, phydev); 901 } 902 } 903 904 static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port, 905 struct phylink_link_state *status) 906 { 907 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 908 909 status->link = false; 910 911 /* MoCA port is special as we do not get link status from CORE_LNKSTS, 912 * which means that we need to force the link at the port override 913 * level to get the data to flow. We do use what the interrupt handler 914 * did determine before. 915 * 916 * For the other ports, we just force the link status, since this is 917 * a fixed PHY device. 918 */ 919 if (port == priv->moca_port) { 920 status->link = priv->port_sts[port].link; 921 /* For MoCA interfaces, also force a link down notification 922 * since some version of the user-space daemon (mocad) use 923 * cmd->autoneg to force the link, which messes up the PHY 924 * state machine and make it go in PHY_FORCING state instead. 925 */ 926 if (!status->link) 927 netif_carrier_off(dsa_to_port(ds, port)->user); 928 status->duplex = DUPLEX_FULL; 929 } else { 930 status->link = true; 931 } 932 } 933 934 static void bcm_sf2_enable_acb(struct dsa_switch *ds) 935 { 936 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 937 u32 reg; 938 939 /* Enable ACB globally */ 940 reg = acb_readl(priv, ACB_CONTROL); 941 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT); 942 acb_writel(priv, reg, ACB_CONTROL); 943 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT); 944 reg |= ACB_EN | ACB_ALGORITHM; 945 acb_writel(priv, reg, ACB_CONTROL); 946 } 947 948 static int bcm_sf2_sw_suspend(struct dsa_switch *ds) 949 { 950 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 951 unsigned int port; 952 953 bcm_sf2_intr_disable(priv); 954 955 /* Disable all ports physically present including the IMP 956 * port, the other ones have already been disabled during 957 * bcm_sf2_sw_setup 958 */ 959 for (port = 0; port < ds->num_ports; port++) { 960 if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port)) 961 bcm_sf2_port_disable(ds, port); 962 } 963 964 if (!priv->wol_ports_mask) 965 clk_disable_unprepare(priv->clk); 966 967 return 0; 968 } 969 970 static int bcm_sf2_sw_resume(struct dsa_switch *ds) 971 { 972 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 973 int ret; 974 975 if (!priv->wol_ports_mask) 976 clk_prepare_enable(priv->clk); 977 978 ret = bcm_sf2_sw_rst(priv); 979 if (ret) { 980 pr_err("%s: failed to software reset switch\n", __func__); 981 return ret; 982 } 983 984 bcm_sf2_crossbar_setup(priv); 985 986 ret = bcm_sf2_cfp_resume(ds); 987 if (ret) 988 return ret; 989 990 if (priv->hw_params.num_gphy == 1) 991 bcm_sf2_gphy_enable_set(ds, true); 992 993 ds->ops->setup(ds); 994 995 return 0; 996 } 997 998 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port, 999 struct ethtool_wolinfo *wol) 1000 { 1001 struct net_device *p = dsa_port_to_conduit(dsa_to_port(ds, port)); 1002 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 1003 struct ethtool_wolinfo pwol = { }; 1004 1005 /* Get the parent device WoL settings */ 1006 if (p->ethtool_ops->get_wol) 1007 p->ethtool_ops->get_wol(p, &pwol); 1008 1009 /* Advertise the parent device supported settings */ 1010 wol->supported = pwol.supported; 1011 memset(&wol->sopass, 0, sizeof(wol->sopass)); 1012 1013 if (pwol.wolopts & WAKE_MAGICSECURE) 1014 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass)); 1015 1016 if (priv->wol_ports_mask & (1 << port)) 1017 wol->wolopts = pwol.wolopts; 1018 else 1019 wol->wolopts = 0; 1020 } 1021 1022 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port, 1023 struct ethtool_wolinfo *wol) 1024 { 1025 struct net_device *p = dsa_port_to_conduit(dsa_to_port(ds, port)); 1026 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 1027 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 1028 struct ethtool_wolinfo pwol = { }; 1029 1030 if (p->ethtool_ops->get_wol) 1031 p->ethtool_ops->get_wol(p, &pwol); 1032 if (wol->wolopts & ~pwol.supported) 1033 return -EINVAL; 1034 1035 if (wol->wolopts) 1036 priv->wol_ports_mask |= (1 << port); 1037 else 1038 priv->wol_ports_mask &= ~(1 << port); 1039 1040 /* If we have at least one port enabled, make sure the CPU port 1041 * is also enabled. If the CPU port is the last one enabled, we disable 1042 * it since this configuration does not make sense. 1043 */ 1044 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port)) 1045 priv->wol_ports_mask |= (1 << cpu_port); 1046 else 1047 priv->wol_ports_mask &= ~(1 << cpu_port); 1048 1049 return p->ethtool_ops->set_wol(p, wol); 1050 } 1051 1052 static int bcm_sf2_sw_setup(struct dsa_switch *ds) 1053 { 1054 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 1055 unsigned int port; 1056 1057 /* Enable all valid ports and disable those unused */ 1058 for (port = 0; port < priv->hw_params.num_ports; port++) { 1059 /* IMP port receives special treatment */ 1060 if (dsa_is_user_port(ds, port)) 1061 bcm_sf2_port_setup(ds, port, NULL); 1062 else if (dsa_is_cpu_port(ds, port)) 1063 bcm_sf2_imp_setup(ds, port); 1064 else 1065 bcm_sf2_port_disable(ds, port); 1066 } 1067 1068 b53_configure_vlan(ds); 1069 bcm_sf2_enable_acb(ds); 1070 1071 return b53_setup_devlink_resources(ds); 1072 } 1073 1074 static void bcm_sf2_sw_teardown(struct dsa_switch *ds) 1075 { 1076 dsa_devlink_resources_unregister(ds); 1077 } 1078 1079 /* The SWITCH_CORE register space is managed by b53 but operates on a page + 1080 * register basis so we need to translate that into an address that the 1081 * bus-glue understands. 1082 */ 1083 #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2) 1084 1085 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg, 1086 u8 *val) 1087 { 1088 struct bcm_sf2_priv *priv = dev->priv; 1089 1090 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 1091 1092 return 0; 1093 } 1094 1095 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg, 1096 u16 *val) 1097 { 1098 struct bcm_sf2_priv *priv = dev->priv; 1099 1100 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 1101 1102 return 0; 1103 } 1104 1105 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg, 1106 u32 *val) 1107 { 1108 struct bcm_sf2_priv *priv = dev->priv; 1109 1110 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 1111 1112 return 0; 1113 } 1114 1115 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg, 1116 u64 *val) 1117 { 1118 struct bcm_sf2_priv *priv = dev->priv; 1119 1120 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg)); 1121 1122 return 0; 1123 } 1124 1125 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg, 1126 u8 value) 1127 { 1128 struct bcm_sf2_priv *priv = dev->priv; 1129 1130 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 1131 1132 return 0; 1133 } 1134 1135 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg, 1136 u16 value) 1137 { 1138 struct bcm_sf2_priv *priv = dev->priv; 1139 1140 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 1141 1142 return 0; 1143 } 1144 1145 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg, 1146 u32 value) 1147 { 1148 struct bcm_sf2_priv *priv = dev->priv; 1149 1150 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 1151 1152 return 0; 1153 } 1154 1155 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg, 1156 u64 value) 1157 { 1158 struct bcm_sf2_priv *priv = dev->priv; 1159 1160 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 1161 1162 return 0; 1163 } 1164 1165 static const struct b53_io_ops bcm_sf2_io_ops = { 1166 .read8 = bcm_sf2_core_read8, 1167 .read16 = bcm_sf2_core_read16, 1168 .read32 = bcm_sf2_core_read32, 1169 .read48 = bcm_sf2_core_read64, 1170 .read64 = bcm_sf2_core_read64, 1171 .write8 = bcm_sf2_core_write8, 1172 .write16 = bcm_sf2_core_write16, 1173 .write32 = bcm_sf2_core_write32, 1174 .write48 = bcm_sf2_core_write64, 1175 .write64 = bcm_sf2_core_write64, 1176 }; 1177 1178 static void bcm_sf2_sw_get_strings(struct dsa_switch *ds, int port, 1179 u32 stringset, uint8_t *data) 1180 { 1181 int cnt = b53_get_sset_count(ds, port, stringset); 1182 1183 b53_get_strings(ds, port, stringset, data); 1184 bcm_sf2_cfp_get_strings(ds, port, stringset, 1185 data + cnt * ETH_GSTRING_LEN); 1186 } 1187 1188 static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds, int port, 1189 uint64_t *data) 1190 { 1191 int cnt = b53_get_sset_count(ds, port, ETH_SS_STATS); 1192 1193 b53_get_ethtool_stats(ds, port, data); 1194 bcm_sf2_cfp_get_ethtool_stats(ds, port, data + cnt); 1195 } 1196 1197 static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds, int port, 1198 int sset) 1199 { 1200 int cnt = b53_get_sset_count(ds, port, sset); 1201 1202 if (cnt < 0) 1203 return cnt; 1204 1205 cnt += bcm_sf2_cfp_get_sset_count(ds, port, sset); 1206 1207 return cnt; 1208 } 1209 1210 static const struct phylink_mac_ops bcm_sf2_phylink_mac_ops = { 1211 .mac_config = bcm_sf2_sw_mac_config, 1212 .mac_link_down = bcm_sf2_sw_mac_link_down, 1213 .mac_link_up = bcm_sf2_sw_mac_link_up, 1214 }; 1215 1216 static const struct dsa_switch_ops bcm_sf2_ops = { 1217 .get_tag_protocol = b53_get_tag_protocol, 1218 .setup = bcm_sf2_sw_setup, 1219 .teardown = bcm_sf2_sw_teardown, 1220 .get_strings = bcm_sf2_sw_get_strings, 1221 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats, 1222 .get_sset_count = bcm_sf2_sw_get_sset_count, 1223 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 1224 .get_phy_flags = bcm_sf2_sw_get_phy_flags, 1225 .phylink_get_caps = bcm_sf2_sw_get_caps, 1226 .phylink_fixed_state = bcm_sf2_sw_fixed_state, 1227 .suspend = bcm_sf2_sw_suspend, 1228 .resume = bcm_sf2_sw_resume, 1229 .get_wol = bcm_sf2_sw_get_wol, 1230 .set_wol = bcm_sf2_sw_set_wol, 1231 .port_enable = bcm_sf2_port_setup, 1232 .port_disable = bcm_sf2_port_disable, 1233 .get_mac_eee = b53_get_mac_eee, 1234 .set_mac_eee = b53_set_mac_eee, 1235 .port_bridge_join = b53_br_join, 1236 .port_bridge_leave = b53_br_leave, 1237 .port_pre_bridge_flags = b53_br_flags_pre, 1238 .port_bridge_flags = b53_br_flags, 1239 .port_stp_state_set = b53_br_set_stp_state, 1240 .port_fast_age = b53_br_fast_age, 1241 .port_vlan_filtering = b53_vlan_filtering, 1242 .port_vlan_add = b53_vlan_add, 1243 .port_vlan_del = b53_vlan_del, 1244 .port_fdb_dump = b53_fdb_dump, 1245 .port_fdb_add = b53_fdb_add, 1246 .port_fdb_del = b53_fdb_del, 1247 .get_rxnfc = bcm_sf2_get_rxnfc, 1248 .set_rxnfc = bcm_sf2_set_rxnfc, 1249 .port_mirror_add = b53_mirror_add, 1250 .port_mirror_del = b53_mirror_del, 1251 .port_mdb_add = b53_mdb_add, 1252 .port_mdb_del = b53_mdb_del, 1253 }; 1254 1255 struct bcm_sf2_of_data { 1256 u32 type; 1257 const u16 *reg_offsets; 1258 unsigned int core_reg_align; 1259 unsigned int num_cfp_rules; 1260 unsigned int num_crossbar_int_ports; 1261 }; 1262 1263 static const u16 bcm_sf2_4908_reg_offsets[] = { 1264 [REG_SWITCH_CNTRL] = 0x00, 1265 [REG_SWITCH_STATUS] = 0x04, 1266 [REG_DIR_DATA_WRITE] = 0x08, 1267 [REG_DIR_DATA_READ] = 0x0c, 1268 [REG_SWITCH_REVISION] = 0x10, 1269 [REG_PHY_REVISION] = 0x14, 1270 [REG_SPHY_CNTRL] = 0x24, 1271 [REG_CROSSBAR] = 0xc8, 1272 [REG_RGMII_11_CNTRL] = 0x014c, 1273 [REG_LED_0_CNTRL] = 0x40, 1274 [REG_LED_1_CNTRL] = 0x4c, 1275 [REG_LED_2_CNTRL] = 0x58, 1276 [REG_LED_3_CNTRL] = 0x64, 1277 [REG_LED_4_CNTRL] = 0x88, 1278 [REG_LED_5_CNTRL] = 0xa0, 1279 [REG_LED_AGGREGATE_CTRL] = 0xb8, 1280 1281 }; 1282 1283 static const struct bcm_sf2_of_data bcm_sf2_4908_data = { 1284 .type = BCM4908_DEVICE_ID, 1285 .core_reg_align = 0, 1286 .reg_offsets = bcm_sf2_4908_reg_offsets, 1287 .num_cfp_rules = 256, 1288 .num_crossbar_int_ports = 2, 1289 }; 1290 1291 /* Register offsets for the SWITCH_REG_* block */ 1292 static const u16 bcm_sf2_7445_reg_offsets[] = { 1293 [REG_SWITCH_CNTRL] = 0x00, 1294 [REG_SWITCH_STATUS] = 0x04, 1295 [REG_DIR_DATA_WRITE] = 0x08, 1296 [REG_DIR_DATA_READ] = 0x0C, 1297 [REG_SWITCH_REVISION] = 0x18, 1298 [REG_PHY_REVISION] = 0x1C, 1299 [REG_SPHY_CNTRL] = 0x2C, 1300 [REG_RGMII_0_CNTRL] = 0x34, 1301 [REG_RGMII_1_CNTRL] = 0x40, 1302 [REG_RGMII_2_CNTRL] = 0x4c, 1303 [REG_LED_0_CNTRL] = 0x90, 1304 [REG_LED_1_CNTRL] = 0x94, 1305 [REG_LED_2_CNTRL] = 0x98, 1306 }; 1307 1308 static const struct bcm_sf2_of_data bcm_sf2_7445_data = { 1309 .type = BCM7445_DEVICE_ID, 1310 .core_reg_align = 0, 1311 .reg_offsets = bcm_sf2_7445_reg_offsets, 1312 .num_cfp_rules = 256, 1313 }; 1314 1315 static const u16 bcm_sf2_7278_reg_offsets[] = { 1316 [REG_SWITCH_CNTRL] = 0x00, 1317 [REG_SWITCH_STATUS] = 0x04, 1318 [REG_DIR_DATA_WRITE] = 0x08, 1319 [REG_DIR_DATA_READ] = 0x0c, 1320 [REG_SWITCH_REVISION] = 0x10, 1321 [REG_PHY_REVISION] = 0x14, 1322 [REG_SPHY_CNTRL] = 0x24, 1323 [REG_RGMII_0_CNTRL] = 0xe0, 1324 [REG_RGMII_1_CNTRL] = 0xec, 1325 [REG_RGMII_2_CNTRL] = 0xf8, 1326 [REG_LED_0_CNTRL] = 0x40, 1327 [REG_LED_1_CNTRL] = 0x4c, 1328 [REG_LED_2_CNTRL] = 0x58, 1329 }; 1330 1331 static const struct bcm_sf2_of_data bcm_sf2_7278_data = { 1332 .type = BCM7278_DEVICE_ID, 1333 .core_reg_align = 1, 1334 .reg_offsets = bcm_sf2_7278_reg_offsets, 1335 .num_cfp_rules = 128, 1336 }; 1337 1338 static const struct of_device_id bcm_sf2_of_match[] = { 1339 { .compatible = "brcm,bcm4908-switch", 1340 .data = &bcm_sf2_4908_data 1341 }, 1342 { .compatible = "brcm,bcm7445-switch-v4.0", 1343 .data = &bcm_sf2_7445_data 1344 }, 1345 { .compatible = "brcm,bcm7278-switch-v4.0", 1346 .data = &bcm_sf2_7278_data 1347 }, 1348 { .compatible = "brcm,bcm7278-switch-v4.8", 1349 .data = &bcm_sf2_7278_data 1350 }, 1351 { /* sentinel */ }, 1352 }; 1353 MODULE_DEVICE_TABLE(of, bcm_sf2_of_match); 1354 1355 static int bcm_sf2_sw_probe(struct platform_device *pdev) 1356 { 1357 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME; 1358 struct device_node *dn = pdev->dev.of_node; 1359 const struct of_device_id *of_id = NULL; 1360 const struct bcm_sf2_of_data *data; 1361 struct b53_platform_data *pdata; 1362 struct dsa_switch_ops *ops; 1363 struct device_node *ports; 1364 struct bcm_sf2_priv *priv; 1365 struct b53_device *dev; 1366 struct dsa_switch *ds; 1367 void __iomem **base; 1368 unsigned int i; 1369 u32 reg, rev; 1370 int ret; 1371 1372 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1373 if (!priv) 1374 return -ENOMEM; 1375 1376 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL); 1377 if (!ops) 1378 return -ENOMEM; 1379 1380 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv); 1381 if (!dev) 1382 return -ENOMEM; 1383 1384 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1385 if (!pdata) 1386 return -ENOMEM; 1387 1388 of_id = of_match_node(bcm_sf2_of_match, dn); 1389 if (!of_id || !of_id->data) 1390 return -EINVAL; 1391 1392 data = of_id->data; 1393 1394 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */ 1395 priv->type = data->type; 1396 priv->reg_offsets = data->reg_offsets; 1397 priv->core_reg_align = data->core_reg_align; 1398 priv->num_cfp_rules = data->num_cfp_rules; 1399 priv->num_crossbar_int_ports = data->num_crossbar_int_ports; 1400 1401 priv->rcdev = devm_reset_control_get_optional_exclusive(&pdev->dev, 1402 "switch"); 1403 if (IS_ERR(priv->rcdev)) 1404 return PTR_ERR(priv->rcdev); 1405 1406 /* Auto-detection using standard registers will not work, so 1407 * provide an indication of what kind of device we are for 1408 * b53_common to work with 1409 */ 1410 pdata->chip_id = priv->type; 1411 dev->pdata = pdata; 1412 1413 priv->dev = dev; 1414 ds = dev->ds; 1415 ds->ops = &bcm_sf2_ops; 1416 ds->phylink_mac_ops = &bcm_sf2_phylink_mac_ops; 1417 1418 /* Advertise the 8 egress queues */ 1419 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES; 1420 1421 dev_set_drvdata(&pdev->dev, priv); 1422 1423 spin_lock_init(&priv->indir_lock); 1424 mutex_init(&priv->cfp.lock); 1425 INIT_LIST_HEAD(&priv->cfp.rules_list); 1426 1427 /* CFP rule #0 cannot be used for specific classifications, flag it as 1428 * permanently used 1429 */ 1430 set_bit(0, priv->cfp.used); 1431 set_bit(0, priv->cfp.unique); 1432 1433 /* Balance of_node_put() done by of_find_node_by_name() */ 1434 of_node_get(dn); 1435 ports = of_find_node_by_name(dn, "ports"); 1436 if (ports) { 1437 bcm_sf2_identify_ports(priv, ports); 1438 of_node_put(ports); 1439 } 1440 1441 priv->irq0 = irq_of_parse_and_map(dn, 0); 1442 priv->irq1 = irq_of_parse_and_map(dn, 1); 1443 1444 base = &priv->core; 1445 for (i = 0; i < BCM_SF2_REGS_NUM; i++) { 1446 *base = devm_platform_ioremap_resource(pdev, i); 1447 if (IS_ERR(*base)) { 1448 pr_err("unable to find register: %s\n", reg_names[i]); 1449 return PTR_ERR(*base); 1450 } 1451 base++; 1452 } 1453 1454 priv->clk = devm_clk_get_optional(&pdev->dev, "sw_switch"); 1455 if (IS_ERR(priv->clk)) 1456 return PTR_ERR(priv->clk); 1457 1458 ret = clk_prepare_enable(priv->clk); 1459 if (ret) 1460 return ret; 1461 1462 priv->clk_mdiv = devm_clk_get_optional(&pdev->dev, "sw_switch_mdiv"); 1463 if (IS_ERR(priv->clk_mdiv)) { 1464 ret = PTR_ERR(priv->clk_mdiv); 1465 goto out_clk; 1466 } 1467 1468 ret = clk_prepare_enable(priv->clk_mdiv); 1469 if (ret) 1470 goto out_clk; 1471 1472 ret = bcm_sf2_sw_rst(priv); 1473 if (ret) { 1474 pr_err("unable to software reset switch: %d\n", ret); 1475 goto out_clk_mdiv; 1476 } 1477 1478 bcm_sf2_crossbar_setup(priv); 1479 1480 bcm_sf2_gphy_enable_set(priv->dev->ds, true); 1481 1482 ret = bcm_sf2_mdio_register(ds); 1483 if (ret) { 1484 pr_err("failed to register MDIO bus\n"); 1485 goto out_clk_mdiv; 1486 } 1487 1488 bcm_sf2_gphy_enable_set(priv->dev->ds, false); 1489 1490 ret = bcm_sf2_cfp_rst(priv); 1491 if (ret) { 1492 pr_err("failed to reset CFP\n"); 1493 goto out_mdio; 1494 } 1495 1496 /* Disable all interrupts and request them */ 1497 bcm_sf2_intr_disable(priv); 1498 1499 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0, 1500 "switch_0", ds); 1501 if (ret < 0) { 1502 pr_err("failed to request switch_0 IRQ\n"); 1503 goto out_mdio; 1504 } 1505 1506 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0, 1507 "switch_1", ds); 1508 if (ret < 0) { 1509 pr_err("failed to request switch_1 IRQ\n"); 1510 goto out_mdio; 1511 } 1512 1513 /* Reset the MIB counters */ 1514 reg = core_readl(priv, CORE_GMNCFGCFG); 1515 reg |= RST_MIB_CNT; 1516 core_writel(priv, reg, CORE_GMNCFGCFG); 1517 reg &= ~RST_MIB_CNT; 1518 core_writel(priv, reg, CORE_GMNCFGCFG); 1519 1520 /* Get the maximum number of ports for this switch */ 1521 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1; 1522 if (priv->hw_params.num_ports > DSA_MAX_PORTS) 1523 priv->hw_params.num_ports = DSA_MAX_PORTS; 1524 1525 /* Assume a single GPHY setup if we can't read that property */ 1526 if (of_property_read_u32(dn, "brcm,num-gphy", 1527 &priv->hw_params.num_gphy)) 1528 priv->hw_params.num_gphy = 1; 1529 1530 rev = reg_readl(priv, REG_SWITCH_REVISION); 1531 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) & 1532 SWITCH_TOP_REV_MASK; 1533 priv->hw_params.core_rev = (rev & SF2_REV_MASK); 1534 1535 rev = reg_readl(priv, REG_PHY_REVISION); 1536 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK; 1537 1538 ret = b53_switch_register(dev); 1539 if (ret) 1540 goto out_mdio; 1541 1542 dev_info(&pdev->dev, 1543 "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n", 1544 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff, 1545 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff, 1546 priv->irq0, priv->irq1); 1547 1548 return 0; 1549 1550 out_mdio: 1551 bcm_sf2_mdio_unregister(priv); 1552 out_clk_mdiv: 1553 clk_disable_unprepare(priv->clk_mdiv); 1554 out_clk: 1555 clk_disable_unprepare(priv->clk); 1556 return ret; 1557 } 1558 1559 static void bcm_sf2_sw_remove(struct platform_device *pdev) 1560 { 1561 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1562 1563 if (!priv) 1564 return; 1565 1566 priv->wol_ports_mask = 0; 1567 /* Disable interrupts */ 1568 bcm_sf2_intr_disable(priv); 1569 dsa_unregister_switch(priv->dev->ds); 1570 bcm_sf2_cfp_exit(priv->dev->ds); 1571 bcm_sf2_mdio_unregister(priv); 1572 clk_disable_unprepare(priv->clk_mdiv); 1573 clk_disable_unprepare(priv->clk); 1574 if (priv->type == BCM7278_DEVICE_ID) 1575 reset_control_assert(priv->rcdev); 1576 } 1577 1578 static void bcm_sf2_sw_shutdown(struct platform_device *pdev) 1579 { 1580 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1581 1582 if (!priv) 1583 return; 1584 1585 /* For a kernel about to be kexec'd we want to keep the GPHY on for a 1586 * successful MDIO bus scan to occur. If we did turn off the GPHY 1587 * before (e.g: port_disable), this will also power it back on. 1588 * 1589 * Do not rely on kexec_in_progress, just power the PHY on. 1590 */ 1591 if (priv->hw_params.num_gphy == 1) 1592 bcm_sf2_gphy_enable_set(priv->dev->ds, true); 1593 1594 dsa_switch_shutdown(priv->dev->ds); 1595 1596 platform_set_drvdata(pdev, NULL); 1597 } 1598 1599 #ifdef CONFIG_PM_SLEEP 1600 static int bcm_sf2_suspend(struct device *dev) 1601 { 1602 struct bcm_sf2_priv *priv = dev_get_drvdata(dev); 1603 1604 return dsa_switch_suspend(priv->dev->ds); 1605 } 1606 1607 static int bcm_sf2_resume(struct device *dev) 1608 { 1609 struct bcm_sf2_priv *priv = dev_get_drvdata(dev); 1610 1611 return dsa_switch_resume(priv->dev->ds); 1612 } 1613 #endif /* CONFIG_PM_SLEEP */ 1614 1615 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops, 1616 bcm_sf2_suspend, bcm_sf2_resume); 1617 1618 1619 static struct platform_driver bcm_sf2_driver = { 1620 .probe = bcm_sf2_sw_probe, 1621 .remove_new = bcm_sf2_sw_remove, 1622 .shutdown = bcm_sf2_sw_shutdown, 1623 .driver = { 1624 .name = "brcm-sf2", 1625 .of_match_table = bcm_sf2_of_match, 1626 .pm = &bcm_sf2_pm_ops, 1627 }, 1628 }; 1629 module_platform_driver(bcm_sf2_driver); 1630 1631 MODULE_AUTHOR("Broadcom Corporation"); 1632 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip"); 1633 MODULE_LICENSE("GPL"); 1634 MODULE_ALIAS("platform:brcm-sf2"); 1635