1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Broadcom Starfighter 2 DSA switch driver 4 * 5 * Copyright (C) 2014, Broadcom Corporation 6 */ 7 8 #include <linux/list.h> 9 #include <linux/module.h> 10 #include <linux/netdevice.h> 11 #include <linux/interrupt.h> 12 #include <linux/platform_device.h> 13 #include <linux/phy.h> 14 #include <linux/phy_fixed.h> 15 #include <linux/phylink.h> 16 #include <linux/mii.h> 17 #include <linux/of.h> 18 #include <linux/of_irq.h> 19 #include <linux/of_address.h> 20 #include <linux/of_net.h> 21 #include <linux/of_mdio.h> 22 #include <net/dsa.h> 23 #include <linux/ethtool.h> 24 #include <linux/if_bridge.h> 25 #include <linux/brcmphy.h> 26 #include <linux/etherdevice.h> 27 #include <linux/platform_data/b53.h> 28 29 #include "bcm_sf2.h" 30 #include "bcm_sf2_regs.h" 31 #include "b53/b53_priv.h" 32 #include "b53/b53_regs.h" 33 34 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port) 35 { 36 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 37 unsigned int i; 38 u32 reg, offset; 39 40 /* Enable the port memories */ 41 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 42 reg &= ~P_TXQ_PSM_VDD(port); 43 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 44 45 /* Enable forwarding */ 46 core_writel(priv, SW_FWDG_EN, CORE_SWMODE); 47 48 /* Enable IMP port in dumb mode */ 49 reg = core_readl(priv, CORE_SWITCH_CTRL); 50 reg |= MII_DUMB_FWDG_EN; 51 core_writel(priv, reg, CORE_SWITCH_CTRL); 52 53 /* Configure Traffic Class to QoS mapping, allow each priority to map 54 * to a different queue number 55 */ 56 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); 57 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) 58 reg |= i << (PRT_TO_QID_SHIFT * i); 59 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); 60 61 b53_brcm_hdr_setup(ds, port); 62 63 if (port == 8) { 64 if (priv->type == BCM7445_DEVICE_ID) 65 offset = CORE_STS_OVERRIDE_IMP; 66 else 67 offset = CORE_STS_OVERRIDE_IMP2; 68 69 /* Force link status for IMP port */ 70 reg = core_readl(priv, offset); 71 reg |= (MII_SW_OR | LINK_STS); 72 reg &= ~GMII_SPEED_UP_2G; 73 core_writel(priv, reg, offset); 74 75 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */ 76 reg = core_readl(priv, CORE_IMP_CTL); 77 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN); 78 reg &= ~(RX_DIS | TX_DIS); 79 core_writel(priv, reg, CORE_IMP_CTL); 80 } else { 81 reg = core_readl(priv, CORE_G_PCTL_PORT(port)); 82 reg &= ~(RX_DIS | TX_DIS); 83 core_writel(priv, reg, CORE_G_PCTL_PORT(port)); 84 } 85 } 86 87 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable) 88 { 89 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 90 u32 reg; 91 92 reg = reg_readl(priv, REG_SPHY_CNTRL); 93 if (enable) { 94 reg |= PHY_RESET; 95 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS); 96 reg_writel(priv, reg, REG_SPHY_CNTRL); 97 udelay(21); 98 reg = reg_readl(priv, REG_SPHY_CNTRL); 99 reg &= ~PHY_RESET; 100 } else { 101 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET; 102 reg_writel(priv, reg, REG_SPHY_CNTRL); 103 mdelay(1); 104 reg |= CK25_DIS; 105 } 106 reg_writel(priv, reg, REG_SPHY_CNTRL); 107 108 /* Use PHY-driven LED signaling */ 109 if (!enable) { 110 reg = reg_readl(priv, REG_LED_CNTRL(0)); 111 reg |= SPDLNK_SRC_SEL; 112 reg_writel(priv, reg, REG_LED_CNTRL(0)); 113 } 114 } 115 116 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv, 117 int port) 118 { 119 unsigned int off; 120 121 switch (port) { 122 case 7: 123 off = P7_IRQ_OFF; 124 break; 125 case 0: 126 /* Port 0 interrupts are located on the first bank */ 127 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF)); 128 return; 129 default: 130 off = P_IRQ_OFF(port); 131 break; 132 } 133 134 intrl2_1_mask_clear(priv, P_IRQ_MASK(off)); 135 } 136 137 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv, 138 int port) 139 { 140 unsigned int off; 141 142 switch (port) { 143 case 7: 144 off = P7_IRQ_OFF; 145 break; 146 case 0: 147 /* Port 0 interrupts are located on the first bank */ 148 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF)); 149 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR); 150 return; 151 default: 152 off = P_IRQ_OFF(port); 153 break; 154 } 155 156 intrl2_1_mask_set(priv, P_IRQ_MASK(off)); 157 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR); 158 } 159 160 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port, 161 struct phy_device *phy) 162 { 163 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 164 unsigned int i; 165 u32 reg; 166 167 if (!dsa_is_user_port(ds, port)) 168 return 0; 169 170 /* Clear the memory power down */ 171 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 172 reg &= ~P_TXQ_PSM_VDD(port); 173 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 174 175 /* Enable learning */ 176 reg = core_readl(priv, CORE_DIS_LEARN); 177 reg &= ~BIT(port); 178 core_writel(priv, reg, CORE_DIS_LEARN); 179 180 /* Enable Broadcom tags for that port if requested */ 181 if (priv->brcm_tag_mask & BIT(port)) 182 b53_brcm_hdr_setup(ds, port); 183 184 /* Configure Traffic Class to QoS mapping, allow each priority to map 185 * to a different queue number 186 */ 187 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); 188 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) 189 reg |= i << (PRT_TO_QID_SHIFT * i); 190 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); 191 192 /* Re-enable the GPHY and re-apply workarounds */ 193 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) { 194 bcm_sf2_gphy_enable_set(ds, true); 195 if (phy) { 196 /* if phy_stop() has been called before, phy 197 * will be in halted state, and phy_start() 198 * will call resume. 199 * 200 * the resume path does not configure back 201 * autoneg settings, and since we hard reset 202 * the phy manually here, we need to reset the 203 * state machine also. 204 */ 205 phy->state = PHY_READY; 206 phy_init_hw(phy); 207 } 208 } 209 210 /* Enable MoCA port interrupts to get notified */ 211 if (port == priv->moca_port) 212 bcm_sf2_port_intr_enable(priv, port); 213 214 /* Set per-queue pause threshold to 32 */ 215 core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port)); 216 217 /* Set ACB threshold to 24 */ 218 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) { 219 reg = acb_readl(priv, ACB_QUEUE_CFG(port * 220 SF2_NUM_EGRESS_QUEUES + i)); 221 reg &= ~XOFF_THRESHOLD_MASK; 222 reg |= 24; 223 acb_writel(priv, reg, ACB_QUEUE_CFG(port * 224 SF2_NUM_EGRESS_QUEUES + i)); 225 } 226 227 return b53_enable_port(ds, port, phy); 228 } 229 230 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port) 231 { 232 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 233 u32 reg; 234 235 /* Disable learning while in WoL mode */ 236 if (priv->wol_ports_mask & (1 << port)) { 237 reg = core_readl(priv, CORE_DIS_LEARN); 238 reg |= BIT(port); 239 core_writel(priv, reg, CORE_DIS_LEARN); 240 return; 241 } 242 243 if (port == priv->moca_port) 244 bcm_sf2_port_intr_disable(priv, port); 245 246 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) 247 bcm_sf2_gphy_enable_set(ds, false); 248 249 b53_disable_port(ds, port); 250 251 /* Power down the port memory */ 252 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 253 reg |= P_TXQ_PSM_VDD(port); 254 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 255 } 256 257 258 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr, 259 int regnum, u16 val) 260 { 261 int ret = 0; 262 u32 reg; 263 264 reg = reg_readl(priv, REG_SWITCH_CNTRL); 265 reg |= MDIO_MASTER_SEL; 266 reg_writel(priv, reg, REG_SWITCH_CNTRL); 267 268 /* Page << 8 | offset */ 269 reg = 0x70; 270 reg <<= 2; 271 core_writel(priv, addr, reg); 272 273 /* Page << 8 | offset */ 274 reg = 0x80 << 8 | regnum << 1; 275 reg <<= 2; 276 277 if (op) 278 ret = core_readl(priv, reg); 279 else 280 core_writel(priv, val, reg); 281 282 reg = reg_readl(priv, REG_SWITCH_CNTRL); 283 reg &= ~MDIO_MASTER_SEL; 284 reg_writel(priv, reg, REG_SWITCH_CNTRL); 285 286 return ret & 0xffff; 287 } 288 289 static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 290 { 291 struct bcm_sf2_priv *priv = bus->priv; 292 293 /* Intercept reads from Broadcom pseudo-PHY address, else, send 294 * them to our master MDIO bus controller 295 */ 296 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) 297 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0); 298 else 299 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum); 300 } 301 302 static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 303 u16 val) 304 { 305 struct bcm_sf2_priv *priv = bus->priv; 306 307 /* Intercept writes to the Broadcom pseudo-PHY address, else, 308 * send them to our master MDIO bus controller 309 */ 310 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) 311 return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val); 312 else 313 return mdiobus_write_nested(priv->master_mii_bus, addr, 314 regnum, val); 315 } 316 317 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id) 318 { 319 struct dsa_switch *ds = dev_id; 320 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 321 322 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) & 323 ~priv->irq0_mask; 324 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR); 325 326 return IRQ_HANDLED; 327 } 328 329 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id) 330 { 331 struct dsa_switch *ds = dev_id; 332 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 333 334 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) & 335 ~priv->irq1_mask; 336 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR); 337 338 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) { 339 priv->port_sts[7].link = true; 340 dsa_port_phylink_mac_change(ds, 7, true); 341 } 342 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) { 343 priv->port_sts[7].link = false; 344 dsa_port_phylink_mac_change(ds, 7, false); 345 } 346 347 return IRQ_HANDLED; 348 } 349 350 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv) 351 { 352 unsigned int timeout = 1000; 353 u32 reg; 354 int ret; 355 356 /* The watchdog reset does not work on 7278, we need to hit the 357 * "external" reset line through the reset controller. 358 */ 359 if (priv->type == BCM7278_DEVICE_ID && !IS_ERR(priv->rcdev)) { 360 ret = reset_control_assert(priv->rcdev); 361 if (ret) 362 return ret; 363 364 return reset_control_deassert(priv->rcdev); 365 } 366 367 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 368 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET; 369 core_writel(priv, reg, CORE_WATCHDOG_CTRL); 370 371 do { 372 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 373 if (!(reg & SOFTWARE_RESET)) 374 break; 375 376 usleep_range(1000, 2000); 377 } while (timeout-- > 0); 378 379 if (timeout == 0) 380 return -ETIMEDOUT; 381 382 return 0; 383 } 384 385 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv) 386 { 387 intrl2_0_mask_set(priv, 0xffffffff); 388 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 389 intrl2_1_mask_set(priv, 0xffffffff); 390 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 391 } 392 393 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv, 394 struct device_node *dn) 395 { 396 struct device_node *port; 397 unsigned int port_num; 398 phy_interface_t mode; 399 int err; 400 401 priv->moca_port = -1; 402 403 for_each_available_child_of_node(dn, port) { 404 if (of_property_read_u32(port, "reg", &port_num)) 405 continue; 406 407 /* Internal PHYs get assigned a specific 'phy-mode' property 408 * value: "internal" to help flag them before MDIO probing 409 * has completed, since they might be turned off at that 410 * time 411 */ 412 err = of_get_phy_mode(port, &mode); 413 if (err) 414 continue; 415 416 if (mode == PHY_INTERFACE_MODE_INTERNAL) 417 priv->int_phy_mask |= 1 << port_num; 418 419 if (mode == PHY_INTERFACE_MODE_MOCA) 420 priv->moca_port = port_num; 421 422 if (of_property_read_bool(port, "brcm,use-bcm-hdr")) 423 priv->brcm_tag_mask |= 1 << port_num; 424 } 425 } 426 427 static int bcm_sf2_mdio_register(struct dsa_switch *ds) 428 { 429 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 430 struct device_node *dn; 431 static int index; 432 int err; 433 434 /* Find our integrated MDIO bus node */ 435 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio"); 436 priv->master_mii_bus = of_mdio_find_bus(dn); 437 if (!priv->master_mii_bus) 438 return -EPROBE_DEFER; 439 440 get_device(&priv->master_mii_bus->dev); 441 priv->master_mii_dn = dn; 442 443 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev); 444 if (!priv->slave_mii_bus) 445 return -ENOMEM; 446 447 priv->slave_mii_bus->priv = priv; 448 priv->slave_mii_bus->name = "sf2 slave mii"; 449 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read; 450 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write; 451 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d", 452 index++); 453 priv->slave_mii_bus->dev.of_node = dn; 454 455 /* Include the pseudo-PHY address to divert reads towards our 456 * workaround. This is only required for 7445D0, since 7445E0 457 * disconnects the internal switch pseudo-PHY such that we can use the 458 * regular SWITCH_MDIO master controller instead. 459 * 460 * Here we flag the pseudo PHY as needing special treatment and would 461 * otherwise make all other PHY read/writes go to the master MDIO bus 462 * controller that comes with this switch backed by the "mdio-unimac" 463 * driver. 464 */ 465 if (of_machine_is_compatible("brcm,bcm7445d0")) 466 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR); 467 else 468 priv->indir_phy_mask = 0; 469 470 ds->phys_mii_mask = priv->indir_phy_mask; 471 ds->slave_mii_bus = priv->slave_mii_bus; 472 priv->slave_mii_bus->parent = ds->dev->parent; 473 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask; 474 475 err = of_mdiobus_register(priv->slave_mii_bus, dn); 476 if (err && dn) 477 of_node_put(dn); 478 479 return err; 480 } 481 482 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv) 483 { 484 mdiobus_unregister(priv->slave_mii_bus); 485 of_node_put(priv->master_mii_dn); 486 } 487 488 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port) 489 { 490 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 491 492 /* The BCM7xxx PHY driver expects to find the integrated PHY revision 493 * in bits 15:8 and the patch level in bits 7:0 which is exactly what 494 * the REG_PHY_REVISION register layout is. 495 */ 496 497 return priv->hw_params.gphy_rev; 498 } 499 500 static void bcm_sf2_sw_validate(struct dsa_switch *ds, int port, 501 unsigned long *supported, 502 struct phylink_link_state *state) 503 { 504 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 505 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 506 507 if (!phy_interface_mode_is_rgmii(state->interface) && 508 state->interface != PHY_INTERFACE_MODE_MII && 509 state->interface != PHY_INTERFACE_MODE_REVMII && 510 state->interface != PHY_INTERFACE_MODE_GMII && 511 state->interface != PHY_INTERFACE_MODE_INTERNAL && 512 state->interface != PHY_INTERFACE_MODE_MOCA) { 513 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 514 if (port != core_readl(priv, CORE_IMP0_PRT_ID)) 515 dev_err(ds->dev, 516 "Unsupported interface: %d for port %d\n", 517 state->interface, port); 518 return; 519 } 520 521 /* Allow all the expected bits */ 522 phylink_set(mask, Autoneg); 523 phylink_set_port_modes(mask); 524 phylink_set(mask, Pause); 525 phylink_set(mask, Asym_Pause); 526 527 /* With the exclusion of MII and Reverse MII, we support Gigabit, 528 * including Half duplex 529 */ 530 if (state->interface != PHY_INTERFACE_MODE_MII && 531 state->interface != PHY_INTERFACE_MODE_REVMII) { 532 phylink_set(mask, 1000baseT_Full); 533 phylink_set(mask, 1000baseT_Half); 534 } 535 536 phylink_set(mask, 10baseT_Half); 537 phylink_set(mask, 10baseT_Full); 538 phylink_set(mask, 100baseT_Half); 539 phylink_set(mask, 100baseT_Full); 540 541 bitmap_and(supported, supported, mask, 542 __ETHTOOL_LINK_MODE_MASK_NBITS); 543 bitmap_and(state->advertising, state->advertising, mask, 544 __ETHTOOL_LINK_MODE_MASK_NBITS); 545 } 546 547 static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port, 548 unsigned int mode, 549 const struct phylink_link_state *state) 550 { 551 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 552 u32 id_mode_dis = 0, port_mode; 553 u32 reg, offset; 554 555 if (port == core_readl(priv, CORE_IMP0_PRT_ID)) 556 return; 557 558 if (priv->type == BCM7445_DEVICE_ID) 559 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port); 560 else 561 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port); 562 563 switch (state->interface) { 564 case PHY_INTERFACE_MODE_RGMII: 565 id_mode_dis = 1; 566 /* fallthrough */ 567 case PHY_INTERFACE_MODE_RGMII_TXID: 568 port_mode = EXT_GPHY; 569 break; 570 case PHY_INTERFACE_MODE_MII: 571 port_mode = EXT_EPHY; 572 break; 573 case PHY_INTERFACE_MODE_REVMII: 574 port_mode = EXT_REVMII; 575 break; 576 default: 577 /* all other PHYs: internal and MoCA */ 578 goto force_link; 579 } 580 581 /* Clear id_mode_dis bit, and the existing port mode, let 582 * RGMII_MODE_EN bet set by mac_link_{up,down} 583 */ 584 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); 585 reg &= ~ID_MODE_DIS; 586 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT); 587 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN); 588 589 reg |= port_mode; 590 if (id_mode_dis) 591 reg |= ID_MODE_DIS; 592 593 if (state->pause & MLO_PAUSE_TXRX_MASK) { 594 if (state->pause & MLO_PAUSE_TX) 595 reg |= TX_PAUSE_EN; 596 reg |= RX_PAUSE_EN; 597 } 598 599 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); 600 601 force_link: 602 /* Force link settings detected from the PHY */ 603 reg = SW_OVERRIDE; 604 switch (state->speed) { 605 case SPEED_1000: 606 reg |= SPDSTS_1000 << SPEED_SHIFT; 607 break; 608 case SPEED_100: 609 reg |= SPDSTS_100 << SPEED_SHIFT; 610 break; 611 } 612 613 if (state->link) 614 reg |= LINK_STS; 615 if (state->duplex == DUPLEX_FULL) 616 reg |= DUPLX_MODE; 617 618 core_writel(priv, reg, offset); 619 } 620 621 static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port, 622 phy_interface_t interface, bool link) 623 { 624 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 625 u32 reg; 626 627 if (!phy_interface_mode_is_rgmii(interface) && 628 interface != PHY_INTERFACE_MODE_MII && 629 interface != PHY_INTERFACE_MODE_REVMII) 630 return; 631 632 /* If the link is down, just disable the interface to conserve power */ 633 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); 634 if (link) 635 reg |= RGMII_MODE_EN; 636 else 637 reg &= ~RGMII_MODE_EN; 638 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); 639 } 640 641 static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port, 642 unsigned int mode, 643 phy_interface_t interface) 644 { 645 bcm_sf2_sw_mac_link_set(ds, port, interface, false); 646 } 647 648 static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port, 649 unsigned int mode, 650 phy_interface_t interface, 651 struct phy_device *phydev, 652 int speed, int duplex, 653 bool tx_pause, bool rx_pause) 654 { 655 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 656 struct ethtool_eee *p = &priv->dev->ports[port].eee; 657 658 bcm_sf2_sw_mac_link_set(ds, port, interface, true); 659 660 if (mode == MLO_AN_PHY && phydev) 661 p->eee_enabled = b53_eee_init(ds, port, phydev); 662 } 663 664 static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port, 665 struct phylink_link_state *status) 666 { 667 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 668 669 status->link = false; 670 671 /* MoCA port is special as we do not get link status from CORE_LNKSTS, 672 * which means that we need to force the link at the port override 673 * level to get the data to flow. We do use what the interrupt handler 674 * did determine before. 675 * 676 * For the other ports, we just force the link status, since this is 677 * a fixed PHY device. 678 */ 679 if (port == priv->moca_port) { 680 status->link = priv->port_sts[port].link; 681 /* For MoCA interfaces, also force a link down notification 682 * since some version of the user-space daemon (mocad) use 683 * cmd->autoneg to force the link, which messes up the PHY 684 * state machine and make it go in PHY_FORCING state instead. 685 */ 686 if (!status->link) 687 netif_carrier_off(dsa_to_port(ds, port)->slave); 688 status->duplex = DUPLEX_FULL; 689 } else { 690 status->link = true; 691 } 692 } 693 694 static void bcm_sf2_enable_acb(struct dsa_switch *ds) 695 { 696 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 697 u32 reg; 698 699 /* Enable ACB globally */ 700 reg = acb_readl(priv, ACB_CONTROL); 701 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT); 702 acb_writel(priv, reg, ACB_CONTROL); 703 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT); 704 reg |= ACB_EN | ACB_ALGORITHM; 705 acb_writel(priv, reg, ACB_CONTROL); 706 } 707 708 static int bcm_sf2_sw_suspend(struct dsa_switch *ds) 709 { 710 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 711 unsigned int port; 712 713 bcm_sf2_intr_disable(priv); 714 715 /* Disable all ports physically present including the IMP 716 * port, the other ones have already been disabled during 717 * bcm_sf2_sw_setup 718 */ 719 for (port = 0; port < ds->num_ports; port++) { 720 if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port)) 721 bcm_sf2_port_disable(ds, port); 722 } 723 724 return 0; 725 } 726 727 static int bcm_sf2_sw_resume(struct dsa_switch *ds) 728 { 729 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 730 int ret; 731 732 ret = bcm_sf2_sw_rst(priv); 733 if (ret) { 734 pr_err("%s: failed to software reset switch\n", __func__); 735 return ret; 736 } 737 738 ret = bcm_sf2_cfp_resume(ds); 739 if (ret) 740 return ret; 741 742 if (priv->hw_params.num_gphy == 1) 743 bcm_sf2_gphy_enable_set(ds, true); 744 745 ds->ops->setup(ds); 746 747 return 0; 748 } 749 750 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port, 751 struct ethtool_wolinfo *wol) 752 { 753 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master; 754 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 755 struct ethtool_wolinfo pwol = { }; 756 757 /* Get the parent device WoL settings */ 758 if (p->ethtool_ops->get_wol) 759 p->ethtool_ops->get_wol(p, &pwol); 760 761 /* Advertise the parent device supported settings */ 762 wol->supported = pwol.supported; 763 memset(&wol->sopass, 0, sizeof(wol->sopass)); 764 765 if (pwol.wolopts & WAKE_MAGICSECURE) 766 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass)); 767 768 if (priv->wol_ports_mask & (1 << port)) 769 wol->wolopts = pwol.wolopts; 770 else 771 wol->wolopts = 0; 772 } 773 774 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port, 775 struct ethtool_wolinfo *wol) 776 { 777 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master; 778 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 779 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 780 struct ethtool_wolinfo pwol = { }; 781 782 if (p->ethtool_ops->get_wol) 783 p->ethtool_ops->get_wol(p, &pwol); 784 if (wol->wolopts & ~pwol.supported) 785 return -EINVAL; 786 787 if (wol->wolopts) 788 priv->wol_ports_mask |= (1 << port); 789 else 790 priv->wol_ports_mask &= ~(1 << port); 791 792 /* If we have at least one port enabled, make sure the CPU port 793 * is also enabled. If the CPU port is the last one enabled, we disable 794 * it since this configuration does not make sense. 795 */ 796 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port)) 797 priv->wol_ports_mask |= (1 << cpu_port); 798 else 799 priv->wol_ports_mask &= ~(1 << cpu_port); 800 801 return p->ethtool_ops->set_wol(p, wol); 802 } 803 804 static int bcm_sf2_sw_setup(struct dsa_switch *ds) 805 { 806 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 807 unsigned int port; 808 809 /* Enable all valid ports and disable those unused */ 810 for (port = 0; port < priv->hw_params.num_ports; port++) { 811 /* IMP port receives special treatment */ 812 if (dsa_is_user_port(ds, port)) 813 bcm_sf2_port_setup(ds, port, NULL); 814 else if (dsa_is_cpu_port(ds, port)) 815 bcm_sf2_imp_setup(ds, port); 816 else 817 bcm_sf2_port_disable(ds, port); 818 } 819 820 b53_configure_vlan(ds); 821 bcm_sf2_enable_acb(ds); 822 823 return 0; 824 } 825 826 /* The SWITCH_CORE register space is managed by b53 but operates on a page + 827 * register basis so we need to translate that into an address that the 828 * bus-glue understands. 829 */ 830 #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2) 831 832 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg, 833 u8 *val) 834 { 835 struct bcm_sf2_priv *priv = dev->priv; 836 837 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 838 839 return 0; 840 } 841 842 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg, 843 u16 *val) 844 { 845 struct bcm_sf2_priv *priv = dev->priv; 846 847 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 848 849 return 0; 850 } 851 852 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg, 853 u32 *val) 854 { 855 struct bcm_sf2_priv *priv = dev->priv; 856 857 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 858 859 return 0; 860 } 861 862 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg, 863 u64 *val) 864 { 865 struct bcm_sf2_priv *priv = dev->priv; 866 867 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg)); 868 869 return 0; 870 } 871 872 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg, 873 u8 value) 874 { 875 struct bcm_sf2_priv *priv = dev->priv; 876 877 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 878 879 return 0; 880 } 881 882 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg, 883 u16 value) 884 { 885 struct bcm_sf2_priv *priv = dev->priv; 886 887 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 888 889 return 0; 890 } 891 892 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg, 893 u32 value) 894 { 895 struct bcm_sf2_priv *priv = dev->priv; 896 897 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 898 899 return 0; 900 } 901 902 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg, 903 u64 value) 904 { 905 struct bcm_sf2_priv *priv = dev->priv; 906 907 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 908 909 return 0; 910 } 911 912 static const struct b53_io_ops bcm_sf2_io_ops = { 913 .read8 = bcm_sf2_core_read8, 914 .read16 = bcm_sf2_core_read16, 915 .read32 = bcm_sf2_core_read32, 916 .read48 = bcm_sf2_core_read64, 917 .read64 = bcm_sf2_core_read64, 918 .write8 = bcm_sf2_core_write8, 919 .write16 = bcm_sf2_core_write16, 920 .write32 = bcm_sf2_core_write32, 921 .write48 = bcm_sf2_core_write64, 922 .write64 = bcm_sf2_core_write64, 923 }; 924 925 static void bcm_sf2_sw_get_strings(struct dsa_switch *ds, int port, 926 u32 stringset, uint8_t *data) 927 { 928 int cnt = b53_get_sset_count(ds, port, stringset); 929 930 b53_get_strings(ds, port, stringset, data); 931 bcm_sf2_cfp_get_strings(ds, port, stringset, 932 data + cnt * ETH_GSTRING_LEN); 933 } 934 935 static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds, int port, 936 uint64_t *data) 937 { 938 int cnt = b53_get_sset_count(ds, port, ETH_SS_STATS); 939 940 b53_get_ethtool_stats(ds, port, data); 941 bcm_sf2_cfp_get_ethtool_stats(ds, port, data + cnt); 942 } 943 944 static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds, int port, 945 int sset) 946 { 947 int cnt = b53_get_sset_count(ds, port, sset); 948 949 if (cnt < 0) 950 return cnt; 951 952 cnt += bcm_sf2_cfp_get_sset_count(ds, port, sset); 953 954 return cnt; 955 } 956 957 static const struct dsa_switch_ops bcm_sf2_ops = { 958 .get_tag_protocol = b53_get_tag_protocol, 959 .setup = bcm_sf2_sw_setup, 960 .get_strings = bcm_sf2_sw_get_strings, 961 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats, 962 .get_sset_count = bcm_sf2_sw_get_sset_count, 963 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 964 .get_phy_flags = bcm_sf2_sw_get_phy_flags, 965 .phylink_validate = bcm_sf2_sw_validate, 966 .phylink_mac_config = bcm_sf2_sw_mac_config, 967 .phylink_mac_link_down = bcm_sf2_sw_mac_link_down, 968 .phylink_mac_link_up = bcm_sf2_sw_mac_link_up, 969 .phylink_fixed_state = bcm_sf2_sw_fixed_state, 970 .suspend = bcm_sf2_sw_suspend, 971 .resume = bcm_sf2_sw_resume, 972 .get_wol = bcm_sf2_sw_get_wol, 973 .set_wol = bcm_sf2_sw_set_wol, 974 .port_enable = bcm_sf2_port_setup, 975 .port_disable = bcm_sf2_port_disable, 976 .get_mac_eee = b53_get_mac_eee, 977 .set_mac_eee = b53_set_mac_eee, 978 .port_bridge_join = b53_br_join, 979 .port_bridge_leave = b53_br_leave, 980 .port_stp_state_set = b53_br_set_stp_state, 981 .port_fast_age = b53_br_fast_age, 982 .port_vlan_filtering = b53_vlan_filtering, 983 .port_vlan_prepare = b53_vlan_prepare, 984 .port_vlan_add = b53_vlan_add, 985 .port_vlan_del = b53_vlan_del, 986 .port_fdb_dump = b53_fdb_dump, 987 .port_fdb_add = b53_fdb_add, 988 .port_fdb_del = b53_fdb_del, 989 .get_rxnfc = bcm_sf2_get_rxnfc, 990 .set_rxnfc = bcm_sf2_set_rxnfc, 991 .port_mirror_add = b53_mirror_add, 992 .port_mirror_del = b53_mirror_del, 993 .port_mdb_prepare = b53_mdb_prepare, 994 .port_mdb_add = b53_mdb_add, 995 .port_mdb_del = b53_mdb_del, 996 }; 997 998 struct bcm_sf2_of_data { 999 u32 type; 1000 const u16 *reg_offsets; 1001 unsigned int core_reg_align; 1002 unsigned int num_cfp_rules; 1003 }; 1004 1005 /* Register offsets for the SWITCH_REG_* block */ 1006 static const u16 bcm_sf2_7445_reg_offsets[] = { 1007 [REG_SWITCH_CNTRL] = 0x00, 1008 [REG_SWITCH_STATUS] = 0x04, 1009 [REG_DIR_DATA_WRITE] = 0x08, 1010 [REG_DIR_DATA_READ] = 0x0C, 1011 [REG_SWITCH_REVISION] = 0x18, 1012 [REG_PHY_REVISION] = 0x1C, 1013 [REG_SPHY_CNTRL] = 0x2C, 1014 [REG_RGMII_0_CNTRL] = 0x34, 1015 [REG_RGMII_1_CNTRL] = 0x40, 1016 [REG_RGMII_2_CNTRL] = 0x4c, 1017 [REG_LED_0_CNTRL] = 0x90, 1018 [REG_LED_1_CNTRL] = 0x94, 1019 [REG_LED_2_CNTRL] = 0x98, 1020 }; 1021 1022 static const struct bcm_sf2_of_data bcm_sf2_7445_data = { 1023 .type = BCM7445_DEVICE_ID, 1024 .core_reg_align = 0, 1025 .reg_offsets = bcm_sf2_7445_reg_offsets, 1026 .num_cfp_rules = 256, 1027 }; 1028 1029 static const u16 bcm_sf2_7278_reg_offsets[] = { 1030 [REG_SWITCH_CNTRL] = 0x00, 1031 [REG_SWITCH_STATUS] = 0x04, 1032 [REG_DIR_DATA_WRITE] = 0x08, 1033 [REG_DIR_DATA_READ] = 0x0c, 1034 [REG_SWITCH_REVISION] = 0x10, 1035 [REG_PHY_REVISION] = 0x14, 1036 [REG_SPHY_CNTRL] = 0x24, 1037 [REG_RGMII_0_CNTRL] = 0xe0, 1038 [REG_RGMII_1_CNTRL] = 0xec, 1039 [REG_RGMII_2_CNTRL] = 0xf8, 1040 [REG_LED_0_CNTRL] = 0x40, 1041 [REG_LED_1_CNTRL] = 0x4c, 1042 [REG_LED_2_CNTRL] = 0x58, 1043 }; 1044 1045 static const struct bcm_sf2_of_data bcm_sf2_7278_data = { 1046 .type = BCM7278_DEVICE_ID, 1047 .core_reg_align = 1, 1048 .reg_offsets = bcm_sf2_7278_reg_offsets, 1049 .num_cfp_rules = 128, 1050 }; 1051 1052 static const struct of_device_id bcm_sf2_of_match[] = { 1053 { .compatible = "brcm,bcm7445-switch-v4.0", 1054 .data = &bcm_sf2_7445_data 1055 }, 1056 { .compatible = "brcm,bcm7278-switch-v4.0", 1057 .data = &bcm_sf2_7278_data 1058 }, 1059 { .compatible = "brcm,bcm7278-switch-v4.8", 1060 .data = &bcm_sf2_7278_data 1061 }, 1062 { /* sentinel */ }, 1063 }; 1064 MODULE_DEVICE_TABLE(of, bcm_sf2_of_match); 1065 1066 static int bcm_sf2_sw_probe(struct platform_device *pdev) 1067 { 1068 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME; 1069 struct device_node *dn = pdev->dev.of_node; 1070 const struct of_device_id *of_id = NULL; 1071 const struct bcm_sf2_of_data *data; 1072 struct b53_platform_data *pdata; 1073 struct dsa_switch_ops *ops; 1074 struct bcm_sf2_priv *priv; 1075 struct b53_device *dev; 1076 struct dsa_switch *ds; 1077 void __iomem **base; 1078 unsigned int i; 1079 u32 reg, rev; 1080 int ret; 1081 1082 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1083 if (!priv) 1084 return -ENOMEM; 1085 1086 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL); 1087 if (!ops) 1088 return -ENOMEM; 1089 1090 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv); 1091 if (!dev) 1092 return -ENOMEM; 1093 1094 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1095 if (!pdata) 1096 return -ENOMEM; 1097 1098 of_id = of_match_node(bcm_sf2_of_match, dn); 1099 if (!of_id || !of_id->data) 1100 return -EINVAL; 1101 1102 data = of_id->data; 1103 1104 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */ 1105 priv->type = data->type; 1106 priv->reg_offsets = data->reg_offsets; 1107 priv->core_reg_align = data->core_reg_align; 1108 priv->num_cfp_rules = data->num_cfp_rules; 1109 1110 priv->rcdev = devm_reset_control_get_optional_exclusive(&pdev->dev, 1111 "switch"); 1112 if (PTR_ERR(priv->rcdev) == -EPROBE_DEFER) 1113 return PTR_ERR(priv->rcdev); 1114 1115 /* Auto-detection using standard registers will not work, so 1116 * provide an indication of what kind of device we are for 1117 * b53_common to work with 1118 */ 1119 pdata->chip_id = priv->type; 1120 dev->pdata = pdata; 1121 1122 priv->dev = dev; 1123 ds = dev->ds; 1124 ds->ops = &bcm_sf2_ops; 1125 1126 /* Advertise the 8 egress queues */ 1127 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES; 1128 1129 dev_set_drvdata(&pdev->dev, priv); 1130 1131 spin_lock_init(&priv->indir_lock); 1132 mutex_init(&priv->cfp.lock); 1133 INIT_LIST_HEAD(&priv->cfp.rules_list); 1134 1135 /* CFP rule #0 cannot be used for specific classifications, flag it as 1136 * permanently used 1137 */ 1138 set_bit(0, priv->cfp.used); 1139 set_bit(0, priv->cfp.unique); 1140 1141 bcm_sf2_identify_ports(priv, dn->child); 1142 1143 priv->irq0 = irq_of_parse_and_map(dn, 0); 1144 priv->irq1 = irq_of_parse_and_map(dn, 1); 1145 1146 base = &priv->core; 1147 for (i = 0; i < BCM_SF2_REGS_NUM; i++) { 1148 *base = devm_platform_ioremap_resource(pdev, i); 1149 if (IS_ERR(*base)) { 1150 pr_err("unable to find register: %s\n", reg_names[i]); 1151 return PTR_ERR(*base); 1152 } 1153 base++; 1154 } 1155 1156 ret = bcm_sf2_sw_rst(priv); 1157 if (ret) { 1158 pr_err("unable to software reset switch: %d\n", ret); 1159 return ret; 1160 } 1161 1162 bcm_sf2_gphy_enable_set(priv->dev->ds, true); 1163 1164 ret = bcm_sf2_mdio_register(ds); 1165 if (ret) { 1166 pr_err("failed to register MDIO bus\n"); 1167 return ret; 1168 } 1169 1170 bcm_sf2_gphy_enable_set(priv->dev->ds, false); 1171 1172 ret = bcm_sf2_cfp_rst(priv); 1173 if (ret) { 1174 pr_err("failed to reset CFP\n"); 1175 goto out_mdio; 1176 } 1177 1178 /* Disable all interrupts and request them */ 1179 bcm_sf2_intr_disable(priv); 1180 1181 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0, 1182 "switch_0", ds); 1183 if (ret < 0) { 1184 pr_err("failed to request switch_0 IRQ\n"); 1185 goto out_mdio; 1186 } 1187 1188 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0, 1189 "switch_1", ds); 1190 if (ret < 0) { 1191 pr_err("failed to request switch_1 IRQ\n"); 1192 goto out_mdio; 1193 } 1194 1195 /* Reset the MIB counters */ 1196 reg = core_readl(priv, CORE_GMNCFGCFG); 1197 reg |= RST_MIB_CNT; 1198 core_writel(priv, reg, CORE_GMNCFGCFG); 1199 reg &= ~RST_MIB_CNT; 1200 core_writel(priv, reg, CORE_GMNCFGCFG); 1201 1202 /* Get the maximum number of ports for this switch */ 1203 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1; 1204 if (priv->hw_params.num_ports > DSA_MAX_PORTS) 1205 priv->hw_params.num_ports = DSA_MAX_PORTS; 1206 1207 /* Assume a single GPHY setup if we can't read that property */ 1208 if (of_property_read_u32(dn, "brcm,num-gphy", 1209 &priv->hw_params.num_gphy)) 1210 priv->hw_params.num_gphy = 1; 1211 1212 rev = reg_readl(priv, REG_SWITCH_REVISION); 1213 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) & 1214 SWITCH_TOP_REV_MASK; 1215 priv->hw_params.core_rev = (rev & SF2_REV_MASK); 1216 1217 rev = reg_readl(priv, REG_PHY_REVISION); 1218 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK; 1219 1220 ret = b53_switch_register(dev); 1221 if (ret) 1222 goto out_mdio; 1223 1224 dev_info(&pdev->dev, 1225 "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n", 1226 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff, 1227 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff, 1228 priv->irq0, priv->irq1); 1229 1230 return 0; 1231 1232 out_mdio: 1233 bcm_sf2_mdio_unregister(priv); 1234 return ret; 1235 } 1236 1237 static int bcm_sf2_sw_remove(struct platform_device *pdev) 1238 { 1239 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1240 1241 priv->wol_ports_mask = 0; 1242 /* Disable interrupts */ 1243 bcm_sf2_intr_disable(priv); 1244 dsa_unregister_switch(priv->dev->ds); 1245 bcm_sf2_cfp_exit(priv->dev->ds); 1246 bcm_sf2_mdio_unregister(priv); 1247 if (priv->type == BCM7278_DEVICE_ID && !IS_ERR(priv->rcdev)) 1248 reset_control_assert(priv->rcdev); 1249 1250 return 0; 1251 } 1252 1253 static void bcm_sf2_sw_shutdown(struct platform_device *pdev) 1254 { 1255 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1256 1257 /* For a kernel about to be kexec'd we want to keep the GPHY on for a 1258 * successful MDIO bus scan to occur. If we did turn off the GPHY 1259 * before (e.g: port_disable), this will also power it back on. 1260 * 1261 * Do not rely on kexec_in_progress, just power the PHY on. 1262 */ 1263 if (priv->hw_params.num_gphy == 1) 1264 bcm_sf2_gphy_enable_set(priv->dev->ds, true); 1265 } 1266 1267 #ifdef CONFIG_PM_SLEEP 1268 static int bcm_sf2_suspend(struct device *dev) 1269 { 1270 struct bcm_sf2_priv *priv = dev_get_drvdata(dev); 1271 1272 return dsa_switch_suspend(priv->dev->ds); 1273 } 1274 1275 static int bcm_sf2_resume(struct device *dev) 1276 { 1277 struct bcm_sf2_priv *priv = dev_get_drvdata(dev); 1278 1279 return dsa_switch_resume(priv->dev->ds); 1280 } 1281 #endif /* CONFIG_PM_SLEEP */ 1282 1283 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops, 1284 bcm_sf2_suspend, bcm_sf2_resume); 1285 1286 1287 static struct platform_driver bcm_sf2_driver = { 1288 .probe = bcm_sf2_sw_probe, 1289 .remove = bcm_sf2_sw_remove, 1290 .shutdown = bcm_sf2_sw_shutdown, 1291 .driver = { 1292 .name = "brcm-sf2", 1293 .of_match_table = bcm_sf2_of_match, 1294 .pm = &bcm_sf2_pm_ops, 1295 }, 1296 }; 1297 module_platform_driver(bcm_sf2_driver); 1298 1299 MODULE_AUTHOR("Broadcom Corporation"); 1300 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip"); 1301 MODULE_LICENSE("GPL"); 1302 MODULE_ALIAS("platform:brcm-sf2"); 1303