1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Broadcom Starfighter 2 DSA switch driver 4 * 5 * Copyright (C) 2014, Broadcom Corporation 6 */ 7 8 #include <linux/list.h> 9 #include <linux/module.h> 10 #include <linux/netdevice.h> 11 #include <linux/interrupt.h> 12 #include <linux/platform_device.h> 13 #include <linux/phy.h> 14 #include <linux/phy_fixed.h> 15 #include <linux/phylink.h> 16 #include <linux/mii.h> 17 #include <linux/clk.h> 18 #include <linux/of.h> 19 #include <linux/of_irq.h> 20 #include <linux/of_address.h> 21 #include <linux/of_net.h> 22 #include <linux/of_mdio.h> 23 #include <net/dsa.h> 24 #include <linux/ethtool.h> 25 #include <linux/if_bridge.h> 26 #include <linux/brcmphy.h> 27 #include <linux/etherdevice.h> 28 #include <linux/platform_data/b53.h> 29 30 #include "bcm_sf2.h" 31 #include "bcm_sf2_regs.h" 32 #include "b53/b53_priv.h" 33 #include "b53/b53_regs.h" 34 35 static u16 bcm_sf2_reg_rgmii_cntrl(struct bcm_sf2_priv *priv, int port) 36 { 37 switch (priv->type) { 38 case BCM4908_DEVICE_ID: 39 switch (port) { 40 case 7: 41 return REG_RGMII_11_CNTRL; 42 default: 43 break; 44 } 45 break; 46 default: 47 switch (port) { 48 case 0: 49 return REG_RGMII_0_CNTRL; 50 case 1: 51 return REG_RGMII_1_CNTRL; 52 case 2: 53 return REG_RGMII_2_CNTRL; 54 default: 55 break; 56 } 57 } 58 59 WARN_ONCE(1, "Unsupported port %d\n", port); 60 61 /* RO fallback reg */ 62 return REG_SWITCH_STATUS; 63 } 64 65 /* Return the number of active ports, not counting the IMP (CPU) port */ 66 static unsigned int bcm_sf2_num_active_ports(struct dsa_switch *ds) 67 { 68 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 69 unsigned int port, count = 0; 70 71 for (port = 0; port < ARRAY_SIZE(priv->port_sts); port++) { 72 if (dsa_is_cpu_port(ds, port)) 73 continue; 74 if (priv->port_sts[port].enabled) 75 count++; 76 } 77 78 return count; 79 } 80 81 static void bcm_sf2_recalc_clock(struct dsa_switch *ds) 82 { 83 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 84 unsigned long new_rate; 85 unsigned int ports_active; 86 /* Frequenty in Mhz */ 87 static const unsigned long rate_table[] = { 88 59220000, 89 60820000, 90 62500000, 91 62500000, 92 }; 93 94 ports_active = bcm_sf2_num_active_ports(ds); 95 if (ports_active == 0 || !priv->clk_mdiv) 96 return; 97 98 /* If we overflow our table, just use the recommended operational 99 * frequency 100 */ 101 if (ports_active > ARRAY_SIZE(rate_table)) 102 new_rate = 90000000; 103 else 104 new_rate = rate_table[ports_active - 1]; 105 clk_set_rate(priv->clk_mdiv, new_rate); 106 } 107 108 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port) 109 { 110 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 111 unsigned int i; 112 u32 reg, offset; 113 114 /* Enable the port memories */ 115 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 116 reg &= ~P_TXQ_PSM_VDD(port); 117 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 118 119 /* Enable forwarding */ 120 core_writel(priv, SW_FWDG_EN, CORE_SWMODE); 121 122 /* Enable IMP port in dumb mode */ 123 reg = core_readl(priv, CORE_SWITCH_CTRL); 124 reg |= MII_DUMB_FWDG_EN; 125 core_writel(priv, reg, CORE_SWITCH_CTRL); 126 127 /* Configure Traffic Class to QoS mapping, allow each priority to map 128 * to a different queue number 129 */ 130 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); 131 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) 132 reg |= i << (PRT_TO_QID_SHIFT * i); 133 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); 134 135 b53_brcm_hdr_setup(ds, port); 136 137 if (port == 8) { 138 if (priv->type == BCM4908_DEVICE_ID || 139 priv->type == BCM7445_DEVICE_ID) 140 offset = CORE_STS_OVERRIDE_IMP; 141 else 142 offset = CORE_STS_OVERRIDE_IMP2; 143 144 /* Force link status for IMP port */ 145 reg = core_readl(priv, offset); 146 reg |= (MII_SW_OR | LINK_STS); 147 reg &= ~GMII_SPEED_UP_2G; 148 core_writel(priv, reg, offset); 149 150 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */ 151 reg = core_readl(priv, CORE_IMP_CTL); 152 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN); 153 reg &= ~(RX_DIS | TX_DIS); 154 core_writel(priv, reg, CORE_IMP_CTL); 155 } else { 156 reg = core_readl(priv, CORE_G_PCTL_PORT(port)); 157 reg &= ~(RX_DIS | TX_DIS); 158 core_writel(priv, reg, CORE_G_PCTL_PORT(port)); 159 } 160 161 priv->port_sts[port].enabled = true; 162 } 163 164 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable) 165 { 166 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 167 u32 reg; 168 169 reg = reg_readl(priv, REG_SPHY_CNTRL); 170 if (enable) { 171 reg |= PHY_RESET; 172 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS); 173 reg_writel(priv, reg, REG_SPHY_CNTRL); 174 udelay(21); 175 reg = reg_readl(priv, REG_SPHY_CNTRL); 176 reg &= ~PHY_RESET; 177 } else { 178 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET; 179 reg_writel(priv, reg, REG_SPHY_CNTRL); 180 mdelay(1); 181 reg |= CK25_DIS; 182 } 183 reg_writel(priv, reg, REG_SPHY_CNTRL); 184 185 /* Use PHY-driven LED signaling */ 186 if (!enable) { 187 reg = reg_readl(priv, REG_LED_CNTRL(0)); 188 reg |= SPDLNK_SRC_SEL; 189 reg_writel(priv, reg, REG_LED_CNTRL(0)); 190 } 191 } 192 193 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv, 194 int port) 195 { 196 unsigned int off; 197 198 switch (port) { 199 case 7: 200 off = P7_IRQ_OFF; 201 break; 202 case 0: 203 /* Port 0 interrupts are located on the first bank */ 204 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF)); 205 return; 206 default: 207 off = P_IRQ_OFF(port); 208 break; 209 } 210 211 intrl2_1_mask_clear(priv, P_IRQ_MASK(off)); 212 } 213 214 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv, 215 int port) 216 { 217 unsigned int off; 218 219 switch (port) { 220 case 7: 221 off = P7_IRQ_OFF; 222 break; 223 case 0: 224 /* Port 0 interrupts are located on the first bank */ 225 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF)); 226 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR); 227 return; 228 default: 229 off = P_IRQ_OFF(port); 230 break; 231 } 232 233 intrl2_1_mask_set(priv, P_IRQ_MASK(off)); 234 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR); 235 } 236 237 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port, 238 struct phy_device *phy) 239 { 240 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 241 unsigned int i; 242 u32 reg; 243 244 if (!dsa_is_user_port(ds, port)) 245 return 0; 246 247 priv->port_sts[port].enabled = true; 248 249 bcm_sf2_recalc_clock(ds); 250 251 /* Clear the memory power down */ 252 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 253 reg &= ~P_TXQ_PSM_VDD(port); 254 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 255 256 /* Enable Broadcom tags for that port if requested */ 257 if (priv->brcm_tag_mask & BIT(port)) 258 b53_brcm_hdr_setup(ds, port); 259 260 /* Configure Traffic Class to QoS mapping, allow each priority to map 261 * to a different queue number 262 */ 263 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); 264 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) 265 reg |= i << (PRT_TO_QID_SHIFT * i); 266 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); 267 268 /* Re-enable the GPHY and re-apply workarounds */ 269 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) { 270 bcm_sf2_gphy_enable_set(ds, true); 271 if (phy) { 272 /* if phy_stop() has been called before, phy 273 * will be in halted state, and phy_start() 274 * will call resume. 275 * 276 * the resume path does not configure back 277 * autoneg settings, and since we hard reset 278 * the phy manually here, we need to reset the 279 * state machine also. 280 */ 281 phy->state = PHY_READY; 282 phy_init_hw(phy); 283 } 284 } 285 286 /* Enable MoCA port interrupts to get notified */ 287 if (port == priv->moca_port) 288 bcm_sf2_port_intr_enable(priv, port); 289 290 /* Set per-queue pause threshold to 32 */ 291 core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port)); 292 293 /* Set ACB threshold to 24 */ 294 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) { 295 reg = acb_readl(priv, ACB_QUEUE_CFG(port * 296 SF2_NUM_EGRESS_QUEUES + i)); 297 reg &= ~XOFF_THRESHOLD_MASK; 298 reg |= 24; 299 acb_writel(priv, reg, ACB_QUEUE_CFG(port * 300 SF2_NUM_EGRESS_QUEUES + i)); 301 } 302 303 return b53_enable_port(ds, port, phy); 304 } 305 306 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port) 307 { 308 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 309 u32 reg; 310 311 /* Disable learning while in WoL mode */ 312 if (priv->wol_ports_mask & (1 << port)) { 313 reg = core_readl(priv, CORE_DIS_LEARN); 314 reg |= BIT(port); 315 core_writel(priv, reg, CORE_DIS_LEARN); 316 return; 317 } 318 319 if (port == priv->moca_port) 320 bcm_sf2_port_intr_disable(priv, port); 321 322 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) 323 bcm_sf2_gphy_enable_set(ds, false); 324 325 b53_disable_port(ds, port); 326 327 /* Power down the port memory */ 328 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 329 reg |= P_TXQ_PSM_VDD(port); 330 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 331 332 priv->port_sts[port].enabled = false; 333 334 bcm_sf2_recalc_clock(ds); 335 } 336 337 338 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr, 339 int regnum, u16 val) 340 { 341 int ret = 0; 342 u32 reg; 343 344 reg = reg_readl(priv, REG_SWITCH_CNTRL); 345 reg |= MDIO_MASTER_SEL; 346 reg_writel(priv, reg, REG_SWITCH_CNTRL); 347 348 /* Page << 8 | offset */ 349 reg = 0x70; 350 reg <<= 2; 351 core_writel(priv, addr, reg); 352 353 /* Page << 8 | offset */ 354 reg = 0x80 << 8 | regnum << 1; 355 reg <<= 2; 356 357 if (op) 358 ret = core_readl(priv, reg); 359 else 360 core_writel(priv, val, reg); 361 362 reg = reg_readl(priv, REG_SWITCH_CNTRL); 363 reg &= ~MDIO_MASTER_SEL; 364 reg_writel(priv, reg, REG_SWITCH_CNTRL); 365 366 return ret & 0xffff; 367 } 368 369 static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 370 { 371 struct bcm_sf2_priv *priv = bus->priv; 372 373 /* Intercept reads from Broadcom pseudo-PHY address, else, send 374 * them to our master MDIO bus controller 375 */ 376 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) 377 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0); 378 else 379 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum); 380 } 381 382 static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 383 u16 val) 384 { 385 struct bcm_sf2_priv *priv = bus->priv; 386 387 /* Intercept writes to the Broadcom pseudo-PHY address, else, 388 * send them to our master MDIO bus controller 389 */ 390 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) 391 return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val); 392 else 393 return mdiobus_write_nested(priv->master_mii_bus, addr, 394 regnum, val); 395 } 396 397 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id) 398 { 399 struct dsa_switch *ds = dev_id; 400 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 401 402 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) & 403 ~priv->irq0_mask; 404 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR); 405 406 return IRQ_HANDLED; 407 } 408 409 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id) 410 { 411 struct dsa_switch *ds = dev_id; 412 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 413 414 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) & 415 ~priv->irq1_mask; 416 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR); 417 418 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) { 419 priv->port_sts[7].link = true; 420 dsa_port_phylink_mac_change(ds, 7, true); 421 } 422 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) { 423 priv->port_sts[7].link = false; 424 dsa_port_phylink_mac_change(ds, 7, false); 425 } 426 427 return IRQ_HANDLED; 428 } 429 430 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv) 431 { 432 unsigned int timeout = 1000; 433 u32 reg; 434 int ret; 435 436 /* The watchdog reset does not work on 7278, we need to hit the 437 * "external" reset line through the reset controller. 438 */ 439 if (priv->type == BCM7278_DEVICE_ID) { 440 ret = reset_control_assert(priv->rcdev); 441 if (ret) 442 return ret; 443 444 return reset_control_deassert(priv->rcdev); 445 } 446 447 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 448 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET; 449 core_writel(priv, reg, CORE_WATCHDOG_CTRL); 450 451 do { 452 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 453 if (!(reg & SOFTWARE_RESET)) 454 break; 455 456 usleep_range(1000, 2000); 457 } while (timeout-- > 0); 458 459 if (timeout == 0) 460 return -ETIMEDOUT; 461 462 return 0; 463 } 464 465 static void bcm_sf2_crossbar_setup(struct bcm_sf2_priv *priv) 466 { 467 struct device *dev = priv->dev->ds->dev; 468 int shift; 469 u32 mask; 470 u32 reg; 471 int i; 472 473 mask = BIT(priv->num_crossbar_int_ports) - 1; 474 475 reg = reg_readl(priv, REG_CROSSBAR); 476 switch (priv->type) { 477 case BCM4908_DEVICE_ID: 478 shift = CROSSBAR_BCM4908_INT_P7 * priv->num_crossbar_int_ports; 479 reg &= ~(mask << shift); 480 if (0) /* FIXME */ 481 reg |= CROSSBAR_BCM4908_EXT_SERDES << shift; 482 else if (priv->int_phy_mask & BIT(7)) 483 reg |= CROSSBAR_BCM4908_EXT_GPHY4 << shift; 484 else if (phy_interface_mode_is_rgmii(priv->port_sts[7].mode)) 485 reg |= CROSSBAR_BCM4908_EXT_RGMII << shift; 486 else if (WARN(1, "Invalid port mode\n")) 487 return; 488 break; 489 default: 490 return; 491 } 492 reg_writel(priv, reg, REG_CROSSBAR); 493 494 reg = reg_readl(priv, REG_CROSSBAR); 495 for (i = 0; i < priv->num_crossbar_int_ports; i++) { 496 shift = i * priv->num_crossbar_int_ports; 497 498 dev_dbg(dev, "crossbar int port #%d - ext port #%d\n", i, 499 (reg >> shift) & mask); 500 } 501 } 502 503 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv) 504 { 505 intrl2_0_mask_set(priv, 0xffffffff); 506 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 507 intrl2_1_mask_set(priv, 0xffffffff); 508 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 509 } 510 511 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv, 512 struct device_node *dn) 513 { 514 struct device *dev = priv->dev->ds->dev; 515 struct bcm_sf2_port_status *port_st; 516 struct device_node *port; 517 unsigned int port_num; 518 struct property *prop; 519 int err; 520 521 priv->moca_port = -1; 522 523 for_each_available_child_of_node(dn, port) { 524 if (of_property_read_u32(port, "reg", &port_num)) 525 continue; 526 527 if (port_num >= DSA_MAX_PORTS) { 528 dev_err(dev, "Invalid port number %d\n", port_num); 529 continue; 530 } 531 532 port_st = &priv->port_sts[port_num]; 533 534 /* Internal PHYs get assigned a specific 'phy-mode' property 535 * value: "internal" to help flag them before MDIO probing 536 * has completed, since they might be turned off at that 537 * time 538 */ 539 err = of_get_phy_mode(port, &port_st->mode); 540 if (err) 541 continue; 542 543 if (port_st->mode == PHY_INTERFACE_MODE_INTERNAL) 544 priv->int_phy_mask |= 1 << port_num; 545 546 if (port_st->mode == PHY_INTERFACE_MODE_MOCA) 547 priv->moca_port = port_num; 548 549 if (of_property_read_bool(port, "brcm,use-bcm-hdr")) 550 priv->brcm_tag_mask |= 1 << port_num; 551 552 /* Ensure that port 5 is not picked up as a DSA CPU port 553 * flavour but a regular port instead. We should be using 554 * devlink to be able to set the port flavour. 555 */ 556 if (port_num == 5 && priv->type == BCM7278_DEVICE_ID) { 557 prop = of_find_property(port, "ethernet", NULL); 558 if (prop) 559 of_remove_property(port, prop); 560 } 561 } 562 } 563 564 static int bcm_sf2_mdio_register(struct dsa_switch *ds) 565 { 566 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 567 struct device_node *dn, *child; 568 struct phy_device *phydev; 569 struct property *prop; 570 static int index; 571 int err, reg; 572 573 /* Find our integrated MDIO bus node */ 574 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio"); 575 priv->master_mii_bus = of_mdio_find_bus(dn); 576 if (!priv->master_mii_bus) { 577 of_node_put(dn); 578 return -EPROBE_DEFER; 579 } 580 581 get_device(&priv->master_mii_bus->dev); 582 priv->master_mii_dn = dn; 583 584 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev); 585 if (!priv->slave_mii_bus) { 586 of_node_put(dn); 587 return -ENOMEM; 588 } 589 590 priv->slave_mii_bus->priv = priv; 591 priv->slave_mii_bus->name = "sf2 slave mii"; 592 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read; 593 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write; 594 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d", 595 index++); 596 priv->slave_mii_bus->dev.of_node = dn; 597 598 /* Include the pseudo-PHY address to divert reads towards our 599 * workaround. This is only required for 7445D0, since 7445E0 600 * disconnects the internal switch pseudo-PHY such that we can use the 601 * regular SWITCH_MDIO master controller instead. 602 * 603 * Here we flag the pseudo PHY as needing special treatment and would 604 * otherwise make all other PHY read/writes go to the master MDIO bus 605 * controller that comes with this switch backed by the "mdio-unimac" 606 * driver. 607 */ 608 if (of_machine_is_compatible("brcm,bcm7445d0")) 609 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR) | (1 << 0); 610 else 611 priv->indir_phy_mask = 0; 612 613 ds->phys_mii_mask = priv->indir_phy_mask; 614 ds->slave_mii_bus = priv->slave_mii_bus; 615 priv->slave_mii_bus->parent = ds->dev->parent; 616 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask; 617 618 /* We need to make sure that of_phy_connect() will not work by 619 * removing the 'phandle' and 'linux,phandle' properties and 620 * unregister the existing PHY device that was already registered. 621 */ 622 for_each_available_child_of_node(dn, child) { 623 if (of_property_read_u32(child, "reg", ®) || 624 reg >= PHY_MAX_ADDR) 625 continue; 626 627 if (!(priv->indir_phy_mask & BIT(reg))) 628 continue; 629 630 prop = of_find_property(child, "phandle", NULL); 631 if (prop) 632 of_remove_property(child, prop); 633 634 prop = of_find_property(child, "linux,phandle", NULL); 635 if (prop) 636 of_remove_property(child, prop); 637 638 phydev = of_phy_find_device(child); 639 if (phydev) 640 phy_device_remove(phydev); 641 } 642 643 err = mdiobus_register(priv->slave_mii_bus); 644 if (err && dn) 645 of_node_put(dn); 646 647 return err; 648 } 649 650 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv) 651 { 652 mdiobus_unregister(priv->slave_mii_bus); 653 of_node_put(priv->master_mii_dn); 654 } 655 656 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port) 657 { 658 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 659 660 /* The BCM7xxx PHY driver expects to find the integrated PHY revision 661 * in bits 15:8 and the patch level in bits 7:0 which is exactly what 662 * the REG_PHY_REVISION register layout is. 663 */ 664 665 return priv->hw_params.gphy_rev; 666 } 667 668 static void bcm_sf2_sw_validate(struct dsa_switch *ds, int port, 669 unsigned long *supported, 670 struct phylink_link_state *state) 671 { 672 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 673 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 674 675 if (!phy_interface_mode_is_rgmii(state->interface) && 676 state->interface != PHY_INTERFACE_MODE_MII && 677 state->interface != PHY_INTERFACE_MODE_REVMII && 678 state->interface != PHY_INTERFACE_MODE_GMII && 679 state->interface != PHY_INTERFACE_MODE_INTERNAL && 680 state->interface != PHY_INTERFACE_MODE_MOCA) { 681 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 682 if (port != core_readl(priv, CORE_IMP0_PRT_ID)) 683 dev_err(ds->dev, 684 "Unsupported interface: %d for port %d\n", 685 state->interface, port); 686 return; 687 } 688 689 /* Allow all the expected bits */ 690 phylink_set(mask, Autoneg); 691 phylink_set_port_modes(mask); 692 phylink_set(mask, Pause); 693 phylink_set(mask, Asym_Pause); 694 695 /* With the exclusion of MII and Reverse MII, we support Gigabit, 696 * including Half duplex 697 */ 698 if (state->interface != PHY_INTERFACE_MODE_MII && 699 state->interface != PHY_INTERFACE_MODE_REVMII) { 700 phylink_set(mask, 1000baseT_Full); 701 phylink_set(mask, 1000baseT_Half); 702 } 703 704 phylink_set(mask, 10baseT_Half); 705 phylink_set(mask, 10baseT_Full); 706 phylink_set(mask, 100baseT_Half); 707 phylink_set(mask, 100baseT_Full); 708 709 bitmap_and(supported, supported, mask, 710 __ETHTOOL_LINK_MODE_MASK_NBITS); 711 bitmap_and(state->advertising, state->advertising, mask, 712 __ETHTOOL_LINK_MODE_MASK_NBITS); 713 } 714 715 static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port, 716 unsigned int mode, 717 const struct phylink_link_state *state) 718 { 719 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 720 u32 id_mode_dis = 0, port_mode; 721 u32 reg_rgmii_ctrl; 722 u32 reg; 723 724 if (port == core_readl(priv, CORE_IMP0_PRT_ID)) 725 return; 726 727 switch (state->interface) { 728 case PHY_INTERFACE_MODE_RGMII: 729 id_mode_dis = 1; 730 fallthrough; 731 case PHY_INTERFACE_MODE_RGMII_TXID: 732 port_mode = EXT_GPHY; 733 break; 734 case PHY_INTERFACE_MODE_MII: 735 port_mode = EXT_EPHY; 736 break; 737 case PHY_INTERFACE_MODE_REVMII: 738 port_mode = EXT_REVMII; 739 break; 740 default: 741 /* Nothing required for all other PHYs: internal and MoCA */ 742 return; 743 } 744 745 reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port); 746 747 /* Clear id_mode_dis bit, and the existing port mode, let 748 * RGMII_MODE_EN bet set by mac_link_{up,down} 749 */ 750 reg = reg_readl(priv, reg_rgmii_ctrl); 751 reg &= ~ID_MODE_DIS; 752 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT); 753 754 reg |= port_mode; 755 if (id_mode_dis) 756 reg |= ID_MODE_DIS; 757 758 reg_writel(priv, reg, reg_rgmii_ctrl); 759 } 760 761 static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port, 762 phy_interface_t interface, bool link) 763 { 764 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 765 u32 reg_rgmii_ctrl; 766 u32 reg; 767 768 if (!phy_interface_mode_is_rgmii(interface) && 769 interface != PHY_INTERFACE_MODE_MII && 770 interface != PHY_INTERFACE_MODE_REVMII) 771 return; 772 773 reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port); 774 775 /* If the link is down, just disable the interface to conserve power */ 776 reg = reg_readl(priv, reg_rgmii_ctrl); 777 if (link) 778 reg |= RGMII_MODE_EN; 779 else 780 reg &= ~RGMII_MODE_EN; 781 reg_writel(priv, reg, reg_rgmii_ctrl); 782 } 783 784 static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port, 785 unsigned int mode, 786 phy_interface_t interface) 787 { 788 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 789 u32 reg, offset; 790 791 if (port != core_readl(priv, CORE_IMP0_PRT_ID)) { 792 if (priv->type == BCM4908_DEVICE_ID || 793 priv->type == BCM7445_DEVICE_ID) 794 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port); 795 else 796 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port); 797 798 reg = core_readl(priv, offset); 799 reg &= ~LINK_STS; 800 core_writel(priv, reg, offset); 801 } 802 803 bcm_sf2_sw_mac_link_set(ds, port, interface, false); 804 } 805 806 static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port, 807 unsigned int mode, 808 phy_interface_t interface, 809 struct phy_device *phydev, 810 int speed, int duplex, 811 bool tx_pause, bool rx_pause) 812 { 813 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 814 struct ethtool_eee *p = &priv->dev->ports[port].eee; 815 816 bcm_sf2_sw_mac_link_set(ds, port, interface, true); 817 818 if (port != core_readl(priv, CORE_IMP0_PRT_ID)) { 819 u32 reg_rgmii_ctrl; 820 u32 reg, offset; 821 822 reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port); 823 824 if (priv->type == BCM4908_DEVICE_ID || 825 priv->type == BCM7445_DEVICE_ID) 826 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port); 827 else 828 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port); 829 830 if (interface == PHY_INTERFACE_MODE_RGMII || 831 interface == PHY_INTERFACE_MODE_RGMII_TXID || 832 interface == PHY_INTERFACE_MODE_MII || 833 interface == PHY_INTERFACE_MODE_REVMII) { 834 reg = reg_readl(priv, reg_rgmii_ctrl); 835 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN); 836 837 if (tx_pause) 838 reg |= TX_PAUSE_EN; 839 if (rx_pause) 840 reg |= RX_PAUSE_EN; 841 842 reg_writel(priv, reg, reg_rgmii_ctrl); 843 } 844 845 reg = SW_OVERRIDE | LINK_STS; 846 switch (speed) { 847 case SPEED_1000: 848 reg |= SPDSTS_1000 << SPEED_SHIFT; 849 break; 850 case SPEED_100: 851 reg |= SPDSTS_100 << SPEED_SHIFT; 852 break; 853 } 854 855 if (duplex == DUPLEX_FULL) 856 reg |= DUPLX_MODE; 857 858 core_writel(priv, reg, offset); 859 } 860 861 if (mode == MLO_AN_PHY && phydev) 862 p->eee_enabled = b53_eee_init(ds, port, phydev); 863 } 864 865 static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port, 866 struct phylink_link_state *status) 867 { 868 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 869 870 status->link = false; 871 872 /* MoCA port is special as we do not get link status from CORE_LNKSTS, 873 * which means that we need to force the link at the port override 874 * level to get the data to flow. We do use what the interrupt handler 875 * did determine before. 876 * 877 * For the other ports, we just force the link status, since this is 878 * a fixed PHY device. 879 */ 880 if (port == priv->moca_port) { 881 status->link = priv->port_sts[port].link; 882 /* For MoCA interfaces, also force a link down notification 883 * since some version of the user-space daemon (mocad) use 884 * cmd->autoneg to force the link, which messes up the PHY 885 * state machine and make it go in PHY_FORCING state instead. 886 */ 887 if (!status->link) 888 netif_carrier_off(dsa_to_port(ds, port)->slave); 889 status->duplex = DUPLEX_FULL; 890 } else { 891 status->link = true; 892 } 893 } 894 895 static void bcm_sf2_enable_acb(struct dsa_switch *ds) 896 { 897 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 898 u32 reg; 899 900 /* Enable ACB globally */ 901 reg = acb_readl(priv, ACB_CONTROL); 902 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT); 903 acb_writel(priv, reg, ACB_CONTROL); 904 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT); 905 reg |= ACB_EN | ACB_ALGORITHM; 906 acb_writel(priv, reg, ACB_CONTROL); 907 } 908 909 static int bcm_sf2_sw_suspend(struct dsa_switch *ds) 910 { 911 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 912 unsigned int port; 913 914 bcm_sf2_intr_disable(priv); 915 916 /* Disable all ports physically present including the IMP 917 * port, the other ones have already been disabled during 918 * bcm_sf2_sw_setup 919 */ 920 for (port = 0; port < ds->num_ports; port++) { 921 if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port)) 922 bcm_sf2_port_disable(ds, port); 923 } 924 925 if (!priv->wol_ports_mask) 926 clk_disable_unprepare(priv->clk); 927 928 return 0; 929 } 930 931 static int bcm_sf2_sw_resume(struct dsa_switch *ds) 932 { 933 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 934 int ret; 935 936 if (!priv->wol_ports_mask) 937 clk_prepare_enable(priv->clk); 938 939 ret = bcm_sf2_sw_rst(priv); 940 if (ret) { 941 pr_err("%s: failed to software reset switch\n", __func__); 942 return ret; 943 } 944 945 bcm_sf2_crossbar_setup(priv); 946 947 ret = bcm_sf2_cfp_resume(ds); 948 if (ret) 949 return ret; 950 951 if (priv->hw_params.num_gphy == 1) 952 bcm_sf2_gphy_enable_set(ds, true); 953 954 ds->ops->setup(ds); 955 956 return 0; 957 } 958 959 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port, 960 struct ethtool_wolinfo *wol) 961 { 962 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master; 963 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 964 struct ethtool_wolinfo pwol = { }; 965 966 /* Get the parent device WoL settings */ 967 if (p->ethtool_ops->get_wol) 968 p->ethtool_ops->get_wol(p, &pwol); 969 970 /* Advertise the parent device supported settings */ 971 wol->supported = pwol.supported; 972 memset(&wol->sopass, 0, sizeof(wol->sopass)); 973 974 if (pwol.wolopts & WAKE_MAGICSECURE) 975 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass)); 976 977 if (priv->wol_ports_mask & (1 << port)) 978 wol->wolopts = pwol.wolopts; 979 else 980 wol->wolopts = 0; 981 } 982 983 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port, 984 struct ethtool_wolinfo *wol) 985 { 986 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master; 987 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 988 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 989 struct ethtool_wolinfo pwol = { }; 990 991 if (p->ethtool_ops->get_wol) 992 p->ethtool_ops->get_wol(p, &pwol); 993 if (wol->wolopts & ~pwol.supported) 994 return -EINVAL; 995 996 if (wol->wolopts) 997 priv->wol_ports_mask |= (1 << port); 998 else 999 priv->wol_ports_mask &= ~(1 << port); 1000 1001 /* If we have at least one port enabled, make sure the CPU port 1002 * is also enabled. If the CPU port is the last one enabled, we disable 1003 * it since this configuration does not make sense. 1004 */ 1005 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port)) 1006 priv->wol_ports_mask |= (1 << cpu_port); 1007 else 1008 priv->wol_ports_mask &= ~(1 << cpu_port); 1009 1010 return p->ethtool_ops->set_wol(p, wol); 1011 } 1012 1013 static int bcm_sf2_sw_setup(struct dsa_switch *ds) 1014 { 1015 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 1016 unsigned int port; 1017 1018 /* Enable all valid ports and disable those unused */ 1019 for (port = 0; port < priv->hw_params.num_ports; port++) { 1020 /* IMP port receives special treatment */ 1021 if (dsa_is_user_port(ds, port)) 1022 bcm_sf2_port_setup(ds, port, NULL); 1023 else if (dsa_is_cpu_port(ds, port)) 1024 bcm_sf2_imp_setup(ds, port); 1025 else 1026 bcm_sf2_port_disable(ds, port); 1027 } 1028 1029 b53_configure_vlan(ds); 1030 bcm_sf2_enable_acb(ds); 1031 1032 return b53_setup_devlink_resources(ds); 1033 } 1034 1035 static void bcm_sf2_sw_teardown(struct dsa_switch *ds) 1036 { 1037 dsa_devlink_resources_unregister(ds); 1038 } 1039 1040 /* The SWITCH_CORE register space is managed by b53 but operates on a page + 1041 * register basis so we need to translate that into an address that the 1042 * bus-glue understands. 1043 */ 1044 #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2) 1045 1046 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg, 1047 u8 *val) 1048 { 1049 struct bcm_sf2_priv *priv = dev->priv; 1050 1051 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 1052 1053 return 0; 1054 } 1055 1056 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg, 1057 u16 *val) 1058 { 1059 struct bcm_sf2_priv *priv = dev->priv; 1060 1061 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 1062 1063 return 0; 1064 } 1065 1066 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg, 1067 u32 *val) 1068 { 1069 struct bcm_sf2_priv *priv = dev->priv; 1070 1071 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 1072 1073 return 0; 1074 } 1075 1076 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg, 1077 u64 *val) 1078 { 1079 struct bcm_sf2_priv *priv = dev->priv; 1080 1081 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg)); 1082 1083 return 0; 1084 } 1085 1086 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg, 1087 u8 value) 1088 { 1089 struct bcm_sf2_priv *priv = dev->priv; 1090 1091 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 1092 1093 return 0; 1094 } 1095 1096 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg, 1097 u16 value) 1098 { 1099 struct bcm_sf2_priv *priv = dev->priv; 1100 1101 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 1102 1103 return 0; 1104 } 1105 1106 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg, 1107 u32 value) 1108 { 1109 struct bcm_sf2_priv *priv = dev->priv; 1110 1111 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 1112 1113 return 0; 1114 } 1115 1116 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg, 1117 u64 value) 1118 { 1119 struct bcm_sf2_priv *priv = dev->priv; 1120 1121 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 1122 1123 return 0; 1124 } 1125 1126 static const struct b53_io_ops bcm_sf2_io_ops = { 1127 .read8 = bcm_sf2_core_read8, 1128 .read16 = bcm_sf2_core_read16, 1129 .read32 = bcm_sf2_core_read32, 1130 .read48 = bcm_sf2_core_read64, 1131 .read64 = bcm_sf2_core_read64, 1132 .write8 = bcm_sf2_core_write8, 1133 .write16 = bcm_sf2_core_write16, 1134 .write32 = bcm_sf2_core_write32, 1135 .write48 = bcm_sf2_core_write64, 1136 .write64 = bcm_sf2_core_write64, 1137 }; 1138 1139 static void bcm_sf2_sw_get_strings(struct dsa_switch *ds, int port, 1140 u32 stringset, uint8_t *data) 1141 { 1142 int cnt = b53_get_sset_count(ds, port, stringset); 1143 1144 b53_get_strings(ds, port, stringset, data); 1145 bcm_sf2_cfp_get_strings(ds, port, stringset, 1146 data + cnt * ETH_GSTRING_LEN); 1147 } 1148 1149 static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds, int port, 1150 uint64_t *data) 1151 { 1152 int cnt = b53_get_sset_count(ds, port, ETH_SS_STATS); 1153 1154 b53_get_ethtool_stats(ds, port, data); 1155 bcm_sf2_cfp_get_ethtool_stats(ds, port, data + cnt); 1156 } 1157 1158 static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds, int port, 1159 int sset) 1160 { 1161 int cnt = b53_get_sset_count(ds, port, sset); 1162 1163 if (cnt < 0) 1164 return cnt; 1165 1166 cnt += bcm_sf2_cfp_get_sset_count(ds, port, sset); 1167 1168 return cnt; 1169 } 1170 1171 static const struct dsa_switch_ops bcm_sf2_ops = { 1172 .get_tag_protocol = b53_get_tag_protocol, 1173 .setup = bcm_sf2_sw_setup, 1174 .teardown = bcm_sf2_sw_teardown, 1175 .get_strings = bcm_sf2_sw_get_strings, 1176 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats, 1177 .get_sset_count = bcm_sf2_sw_get_sset_count, 1178 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 1179 .get_phy_flags = bcm_sf2_sw_get_phy_flags, 1180 .phylink_validate = bcm_sf2_sw_validate, 1181 .phylink_mac_config = bcm_sf2_sw_mac_config, 1182 .phylink_mac_link_down = bcm_sf2_sw_mac_link_down, 1183 .phylink_mac_link_up = bcm_sf2_sw_mac_link_up, 1184 .phylink_fixed_state = bcm_sf2_sw_fixed_state, 1185 .suspend = bcm_sf2_sw_suspend, 1186 .resume = bcm_sf2_sw_resume, 1187 .get_wol = bcm_sf2_sw_get_wol, 1188 .set_wol = bcm_sf2_sw_set_wol, 1189 .port_enable = bcm_sf2_port_setup, 1190 .port_disable = bcm_sf2_port_disable, 1191 .get_mac_eee = b53_get_mac_eee, 1192 .set_mac_eee = b53_set_mac_eee, 1193 .port_bridge_join = b53_br_join, 1194 .port_bridge_leave = b53_br_leave, 1195 .port_pre_bridge_flags = b53_br_flags_pre, 1196 .port_bridge_flags = b53_br_flags, 1197 .port_stp_state_set = b53_br_set_stp_state, 1198 .port_set_mrouter = b53_set_mrouter, 1199 .port_fast_age = b53_br_fast_age, 1200 .port_vlan_filtering = b53_vlan_filtering, 1201 .port_vlan_add = b53_vlan_add, 1202 .port_vlan_del = b53_vlan_del, 1203 .port_fdb_dump = b53_fdb_dump, 1204 .port_fdb_add = b53_fdb_add, 1205 .port_fdb_del = b53_fdb_del, 1206 .get_rxnfc = bcm_sf2_get_rxnfc, 1207 .set_rxnfc = bcm_sf2_set_rxnfc, 1208 .port_mirror_add = b53_mirror_add, 1209 .port_mirror_del = b53_mirror_del, 1210 .port_mdb_add = b53_mdb_add, 1211 .port_mdb_del = b53_mdb_del, 1212 }; 1213 1214 struct bcm_sf2_of_data { 1215 u32 type; 1216 const u16 *reg_offsets; 1217 unsigned int core_reg_align; 1218 unsigned int num_cfp_rules; 1219 unsigned int num_crossbar_int_ports; 1220 }; 1221 1222 static const u16 bcm_sf2_4908_reg_offsets[] = { 1223 [REG_SWITCH_CNTRL] = 0x00, 1224 [REG_SWITCH_STATUS] = 0x04, 1225 [REG_DIR_DATA_WRITE] = 0x08, 1226 [REG_DIR_DATA_READ] = 0x0c, 1227 [REG_SWITCH_REVISION] = 0x10, 1228 [REG_PHY_REVISION] = 0x14, 1229 [REG_SPHY_CNTRL] = 0x24, 1230 [REG_CROSSBAR] = 0xc8, 1231 [REG_RGMII_11_CNTRL] = 0x014c, 1232 [REG_LED_0_CNTRL] = 0x40, 1233 [REG_LED_1_CNTRL] = 0x4c, 1234 [REG_LED_2_CNTRL] = 0x58, 1235 }; 1236 1237 static const struct bcm_sf2_of_data bcm_sf2_4908_data = { 1238 .type = BCM4908_DEVICE_ID, 1239 .core_reg_align = 0, 1240 .reg_offsets = bcm_sf2_4908_reg_offsets, 1241 .num_cfp_rules = 256, 1242 .num_crossbar_int_ports = 2, 1243 }; 1244 1245 /* Register offsets for the SWITCH_REG_* block */ 1246 static const u16 bcm_sf2_7445_reg_offsets[] = { 1247 [REG_SWITCH_CNTRL] = 0x00, 1248 [REG_SWITCH_STATUS] = 0x04, 1249 [REG_DIR_DATA_WRITE] = 0x08, 1250 [REG_DIR_DATA_READ] = 0x0C, 1251 [REG_SWITCH_REVISION] = 0x18, 1252 [REG_PHY_REVISION] = 0x1C, 1253 [REG_SPHY_CNTRL] = 0x2C, 1254 [REG_RGMII_0_CNTRL] = 0x34, 1255 [REG_RGMII_1_CNTRL] = 0x40, 1256 [REG_RGMII_2_CNTRL] = 0x4c, 1257 [REG_LED_0_CNTRL] = 0x90, 1258 [REG_LED_1_CNTRL] = 0x94, 1259 [REG_LED_2_CNTRL] = 0x98, 1260 }; 1261 1262 static const struct bcm_sf2_of_data bcm_sf2_7445_data = { 1263 .type = BCM7445_DEVICE_ID, 1264 .core_reg_align = 0, 1265 .reg_offsets = bcm_sf2_7445_reg_offsets, 1266 .num_cfp_rules = 256, 1267 }; 1268 1269 static const u16 bcm_sf2_7278_reg_offsets[] = { 1270 [REG_SWITCH_CNTRL] = 0x00, 1271 [REG_SWITCH_STATUS] = 0x04, 1272 [REG_DIR_DATA_WRITE] = 0x08, 1273 [REG_DIR_DATA_READ] = 0x0c, 1274 [REG_SWITCH_REVISION] = 0x10, 1275 [REG_PHY_REVISION] = 0x14, 1276 [REG_SPHY_CNTRL] = 0x24, 1277 [REG_RGMII_0_CNTRL] = 0xe0, 1278 [REG_RGMII_1_CNTRL] = 0xec, 1279 [REG_RGMII_2_CNTRL] = 0xf8, 1280 [REG_LED_0_CNTRL] = 0x40, 1281 [REG_LED_1_CNTRL] = 0x4c, 1282 [REG_LED_2_CNTRL] = 0x58, 1283 }; 1284 1285 static const struct bcm_sf2_of_data bcm_sf2_7278_data = { 1286 .type = BCM7278_DEVICE_ID, 1287 .core_reg_align = 1, 1288 .reg_offsets = bcm_sf2_7278_reg_offsets, 1289 .num_cfp_rules = 128, 1290 }; 1291 1292 static const struct of_device_id bcm_sf2_of_match[] = { 1293 { .compatible = "brcm,bcm4908-switch", 1294 .data = &bcm_sf2_4908_data 1295 }, 1296 { .compatible = "brcm,bcm7445-switch-v4.0", 1297 .data = &bcm_sf2_7445_data 1298 }, 1299 { .compatible = "brcm,bcm7278-switch-v4.0", 1300 .data = &bcm_sf2_7278_data 1301 }, 1302 { .compatible = "brcm,bcm7278-switch-v4.8", 1303 .data = &bcm_sf2_7278_data 1304 }, 1305 { /* sentinel */ }, 1306 }; 1307 MODULE_DEVICE_TABLE(of, bcm_sf2_of_match); 1308 1309 static int bcm_sf2_sw_probe(struct platform_device *pdev) 1310 { 1311 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME; 1312 struct device_node *dn = pdev->dev.of_node; 1313 const struct of_device_id *of_id = NULL; 1314 const struct bcm_sf2_of_data *data; 1315 struct b53_platform_data *pdata; 1316 struct dsa_switch_ops *ops; 1317 struct device_node *ports; 1318 struct bcm_sf2_priv *priv; 1319 struct b53_device *dev; 1320 struct dsa_switch *ds; 1321 void __iomem **base; 1322 unsigned int i; 1323 u32 reg, rev; 1324 int ret; 1325 1326 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1327 if (!priv) 1328 return -ENOMEM; 1329 1330 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL); 1331 if (!ops) 1332 return -ENOMEM; 1333 1334 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv); 1335 if (!dev) 1336 return -ENOMEM; 1337 1338 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1339 if (!pdata) 1340 return -ENOMEM; 1341 1342 of_id = of_match_node(bcm_sf2_of_match, dn); 1343 if (!of_id || !of_id->data) 1344 return -EINVAL; 1345 1346 data = of_id->data; 1347 1348 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */ 1349 priv->type = data->type; 1350 priv->reg_offsets = data->reg_offsets; 1351 priv->core_reg_align = data->core_reg_align; 1352 priv->num_cfp_rules = data->num_cfp_rules; 1353 priv->num_crossbar_int_ports = data->num_crossbar_int_ports; 1354 1355 priv->rcdev = devm_reset_control_get_optional_exclusive(&pdev->dev, 1356 "switch"); 1357 if (IS_ERR(priv->rcdev)) 1358 return PTR_ERR(priv->rcdev); 1359 1360 /* Auto-detection using standard registers will not work, so 1361 * provide an indication of what kind of device we are for 1362 * b53_common to work with 1363 */ 1364 pdata->chip_id = priv->type; 1365 dev->pdata = pdata; 1366 1367 priv->dev = dev; 1368 ds = dev->ds; 1369 ds->ops = &bcm_sf2_ops; 1370 1371 /* Advertise the 8 egress queues */ 1372 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES; 1373 1374 dev_set_drvdata(&pdev->dev, priv); 1375 1376 spin_lock_init(&priv->indir_lock); 1377 mutex_init(&priv->cfp.lock); 1378 INIT_LIST_HEAD(&priv->cfp.rules_list); 1379 1380 /* CFP rule #0 cannot be used for specific classifications, flag it as 1381 * permanently used 1382 */ 1383 set_bit(0, priv->cfp.used); 1384 set_bit(0, priv->cfp.unique); 1385 1386 /* Balance of_node_put() done by of_find_node_by_name() */ 1387 of_node_get(dn); 1388 ports = of_find_node_by_name(dn, "ports"); 1389 if (ports) { 1390 bcm_sf2_identify_ports(priv, ports); 1391 of_node_put(ports); 1392 } 1393 1394 priv->irq0 = irq_of_parse_and_map(dn, 0); 1395 priv->irq1 = irq_of_parse_and_map(dn, 1); 1396 1397 base = &priv->core; 1398 for (i = 0; i < BCM_SF2_REGS_NUM; i++) { 1399 *base = devm_platform_ioremap_resource(pdev, i); 1400 if (IS_ERR(*base)) { 1401 pr_err("unable to find register: %s\n", reg_names[i]); 1402 return PTR_ERR(*base); 1403 } 1404 base++; 1405 } 1406 1407 priv->clk = devm_clk_get_optional(&pdev->dev, "sw_switch"); 1408 if (IS_ERR(priv->clk)) 1409 return PTR_ERR(priv->clk); 1410 1411 clk_prepare_enable(priv->clk); 1412 1413 priv->clk_mdiv = devm_clk_get_optional(&pdev->dev, "sw_switch_mdiv"); 1414 if (IS_ERR(priv->clk_mdiv)) { 1415 ret = PTR_ERR(priv->clk_mdiv); 1416 goto out_clk; 1417 } 1418 1419 clk_prepare_enable(priv->clk_mdiv); 1420 1421 ret = bcm_sf2_sw_rst(priv); 1422 if (ret) { 1423 pr_err("unable to software reset switch: %d\n", ret); 1424 goto out_clk_mdiv; 1425 } 1426 1427 bcm_sf2_crossbar_setup(priv); 1428 1429 bcm_sf2_gphy_enable_set(priv->dev->ds, true); 1430 1431 ret = bcm_sf2_mdio_register(ds); 1432 if (ret) { 1433 pr_err("failed to register MDIO bus\n"); 1434 goto out_clk_mdiv; 1435 } 1436 1437 bcm_sf2_gphy_enable_set(priv->dev->ds, false); 1438 1439 ret = bcm_sf2_cfp_rst(priv); 1440 if (ret) { 1441 pr_err("failed to reset CFP\n"); 1442 goto out_mdio; 1443 } 1444 1445 /* Disable all interrupts and request them */ 1446 bcm_sf2_intr_disable(priv); 1447 1448 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0, 1449 "switch_0", ds); 1450 if (ret < 0) { 1451 pr_err("failed to request switch_0 IRQ\n"); 1452 goto out_mdio; 1453 } 1454 1455 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0, 1456 "switch_1", ds); 1457 if (ret < 0) { 1458 pr_err("failed to request switch_1 IRQ\n"); 1459 goto out_mdio; 1460 } 1461 1462 /* Reset the MIB counters */ 1463 reg = core_readl(priv, CORE_GMNCFGCFG); 1464 reg |= RST_MIB_CNT; 1465 core_writel(priv, reg, CORE_GMNCFGCFG); 1466 reg &= ~RST_MIB_CNT; 1467 core_writel(priv, reg, CORE_GMNCFGCFG); 1468 1469 /* Get the maximum number of ports for this switch */ 1470 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1; 1471 if (priv->hw_params.num_ports > DSA_MAX_PORTS) 1472 priv->hw_params.num_ports = DSA_MAX_PORTS; 1473 1474 /* Assume a single GPHY setup if we can't read that property */ 1475 if (of_property_read_u32(dn, "brcm,num-gphy", 1476 &priv->hw_params.num_gphy)) 1477 priv->hw_params.num_gphy = 1; 1478 1479 rev = reg_readl(priv, REG_SWITCH_REVISION); 1480 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) & 1481 SWITCH_TOP_REV_MASK; 1482 priv->hw_params.core_rev = (rev & SF2_REV_MASK); 1483 1484 rev = reg_readl(priv, REG_PHY_REVISION); 1485 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK; 1486 1487 ret = b53_switch_register(dev); 1488 if (ret) 1489 goto out_mdio; 1490 1491 dev_info(&pdev->dev, 1492 "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n", 1493 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff, 1494 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff, 1495 priv->irq0, priv->irq1); 1496 1497 return 0; 1498 1499 out_mdio: 1500 bcm_sf2_mdio_unregister(priv); 1501 out_clk_mdiv: 1502 clk_disable_unprepare(priv->clk_mdiv); 1503 out_clk: 1504 clk_disable_unprepare(priv->clk); 1505 return ret; 1506 } 1507 1508 static int bcm_sf2_sw_remove(struct platform_device *pdev) 1509 { 1510 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1511 1512 priv->wol_ports_mask = 0; 1513 /* Disable interrupts */ 1514 bcm_sf2_intr_disable(priv); 1515 dsa_unregister_switch(priv->dev->ds); 1516 bcm_sf2_cfp_exit(priv->dev->ds); 1517 bcm_sf2_mdio_unregister(priv); 1518 clk_disable_unprepare(priv->clk_mdiv); 1519 clk_disable_unprepare(priv->clk); 1520 if (priv->type == BCM7278_DEVICE_ID) 1521 reset_control_assert(priv->rcdev); 1522 1523 return 0; 1524 } 1525 1526 static void bcm_sf2_sw_shutdown(struct platform_device *pdev) 1527 { 1528 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1529 1530 /* For a kernel about to be kexec'd we want to keep the GPHY on for a 1531 * successful MDIO bus scan to occur. If we did turn off the GPHY 1532 * before (e.g: port_disable), this will also power it back on. 1533 * 1534 * Do not rely on kexec_in_progress, just power the PHY on. 1535 */ 1536 if (priv->hw_params.num_gphy == 1) 1537 bcm_sf2_gphy_enable_set(priv->dev->ds, true); 1538 } 1539 1540 #ifdef CONFIG_PM_SLEEP 1541 static int bcm_sf2_suspend(struct device *dev) 1542 { 1543 struct bcm_sf2_priv *priv = dev_get_drvdata(dev); 1544 1545 return dsa_switch_suspend(priv->dev->ds); 1546 } 1547 1548 static int bcm_sf2_resume(struct device *dev) 1549 { 1550 struct bcm_sf2_priv *priv = dev_get_drvdata(dev); 1551 1552 return dsa_switch_resume(priv->dev->ds); 1553 } 1554 #endif /* CONFIG_PM_SLEEP */ 1555 1556 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops, 1557 bcm_sf2_suspend, bcm_sf2_resume); 1558 1559 1560 static struct platform_driver bcm_sf2_driver = { 1561 .probe = bcm_sf2_sw_probe, 1562 .remove = bcm_sf2_sw_remove, 1563 .shutdown = bcm_sf2_sw_shutdown, 1564 .driver = { 1565 .name = "brcm-sf2", 1566 .of_match_table = bcm_sf2_of_match, 1567 .pm = &bcm_sf2_pm_ops, 1568 }, 1569 }; 1570 module_platform_driver(bcm_sf2_driver); 1571 1572 MODULE_AUTHOR("Broadcom Corporation"); 1573 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip"); 1574 MODULE_LICENSE("GPL"); 1575 MODULE_ALIAS("platform:brcm-sf2"); 1576