1 /* 2 * Broadcom Starfighter 2 DSA switch driver 3 * 4 * Copyright (C) 2014, Broadcom Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #include <linux/list.h> 13 #include <linux/module.h> 14 #include <linux/netdevice.h> 15 #include <linux/interrupt.h> 16 #include <linux/platform_device.h> 17 #include <linux/of.h> 18 #include <linux/phy.h> 19 #include <linux/phy_fixed.h> 20 #include <linux/mii.h> 21 #include <linux/of.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_address.h> 24 #include <linux/of_net.h> 25 #include <net/dsa.h> 26 #include <linux/ethtool.h> 27 #include <linux/if_bridge.h> 28 #include <linux/brcmphy.h> 29 #include <linux/etherdevice.h> 30 #include <net/switchdev.h> 31 32 #include "bcm_sf2.h" 33 #include "bcm_sf2_regs.h" 34 35 /* String, offset, and register size in bytes if different from 4 bytes */ 36 static const struct bcm_sf2_hw_stats bcm_sf2_mib[] = { 37 { "TxOctets", 0x000, 8 }, 38 { "TxDropPkts", 0x020 }, 39 { "TxQPKTQ0", 0x030 }, 40 { "TxBroadcastPkts", 0x040 }, 41 { "TxMulticastPkts", 0x050 }, 42 { "TxUnicastPKts", 0x060 }, 43 { "TxCollisions", 0x070 }, 44 { "TxSingleCollision", 0x080 }, 45 { "TxMultipleCollision", 0x090 }, 46 { "TxDeferredCollision", 0x0a0 }, 47 { "TxLateCollision", 0x0b0 }, 48 { "TxExcessiveCollision", 0x0c0 }, 49 { "TxFrameInDisc", 0x0d0 }, 50 { "TxPausePkts", 0x0e0 }, 51 { "TxQPKTQ1", 0x0f0 }, 52 { "TxQPKTQ2", 0x100 }, 53 { "TxQPKTQ3", 0x110 }, 54 { "TxQPKTQ4", 0x120 }, 55 { "TxQPKTQ5", 0x130 }, 56 { "RxOctets", 0x140, 8 }, 57 { "RxUndersizePkts", 0x160 }, 58 { "RxPausePkts", 0x170 }, 59 { "RxPkts64Octets", 0x180 }, 60 { "RxPkts65to127Octets", 0x190 }, 61 { "RxPkts128to255Octets", 0x1a0 }, 62 { "RxPkts256to511Octets", 0x1b0 }, 63 { "RxPkts512to1023Octets", 0x1c0 }, 64 { "RxPkts1024toMaxPktsOctets", 0x1d0 }, 65 { "RxOversizePkts", 0x1e0 }, 66 { "RxJabbers", 0x1f0 }, 67 { "RxAlignmentErrors", 0x200 }, 68 { "RxFCSErrors", 0x210 }, 69 { "RxGoodOctets", 0x220, 8 }, 70 { "RxDropPkts", 0x240 }, 71 { "RxUnicastPkts", 0x250 }, 72 { "RxMulticastPkts", 0x260 }, 73 { "RxBroadcastPkts", 0x270 }, 74 { "RxSAChanges", 0x280 }, 75 { "RxFragments", 0x290 }, 76 { "RxJumboPkt", 0x2a0 }, 77 { "RxSymblErr", 0x2b0 }, 78 { "InRangeErrCount", 0x2c0 }, 79 { "OutRangeErrCount", 0x2d0 }, 80 { "EEELpiEvent", 0x2e0 }, 81 { "EEELpiDuration", 0x2f0 }, 82 { "RxDiscard", 0x300, 8 }, 83 { "TxQPKTQ6", 0x320 }, 84 { "TxQPKTQ7", 0x330 }, 85 { "TxPkts64Octets", 0x340 }, 86 { "TxPkts65to127Octets", 0x350 }, 87 { "TxPkts128to255Octets", 0x360 }, 88 { "TxPkts256to511Ocets", 0x370 }, 89 { "TxPkts512to1023Ocets", 0x380 }, 90 { "TxPkts1024toMaxPktOcets", 0x390 }, 91 }; 92 93 #define BCM_SF2_STATS_SIZE ARRAY_SIZE(bcm_sf2_mib) 94 95 static void bcm_sf2_sw_get_strings(struct dsa_switch *ds, 96 int port, uint8_t *data) 97 { 98 unsigned int i; 99 100 for (i = 0; i < BCM_SF2_STATS_SIZE; i++) 101 memcpy(data + i * ETH_GSTRING_LEN, 102 bcm_sf2_mib[i].string, ETH_GSTRING_LEN); 103 } 104 105 static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds, 106 int port, uint64_t *data) 107 { 108 struct bcm_sf2_priv *priv = ds_to_priv(ds); 109 const struct bcm_sf2_hw_stats *s; 110 unsigned int i; 111 u64 val = 0; 112 u32 offset; 113 114 mutex_lock(&priv->stats_mutex); 115 116 /* Now fetch the per-port counters */ 117 for (i = 0; i < BCM_SF2_STATS_SIZE; i++) { 118 s = &bcm_sf2_mib[i]; 119 120 /* Do a latched 64-bit read if needed */ 121 offset = s->reg + CORE_P_MIB_OFFSET(port); 122 if (s->sizeof_stat == 8) 123 val = core_readq(priv, offset); 124 else 125 val = core_readl(priv, offset); 126 127 data[i] = (u64)val; 128 } 129 130 mutex_unlock(&priv->stats_mutex); 131 } 132 133 static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds) 134 { 135 return BCM_SF2_STATS_SIZE; 136 } 137 138 static char *bcm_sf2_sw_probe(struct device *host_dev, int sw_addr) 139 { 140 return "Broadcom Starfighter 2"; 141 } 142 143 static void bcm_sf2_imp_vlan_setup(struct dsa_switch *ds, int cpu_port) 144 { 145 struct bcm_sf2_priv *priv = ds_to_priv(ds); 146 unsigned int i; 147 u32 reg; 148 149 /* Enable the IMP Port to be in the same VLAN as the other ports 150 * on a per-port basis such that we only have Port i and IMP in 151 * the same VLAN. 152 */ 153 for (i = 0; i < priv->hw_params.num_ports; i++) { 154 if (!((1 << i) & ds->phys_port_mask)) 155 continue; 156 157 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i)); 158 reg |= (1 << cpu_port); 159 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i)); 160 } 161 } 162 163 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port) 164 { 165 struct bcm_sf2_priv *priv = ds_to_priv(ds); 166 u32 reg, val; 167 168 /* Enable the port memories */ 169 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 170 reg &= ~P_TXQ_PSM_VDD(port); 171 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 172 173 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */ 174 reg = core_readl(priv, CORE_IMP_CTL); 175 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN); 176 reg &= ~(RX_DIS | TX_DIS); 177 core_writel(priv, reg, CORE_IMP_CTL); 178 179 /* Enable forwarding */ 180 core_writel(priv, SW_FWDG_EN, CORE_SWMODE); 181 182 /* Enable IMP port in dumb mode */ 183 reg = core_readl(priv, CORE_SWITCH_CTRL); 184 reg |= MII_DUMB_FWDG_EN; 185 core_writel(priv, reg, CORE_SWITCH_CTRL); 186 187 /* Resolve which bit controls the Broadcom tag */ 188 switch (port) { 189 case 8: 190 val = BRCM_HDR_EN_P8; 191 break; 192 case 7: 193 val = BRCM_HDR_EN_P7; 194 break; 195 case 5: 196 val = BRCM_HDR_EN_P5; 197 break; 198 default: 199 val = 0; 200 break; 201 } 202 203 /* Enable Broadcom tags for IMP port */ 204 reg = core_readl(priv, CORE_BRCM_HDR_CTRL); 205 reg |= val; 206 core_writel(priv, reg, CORE_BRCM_HDR_CTRL); 207 208 /* Enable reception Broadcom tag for CPU TX (switch RX) to 209 * allow us to tag outgoing frames 210 */ 211 reg = core_readl(priv, CORE_BRCM_HDR_RX_DIS); 212 reg &= ~(1 << port); 213 core_writel(priv, reg, CORE_BRCM_HDR_RX_DIS); 214 215 /* Enable transmission of Broadcom tags from the switch (CPU RX) to 216 * allow delivering frames to the per-port net_devices 217 */ 218 reg = core_readl(priv, CORE_BRCM_HDR_TX_DIS); 219 reg &= ~(1 << port); 220 core_writel(priv, reg, CORE_BRCM_HDR_TX_DIS); 221 222 /* Force link status for IMP port */ 223 reg = core_readl(priv, CORE_STS_OVERRIDE_IMP); 224 reg |= (MII_SW_OR | LINK_STS); 225 core_writel(priv, reg, CORE_STS_OVERRIDE_IMP); 226 } 227 228 static void bcm_sf2_eee_enable_set(struct dsa_switch *ds, int port, bool enable) 229 { 230 struct bcm_sf2_priv *priv = ds_to_priv(ds); 231 u32 reg; 232 233 reg = core_readl(priv, CORE_EEE_EN_CTRL); 234 if (enable) 235 reg |= 1 << port; 236 else 237 reg &= ~(1 << port); 238 core_writel(priv, reg, CORE_EEE_EN_CTRL); 239 } 240 241 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable) 242 { 243 struct bcm_sf2_priv *priv = ds_to_priv(ds); 244 u32 reg; 245 246 reg = reg_readl(priv, REG_SPHY_CNTRL); 247 if (enable) { 248 reg |= PHY_RESET; 249 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | CK25_DIS); 250 reg_writel(priv, reg, REG_SPHY_CNTRL); 251 udelay(21); 252 reg = reg_readl(priv, REG_SPHY_CNTRL); 253 reg &= ~PHY_RESET; 254 } else { 255 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET; 256 reg_writel(priv, reg, REG_SPHY_CNTRL); 257 mdelay(1); 258 reg |= CK25_DIS; 259 } 260 reg_writel(priv, reg, REG_SPHY_CNTRL); 261 262 /* Use PHY-driven LED signaling */ 263 if (!enable) { 264 reg = reg_readl(priv, REG_LED_CNTRL(0)); 265 reg |= SPDLNK_SRC_SEL; 266 reg_writel(priv, reg, REG_LED_CNTRL(0)); 267 } 268 } 269 270 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv, 271 int port) 272 { 273 unsigned int off; 274 275 switch (port) { 276 case 7: 277 off = P7_IRQ_OFF; 278 break; 279 case 0: 280 /* Port 0 interrupts are located on the first bank */ 281 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF)); 282 return; 283 default: 284 off = P_IRQ_OFF(port); 285 break; 286 } 287 288 intrl2_1_mask_clear(priv, P_IRQ_MASK(off)); 289 } 290 291 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv, 292 int port) 293 { 294 unsigned int off; 295 296 switch (port) { 297 case 7: 298 off = P7_IRQ_OFF; 299 break; 300 case 0: 301 /* Port 0 interrupts are located on the first bank */ 302 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF)); 303 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR); 304 return; 305 default: 306 off = P_IRQ_OFF(port); 307 break; 308 } 309 310 intrl2_1_mask_set(priv, P_IRQ_MASK(off)); 311 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR); 312 } 313 314 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port, 315 struct phy_device *phy) 316 { 317 struct bcm_sf2_priv *priv = ds_to_priv(ds); 318 s8 cpu_port = ds->dst[ds->index].cpu_port; 319 u32 reg; 320 321 /* Clear the memory power down */ 322 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 323 reg &= ~P_TXQ_PSM_VDD(port); 324 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 325 326 /* Clear the Rx and Tx disable bits and set to no spanning tree */ 327 core_writel(priv, 0, CORE_G_PCTL_PORT(port)); 328 329 /* Re-enable the GPHY and re-apply workarounds */ 330 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) { 331 bcm_sf2_gphy_enable_set(ds, true); 332 if (phy) { 333 /* if phy_stop() has been called before, phy 334 * will be in halted state, and phy_start() 335 * will call resume. 336 * 337 * the resume path does not configure back 338 * autoneg settings, and since we hard reset 339 * the phy manually here, we need to reset the 340 * state machine also. 341 */ 342 phy->state = PHY_READY; 343 phy_init_hw(phy); 344 } 345 } 346 347 /* Enable MoCA port interrupts to get notified */ 348 if (port == priv->moca_port) 349 bcm_sf2_port_intr_enable(priv, port); 350 351 /* Set this port, and only this one to be in the default VLAN, 352 * if member of a bridge, restore its membership prior to 353 * bringing down this port. 354 */ 355 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port)); 356 reg &= ~PORT_VLAN_CTRL_MASK; 357 reg |= (1 << port); 358 reg |= priv->port_sts[port].vlan_ctl_mask; 359 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(port)); 360 361 bcm_sf2_imp_vlan_setup(ds, cpu_port); 362 363 /* If EEE was enabled, restore it */ 364 if (priv->port_sts[port].eee.eee_enabled) 365 bcm_sf2_eee_enable_set(ds, port, true); 366 367 return 0; 368 } 369 370 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port, 371 struct phy_device *phy) 372 { 373 struct bcm_sf2_priv *priv = ds_to_priv(ds); 374 u32 off, reg; 375 376 if (priv->wol_ports_mask & (1 << port)) 377 return; 378 379 if (port == priv->moca_port) 380 bcm_sf2_port_intr_disable(priv, port); 381 382 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) 383 bcm_sf2_gphy_enable_set(ds, false); 384 385 if (dsa_is_cpu_port(ds, port)) 386 off = CORE_IMP_CTL; 387 else 388 off = CORE_G_PCTL_PORT(port); 389 390 reg = core_readl(priv, off); 391 reg |= RX_DIS | TX_DIS; 392 core_writel(priv, reg, off); 393 394 /* Power down the port memory */ 395 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 396 reg |= P_TXQ_PSM_VDD(port); 397 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 398 } 399 400 /* Returns 0 if EEE was not enabled, or 1 otherwise 401 */ 402 static int bcm_sf2_eee_init(struct dsa_switch *ds, int port, 403 struct phy_device *phy) 404 { 405 struct bcm_sf2_priv *priv = ds_to_priv(ds); 406 struct ethtool_eee *p = &priv->port_sts[port].eee; 407 int ret; 408 409 p->supported = (SUPPORTED_1000baseT_Full | SUPPORTED_100baseT_Full); 410 411 ret = phy_init_eee(phy, 0); 412 if (ret) 413 return 0; 414 415 bcm_sf2_eee_enable_set(ds, port, true); 416 417 return 1; 418 } 419 420 static int bcm_sf2_sw_get_eee(struct dsa_switch *ds, int port, 421 struct ethtool_eee *e) 422 { 423 struct bcm_sf2_priv *priv = ds_to_priv(ds); 424 struct ethtool_eee *p = &priv->port_sts[port].eee; 425 u32 reg; 426 427 reg = core_readl(priv, CORE_EEE_LPI_INDICATE); 428 e->eee_enabled = p->eee_enabled; 429 e->eee_active = !!(reg & (1 << port)); 430 431 return 0; 432 } 433 434 static int bcm_sf2_sw_set_eee(struct dsa_switch *ds, int port, 435 struct phy_device *phydev, 436 struct ethtool_eee *e) 437 { 438 struct bcm_sf2_priv *priv = ds_to_priv(ds); 439 struct ethtool_eee *p = &priv->port_sts[port].eee; 440 441 p->eee_enabled = e->eee_enabled; 442 443 if (!p->eee_enabled) { 444 bcm_sf2_eee_enable_set(ds, port, false); 445 } else { 446 p->eee_enabled = bcm_sf2_eee_init(ds, port, phydev); 447 if (!p->eee_enabled) 448 return -EOPNOTSUPP; 449 } 450 451 return 0; 452 } 453 454 /* Fast-ageing of ARL entries for a given port, equivalent to an ARL 455 * flush for that port. 456 */ 457 static int bcm_sf2_sw_fast_age_port(struct dsa_switch *ds, int port) 458 { 459 struct bcm_sf2_priv *priv = ds_to_priv(ds); 460 unsigned int timeout = 1000; 461 u32 reg; 462 463 core_writel(priv, port, CORE_FAST_AGE_PORT); 464 465 reg = core_readl(priv, CORE_FAST_AGE_CTRL); 466 reg |= EN_AGE_PORT | EN_AGE_DYNAMIC | FAST_AGE_STR_DONE; 467 core_writel(priv, reg, CORE_FAST_AGE_CTRL); 468 469 do { 470 reg = core_readl(priv, CORE_FAST_AGE_CTRL); 471 if (!(reg & FAST_AGE_STR_DONE)) 472 break; 473 474 cpu_relax(); 475 } while (timeout--); 476 477 if (!timeout) 478 return -ETIMEDOUT; 479 480 core_writel(priv, 0, CORE_FAST_AGE_CTRL); 481 482 return 0; 483 } 484 485 static int bcm_sf2_sw_br_join(struct dsa_switch *ds, int port, 486 struct net_device *bridge) 487 { 488 struct bcm_sf2_priv *priv = ds_to_priv(ds); 489 unsigned int i; 490 u32 reg, p_ctl; 491 492 priv->port_sts[port].bridge_dev = bridge; 493 p_ctl = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port)); 494 495 for (i = 0; i < priv->hw_params.num_ports; i++) { 496 if (priv->port_sts[i].bridge_dev != bridge) 497 continue; 498 499 /* Add this local port to the remote port VLAN control 500 * membership and update the remote port bitmask 501 */ 502 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i)); 503 reg |= 1 << port; 504 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i)); 505 priv->port_sts[i].vlan_ctl_mask = reg; 506 507 p_ctl |= 1 << i; 508 } 509 510 /* Configure the local port VLAN control membership to include 511 * remote ports and update the local port bitmask 512 */ 513 core_writel(priv, p_ctl, CORE_PORT_VLAN_CTL_PORT(port)); 514 priv->port_sts[port].vlan_ctl_mask = p_ctl; 515 516 return 0; 517 } 518 519 static int bcm_sf2_sw_br_leave(struct dsa_switch *ds, int port) 520 { 521 struct bcm_sf2_priv *priv = ds_to_priv(ds); 522 struct net_device *bridge = priv->port_sts[port].bridge_dev; 523 unsigned int i; 524 u32 reg, p_ctl; 525 526 p_ctl = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port)); 527 528 for (i = 0; i < priv->hw_params.num_ports; i++) { 529 /* Don't touch the remaining ports */ 530 if (priv->port_sts[i].bridge_dev != bridge) 531 continue; 532 533 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i)); 534 reg &= ~(1 << port); 535 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i)); 536 priv->port_sts[port].vlan_ctl_mask = reg; 537 538 /* Prevent self removal to preserve isolation */ 539 if (port != i) 540 p_ctl &= ~(1 << i); 541 } 542 543 core_writel(priv, p_ctl, CORE_PORT_VLAN_CTL_PORT(port)); 544 priv->port_sts[port].vlan_ctl_mask = p_ctl; 545 priv->port_sts[port].bridge_dev = NULL; 546 547 return 0; 548 } 549 550 static int bcm_sf2_sw_br_set_stp_state(struct dsa_switch *ds, int port, 551 u8 state) 552 { 553 struct bcm_sf2_priv *priv = ds_to_priv(ds); 554 u8 hw_state, cur_hw_state; 555 int ret = 0; 556 u32 reg; 557 558 reg = core_readl(priv, CORE_G_PCTL_PORT(port)); 559 cur_hw_state = reg & (G_MISTP_STATE_MASK << G_MISTP_STATE_SHIFT); 560 561 switch (state) { 562 case BR_STATE_DISABLED: 563 hw_state = G_MISTP_DIS_STATE; 564 break; 565 case BR_STATE_LISTENING: 566 hw_state = G_MISTP_LISTEN_STATE; 567 break; 568 case BR_STATE_LEARNING: 569 hw_state = G_MISTP_LEARN_STATE; 570 break; 571 case BR_STATE_FORWARDING: 572 hw_state = G_MISTP_FWD_STATE; 573 break; 574 case BR_STATE_BLOCKING: 575 hw_state = G_MISTP_BLOCK_STATE; 576 break; 577 default: 578 pr_err("%s: invalid STP state: %d\n", __func__, state); 579 return -EINVAL; 580 } 581 582 /* Fast-age ARL entries if we are moving a port from Learning or 583 * Forwarding (cur_hw_state) state to Disabled, Blocking or Listening 584 * state (hw_state) 585 */ 586 if (cur_hw_state != hw_state) { 587 if (cur_hw_state >= G_MISTP_LEARN_STATE && 588 hw_state <= G_MISTP_LISTEN_STATE) { 589 ret = bcm_sf2_sw_fast_age_port(ds, port); 590 if (ret) { 591 pr_err("%s: fast-ageing failed\n", __func__); 592 return ret; 593 } 594 } 595 } 596 597 reg = core_readl(priv, CORE_G_PCTL_PORT(port)); 598 reg &= ~(G_MISTP_STATE_MASK << G_MISTP_STATE_SHIFT); 599 reg |= hw_state; 600 core_writel(priv, reg, CORE_G_PCTL_PORT(port)); 601 602 return 0; 603 } 604 605 /* Address Resolution Logic routines */ 606 static int bcm_sf2_arl_op_wait(struct bcm_sf2_priv *priv) 607 { 608 unsigned int timeout = 10; 609 u32 reg; 610 611 do { 612 reg = core_readl(priv, CORE_ARLA_RWCTL); 613 if (!(reg & ARL_STRTDN)) 614 return 0; 615 616 usleep_range(1000, 2000); 617 } while (timeout--); 618 619 return -ETIMEDOUT; 620 } 621 622 static int bcm_sf2_arl_rw_op(struct bcm_sf2_priv *priv, unsigned int op) 623 { 624 u32 cmd; 625 626 if (op > ARL_RW) 627 return -EINVAL; 628 629 cmd = core_readl(priv, CORE_ARLA_RWCTL); 630 cmd &= ~IVL_SVL_SELECT; 631 cmd |= ARL_STRTDN; 632 if (op) 633 cmd |= ARL_RW; 634 else 635 cmd &= ~ARL_RW; 636 core_writel(priv, cmd, CORE_ARLA_RWCTL); 637 638 return bcm_sf2_arl_op_wait(priv); 639 } 640 641 static int bcm_sf2_arl_read(struct bcm_sf2_priv *priv, u64 mac, 642 u16 vid, struct bcm_sf2_arl_entry *ent, u8 *idx, 643 bool is_valid) 644 { 645 unsigned int i; 646 int ret; 647 648 ret = bcm_sf2_arl_op_wait(priv); 649 if (ret) 650 return ret; 651 652 /* Read the 4 bins */ 653 for (i = 0; i < 4; i++) { 654 u64 mac_vid; 655 u32 fwd_entry; 656 657 mac_vid = core_readq(priv, CORE_ARLA_MACVID_ENTRY(i)); 658 fwd_entry = core_readl(priv, CORE_ARLA_FWD_ENTRY(i)); 659 bcm_sf2_arl_to_entry(ent, mac_vid, fwd_entry); 660 661 if (ent->is_valid && is_valid) { 662 *idx = i; 663 return 0; 664 } 665 666 /* This is the MAC we just deleted */ 667 if (!is_valid && (mac_vid & mac)) 668 return 0; 669 } 670 671 return -ENOENT; 672 } 673 674 static int bcm_sf2_arl_op(struct bcm_sf2_priv *priv, int op, int port, 675 const unsigned char *addr, u16 vid, bool is_valid) 676 { 677 struct bcm_sf2_arl_entry ent; 678 u32 fwd_entry; 679 u64 mac, mac_vid = 0; 680 u8 idx = 0; 681 int ret; 682 683 /* Convert the array into a 64-bit MAC */ 684 mac = bcm_sf2_mac_to_u64(addr); 685 686 /* Perform a read for the given MAC and VID */ 687 core_writeq(priv, mac, CORE_ARLA_MAC); 688 core_writel(priv, vid, CORE_ARLA_VID); 689 690 /* Issue a read operation for this MAC */ 691 ret = bcm_sf2_arl_rw_op(priv, 1); 692 if (ret) 693 return ret; 694 695 ret = bcm_sf2_arl_read(priv, mac, vid, &ent, &idx, is_valid); 696 /* If this is a read, just finish now */ 697 if (op) 698 return ret; 699 700 /* We could not find a matching MAC, so reset to a new entry */ 701 if (ret) { 702 fwd_entry = 0; 703 idx = 0; 704 } 705 706 memset(&ent, 0, sizeof(ent)); 707 ent.port = port; 708 ent.is_valid = is_valid; 709 ent.vid = vid; 710 ent.is_static = true; 711 memcpy(ent.mac, addr, ETH_ALEN); 712 bcm_sf2_arl_from_entry(&mac_vid, &fwd_entry, &ent); 713 714 core_writeq(priv, mac_vid, CORE_ARLA_MACVID_ENTRY(idx)); 715 core_writel(priv, fwd_entry, CORE_ARLA_FWD_ENTRY(idx)); 716 717 ret = bcm_sf2_arl_rw_op(priv, 0); 718 if (ret) 719 return ret; 720 721 /* Re-read the entry to check */ 722 return bcm_sf2_arl_read(priv, mac, vid, &ent, &idx, is_valid); 723 } 724 725 static int bcm_sf2_sw_fdb_prepare(struct dsa_switch *ds, int port, 726 const struct switchdev_obj_port_fdb *fdb, 727 struct switchdev_trans *trans) 728 { 729 /* We do not need to do anything specific here yet */ 730 return 0; 731 } 732 733 static int bcm_sf2_sw_fdb_add(struct dsa_switch *ds, int port, 734 const struct switchdev_obj_port_fdb *fdb, 735 struct switchdev_trans *trans) 736 { 737 struct bcm_sf2_priv *priv = ds_to_priv(ds); 738 739 return bcm_sf2_arl_op(priv, 0, port, fdb->addr, fdb->vid, true); 740 } 741 742 static int bcm_sf2_sw_fdb_del(struct dsa_switch *ds, int port, 743 const struct switchdev_obj_port_fdb *fdb) 744 { 745 struct bcm_sf2_priv *priv = ds_to_priv(ds); 746 747 return bcm_sf2_arl_op(priv, 0, port, fdb->addr, fdb->vid, false); 748 } 749 750 static int bcm_sf2_arl_search_wait(struct bcm_sf2_priv *priv) 751 { 752 unsigned timeout = 1000; 753 u32 reg; 754 755 do { 756 reg = core_readl(priv, CORE_ARLA_SRCH_CTL); 757 if (!(reg & ARLA_SRCH_STDN)) 758 return 0; 759 760 if (reg & ARLA_SRCH_VLID) 761 return 0; 762 763 usleep_range(1000, 2000); 764 } while (timeout--); 765 766 return -ETIMEDOUT; 767 } 768 769 static void bcm_sf2_arl_search_rd(struct bcm_sf2_priv *priv, u8 idx, 770 struct bcm_sf2_arl_entry *ent) 771 { 772 u64 mac_vid; 773 u32 fwd_entry; 774 775 mac_vid = core_readq(priv, CORE_ARLA_SRCH_RSLT_MACVID(idx)); 776 fwd_entry = core_readl(priv, CORE_ARLA_SRCH_RSLT(idx)); 777 bcm_sf2_arl_to_entry(ent, mac_vid, fwd_entry); 778 } 779 780 static int bcm_sf2_sw_fdb_copy(struct net_device *dev, int port, 781 const struct bcm_sf2_arl_entry *ent, 782 struct switchdev_obj_port_fdb *fdb, 783 int (*cb)(struct switchdev_obj *obj)) 784 { 785 if (!ent->is_valid) 786 return 0; 787 788 if (port != ent->port) 789 return 0; 790 791 ether_addr_copy(fdb->addr, ent->mac); 792 fdb->vid = ent->vid; 793 fdb->ndm_state = ent->is_static ? NUD_NOARP : NUD_REACHABLE; 794 795 return cb(&fdb->obj); 796 } 797 798 static int bcm_sf2_sw_fdb_dump(struct dsa_switch *ds, int port, 799 struct switchdev_obj_port_fdb *fdb, 800 int (*cb)(struct switchdev_obj *obj)) 801 { 802 struct bcm_sf2_priv *priv = ds_to_priv(ds); 803 struct net_device *dev = ds->ports[port]; 804 struct bcm_sf2_arl_entry results[2]; 805 unsigned int count = 0; 806 int ret; 807 808 /* Start search operation */ 809 core_writel(priv, ARLA_SRCH_STDN, CORE_ARLA_SRCH_CTL); 810 811 do { 812 ret = bcm_sf2_arl_search_wait(priv); 813 if (ret) 814 return ret; 815 816 /* Read both entries, then return their values back */ 817 bcm_sf2_arl_search_rd(priv, 0, &results[0]); 818 ret = bcm_sf2_sw_fdb_copy(dev, port, &results[0], fdb, cb); 819 if (ret) 820 return ret; 821 822 bcm_sf2_arl_search_rd(priv, 1, &results[1]); 823 ret = bcm_sf2_sw_fdb_copy(dev, port, &results[1], fdb, cb); 824 if (ret) 825 return ret; 826 827 if (!results[0].is_valid && !results[1].is_valid) 828 break; 829 830 } while (count++ < CORE_ARLA_NUM_ENTRIES); 831 832 return 0; 833 } 834 835 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id) 836 { 837 struct bcm_sf2_priv *priv = dev_id; 838 839 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) & 840 ~priv->irq0_mask; 841 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR); 842 843 return IRQ_HANDLED; 844 } 845 846 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id) 847 { 848 struct bcm_sf2_priv *priv = dev_id; 849 850 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) & 851 ~priv->irq1_mask; 852 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR); 853 854 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) 855 priv->port_sts[7].link = 1; 856 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) 857 priv->port_sts[7].link = 0; 858 859 return IRQ_HANDLED; 860 } 861 862 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv) 863 { 864 unsigned int timeout = 1000; 865 u32 reg; 866 867 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 868 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET; 869 core_writel(priv, reg, CORE_WATCHDOG_CTRL); 870 871 do { 872 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 873 if (!(reg & SOFTWARE_RESET)) 874 break; 875 876 usleep_range(1000, 2000); 877 } while (timeout-- > 0); 878 879 if (timeout == 0) 880 return -ETIMEDOUT; 881 882 return 0; 883 } 884 885 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv) 886 { 887 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET); 888 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 889 intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR); 890 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET); 891 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 892 intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR); 893 } 894 895 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv, 896 struct device_node *dn) 897 { 898 struct device_node *port; 899 const char *phy_mode_str; 900 int mode; 901 unsigned int port_num; 902 int ret; 903 904 priv->moca_port = -1; 905 906 for_each_available_child_of_node(dn, port) { 907 if (of_property_read_u32(port, "reg", &port_num)) 908 continue; 909 910 /* Internal PHYs get assigned a specific 'phy-mode' property 911 * value: "internal" to help flag them before MDIO probing 912 * has completed, since they might be turned off at that 913 * time 914 */ 915 mode = of_get_phy_mode(port); 916 if (mode < 0) { 917 ret = of_property_read_string(port, "phy-mode", 918 &phy_mode_str); 919 if (ret < 0) 920 continue; 921 922 if (!strcasecmp(phy_mode_str, "internal")) 923 priv->int_phy_mask |= 1 << port_num; 924 } 925 926 if (mode == PHY_INTERFACE_MODE_MOCA) 927 priv->moca_port = port_num; 928 } 929 } 930 931 static int bcm_sf2_sw_setup(struct dsa_switch *ds) 932 { 933 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME; 934 struct bcm_sf2_priv *priv = ds_to_priv(ds); 935 struct device_node *dn; 936 void __iomem **base; 937 unsigned int port; 938 unsigned int i; 939 u32 reg, rev; 940 int ret; 941 942 spin_lock_init(&priv->indir_lock); 943 mutex_init(&priv->stats_mutex); 944 945 /* All the interesting properties are at the parent device_node 946 * level 947 */ 948 dn = ds->pd->of_node->parent; 949 bcm_sf2_identify_ports(priv, ds->pd->of_node); 950 951 priv->irq0 = irq_of_parse_and_map(dn, 0); 952 priv->irq1 = irq_of_parse_and_map(dn, 1); 953 954 base = &priv->core; 955 for (i = 0; i < BCM_SF2_REGS_NUM; i++) { 956 *base = of_iomap(dn, i); 957 if (*base == NULL) { 958 pr_err("unable to find register: %s\n", reg_names[i]); 959 ret = -ENOMEM; 960 goto out_unmap; 961 } 962 base++; 963 } 964 965 ret = bcm_sf2_sw_rst(priv); 966 if (ret) { 967 pr_err("unable to software reset switch: %d\n", ret); 968 goto out_unmap; 969 } 970 971 /* Disable all interrupts and request them */ 972 bcm_sf2_intr_disable(priv); 973 974 ret = request_irq(priv->irq0, bcm_sf2_switch_0_isr, 0, 975 "switch_0", priv); 976 if (ret < 0) { 977 pr_err("failed to request switch_0 IRQ\n"); 978 goto out_unmap; 979 } 980 981 ret = request_irq(priv->irq1, bcm_sf2_switch_1_isr, 0, 982 "switch_1", priv); 983 if (ret < 0) { 984 pr_err("failed to request switch_1 IRQ\n"); 985 goto out_free_irq0; 986 } 987 988 /* Reset the MIB counters */ 989 reg = core_readl(priv, CORE_GMNCFGCFG); 990 reg |= RST_MIB_CNT; 991 core_writel(priv, reg, CORE_GMNCFGCFG); 992 reg &= ~RST_MIB_CNT; 993 core_writel(priv, reg, CORE_GMNCFGCFG); 994 995 /* Get the maximum number of ports for this switch */ 996 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1; 997 if (priv->hw_params.num_ports > DSA_MAX_PORTS) 998 priv->hw_params.num_ports = DSA_MAX_PORTS; 999 1000 /* Assume a single GPHY setup if we can't read that property */ 1001 if (of_property_read_u32(dn, "brcm,num-gphy", 1002 &priv->hw_params.num_gphy)) 1003 priv->hw_params.num_gphy = 1; 1004 1005 /* Enable all valid ports and disable those unused */ 1006 for (port = 0; port < priv->hw_params.num_ports; port++) { 1007 /* IMP port receives special treatment */ 1008 if ((1 << port) & ds->phys_port_mask) 1009 bcm_sf2_port_setup(ds, port, NULL); 1010 else if (dsa_is_cpu_port(ds, port)) 1011 bcm_sf2_imp_setup(ds, port); 1012 else 1013 bcm_sf2_port_disable(ds, port, NULL); 1014 } 1015 1016 /* Include the pseudo-PHY address and the broadcast PHY address to 1017 * divert reads towards our workaround. This is only required for 1018 * 7445D0, since 7445E0 disconnects the internal switch pseudo-PHY such 1019 * that we can use the regular SWITCH_MDIO master controller instead. 1020 * 1021 * By default, DSA initializes ds->phys_mii_mask to ds->phys_port_mask 1022 * to have a 1:1 mapping between Port address and PHY address in order 1023 * to utilize the slave_mii_bus instance to read from Port PHYs. This is 1024 * not what we want here, so we initialize phys_mii_mask 0 to always 1025 * utilize the "master" MDIO bus backed by the "mdio-unimac" driver. 1026 */ 1027 if (of_machine_is_compatible("brcm,bcm7445d0")) 1028 ds->phys_mii_mask |= ((1 << BRCM_PSEUDO_PHY_ADDR) | (1 << 0)); 1029 else 1030 ds->phys_mii_mask = 0; 1031 1032 rev = reg_readl(priv, REG_SWITCH_REVISION); 1033 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) & 1034 SWITCH_TOP_REV_MASK; 1035 priv->hw_params.core_rev = (rev & SF2_REV_MASK); 1036 1037 rev = reg_readl(priv, REG_PHY_REVISION); 1038 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK; 1039 1040 pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n", 1041 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff, 1042 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff, 1043 priv->core, priv->irq0, priv->irq1); 1044 1045 return 0; 1046 1047 out_free_irq0: 1048 free_irq(priv->irq0, priv); 1049 out_unmap: 1050 base = &priv->core; 1051 for (i = 0; i < BCM_SF2_REGS_NUM; i++) { 1052 if (*base) 1053 iounmap(*base); 1054 base++; 1055 } 1056 return ret; 1057 } 1058 1059 static int bcm_sf2_sw_set_addr(struct dsa_switch *ds, u8 *addr) 1060 { 1061 return 0; 1062 } 1063 1064 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port) 1065 { 1066 struct bcm_sf2_priv *priv = ds_to_priv(ds); 1067 1068 /* The BCM7xxx PHY driver expects to find the integrated PHY revision 1069 * in bits 15:8 and the patch level in bits 7:0 which is exactly what 1070 * the REG_PHY_REVISION register layout is. 1071 */ 1072 1073 return priv->hw_params.gphy_rev; 1074 } 1075 1076 static int bcm_sf2_sw_indir_rw(struct dsa_switch *ds, int op, int addr, 1077 int regnum, u16 val) 1078 { 1079 struct bcm_sf2_priv *priv = ds_to_priv(ds); 1080 int ret = 0; 1081 u32 reg; 1082 1083 reg = reg_readl(priv, REG_SWITCH_CNTRL); 1084 reg |= MDIO_MASTER_SEL; 1085 reg_writel(priv, reg, REG_SWITCH_CNTRL); 1086 1087 /* Page << 8 | offset */ 1088 reg = 0x70; 1089 reg <<= 2; 1090 core_writel(priv, addr, reg); 1091 1092 /* Page << 8 | offset */ 1093 reg = 0x80 << 8 | regnum << 1; 1094 reg <<= 2; 1095 1096 if (op) 1097 ret = core_readl(priv, reg); 1098 else 1099 core_writel(priv, val, reg); 1100 1101 reg = reg_readl(priv, REG_SWITCH_CNTRL); 1102 reg &= ~MDIO_MASTER_SEL; 1103 reg_writel(priv, reg, REG_SWITCH_CNTRL); 1104 1105 return ret & 0xffff; 1106 } 1107 1108 static int bcm_sf2_sw_phy_read(struct dsa_switch *ds, int addr, int regnum) 1109 { 1110 /* Intercept reads from the MDIO broadcast address or Broadcom 1111 * pseudo-PHY address 1112 */ 1113 switch (addr) { 1114 case 0: 1115 case BRCM_PSEUDO_PHY_ADDR: 1116 return bcm_sf2_sw_indir_rw(ds, 1, addr, regnum, 0); 1117 default: 1118 return 0xffff; 1119 } 1120 } 1121 1122 static int bcm_sf2_sw_phy_write(struct dsa_switch *ds, int addr, int regnum, 1123 u16 val) 1124 { 1125 /* Intercept writes to the MDIO broadcast address or Broadcom 1126 * pseudo-PHY address 1127 */ 1128 switch (addr) { 1129 case 0: 1130 case BRCM_PSEUDO_PHY_ADDR: 1131 bcm_sf2_sw_indir_rw(ds, 0, addr, regnum, val); 1132 break; 1133 } 1134 1135 return 0; 1136 } 1137 1138 static void bcm_sf2_sw_adjust_link(struct dsa_switch *ds, int port, 1139 struct phy_device *phydev) 1140 { 1141 struct bcm_sf2_priv *priv = ds_to_priv(ds); 1142 u32 id_mode_dis = 0, port_mode; 1143 const char *str = NULL; 1144 u32 reg; 1145 1146 switch (phydev->interface) { 1147 case PHY_INTERFACE_MODE_RGMII: 1148 str = "RGMII (no delay)"; 1149 id_mode_dis = 1; 1150 case PHY_INTERFACE_MODE_RGMII_TXID: 1151 if (!str) 1152 str = "RGMII (TX delay)"; 1153 port_mode = EXT_GPHY; 1154 break; 1155 case PHY_INTERFACE_MODE_MII: 1156 str = "MII"; 1157 port_mode = EXT_EPHY; 1158 break; 1159 case PHY_INTERFACE_MODE_REVMII: 1160 str = "Reverse MII"; 1161 port_mode = EXT_REVMII; 1162 break; 1163 default: 1164 /* All other PHYs: internal and MoCA */ 1165 goto force_link; 1166 } 1167 1168 /* If the link is down, just disable the interface to conserve power */ 1169 if (!phydev->link) { 1170 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); 1171 reg &= ~RGMII_MODE_EN; 1172 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); 1173 goto force_link; 1174 } 1175 1176 /* Clear id_mode_dis bit, and the existing port mode, but 1177 * make sure we enable the RGMII block for data to pass 1178 */ 1179 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); 1180 reg &= ~ID_MODE_DIS; 1181 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT); 1182 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN); 1183 1184 reg |= port_mode | RGMII_MODE_EN; 1185 if (id_mode_dis) 1186 reg |= ID_MODE_DIS; 1187 1188 if (phydev->pause) { 1189 if (phydev->asym_pause) 1190 reg |= TX_PAUSE_EN; 1191 reg |= RX_PAUSE_EN; 1192 } 1193 1194 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); 1195 1196 pr_info("Port %d configured for %s\n", port, str); 1197 1198 force_link: 1199 /* Force link settings detected from the PHY */ 1200 reg = SW_OVERRIDE; 1201 switch (phydev->speed) { 1202 case SPEED_1000: 1203 reg |= SPDSTS_1000 << SPEED_SHIFT; 1204 break; 1205 case SPEED_100: 1206 reg |= SPDSTS_100 << SPEED_SHIFT; 1207 break; 1208 } 1209 1210 if (phydev->link) 1211 reg |= LINK_STS; 1212 if (phydev->duplex == DUPLEX_FULL) 1213 reg |= DUPLX_MODE; 1214 1215 core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port)); 1216 } 1217 1218 static void bcm_sf2_sw_fixed_link_update(struct dsa_switch *ds, int port, 1219 struct fixed_phy_status *status) 1220 { 1221 struct bcm_sf2_priv *priv = ds_to_priv(ds); 1222 u32 duplex, pause; 1223 u32 reg; 1224 1225 duplex = core_readl(priv, CORE_DUPSTS); 1226 pause = core_readl(priv, CORE_PAUSESTS); 1227 1228 status->link = 0; 1229 1230 /* MoCA port is special as we do not get link status from CORE_LNKSTS, 1231 * which means that we need to force the link at the port override 1232 * level to get the data to flow. We do use what the interrupt handler 1233 * did determine before. 1234 * 1235 * For the other ports, we just force the link status, since this is 1236 * a fixed PHY device. 1237 */ 1238 if (port == priv->moca_port) { 1239 status->link = priv->port_sts[port].link; 1240 /* For MoCA interfaces, also force a link down notification 1241 * since some version of the user-space daemon (mocad) use 1242 * cmd->autoneg to force the link, which messes up the PHY 1243 * state machine and make it go in PHY_FORCING state instead. 1244 */ 1245 if (!status->link) 1246 netif_carrier_off(ds->ports[port]); 1247 status->duplex = 1; 1248 } else { 1249 status->link = 1; 1250 status->duplex = !!(duplex & (1 << port)); 1251 } 1252 1253 reg = core_readl(priv, CORE_STS_OVERRIDE_GMIIP_PORT(port)); 1254 reg |= SW_OVERRIDE; 1255 if (status->link) 1256 reg |= LINK_STS; 1257 else 1258 reg &= ~LINK_STS; 1259 core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port)); 1260 1261 if ((pause & (1 << port)) && 1262 (pause & (1 << (port + PAUSESTS_TX_PAUSE_SHIFT)))) { 1263 status->asym_pause = 1; 1264 status->pause = 1; 1265 } 1266 1267 if (pause & (1 << port)) 1268 status->pause = 1; 1269 } 1270 1271 static int bcm_sf2_sw_suspend(struct dsa_switch *ds) 1272 { 1273 struct bcm_sf2_priv *priv = ds_to_priv(ds); 1274 unsigned int port; 1275 1276 bcm_sf2_intr_disable(priv); 1277 1278 /* Disable all ports physically present including the IMP 1279 * port, the other ones have already been disabled during 1280 * bcm_sf2_sw_setup 1281 */ 1282 for (port = 0; port < DSA_MAX_PORTS; port++) { 1283 if ((1 << port) & ds->phys_port_mask || 1284 dsa_is_cpu_port(ds, port)) 1285 bcm_sf2_port_disable(ds, port, NULL); 1286 } 1287 1288 return 0; 1289 } 1290 1291 static int bcm_sf2_sw_resume(struct dsa_switch *ds) 1292 { 1293 struct bcm_sf2_priv *priv = ds_to_priv(ds); 1294 unsigned int port; 1295 int ret; 1296 1297 ret = bcm_sf2_sw_rst(priv); 1298 if (ret) { 1299 pr_err("%s: failed to software reset switch\n", __func__); 1300 return ret; 1301 } 1302 1303 if (priv->hw_params.num_gphy == 1) 1304 bcm_sf2_gphy_enable_set(ds, true); 1305 1306 for (port = 0; port < DSA_MAX_PORTS; port++) { 1307 if ((1 << port) & ds->phys_port_mask) 1308 bcm_sf2_port_setup(ds, port, NULL); 1309 else if (dsa_is_cpu_port(ds, port)) 1310 bcm_sf2_imp_setup(ds, port); 1311 } 1312 1313 return 0; 1314 } 1315 1316 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port, 1317 struct ethtool_wolinfo *wol) 1318 { 1319 struct net_device *p = ds->dst[ds->index].master_netdev; 1320 struct bcm_sf2_priv *priv = ds_to_priv(ds); 1321 struct ethtool_wolinfo pwol; 1322 1323 /* Get the parent device WoL settings */ 1324 p->ethtool_ops->get_wol(p, &pwol); 1325 1326 /* Advertise the parent device supported settings */ 1327 wol->supported = pwol.supported; 1328 memset(&wol->sopass, 0, sizeof(wol->sopass)); 1329 1330 if (pwol.wolopts & WAKE_MAGICSECURE) 1331 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass)); 1332 1333 if (priv->wol_ports_mask & (1 << port)) 1334 wol->wolopts = pwol.wolopts; 1335 else 1336 wol->wolopts = 0; 1337 } 1338 1339 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port, 1340 struct ethtool_wolinfo *wol) 1341 { 1342 struct net_device *p = ds->dst[ds->index].master_netdev; 1343 struct bcm_sf2_priv *priv = ds_to_priv(ds); 1344 s8 cpu_port = ds->dst[ds->index].cpu_port; 1345 struct ethtool_wolinfo pwol; 1346 1347 p->ethtool_ops->get_wol(p, &pwol); 1348 if (wol->wolopts & ~pwol.supported) 1349 return -EINVAL; 1350 1351 if (wol->wolopts) 1352 priv->wol_ports_mask |= (1 << port); 1353 else 1354 priv->wol_ports_mask &= ~(1 << port); 1355 1356 /* If we have at least one port enabled, make sure the CPU port 1357 * is also enabled. If the CPU port is the last one enabled, we disable 1358 * it since this configuration does not make sense. 1359 */ 1360 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port)) 1361 priv->wol_ports_mask |= (1 << cpu_port); 1362 else 1363 priv->wol_ports_mask &= ~(1 << cpu_port); 1364 1365 return p->ethtool_ops->set_wol(p, wol); 1366 } 1367 1368 static struct dsa_switch_driver bcm_sf2_switch_driver = { 1369 .tag_protocol = DSA_TAG_PROTO_BRCM, 1370 .priv_size = sizeof(struct bcm_sf2_priv), 1371 .probe = bcm_sf2_sw_probe, 1372 .setup = bcm_sf2_sw_setup, 1373 .set_addr = bcm_sf2_sw_set_addr, 1374 .get_phy_flags = bcm_sf2_sw_get_phy_flags, 1375 .phy_read = bcm_sf2_sw_phy_read, 1376 .phy_write = bcm_sf2_sw_phy_write, 1377 .get_strings = bcm_sf2_sw_get_strings, 1378 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats, 1379 .get_sset_count = bcm_sf2_sw_get_sset_count, 1380 .adjust_link = bcm_sf2_sw_adjust_link, 1381 .fixed_link_update = bcm_sf2_sw_fixed_link_update, 1382 .suspend = bcm_sf2_sw_suspend, 1383 .resume = bcm_sf2_sw_resume, 1384 .get_wol = bcm_sf2_sw_get_wol, 1385 .set_wol = bcm_sf2_sw_set_wol, 1386 .port_enable = bcm_sf2_port_setup, 1387 .port_disable = bcm_sf2_port_disable, 1388 .get_eee = bcm_sf2_sw_get_eee, 1389 .set_eee = bcm_sf2_sw_set_eee, 1390 .port_join_bridge = bcm_sf2_sw_br_join, 1391 .port_leave_bridge = bcm_sf2_sw_br_leave, 1392 .port_stp_update = bcm_sf2_sw_br_set_stp_state, 1393 .port_fdb_prepare = bcm_sf2_sw_fdb_prepare, 1394 .port_fdb_add = bcm_sf2_sw_fdb_add, 1395 .port_fdb_del = bcm_sf2_sw_fdb_del, 1396 .port_fdb_dump = bcm_sf2_sw_fdb_dump, 1397 }; 1398 1399 static int __init bcm_sf2_init(void) 1400 { 1401 register_switch_driver(&bcm_sf2_switch_driver); 1402 1403 return 0; 1404 } 1405 module_init(bcm_sf2_init); 1406 1407 static void __exit bcm_sf2_exit(void) 1408 { 1409 unregister_switch_driver(&bcm_sf2_switch_driver); 1410 } 1411 module_exit(bcm_sf2_exit); 1412 1413 MODULE_AUTHOR("Broadcom Corporation"); 1414 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip"); 1415 MODULE_LICENSE("GPL"); 1416 MODULE_ALIAS("platform:brcm-sf2"); 1417