1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Broadcom Starfighter 2 DSA switch driver 4 * 5 * Copyright (C) 2014, Broadcom Corporation 6 */ 7 8 #include <linux/list.h> 9 #include <linux/module.h> 10 #include <linux/netdevice.h> 11 #include <linux/interrupt.h> 12 #include <linux/platform_device.h> 13 #include <linux/phy.h> 14 #include <linux/phy_fixed.h> 15 #include <linux/phylink.h> 16 #include <linux/mii.h> 17 #include <linux/of.h> 18 #include <linux/of_irq.h> 19 #include <linux/of_address.h> 20 #include <linux/of_net.h> 21 #include <linux/of_mdio.h> 22 #include <net/dsa.h> 23 #include <linux/ethtool.h> 24 #include <linux/if_bridge.h> 25 #include <linux/brcmphy.h> 26 #include <linux/etherdevice.h> 27 #include <linux/platform_data/b53.h> 28 29 #include "bcm_sf2.h" 30 #include "bcm_sf2_regs.h" 31 #include "b53/b53_priv.h" 32 #include "b53/b53_regs.h" 33 34 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port) 35 { 36 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 37 unsigned int i; 38 u32 reg, offset; 39 40 /* Enable the port memories */ 41 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 42 reg &= ~P_TXQ_PSM_VDD(port); 43 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 44 45 /* Enable forwarding */ 46 core_writel(priv, SW_FWDG_EN, CORE_SWMODE); 47 48 /* Enable IMP port in dumb mode */ 49 reg = core_readl(priv, CORE_SWITCH_CTRL); 50 reg |= MII_DUMB_FWDG_EN; 51 core_writel(priv, reg, CORE_SWITCH_CTRL); 52 53 /* Configure Traffic Class to QoS mapping, allow each priority to map 54 * to a different queue number 55 */ 56 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); 57 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) 58 reg |= i << (PRT_TO_QID_SHIFT * i); 59 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); 60 61 b53_brcm_hdr_setup(ds, port); 62 63 if (port == 8) { 64 if (priv->type == BCM7445_DEVICE_ID) 65 offset = CORE_STS_OVERRIDE_IMP; 66 else 67 offset = CORE_STS_OVERRIDE_IMP2; 68 69 /* Force link status for IMP port */ 70 reg = core_readl(priv, offset); 71 reg |= (MII_SW_OR | LINK_STS); 72 if (priv->type == BCM7278_DEVICE_ID) 73 reg |= GMII_SPEED_UP_2G; 74 core_writel(priv, reg, offset); 75 76 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */ 77 reg = core_readl(priv, CORE_IMP_CTL); 78 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN); 79 reg &= ~(RX_DIS | TX_DIS); 80 core_writel(priv, reg, CORE_IMP_CTL); 81 } else { 82 reg = core_readl(priv, CORE_G_PCTL_PORT(port)); 83 reg &= ~(RX_DIS | TX_DIS); 84 core_writel(priv, reg, CORE_G_PCTL_PORT(port)); 85 } 86 } 87 88 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable) 89 { 90 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 91 u32 reg; 92 93 reg = reg_readl(priv, REG_SPHY_CNTRL); 94 if (enable) { 95 reg |= PHY_RESET; 96 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS); 97 reg_writel(priv, reg, REG_SPHY_CNTRL); 98 udelay(21); 99 reg = reg_readl(priv, REG_SPHY_CNTRL); 100 reg &= ~PHY_RESET; 101 } else { 102 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET; 103 reg_writel(priv, reg, REG_SPHY_CNTRL); 104 mdelay(1); 105 reg |= CK25_DIS; 106 } 107 reg_writel(priv, reg, REG_SPHY_CNTRL); 108 109 /* Use PHY-driven LED signaling */ 110 if (!enable) { 111 reg = reg_readl(priv, REG_LED_CNTRL(0)); 112 reg |= SPDLNK_SRC_SEL; 113 reg_writel(priv, reg, REG_LED_CNTRL(0)); 114 } 115 } 116 117 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv, 118 int port) 119 { 120 unsigned int off; 121 122 switch (port) { 123 case 7: 124 off = P7_IRQ_OFF; 125 break; 126 case 0: 127 /* Port 0 interrupts are located on the first bank */ 128 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF)); 129 return; 130 default: 131 off = P_IRQ_OFF(port); 132 break; 133 } 134 135 intrl2_1_mask_clear(priv, P_IRQ_MASK(off)); 136 } 137 138 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv, 139 int port) 140 { 141 unsigned int off; 142 143 switch (port) { 144 case 7: 145 off = P7_IRQ_OFF; 146 break; 147 case 0: 148 /* Port 0 interrupts are located on the first bank */ 149 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF)); 150 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR); 151 return; 152 default: 153 off = P_IRQ_OFF(port); 154 break; 155 } 156 157 intrl2_1_mask_set(priv, P_IRQ_MASK(off)); 158 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR); 159 } 160 161 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port, 162 struct phy_device *phy) 163 { 164 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 165 unsigned int i; 166 u32 reg; 167 168 if (!dsa_is_user_port(ds, port)) 169 return 0; 170 171 /* Clear the memory power down */ 172 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 173 reg &= ~P_TXQ_PSM_VDD(port); 174 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 175 176 /* Enable learning */ 177 reg = core_readl(priv, CORE_DIS_LEARN); 178 reg &= ~BIT(port); 179 core_writel(priv, reg, CORE_DIS_LEARN); 180 181 /* Enable Broadcom tags for that port if requested */ 182 if (priv->brcm_tag_mask & BIT(port)) 183 b53_brcm_hdr_setup(ds, port); 184 185 /* Configure Traffic Class to QoS mapping, allow each priority to map 186 * to a different queue number 187 */ 188 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); 189 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) 190 reg |= i << (PRT_TO_QID_SHIFT * i); 191 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); 192 193 /* Re-enable the GPHY and re-apply workarounds */ 194 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) { 195 bcm_sf2_gphy_enable_set(ds, true); 196 if (phy) { 197 /* if phy_stop() has been called before, phy 198 * will be in halted state, and phy_start() 199 * will call resume. 200 * 201 * the resume path does not configure back 202 * autoneg settings, and since we hard reset 203 * the phy manually here, we need to reset the 204 * state machine also. 205 */ 206 phy->state = PHY_READY; 207 phy_init_hw(phy); 208 } 209 } 210 211 /* Enable MoCA port interrupts to get notified */ 212 if (port == priv->moca_port) 213 bcm_sf2_port_intr_enable(priv, port); 214 215 /* Set per-queue pause threshold to 32 */ 216 core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port)); 217 218 /* Set ACB threshold to 24 */ 219 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) { 220 reg = acb_readl(priv, ACB_QUEUE_CFG(port * 221 SF2_NUM_EGRESS_QUEUES + i)); 222 reg &= ~XOFF_THRESHOLD_MASK; 223 reg |= 24; 224 acb_writel(priv, reg, ACB_QUEUE_CFG(port * 225 SF2_NUM_EGRESS_QUEUES + i)); 226 } 227 228 return b53_enable_port(ds, port, phy); 229 } 230 231 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port) 232 { 233 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 234 u32 reg; 235 236 /* Disable learning while in WoL mode */ 237 if (priv->wol_ports_mask & (1 << port)) { 238 reg = core_readl(priv, CORE_DIS_LEARN); 239 reg |= BIT(port); 240 core_writel(priv, reg, CORE_DIS_LEARN); 241 return; 242 } 243 244 if (port == priv->moca_port) 245 bcm_sf2_port_intr_disable(priv, port); 246 247 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) 248 bcm_sf2_gphy_enable_set(ds, false); 249 250 b53_disable_port(ds, port); 251 252 /* Power down the port memory */ 253 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 254 reg |= P_TXQ_PSM_VDD(port); 255 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 256 } 257 258 259 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr, 260 int regnum, u16 val) 261 { 262 int ret = 0; 263 u32 reg; 264 265 reg = reg_readl(priv, REG_SWITCH_CNTRL); 266 reg |= MDIO_MASTER_SEL; 267 reg_writel(priv, reg, REG_SWITCH_CNTRL); 268 269 /* Page << 8 | offset */ 270 reg = 0x70; 271 reg <<= 2; 272 core_writel(priv, addr, reg); 273 274 /* Page << 8 | offset */ 275 reg = 0x80 << 8 | regnum << 1; 276 reg <<= 2; 277 278 if (op) 279 ret = core_readl(priv, reg); 280 else 281 core_writel(priv, val, reg); 282 283 reg = reg_readl(priv, REG_SWITCH_CNTRL); 284 reg &= ~MDIO_MASTER_SEL; 285 reg_writel(priv, reg, REG_SWITCH_CNTRL); 286 287 return ret & 0xffff; 288 } 289 290 static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 291 { 292 struct bcm_sf2_priv *priv = bus->priv; 293 294 /* Intercept reads from Broadcom pseudo-PHY address, else, send 295 * them to our master MDIO bus controller 296 */ 297 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) 298 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0); 299 else 300 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum); 301 } 302 303 static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 304 u16 val) 305 { 306 struct bcm_sf2_priv *priv = bus->priv; 307 308 /* Intercept writes to the Broadcom pseudo-PHY address, else, 309 * send them to our master MDIO bus controller 310 */ 311 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) 312 return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val); 313 else 314 return mdiobus_write_nested(priv->master_mii_bus, addr, 315 regnum, val); 316 } 317 318 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id) 319 { 320 struct dsa_switch *ds = dev_id; 321 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 322 323 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) & 324 ~priv->irq0_mask; 325 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR); 326 327 return IRQ_HANDLED; 328 } 329 330 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id) 331 { 332 struct dsa_switch *ds = dev_id; 333 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 334 335 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) & 336 ~priv->irq1_mask; 337 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR); 338 339 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) { 340 priv->port_sts[7].link = true; 341 dsa_port_phylink_mac_change(ds, 7, true); 342 } 343 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) { 344 priv->port_sts[7].link = false; 345 dsa_port_phylink_mac_change(ds, 7, false); 346 } 347 348 return IRQ_HANDLED; 349 } 350 351 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv) 352 { 353 unsigned int timeout = 1000; 354 u32 reg; 355 int ret; 356 357 /* The watchdog reset does not work on 7278, we need to hit the 358 * "external" reset line through the reset controller. 359 */ 360 if (priv->type == BCM7278_DEVICE_ID && !IS_ERR(priv->rcdev)) { 361 ret = reset_control_assert(priv->rcdev); 362 if (ret) 363 return ret; 364 365 return reset_control_deassert(priv->rcdev); 366 } 367 368 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 369 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET; 370 core_writel(priv, reg, CORE_WATCHDOG_CTRL); 371 372 do { 373 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 374 if (!(reg & SOFTWARE_RESET)) 375 break; 376 377 usleep_range(1000, 2000); 378 } while (timeout-- > 0); 379 380 if (timeout == 0) 381 return -ETIMEDOUT; 382 383 return 0; 384 } 385 386 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv) 387 { 388 intrl2_0_mask_set(priv, 0xffffffff); 389 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 390 intrl2_1_mask_set(priv, 0xffffffff); 391 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 392 } 393 394 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv, 395 struct device_node *dn) 396 { 397 struct device_node *port; 398 unsigned int port_num; 399 phy_interface_t mode; 400 int err; 401 402 priv->moca_port = -1; 403 404 for_each_available_child_of_node(dn, port) { 405 if (of_property_read_u32(port, "reg", &port_num)) 406 continue; 407 408 /* Internal PHYs get assigned a specific 'phy-mode' property 409 * value: "internal" to help flag them before MDIO probing 410 * has completed, since they might be turned off at that 411 * time 412 */ 413 err = of_get_phy_mode(port, &mode); 414 if (err) 415 continue; 416 417 if (mode == PHY_INTERFACE_MODE_INTERNAL) 418 priv->int_phy_mask |= 1 << port_num; 419 420 if (mode == PHY_INTERFACE_MODE_MOCA) 421 priv->moca_port = port_num; 422 423 if (of_property_read_bool(port, "brcm,use-bcm-hdr")) 424 priv->brcm_tag_mask |= 1 << port_num; 425 } 426 } 427 428 static int bcm_sf2_mdio_register(struct dsa_switch *ds) 429 { 430 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 431 struct device_node *dn; 432 static int index; 433 int err; 434 435 /* Find our integrated MDIO bus node */ 436 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio"); 437 priv->master_mii_bus = of_mdio_find_bus(dn); 438 if (!priv->master_mii_bus) 439 return -EPROBE_DEFER; 440 441 get_device(&priv->master_mii_bus->dev); 442 priv->master_mii_dn = dn; 443 444 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev); 445 if (!priv->slave_mii_bus) 446 return -ENOMEM; 447 448 priv->slave_mii_bus->priv = priv; 449 priv->slave_mii_bus->name = "sf2 slave mii"; 450 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read; 451 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write; 452 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d", 453 index++); 454 priv->slave_mii_bus->dev.of_node = dn; 455 456 /* Include the pseudo-PHY address to divert reads towards our 457 * workaround. This is only required for 7445D0, since 7445E0 458 * disconnects the internal switch pseudo-PHY such that we can use the 459 * regular SWITCH_MDIO master controller instead. 460 * 461 * Here we flag the pseudo PHY as needing special treatment and would 462 * otherwise make all other PHY read/writes go to the master MDIO bus 463 * controller that comes with this switch backed by the "mdio-unimac" 464 * driver. 465 */ 466 if (of_machine_is_compatible("brcm,bcm7445d0")) 467 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR); 468 else 469 priv->indir_phy_mask = 0; 470 471 ds->phys_mii_mask = priv->indir_phy_mask; 472 ds->slave_mii_bus = priv->slave_mii_bus; 473 priv->slave_mii_bus->parent = ds->dev->parent; 474 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask; 475 476 err = of_mdiobus_register(priv->slave_mii_bus, dn); 477 if (err && dn) 478 of_node_put(dn); 479 480 return err; 481 } 482 483 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv) 484 { 485 mdiobus_unregister(priv->slave_mii_bus); 486 of_node_put(priv->master_mii_dn); 487 } 488 489 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port) 490 { 491 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 492 493 /* The BCM7xxx PHY driver expects to find the integrated PHY revision 494 * in bits 15:8 and the patch level in bits 7:0 which is exactly what 495 * the REG_PHY_REVISION register layout is. 496 */ 497 498 return priv->hw_params.gphy_rev; 499 } 500 501 static void bcm_sf2_sw_validate(struct dsa_switch *ds, int port, 502 unsigned long *supported, 503 struct phylink_link_state *state) 504 { 505 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 506 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 507 508 if (!phy_interface_mode_is_rgmii(state->interface) && 509 state->interface != PHY_INTERFACE_MODE_MII && 510 state->interface != PHY_INTERFACE_MODE_REVMII && 511 state->interface != PHY_INTERFACE_MODE_GMII && 512 state->interface != PHY_INTERFACE_MODE_INTERNAL && 513 state->interface != PHY_INTERFACE_MODE_MOCA) { 514 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 515 if (port != core_readl(priv, CORE_IMP0_PRT_ID)) 516 dev_err(ds->dev, 517 "Unsupported interface: %d for port %d\n", 518 state->interface, port); 519 return; 520 } 521 522 /* Allow all the expected bits */ 523 phylink_set(mask, Autoneg); 524 phylink_set_port_modes(mask); 525 phylink_set(mask, Pause); 526 phylink_set(mask, Asym_Pause); 527 528 /* With the exclusion of MII and Reverse MII, we support Gigabit, 529 * including Half duplex 530 */ 531 if (state->interface != PHY_INTERFACE_MODE_MII && 532 state->interface != PHY_INTERFACE_MODE_REVMII) { 533 phylink_set(mask, 1000baseT_Full); 534 phylink_set(mask, 1000baseT_Half); 535 } 536 537 phylink_set(mask, 10baseT_Half); 538 phylink_set(mask, 10baseT_Full); 539 phylink_set(mask, 100baseT_Half); 540 phylink_set(mask, 100baseT_Full); 541 542 bitmap_and(supported, supported, mask, 543 __ETHTOOL_LINK_MODE_MASK_NBITS); 544 bitmap_and(state->advertising, state->advertising, mask, 545 __ETHTOOL_LINK_MODE_MASK_NBITS); 546 } 547 548 static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port, 549 unsigned int mode, 550 const struct phylink_link_state *state) 551 { 552 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 553 u32 id_mode_dis = 0, port_mode; 554 u32 reg, offset; 555 556 if (port == core_readl(priv, CORE_IMP0_PRT_ID)) 557 return; 558 559 if (priv->type == BCM7445_DEVICE_ID) 560 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port); 561 else 562 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port); 563 564 switch (state->interface) { 565 case PHY_INTERFACE_MODE_RGMII: 566 id_mode_dis = 1; 567 /* fallthrough */ 568 case PHY_INTERFACE_MODE_RGMII_TXID: 569 port_mode = EXT_GPHY; 570 break; 571 case PHY_INTERFACE_MODE_MII: 572 port_mode = EXT_EPHY; 573 break; 574 case PHY_INTERFACE_MODE_REVMII: 575 port_mode = EXT_REVMII; 576 break; 577 default: 578 /* all other PHYs: internal and MoCA */ 579 goto force_link; 580 } 581 582 /* Clear id_mode_dis bit, and the existing port mode, let 583 * RGMII_MODE_EN bet set by mac_link_{up,down} 584 */ 585 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); 586 reg &= ~ID_MODE_DIS; 587 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT); 588 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN); 589 590 reg |= port_mode; 591 if (id_mode_dis) 592 reg |= ID_MODE_DIS; 593 594 if (state->pause & MLO_PAUSE_TXRX_MASK) { 595 if (state->pause & MLO_PAUSE_TX) 596 reg |= TX_PAUSE_EN; 597 reg |= RX_PAUSE_EN; 598 } 599 600 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); 601 602 force_link: 603 /* Force link settings detected from the PHY */ 604 reg = SW_OVERRIDE; 605 switch (state->speed) { 606 case SPEED_1000: 607 reg |= SPDSTS_1000 << SPEED_SHIFT; 608 break; 609 case SPEED_100: 610 reg |= SPDSTS_100 << SPEED_SHIFT; 611 break; 612 } 613 614 if (state->link) 615 reg |= LINK_STS; 616 if (state->duplex == DUPLEX_FULL) 617 reg |= DUPLX_MODE; 618 619 if (priv->type == BCM7278_DEVICE_ID && dsa_is_cpu_port(ds, port)) 620 reg |= GMIIP_SPEED_UP_2G; 621 622 core_writel(priv, reg, offset); 623 } 624 625 static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port, 626 phy_interface_t interface, bool link) 627 { 628 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 629 u32 reg; 630 631 if (!phy_interface_mode_is_rgmii(interface) && 632 interface != PHY_INTERFACE_MODE_MII && 633 interface != PHY_INTERFACE_MODE_REVMII) 634 return; 635 636 /* If the link is down, just disable the interface to conserve power */ 637 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); 638 if (link) 639 reg |= RGMII_MODE_EN; 640 else 641 reg &= ~RGMII_MODE_EN; 642 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); 643 } 644 645 static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port, 646 unsigned int mode, 647 phy_interface_t interface) 648 { 649 bcm_sf2_sw_mac_link_set(ds, port, interface, false); 650 } 651 652 static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port, 653 unsigned int mode, 654 phy_interface_t interface, 655 struct phy_device *phydev) 656 { 657 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 658 struct ethtool_eee *p = &priv->dev->ports[port].eee; 659 660 bcm_sf2_sw_mac_link_set(ds, port, interface, true); 661 662 if (mode == MLO_AN_PHY && phydev) 663 p->eee_enabled = b53_eee_init(ds, port, phydev); 664 } 665 666 static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port, 667 struct phylink_link_state *status) 668 { 669 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 670 671 status->link = false; 672 673 /* MoCA port is special as we do not get link status from CORE_LNKSTS, 674 * which means that we need to force the link at the port override 675 * level to get the data to flow. We do use what the interrupt handler 676 * did determine before. 677 * 678 * For the other ports, we just force the link status, since this is 679 * a fixed PHY device. 680 */ 681 if (port == priv->moca_port) { 682 status->link = priv->port_sts[port].link; 683 /* For MoCA interfaces, also force a link down notification 684 * since some version of the user-space daemon (mocad) use 685 * cmd->autoneg to force the link, which messes up the PHY 686 * state machine and make it go in PHY_FORCING state instead. 687 */ 688 if (!status->link) 689 netif_carrier_off(dsa_to_port(ds, port)->slave); 690 status->duplex = DUPLEX_FULL; 691 } else { 692 status->link = true; 693 } 694 } 695 696 static void bcm_sf2_enable_acb(struct dsa_switch *ds) 697 { 698 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 699 u32 reg; 700 701 /* Enable ACB globally */ 702 reg = acb_readl(priv, ACB_CONTROL); 703 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT); 704 acb_writel(priv, reg, ACB_CONTROL); 705 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT); 706 reg |= ACB_EN | ACB_ALGORITHM; 707 acb_writel(priv, reg, ACB_CONTROL); 708 } 709 710 static int bcm_sf2_sw_suspend(struct dsa_switch *ds) 711 { 712 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 713 unsigned int port; 714 715 bcm_sf2_intr_disable(priv); 716 717 /* Disable all ports physically present including the IMP 718 * port, the other ones have already been disabled during 719 * bcm_sf2_sw_setup 720 */ 721 for (port = 0; port < ds->num_ports; port++) { 722 if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port)) 723 bcm_sf2_port_disable(ds, port); 724 } 725 726 return 0; 727 } 728 729 static int bcm_sf2_sw_resume(struct dsa_switch *ds) 730 { 731 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 732 int ret; 733 734 ret = bcm_sf2_sw_rst(priv); 735 if (ret) { 736 pr_err("%s: failed to software reset switch\n", __func__); 737 return ret; 738 } 739 740 ret = bcm_sf2_cfp_resume(ds); 741 if (ret) 742 return ret; 743 744 if (priv->hw_params.num_gphy == 1) 745 bcm_sf2_gphy_enable_set(ds, true); 746 747 ds->ops->setup(ds); 748 749 return 0; 750 } 751 752 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port, 753 struct ethtool_wolinfo *wol) 754 { 755 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master; 756 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 757 struct ethtool_wolinfo pwol = { }; 758 759 /* Get the parent device WoL settings */ 760 if (p->ethtool_ops->get_wol) 761 p->ethtool_ops->get_wol(p, &pwol); 762 763 /* Advertise the parent device supported settings */ 764 wol->supported = pwol.supported; 765 memset(&wol->sopass, 0, sizeof(wol->sopass)); 766 767 if (pwol.wolopts & WAKE_MAGICSECURE) 768 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass)); 769 770 if (priv->wol_ports_mask & (1 << port)) 771 wol->wolopts = pwol.wolopts; 772 else 773 wol->wolopts = 0; 774 } 775 776 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port, 777 struct ethtool_wolinfo *wol) 778 { 779 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master; 780 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 781 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 782 struct ethtool_wolinfo pwol = { }; 783 784 if (p->ethtool_ops->get_wol) 785 p->ethtool_ops->get_wol(p, &pwol); 786 if (wol->wolopts & ~pwol.supported) 787 return -EINVAL; 788 789 if (wol->wolopts) 790 priv->wol_ports_mask |= (1 << port); 791 else 792 priv->wol_ports_mask &= ~(1 << port); 793 794 /* If we have at least one port enabled, make sure the CPU port 795 * is also enabled. If the CPU port is the last one enabled, we disable 796 * it since this configuration does not make sense. 797 */ 798 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port)) 799 priv->wol_ports_mask |= (1 << cpu_port); 800 else 801 priv->wol_ports_mask &= ~(1 << cpu_port); 802 803 return p->ethtool_ops->set_wol(p, wol); 804 } 805 806 static int bcm_sf2_sw_setup(struct dsa_switch *ds) 807 { 808 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 809 unsigned int port; 810 811 /* Enable all valid ports and disable those unused */ 812 for (port = 0; port < priv->hw_params.num_ports; port++) { 813 /* IMP port receives special treatment */ 814 if (dsa_is_user_port(ds, port)) 815 bcm_sf2_port_setup(ds, port, NULL); 816 else if (dsa_is_cpu_port(ds, port)) 817 bcm_sf2_imp_setup(ds, port); 818 else 819 bcm_sf2_port_disable(ds, port); 820 } 821 822 b53_configure_vlan(ds); 823 bcm_sf2_enable_acb(ds); 824 825 return 0; 826 } 827 828 /* The SWITCH_CORE register space is managed by b53 but operates on a page + 829 * register basis so we need to translate that into an address that the 830 * bus-glue understands. 831 */ 832 #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2) 833 834 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg, 835 u8 *val) 836 { 837 struct bcm_sf2_priv *priv = dev->priv; 838 839 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 840 841 return 0; 842 } 843 844 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg, 845 u16 *val) 846 { 847 struct bcm_sf2_priv *priv = dev->priv; 848 849 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 850 851 return 0; 852 } 853 854 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg, 855 u32 *val) 856 { 857 struct bcm_sf2_priv *priv = dev->priv; 858 859 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 860 861 return 0; 862 } 863 864 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg, 865 u64 *val) 866 { 867 struct bcm_sf2_priv *priv = dev->priv; 868 869 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg)); 870 871 return 0; 872 } 873 874 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg, 875 u8 value) 876 { 877 struct bcm_sf2_priv *priv = dev->priv; 878 879 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 880 881 return 0; 882 } 883 884 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg, 885 u16 value) 886 { 887 struct bcm_sf2_priv *priv = dev->priv; 888 889 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 890 891 return 0; 892 } 893 894 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg, 895 u32 value) 896 { 897 struct bcm_sf2_priv *priv = dev->priv; 898 899 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 900 901 return 0; 902 } 903 904 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg, 905 u64 value) 906 { 907 struct bcm_sf2_priv *priv = dev->priv; 908 909 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 910 911 return 0; 912 } 913 914 static const struct b53_io_ops bcm_sf2_io_ops = { 915 .read8 = bcm_sf2_core_read8, 916 .read16 = bcm_sf2_core_read16, 917 .read32 = bcm_sf2_core_read32, 918 .read48 = bcm_sf2_core_read64, 919 .read64 = bcm_sf2_core_read64, 920 .write8 = bcm_sf2_core_write8, 921 .write16 = bcm_sf2_core_write16, 922 .write32 = bcm_sf2_core_write32, 923 .write48 = bcm_sf2_core_write64, 924 .write64 = bcm_sf2_core_write64, 925 }; 926 927 static void bcm_sf2_sw_get_strings(struct dsa_switch *ds, int port, 928 u32 stringset, uint8_t *data) 929 { 930 int cnt = b53_get_sset_count(ds, port, stringset); 931 932 b53_get_strings(ds, port, stringset, data); 933 bcm_sf2_cfp_get_strings(ds, port, stringset, 934 data + cnt * ETH_GSTRING_LEN); 935 } 936 937 static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds, int port, 938 uint64_t *data) 939 { 940 int cnt = b53_get_sset_count(ds, port, ETH_SS_STATS); 941 942 b53_get_ethtool_stats(ds, port, data); 943 bcm_sf2_cfp_get_ethtool_stats(ds, port, data + cnt); 944 } 945 946 static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds, int port, 947 int sset) 948 { 949 int cnt = b53_get_sset_count(ds, port, sset); 950 951 if (cnt < 0) 952 return cnt; 953 954 cnt += bcm_sf2_cfp_get_sset_count(ds, port, sset); 955 956 return cnt; 957 } 958 959 static const struct dsa_switch_ops bcm_sf2_ops = { 960 .get_tag_protocol = b53_get_tag_protocol, 961 .setup = bcm_sf2_sw_setup, 962 .get_strings = bcm_sf2_sw_get_strings, 963 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats, 964 .get_sset_count = bcm_sf2_sw_get_sset_count, 965 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 966 .get_phy_flags = bcm_sf2_sw_get_phy_flags, 967 .phylink_validate = bcm_sf2_sw_validate, 968 .phylink_mac_config = bcm_sf2_sw_mac_config, 969 .phylink_mac_link_down = bcm_sf2_sw_mac_link_down, 970 .phylink_mac_link_up = bcm_sf2_sw_mac_link_up, 971 .phylink_fixed_state = bcm_sf2_sw_fixed_state, 972 .suspend = bcm_sf2_sw_suspend, 973 .resume = bcm_sf2_sw_resume, 974 .get_wol = bcm_sf2_sw_get_wol, 975 .set_wol = bcm_sf2_sw_set_wol, 976 .port_enable = bcm_sf2_port_setup, 977 .port_disable = bcm_sf2_port_disable, 978 .get_mac_eee = b53_get_mac_eee, 979 .set_mac_eee = b53_set_mac_eee, 980 .port_bridge_join = b53_br_join, 981 .port_bridge_leave = b53_br_leave, 982 .port_stp_state_set = b53_br_set_stp_state, 983 .port_fast_age = b53_br_fast_age, 984 .port_vlan_filtering = b53_vlan_filtering, 985 .port_vlan_prepare = b53_vlan_prepare, 986 .port_vlan_add = b53_vlan_add, 987 .port_vlan_del = b53_vlan_del, 988 .port_fdb_dump = b53_fdb_dump, 989 .port_fdb_add = b53_fdb_add, 990 .port_fdb_del = b53_fdb_del, 991 .get_rxnfc = bcm_sf2_get_rxnfc, 992 .set_rxnfc = bcm_sf2_set_rxnfc, 993 .port_mirror_add = b53_mirror_add, 994 .port_mirror_del = b53_mirror_del, 995 .port_mdb_prepare = b53_mdb_prepare, 996 .port_mdb_add = b53_mdb_add, 997 .port_mdb_del = b53_mdb_del, 998 }; 999 1000 struct bcm_sf2_of_data { 1001 u32 type; 1002 const u16 *reg_offsets; 1003 unsigned int core_reg_align; 1004 unsigned int num_cfp_rules; 1005 }; 1006 1007 /* Register offsets for the SWITCH_REG_* block */ 1008 static const u16 bcm_sf2_7445_reg_offsets[] = { 1009 [REG_SWITCH_CNTRL] = 0x00, 1010 [REG_SWITCH_STATUS] = 0x04, 1011 [REG_DIR_DATA_WRITE] = 0x08, 1012 [REG_DIR_DATA_READ] = 0x0C, 1013 [REG_SWITCH_REVISION] = 0x18, 1014 [REG_PHY_REVISION] = 0x1C, 1015 [REG_SPHY_CNTRL] = 0x2C, 1016 [REG_RGMII_0_CNTRL] = 0x34, 1017 [REG_RGMII_1_CNTRL] = 0x40, 1018 [REG_RGMII_2_CNTRL] = 0x4c, 1019 [REG_LED_0_CNTRL] = 0x90, 1020 [REG_LED_1_CNTRL] = 0x94, 1021 [REG_LED_2_CNTRL] = 0x98, 1022 }; 1023 1024 static const struct bcm_sf2_of_data bcm_sf2_7445_data = { 1025 .type = BCM7445_DEVICE_ID, 1026 .core_reg_align = 0, 1027 .reg_offsets = bcm_sf2_7445_reg_offsets, 1028 .num_cfp_rules = 256, 1029 }; 1030 1031 static const u16 bcm_sf2_7278_reg_offsets[] = { 1032 [REG_SWITCH_CNTRL] = 0x00, 1033 [REG_SWITCH_STATUS] = 0x04, 1034 [REG_DIR_DATA_WRITE] = 0x08, 1035 [REG_DIR_DATA_READ] = 0x0c, 1036 [REG_SWITCH_REVISION] = 0x10, 1037 [REG_PHY_REVISION] = 0x14, 1038 [REG_SPHY_CNTRL] = 0x24, 1039 [REG_RGMII_0_CNTRL] = 0xe0, 1040 [REG_RGMII_1_CNTRL] = 0xec, 1041 [REG_RGMII_2_CNTRL] = 0xf8, 1042 [REG_LED_0_CNTRL] = 0x40, 1043 [REG_LED_1_CNTRL] = 0x4c, 1044 [REG_LED_2_CNTRL] = 0x58, 1045 }; 1046 1047 static const struct bcm_sf2_of_data bcm_sf2_7278_data = { 1048 .type = BCM7278_DEVICE_ID, 1049 .core_reg_align = 1, 1050 .reg_offsets = bcm_sf2_7278_reg_offsets, 1051 .num_cfp_rules = 128, 1052 }; 1053 1054 static const struct of_device_id bcm_sf2_of_match[] = { 1055 { .compatible = "brcm,bcm7445-switch-v4.0", 1056 .data = &bcm_sf2_7445_data 1057 }, 1058 { .compatible = "brcm,bcm7278-switch-v4.0", 1059 .data = &bcm_sf2_7278_data 1060 }, 1061 { .compatible = "brcm,bcm7278-switch-v4.8", 1062 .data = &bcm_sf2_7278_data 1063 }, 1064 { /* sentinel */ }, 1065 }; 1066 MODULE_DEVICE_TABLE(of, bcm_sf2_of_match); 1067 1068 static int bcm_sf2_sw_probe(struct platform_device *pdev) 1069 { 1070 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME; 1071 struct device_node *dn = pdev->dev.of_node; 1072 const struct of_device_id *of_id = NULL; 1073 const struct bcm_sf2_of_data *data; 1074 struct b53_platform_data *pdata; 1075 struct dsa_switch_ops *ops; 1076 struct bcm_sf2_priv *priv; 1077 struct b53_device *dev; 1078 struct dsa_switch *ds; 1079 void __iomem **base; 1080 unsigned int i; 1081 u32 reg, rev; 1082 int ret; 1083 1084 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1085 if (!priv) 1086 return -ENOMEM; 1087 1088 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL); 1089 if (!ops) 1090 return -ENOMEM; 1091 1092 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv); 1093 if (!dev) 1094 return -ENOMEM; 1095 1096 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1097 if (!pdata) 1098 return -ENOMEM; 1099 1100 of_id = of_match_node(bcm_sf2_of_match, dn); 1101 if (!of_id || !of_id->data) 1102 return -EINVAL; 1103 1104 data = of_id->data; 1105 1106 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */ 1107 priv->type = data->type; 1108 priv->reg_offsets = data->reg_offsets; 1109 priv->core_reg_align = data->core_reg_align; 1110 priv->num_cfp_rules = data->num_cfp_rules; 1111 1112 priv->rcdev = devm_reset_control_get_optional_exclusive(&pdev->dev, 1113 "switch"); 1114 if (PTR_ERR(priv->rcdev) == -EPROBE_DEFER) 1115 return PTR_ERR(priv->rcdev); 1116 1117 /* Auto-detection using standard registers will not work, so 1118 * provide an indication of what kind of device we are for 1119 * b53_common to work with 1120 */ 1121 pdata->chip_id = priv->type; 1122 dev->pdata = pdata; 1123 1124 priv->dev = dev; 1125 ds = dev->ds; 1126 ds->ops = &bcm_sf2_ops; 1127 1128 /* Advertise the 8 egress queues */ 1129 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES; 1130 1131 dev_set_drvdata(&pdev->dev, priv); 1132 1133 spin_lock_init(&priv->indir_lock); 1134 mutex_init(&priv->cfp.lock); 1135 INIT_LIST_HEAD(&priv->cfp.rules_list); 1136 1137 /* CFP rule #0 cannot be used for specific classifications, flag it as 1138 * permanently used 1139 */ 1140 set_bit(0, priv->cfp.used); 1141 set_bit(0, priv->cfp.unique); 1142 1143 bcm_sf2_identify_ports(priv, dn->child); 1144 1145 priv->irq0 = irq_of_parse_and_map(dn, 0); 1146 priv->irq1 = irq_of_parse_and_map(dn, 1); 1147 1148 base = &priv->core; 1149 for (i = 0; i < BCM_SF2_REGS_NUM; i++) { 1150 *base = devm_platform_ioremap_resource(pdev, i); 1151 if (IS_ERR(*base)) { 1152 pr_err("unable to find register: %s\n", reg_names[i]); 1153 return PTR_ERR(*base); 1154 } 1155 base++; 1156 } 1157 1158 ret = bcm_sf2_sw_rst(priv); 1159 if (ret) { 1160 pr_err("unable to software reset switch: %d\n", ret); 1161 return ret; 1162 } 1163 1164 bcm_sf2_gphy_enable_set(priv->dev->ds, true); 1165 1166 ret = bcm_sf2_mdio_register(ds); 1167 if (ret) { 1168 pr_err("failed to register MDIO bus\n"); 1169 return ret; 1170 } 1171 1172 bcm_sf2_gphy_enable_set(priv->dev->ds, false); 1173 1174 ret = bcm_sf2_cfp_rst(priv); 1175 if (ret) { 1176 pr_err("failed to reset CFP\n"); 1177 goto out_mdio; 1178 } 1179 1180 /* Disable all interrupts and request them */ 1181 bcm_sf2_intr_disable(priv); 1182 1183 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0, 1184 "switch_0", ds); 1185 if (ret < 0) { 1186 pr_err("failed to request switch_0 IRQ\n"); 1187 goto out_mdio; 1188 } 1189 1190 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0, 1191 "switch_1", ds); 1192 if (ret < 0) { 1193 pr_err("failed to request switch_1 IRQ\n"); 1194 goto out_mdio; 1195 } 1196 1197 /* Reset the MIB counters */ 1198 reg = core_readl(priv, CORE_GMNCFGCFG); 1199 reg |= RST_MIB_CNT; 1200 core_writel(priv, reg, CORE_GMNCFGCFG); 1201 reg &= ~RST_MIB_CNT; 1202 core_writel(priv, reg, CORE_GMNCFGCFG); 1203 1204 /* Get the maximum number of ports for this switch */ 1205 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1; 1206 if (priv->hw_params.num_ports > DSA_MAX_PORTS) 1207 priv->hw_params.num_ports = DSA_MAX_PORTS; 1208 1209 /* Assume a single GPHY setup if we can't read that property */ 1210 if (of_property_read_u32(dn, "brcm,num-gphy", 1211 &priv->hw_params.num_gphy)) 1212 priv->hw_params.num_gphy = 1; 1213 1214 rev = reg_readl(priv, REG_SWITCH_REVISION); 1215 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) & 1216 SWITCH_TOP_REV_MASK; 1217 priv->hw_params.core_rev = (rev & SF2_REV_MASK); 1218 1219 rev = reg_readl(priv, REG_PHY_REVISION); 1220 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK; 1221 1222 ret = b53_switch_register(dev); 1223 if (ret) 1224 goto out_mdio; 1225 1226 dev_info(&pdev->dev, 1227 "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n", 1228 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff, 1229 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff, 1230 priv->irq0, priv->irq1); 1231 1232 return 0; 1233 1234 out_mdio: 1235 bcm_sf2_mdio_unregister(priv); 1236 return ret; 1237 } 1238 1239 static int bcm_sf2_sw_remove(struct platform_device *pdev) 1240 { 1241 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1242 1243 priv->wol_ports_mask = 0; 1244 /* Disable interrupts */ 1245 bcm_sf2_intr_disable(priv); 1246 dsa_unregister_switch(priv->dev->ds); 1247 bcm_sf2_cfp_exit(priv->dev->ds); 1248 bcm_sf2_mdio_unregister(priv); 1249 if (priv->type == BCM7278_DEVICE_ID && !IS_ERR(priv->rcdev)) 1250 reset_control_assert(priv->rcdev); 1251 1252 return 0; 1253 } 1254 1255 static void bcm_sf2_sw_shutdown(struct platform_device *pdev) 1256 { 1257 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1258 1259 /* For a kernel about to be kexec'd we want to keep the GPHY on for a 1260 * successful MDIO bus scan to occur. If we did turn off the GPHY 1261 * before (e.g: port_disable), this will also power it back on. 1262 * 1263 * Do not rely on kexec_in_progress, just power the PHY on. 1264 */ 1265 if (priv->hw_params.num_gphy == 1) 1266 bcm_sf2_gphy_enable_set(priv->dev->ds, true); 1267 } 1268 1269 #ifdef CONFIG_PM_SLEEP 1270 static int bcm_sf2_suspend(struct device *dev) 1271 { 1272 struct bcm_sf2_priv *priv = dev_get_drvdata(dev); 1273 1274 return dsa_switch_suspend(priv->dev->ds); 1275 } 1276 1277 static int bcm_sf2_resume(struct device *dev) 1278 { 1279 struct bcm_sf2_priv *priv = dev_get_drvdata(dev); 1280 1281 return dsa_switch_resume(priv->dev->ds); 1282 } 1283 #endif /* CONFIG_PM_SLEEP */ 1284 1285 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops, 1286 bcm_sf2_suspend, bcm_sf2_resume); 1287 1288 1289 static struct platform_driver bcm_sf2_driver = { 1290 .probe = bcm_sf2_sw_probe, 1291 .remove = bcm_sf2_sw_remove, 1292 .shutdown = bcm_sf2_sw_shutdown, 1293 .driver = { 1294 .name = "brcm-sf2", 1295 .of_match_table = bcm_sf2_of_match, 1296 .pm = &bcm_sf2_pm_ops, 1297 }, 1298 }; 1299 module_platform_driver(bcm_sf2_driver); 1300 1301 MODULE_AUTHOR("Broadcom Corporation"); 1302 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip"); 1303 MODULE_LICENSE("GPL"); 1304 MODULE_ALIAS("platform:brcm-sf2"); 1305