1 /* 2 * Broadcom Starfighter 2 DSA switch driver 3 * 4 * Copyright (C) 2014, Broadcom Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #include <linux/list.h> 13 #include <linux/module.h> 14 #include <linux/netdevice.h> 15 #include <linux/interrupt.h> 16 #include <linux/platform_device.h> 17 #include <linux/phy.h> 18 #include <linux/phy_fixed.h> 19 #include <linux/phylink.h> 20 #include <linux/mii.h> 21 #include <linux/of.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_address.h> 24 #include <linux/of_net.h> 25 #include <linux/of_mdio.h> 26 #include <net/dsa.h> 27 #include <linux/ethtool.h> 28 #include <linux/if_bridge.h> 29 #include <linux/brcmphy.h> 30 #include <linux/etherdevice.h> 31 #include <linux/platform_data/b53.h> 32 33 #include "bcm_sf2.h" 34 #include "bcm_sf2_regs.h" 35 #include "b53/b53_priv.h" 36 #include "b53/b53_regs.h" 37 38 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port) 39 { 40 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 41 unsigned int i; 42 u32 reg, offset; 43 44 if (priv->type == BCM7445_DEVICE_ID) 45 offset = CORE_STS_OVERRIDE_IMP; 46 else 47 offset = CORE_STS_OVERRIDE_IMP2; 48 49 /* Enable the port memories */ 50 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 51 reg &= ~P_TXQ_PSM_VDD(port); 52 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 53 54 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */ 55 reg = core_readl(priv, CORE_IMP_CTL); 56 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN); 57 reg &= ~(RX_DIS | TX_DIS); 58 core_writel(priv, reg, CORE_IMP_CTL); 59 60 /* Enable forwarding */ 61 core_writel(priv, SW_FWDG_EN, CORE_SWMODE); 62 63 /* Enable IMP port in dumb mode */ 64 reg = core_readl(priv, CORE_SWITCH_CTRL); 65 reg |= MII_DUMB_FWDG_EN; 66 core_writel(priv, reg, CORE_SWITCH_CTRL); 67 68 /* Configure Traffic Class to QoS mapping, allow each priority to map 69 * to a different queue number 70 */ 71 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); 72 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) 73 reg |= i << (PRT_TO_QID_SHIFT * i); 74 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); 75 76 b53_brcm_hdr_setup(ds, port); 77 78 /* Force link status for IMP port */ 79 reg = core_readl(priv, offset); 80 reg |= (MII_SW_OR | LINK_STS); 81 core_writel(priv, reg, offset); 82 } 83 84 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable) 85 { 86 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 87 u32 reg; 88 89 reg = reg_readl(priv, REG_SPHY_CNTRL); 90 if (enable) { 91 reg |= PHY_RESET; 92 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS); 93 reg_writel(priv, reg, REG_SPHY_CNTRL); 94 udelay(21); 95 reg = reg_readl(priv, REG_SPHY_CNTRL); 96 reg &= ~PHY_RESET; 97 } else { 98 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET; 99 reg_writel(priv, reg, REG_SPHY_CNTRL); 100 mdelay(1); 101 reg |= CK25_DIS; 102 } 103 reg_writel(priv, reg, REG_SPHY_CNTRL); 104 105 /* Use PHY-driven LED signaling */ 106 if (!enable) { 107 reg = reg_readl(priv, REG_LED_CNTRL(0)); 108 reg |= SPDLNK_SRC_SEL; 109 reg_writel(priv, reg, REG_LED_CNTRL(0)); 110 } 111 } 112 113 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv, 114 int port) 115 { 116 unsigned int off; 117 118 switch (port) { 119 case 7: 120 off = P7_IRQ_OFF; 121 break; 122 case 0: 123 /* Port 0 interrupts are located on the first bank */ 124 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF)); 125 return; 126 default: 127 off = P_IRQ_OFF(port); 128 break; 129 } 130 131 intrl2_1_mask_clear(priv, P_IRQ_MASK(off)); 132 } 133 134 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv, 135 int port) 136 { 137 unsigned int off; 138 139 switch (port) { 140 case 7: 141 off = P7_IRQ_OFF; 142 break; 143 case 0: 144 /* Port 0 interrupts are located on the first bank */ 145 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF)); 146 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR); 147 return; 148 default: 149 off = P_IRQ_OFF(port); 150 break; 151 } 152 153 intrl2_1_mask_set(priv, P_IRQ_MASK(off)); 154 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR); 155 } 156 157 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port, 158 struct phy_device *phy) 159 { 160 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 161 unsigned int i; 162 u32 reg; 163 164 /* Clear the memory power down */ 165 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 166 reg &= ~P_TXQ_PSM_VDD(port); 167 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 168 169 /* Enable learning */ 170 reg = core_readl(priv, CORE_DIS_LEARN); 171 reg &= ~BIT(port); 172 core_writel(priv, reg, CORE_DIS_LEARN); 173 174 /* Enable Broadcom tags for that port if requested */ 175 if (priv->brcm_tag_mask & BIT(port)) 176 b53_brcm_hdr_setup(ds, port); 177 178 /* Configure Traffic Class to QoS mapping, allow each priority to map 179 * to a different queue number 180 */ 181 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); 182 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) 183 reg |= i << (PRT_TO_QID_SHIFT * i); 184 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); 185 186 /* Re-enable the GPHY and re-apply workarounds */ 187 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) { 188 bcm_sf2_gphy_enable_set(ds, true); 189 if (phy) { 190 /* if phy_stop() has been called before, phy 191 * will be in halted state, and phy_start() 192 * will call resume. 193 * 194 * the resume path does not configure back 195 * autoneg settings, and since we hard reset 196 * the phy manually here, we need to reset the 197 * state machine also. 198 */ 199 phy->state = PHY_READY; 200 phy_init_hw(phy); 201 } 202 } 203 204 /* Enable MoCA port interrupts to get notified */ 205 if (port == priv->moca_port) 206 bcm_sf2_port_intr_enable(priv, port); 207 208 /* Set per-queue pause threshold to 32 */ 209 core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port)); 210 211 /* Set ACB threshold to 24 */ 212 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) { 213 reg = acb_readl(priv, ACB_QUEUE_CFG(port * 214 SF2_NUM_EGRESS_QUEUES + i)); 215 reg &= ~XOFF_THRESHOLD_MASK; 216 reg |= 24; 217 acb_writel(priv, reg, ACB_QUEUE_CFG(port * 218 SF2_NUM_EGRESS_QUEUES + i)); 219 } 220 221 return b53_enable_port(ds, port, phy); 222 } 223 224 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port, 225 struct phy_device *phy) 226 { 227 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 228 u32 reg; 229 230 /* Disable learning while in WoL mode */ 231 if (priv->wol_ports_mask & (1 << port)) { 232 reg = core_readl(priv, CORE_DIS_LEARN); 233 reg |= BIT(port); 234 core_writel(priv, reg, CORE_DIS_LEARN); 235 return; 236 } 237 238 if (port == priv->moca_port) 239 bcm_sf2_port_intr_disable(priv, port); 240 241 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) 242 bcm_sf2_gphy_enable_set(ds, false); 243 244 b53_disable_port(ds, port, phy); 245 246 /* Power down the port memory */ 247 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 248 reg |= P_TXQ_PSM_VDD(port); 249 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 250 } 251 252 253 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr, 254 int regnum, u16 val) 255 { 256 int ret = 0; 257 u32 reg; 258 259 reg = reg_readl(priv, REG_SWITCH_CNTRL); 260 reg |= MDIO_MASTER_SEL; 261 reg_writel(priv, reg, REG_SWITCH_CNTRL); 262 263 /* Page << 8 | offset */ 264 reg = 0x70; 265 reg <<= 2; 266 core_writel(priv, addr, reg); 267 268 /* Page << 8 | offset */ 269 reg = 0x80 << 8 | regnum << 1; 270 reg <<= 2; 271 272 if (op) 273 ret = core_readl(priv, reg); 274 else 275 core_writel(priv, val, reg); 276 277 reg = reg_readl(priv, REG_SWITCH_CNTRL); 278 reg &= ~MDIO_MASTER_SEL; 279 reg_writel(priv, reg, REG_SWITCH_CNTRL); 280 281 return ret & 0xffff; 282 } 283 284 static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 285 { 286 struct bcm_sf2_priv *priv = bus->priv; 287 288 /* Intercept reads from Broadcom pseudo-PHY address, else, send 289 * them to our master MDIO bus controller 290 */ 291 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) 292 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0); 293 else 294 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum); 295 } 296 297 static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 298 u16 val) 299 { 300 struct bcm_sf2_priv *priv = bus->priv; 301 302 /* Intercept writes to the Broadcom pseudo-PHY address, else, 303 * send them to our master MDIO bus controller 304 */ 305 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) 306 bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val); 307 else 308 mdiobus_write_nested(priv->master_mii_bus, addr, regnum, val); 309 310 return 0; 311 } 312 313 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id) 314 { 315 struct dsa_switch *ds = dev_id; 316 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 317 318 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) & 319 ~priv->irq0_mask; 320 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR); 321 322 return IRQ_HANDLED; 323 } 324 325 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id) 326 { 327 struct dsa_switch *ds = dev_id; 328 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 329 330 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) & 331 ~priv->irq1_mask; 332 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR); 333 334 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) { 335 priv->port_sts[7].link = true; 336 dsa_port_phylink_mac_change(ds, 7, true); 337 } 338 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) { 339 priv->port_sts[7].link = false; 340 dsa_port_phylink_mac_change(ds, 7, false); 341 } 342 343 return IRQ_HANDLED; 344 } 345 346 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv) 347 { 348 unsigned int timeout = 1000; 349 u32 reg; 350 351 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 352 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET; 353 core_writel(priv, reg, CORE_WATCHDOG_CTRL); 354 355 do { 356 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 357 if (!(reg & SOFTWARE_RESET)) 358 break; 359 360 usleep_range(1000, 2000); 361 } while (timeout-- > 0); 362 363 if (timeout == 0) 364 return -ETIMEDOUT; 365 366 return 0; 367 } 368 369 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv) 370 { 371 intrl2_0_mask_set(priv, 0xffffffff); 372 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 373 intrl2_1_mask_set(priv, 0xffffffff); 374 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 375 } 376 377 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv, 378 struct device_node *dn) 379 { 380 struct device_node *port; 381 int mode; 382 unsigned int port_num; 383 384 priv->moca_port = -1; 385 386 for_each_available_child_of_node(dn, port) { 387 if (of_property_read_u32(port, "reg", &port_num)) 388 continue; 389 390 /* Internal PHYs get assigned a specific 'phy-mode' property 391 * value: "internal" to help flag them before MDIO probing 392 * has completed, since they might be turned off at that 393 * time 394 */ 395 mode = of_get_phy_mode(port); 396 if (mode < 0) 397 continue; 398 399 if (mode == PHY_INTERFACE_MODE_INTERNAL) 400 priv->int_phy_mask |= 1 << port_num; 401 402 if (mode == PHY_INTERFACE_MODE_MOCA) 403 priv->moca_port = port_num; 404 405 if (of_property_read_bool(port, "brcm,use-bcm-hdr")) 406 priv->brcm_tag_mask |= 1 << port_num; 407 } 408 } 409 410 static int bcm_sf2_mdio_register(struct dsa_switch *ds) 411 { 412 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 413 struct device_node *dn; 414 static int index; 415 int err; 416 417 /* Find our integrated MDIO bus node */ 418 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio"); 419 priv->master_mii_bus = of_mdio_find_bus(dn); 420 if (!priv->master_mii_bus) 421 return -EPROBE_DEFER; 422 423 get_device(&priv->master_mii_bus->dev); 424 priv->master_mii_dn = dn; 425 426 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev); 427 if (!priv->slave_mii_bus) 428 return -ENOMEM; 429 430 priv->slave_mii_bus->priv = priv; 431 priv->slave_mii_bus->name = "sf2 slave mii"; 432 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read; 433 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write; 434 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d", 435 index++); 436 priv->slave_mii_bus->dev.of_node = dn; 437 438 /* Include the pseudo-PHY address to divert reads towards our 439 * workaround. This is only required for 7445D0, since 7445E0 440 * disconnects the internal switch pseudo-PHY such that we can use the 441 * regular SWITCH_MDIO master controller instead. 442 * 443 * Here we flag the pseudo PHY as needing special treatment and would 444 * otherwise make all other PHY read/writes go to the master MDIO bus 445 * controller that comes with this switch backed by the "mdio-unimac" 446 * driver. 447 */ 448 if (of_machine_is_compatible("brcm,bcm7445d0")) 449 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR); 450 else 451 priv->indir_phy_mask = 0; 452 453 ds->phys_mii_mask = priv->indir_phy_mask; 454 ds->slave_mii_bus = priv->slave_mii_bus; 455 priv->slave_mii_bus->parent = ds->dev->parent; 456 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask; 457 458 err = of_mdiobus_register(priv->slave_mii_bus, dn); 459 if (err && dn) 460 of_node_put(dn); 461 462 return err; 463 } 464 465 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv) 466 { 467 mdiobus_unregister(priv->slave_mii_bus); 468 of_node_put(priv->master_mii_dn); 469 } 470 471 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port) 472 { 473 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 474 475 /* The BCM7xxx PHY driver expects to find the integrated PHY revision 476 * in bits 15:8 and the patch level in bits 7:0 which is exactly what 477 * the REG_PHY_REVISION register layout is. 478 */ 479 480 return priv->hw_params.gphy_rev; 481 } 482 483 static void bcm_sf2_sw_validate(struct dsa_switch *ds, int port, 484 unsigned long *supported, 485 struct phylink_link_state *state) 486 { 487 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 488 489 if (!phy_interface_mode_is_rgmii(state->interface) && 490 state->interface != PHY_INTERFACE_MODE_MII && 491 state->interface != PHY_INTERFACE_MODE_REVMII && 492 state->interface != PHY_INTERFACE_MODE_GMII && 493 state->interface != PHY_INTERFACE_MODE_INTERNAL && 494 state->interface != PHY_INTERFACE_MODE_MOCA) { 495 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 496 dev_err(ds->dev, 497 "Unsupported interface: %d\n", state->interface); 498 return; 499 } 500 501 /* Allow all the expected bits */ 502 phylink_set(mask, Autoneg); 503 phylink_set_port_modes(mask); 504 phylink_set(mask, Pause); 505 phylink_set(mask, Asym_Pause); 506 507 /* With the exclusion of MII and Reverse MII, we support Gigabit, 508 * including Half duplex 509 */ 510 if (state->interface != PHY_INTERFACE_MODE_MII && 511 state->interface != PHY_INTERFACE_MODE_REVMII) { 512 phylink_set(mask, 1000baseT_Full); 513 phylink_set(mask, 1000baseT_Half); 514 } 515 516 phylink_set(mask, 10baseT_Half); 517 phylink_set(mask, 10baseT_Full); 518 phylink_set(mask, 100baseT_Half); 519 phylink_set(mask, 100baseT_Full); 520 521 bitmap_and(supported, supported, mask, 522 __ETHTOOL_LINK_MODE_MASK_NBITS); 523 bitmap_and(state->advertising, state->advertising, mask, 524 __ETHTOOL_LINK_MODE_MASK_NBITS); 525 } 526 527 static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port, 528 unsigned int mode, 529 const struct phylink_link_state *state) 530 { 531 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 532 u32 id_mode_dis = 0, port_mode; 533 u32 reg, offset; 534 535 if (priv->type == BCM7445_DEVICE_ID) 536 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port); 537 else 538 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port); 539 540 switch (state->interface) { 541 case PHY_INTERFACE_MODE_RGMII: 542 id_mode_dis = 1; 543 /* fallthrough */ 544 case PHY_INTERFACE_MODE_RGMII_TXID: 545 port_mode = EXT_GPHY; 546 break; 547 case PHY_INTERFACE_MODE_MII: 548 port_mode = EXT_EPHY; 549 break; 550 case PHY_INTERFACE_MODE_REVMII: 551 port_mode = EXT_REVMII; 552 break; 553 default: 554 /* all other PHYs: internal and MoCA */ 555 goto force_link; 556 } 557 558 /* Clear id_mode_dis bit, and the existing port mode, let 559 * RGMII_MODE_EN bet set by mac_link_{up,down} 560 */ 561 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); 562 reg &= ~ID_MODE_DIS; 563 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT); 564 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN); 565 566 reg |= port_mode; 567 if (id_mode_dis) 568 reg |= ID_MODE_DIS; 569 570 if (state->pause & MLO_PAUSE_TXRX_MASK) { 571 if (state->pause & MLO_PAUSE_TX) 572 reg |= TX_PAUSE_EN; 573 reg |= RX_PAUSE_EN; 574 } 575 576 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); 577 578 force_link: 579 /* Force link settings detected from the PHY */ 580 reg = SW_OVERRIDE; 581 switch (state->speed) { 582 case SPEED_1000: 583 reg |= SPDSTS_1000 << SPEED_SHIFT; 584 break; 585 case SPEED_100: 586 reg |= SPDSTS_100 << SPEED_SHIFT; 587 break; 588 } 589 590 if (state->link) 591 reg |= LINK_STS; 592 if (state->duplex == DUPLEX_FULL) 593 reg |= DUPLX_MODE; 594 595 core_writel(priv, reg, offset); 596 } 597 598 static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port, 599 phy_interface_t interface, bool link) 600 { 601 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 602 u32 reg; 603 604 if (!phy_interface_mode_is_rgmii(interface) && 605 interface != PHY_INTERFACE_MODE_MII && 606 interface != PHY_INTERFACE_MODE_REVMII) 607 return; 608 609 /* If the link is down, just disable the interface to conserve power */ 610 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); 611 if (link) 612 reg |= RGMII_MODE_EN; 613 else 614 reg &= ~RGMII_MODE_EN; 615 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); 616 } 617 618 static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port, 619 unsigned int mode, 620 phy_interface_t interface) 621 { 622 bcm_sf2_sw_mac_link_set(ds, port, interface, false); 623 } 624 625 static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port, 626 unsigned int mode, 627 phy_interface_t interface, 628 struct phy_device *phydev) 629 { 630 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 631 struct ethtool_eee *p = &priv->dev->ports[port].eee; 632 633 bcm_sf2_sw_mac_link_set(ds, port, interface, true); 634 635 if (mode == MLO_AN_PHY && phydev) 636 p->eee_enabled = b53_eee_init(ds, port, phydev); 637 } 638 639 static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port, 640 struct phylink_link_state *status) 641 { 642 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 643 644 status->link = false; 645 646 /* MoCA port is special as we do not get link status from CORE_LNKSTS, 647 * which means that we need to force the link at the port override 648 * level to get the data to flow. We do use what the interrupt handler 649 * did determine before. 650 * 651 * For the other ports, we just force the link status, since this is 652 * a fixed PHY device. 653 */ 654 if (port == priv->moca_port) { 655 status->link = priv->port_sts[port].link; 656 /* For MoCA interfaces, also force a link down notification 657 * since some version of the user-space daemon (mocad) use 658 * cmd->autoneg to force the link, which messes up the PHY 659 * state machine and make it go in PHY_FORCING state instead. 660 */ 661 if (!status->link) 662 netif_carrier_off(ds->ports[port].slave); 663 status->duplex = DUPLEX_FULL; 664 } else { 665 status->link = true; 666 } 667 } 668 669 static void bcm_sf2_enable_acb(struct dsa_switch *ds) 670 { 671 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 672 u32 reg; 673 674 /* Enable ACB globally */ 675 reg = acb_readl(priv, ACB_CONTROL); 676 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT); 677 acb_writel(priv, reg, ACB_CONTROL); 678 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT); 679 reg |= ACB_EN | ACB_ALGORITHM; 680 acb_writel(priv, reg, ACB_CONTROL); 681 } 682 683 static int bcm_sf2_sw_suspend(struct dsa_switch *ds) 684 { 685 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 686 unsigned int port; 687 688 bcm_sf2_intr_disable(priv); 689 690 /* Disable all ports physically present including the IMP 691 * port, the other ones have already been disabled during 692 * bcm_sf2_sw_setup 693 */ 694 for (port = 0; port < DSA_MAX_PORTS; port++) { 695 if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port)) 696 bcm_sf2_port_disable(ds, port, NULL); 697 } 698 699 return 0; 700 } 701 702 static int bcm_sf2_sw_resume(struct dsa_switch *ds) 703 { 704 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 705 int ret; 706 707 ret = bcm_sf2_sw_rst(priv); 708 if (ret) { 709 pr_err("%s: failed to software reset switch\n", __func__); 710 return ret; 711 } 712 713 ret = bcm_sf2_cfp_resume(ds); 714 if (ret) 715 return ret; 716 717 if (priv->hw_params.num_gphy == 1) 718 bcm_sf2_gphy_enable_set(ds, true); 719 720 ds->ops->setup(ds); 721 722 return 0; 723 } 724 725 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port, 726 struct ethtool_wolinfo *wol) 727 { 728 struct net_device *p = ds->ports[port].cpu_dp->master; 729 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 730 struct ethtool_wolinfo pwol; 731 732 /* Get the parent device WoL settings */ 733 p->ethtool_ops->get_wol(p, &pwol); 734 735 /* Advertise the parent device supported settings */ 736 wol->supported = pwol.supported; 737 memset(&wol->sopass, 0, sizeof(wol->sopass)); 738 739 if (pwol.wolopts & WAKE_MAGICSECURE) 740 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass)); 741 742 if (priv->wol_ports_mask & (1 << port)) 743 wol->wolopts = pwol.wolopts; 744 else 745 wol->wolopts = 0; 746 } 747 748 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port, 749 struct ethtool_wolinfo *wol) 750 { 751 struct net_device *p = ds->ports[port].cpu_dp->master; 752 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 753 s8 cpu_port = ds->ports[port].cpu_dp->index; 754 struct ethtool_wolinfo pwol; 755 756 p->ethtool_ops->get_wol(p, &pwol); 757 if (wol->wolopts & ~pwol.supported) 758 return -EINVAL; 759 760 if (wol->wolopts) 761 priv->wol_ports_mask |= (1 << port); 762 else 763 priv->wol_ports_mask &= ~(1 << port); 764 765 /* If we have at least one port enabled, make sure the CPU port 766 * is also enabled. If the CPU port is the last one enabled, we disable 767 * it since this configuration does not make sense. 768 */ 769 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port)) 770 priv->wol_ports_mask |= (1 << cpu_port); 771 else 772 priv->wol_ports_mask &= ~(1 << cpu_port); 773 774 return p->ethtool_ops->set_wol(p, wol); 775 } 776 777 static int bcm_sf2_sw_setup(struct dsa_switch *ds) 778 { 779 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 780 unsigned int port; 781 782 /* Enable all valid ports and disable those unused */ 783 for (port = 0; port < priv->hw_params.num_ports; port++) { 784 /* IMP port receives special treatment */ 785 if (dsa_is_user_port(ds, port)) 786 bcm_sf2_port_setup(ds, port, NULL); 787 else if (dsa_is_cpu_port(ds, port)) 788 bcm_sf2_imp_setup(ds, port); 789 else 790 bcm_sf2_port_disable(ds, port, NULL); 791 } 792 793 b53_configure_vlan(ds); 794 bcm_sf2_enable_acb(ds); 795 796 return 0; 797 } 798 799 /* The SWITCH_CORE register space is managed by b53 but operates on a page + 800 * register basis so we need to translate that into an address that the 801 * bus-glue understands. 802 */ 803 #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2) 804 805 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg, 806 u8 *val) 807 { 808 struct bcm_sf2_priv *priv = dev->priv; 809 810 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 811 812 return 0; 813 } 814 815 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg, 816 u16 *val) 817 { 818 struct bcm_sf2_priv *priv = dev->priv; 819 820 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 821 822 return 0; 823 } 824 825 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg, 826 u32 *val) 827 { 828 struct bcm_sf2_priv *priv = dev->priv; 829 830 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 831 832 return 0; 833 } 834 835 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg, 836 u64 *val) 837 { 838 struct bcm_sf2_priv *priv = dev->priv; 839 840 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg)); 841 842 return 0; 843 } 844 845 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg, 846 u8 value) 847 { 848 struct bcm_sf2_priv *priv = dev->priv; 849 850 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 851 852 return 0; 853 } 854 855 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg, 856 u16 value) 857 { 858 struct bcm_sf2_priv *priv = dev->priv; 859 860 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 861 862 return 0; 863 } 864 865 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg, 866 u32 value) 867 { 868 struct bcm_sf2_priv *priv = dev->priv; 869 870 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 871 872 return 0; 873 } 874 875 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg, 876 u64 value) 877 { 878 struct bcm_sf2_priv *priv = dev->priv; 879 880 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 881 882 return 0; 883 } 884 885 static const struct b53_io_ops bcm_sf2_io_ops = { 886 .read8 = bcm_sf2_core_read8, 887 .read16 = bcm_sf2_core_read16, 888 .read32 = bcm_sf2_core_read32, 889 .read48 = bcm_sf2_core_read64, 890 .read64 = bcm_sf2_core_read64, 891 .write8 = bcm_sf2_core_write8, 892 .write16 = bcm_sf2_core_write16, 893 .write32 = bcm_sf2_core_write32, 894 .write48 = bcm_sf2_core_write64, 895 .write64 = bcm_sf2_core_write64, 896 }; 897 898 static const struct dsa_switch_ops bcm_sf2_ops = { 899 .get_tag_protocol = b53_get_tag_protocol, 900 .setup = bcm_sf2_sw_setup, 901 .get_strings = b53_get_strings, 902 .get_ethtool_stats = b53_get_ethtool_stats, 903 .get_sset_count = b53_get_sset_count, 904 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 905 .get_phy_flags = bcm_sf2_sw_get_phy_flags, 906 .phylink_validate = bcm_sf2_sw_validate, 907 .phylink_mac_config = bcm_sf2_sw_mac_config, 908 .phylink_mac_link_down = bcm_sf2_sw_mac_link_down, 909 .phylink_mac_link_up = bcm_sf2_sw_mac_link_up, 910 .phylink_fixed_state = bcm_sf2_sw_fixed_state, 911 .suspend = bcm_sf2_sw_suspend, 912 .resume = bcm_sf2_sw_resume, 913 .get_wol = bcm_sf2_sw_get_wol, 914 .set_wol = bcm_sf2_sw_set_wol, 915 .port_enable = bcm_sf2_port_setup, 916 .port_disable = bcm_sf2_port_disable, 917 .get_mac_eee = b53_get_mac_eee, 918 .set_mac_eee = b53_set_mac_eee, 919 .port_bridge_join = b53_br_join, 920 .port_bridge_leave = b53_br_leave, 921 .port_stp_state_set = b53_br_set_stp_state, 922 .port_fast_age = b53_br_fast_age, 923 .port_vlan_filtering = b53_vlan_filtering, 924 .port_vlan_prepare = b53_vlan_prepare, 925 .port_vlan_add = b53_vlan_add, 926 .port_vlan_del = b53_vlan_del, 927 .port_fdb_dump = b53_fdb_dump, 928 .port_fdb_add = b53_fdb_add, 929 .port_fdb_del = b53_fdb_del, 930 .get_rxnfc = bcm_sf2_get_rxnfc, 931 .set_rxnfc = bcm_sf2_set_rxnfc, 932 .port_mirror_add = b53_mirror_add, 933 .port_mirror_del = b53_mirror_del, 934 }; 935 936 struct bcm_sf2_of_data { 937 u32 type; 938 const u16 *reg_offsets; 939 unsigned int core_reg_align; 940 unsigned int num_cfp_rules; 941 }; 942 943 /* Register offsets for the SWITCH_REG_* block */ 944 static const u16 bcm_sf2_7445_reg_offsets[] = { 945 [REG_SWITCH_CNTRL] = 0x00, 946 [REG_SWITCH_STATUS] = 0x04, 947 [REG_DIR_DATA_WRITE] = 0x08, 948 [REG_DIR_DATA_READ] = 0x0C, 949 [REG_SWITCH_REVISION] = 0x18, 950 [REG_PHY_REVISION] = 0x1C, 951 [REG_SPHY_CNTRL] = 0x2C, 952 [REG_RGMII_0_CNTRL] = 0x34, 953 [REG_RGMII_1_CNTRL] = 0x40, 954 [REG_RGMII_2_CNTRL] = 0x4c, 955 [REG_LED_0_CNTRL] = 0x90, 956 [REG_LED_1_CNTRL] = 0x94, 957 [REG_LED_2_CNTRL] = 0x98, 958 }; 959 960 static const struct bcm_sf2_of_data bcm_sf2_7445_data = { 961 .type = BCM7445_DEVICE_ID, 962 .core_reg_align = 0, 963 .reg_offsets = bcm_sf2_7445_reg_offsets, 964 .num_cfp_rules = 256, 965 }; 966 967 static const u16 bcm_sf2_7278_reg_offsets[] = { 968 [REG_SWITCH_CNTRL] = 0x00, 969 [REG_SWITCH_STATUS] = 0x04, 970 [REG_DIR_DATA_WRITE] = 0x08, 971 [REG_DIR_DATA_READ] = 0x0c, 972 [REG_SWITCH_REVISION] = 0x10, 973 [REG_PHY_REVISION] = 0x14, 974 [REG_SPHY_CNTRL] = 0x24, 975 [REG_RGMII_0_CNTRL] = 0xe0, 976 [REG_RGMII_1_CNTRL] = 0xec, 977 [REG_RGMII_2_CNTRL] = 0xf8, 978 [REG_LED_0_CNTRL] = 0x40, 979 [REG_LED_1_CNTRL] = 0x4c, 980 [REG_LED_2_CNTRL] = 0x58, 981 }; 982 983 static const struct bcm_sf2_of_data bcm_sf2_7278_data = { 984 .type = BCM7278_DEVICE_ID, 985 .core_reg_align = 1, 986 .reg_offsets = bcm_sf2_7278_reg_offsets, 987 .num_cfp_rules = 128, 988 }; 989 990 static const struct of_device_id bcm_sf2_of_match[] = { 991 { .compatible = "brcm,bcm7445-switch-v4.0", 992 .data = &bcm_sf2_7445_data 993 }, 994 { .compatible = "brcm,bcm7278-switch-v4.0", 995 .data = &bcm_sf2_7278_data 996 }, 997 { .compatible = "brcm,bcm7278-switch-v4.8", 998 .data = &bcm_sf2_7278_data 999 }, 1000 { /* sentinel */ }, 1001 }; 1002 MODULE_DEVICE_TABLE(of, bcm_sf2_of_match); 1003 1004 static int bcm_sf2_sw_probe(struct platform_device *pdev) 1005 { 1006 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME; 1007 struct device_node *dn = pdev->dev.of_node; 1008 const struct of_device_id *of_id = NULL; 1009 const struct bcm_sf2_of_data *data; 1010 struct b53_platform_data *pdata; 1011 struct dsa_switch_ops *ops; 1012 struct bcm_sf2_priv *priv; 1013 struct b53_device *dev; 1014 struct dsa_switch *ds; 1015 void __iomem **base; 1016 struct resource *r; 1017 unsigned int i; 1018 u32 reg, rev; 1019 int ret; 1020 1021 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1022 if (!priv) 1023 return -ENOMEM; 1024 1025 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL); 1026 if (!ops) 1027 return -ENOMEM; 1028 1029 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv); 1030 if (!dev) 1031 return -ENOMEM; 1032 1033 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1034 if (!pdata) 1035 return -ENOMEM; 1036 1037 of_id = of_match_node(bcm_sf2_of_match, dn); 1038 if (!of_id || !of_id->data) 1039 return -EINVAL; 1040 1041 data = of_id->data; 1042 1043 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */ 1044 priv->type = data->type; 1045 priv->reg_offsets = data->reg_offsets; 1046 priv->core_reg_align = data->core_reg_align; 1047 priv->num_cfp_rules = data->num_cfp_rules; 1048 1049 /* Auto-detection using standard registers will not work, so 1050 * provide an indication of what kind of device we are for 1051 * b53_common to work with 1052 */ 1053 pdata->chip_id = priv->type; 1054 dev->pdata = pdata; 1055 1056 priv->dev = dev; 1057 ds = dev->ds; 1058 ds->ops = &bcm_sf2_ops; 1059 1060 /* Advertise the 8 egress queues */ 1061 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES; 1062 1063 dev_set_drvdata(&pdev->dev, priv); 1064 1065 spin_lock_init(&priv->indir_lock); 1066 mutex_init(&priv->stats_mutex); 1067 mutex_init(&priv->cfp.lock); 1068 INIT_LIST_HEAD(&priv->cfp.rules_list); 1069 1070 /* CFP rule #0 cannot be used for specific classifications, flag it as 1071 * permanently used 1072 */ 1073 set_bit(0, priv->cfp.used); 1074 set_bit(0, priv->cfp.unique); 1075 1076 bcm_sf2_identify_ports(priv, dn->child); 1077 1078 priv->irq0 = irq_of_parse_and_map(dn, 0); 1079 priv->irq1 = irq_of_parse_and_map(dn, 1); 1080 1081 base = &priv->core; 1082 for (i = 0; i < BCM_SF2_REGS_NUM; i++) { 1083 r = platform_get_resource(pdev, IORESOURCE_MEM, i); 1084 *base = devm_ioremap_resource(&pdev->dev, r); 1085 if (IS_ERR(*base)) { 1086 pr_err("unable to find register: %s\n", reg_names[i]); 1087 return PTR_ERR(*base); 1088 } 1089 base++; 1090 } 1091 1092 ret = bcm_sf2_sw_rst(priv); 1093 if (ret) { 1094 pr_err("unable to software reset switch: %d\n", ret); 1095 return ret; 1096 } 1097 1098 bcm_sf2_gphy_enable_set(priv->dev->ds, true); 1099 1100 ret = bcm_sf2_mdio_register(ds); 1101 if (ret) { 1102 pr_err("failed to register MDIO bus\n"); 1103 return ret; 1104 } 1105 1106 bcm_sf2_gphy_enable_set(priv->dev->ds, false); 1107 1108 ret = bcm_sf2_cfp_rst(priv); 1109 if (ret) { 1110 pr_err("failed to reset CFP\n"); 1111 goto out_mdio; 1112 } 1113 1114 /* Disable all interrupts and request them */ 1115 bcm_sf2_intr_disable(priv); 1116 1117 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0, 1118 "switch_0", ds); 1119 if (ret < 0) { 1120 pr_err("failed to request switch_0 IRQ\n"); 1121 goto out_mdio; 1122 } 1123 1124 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0, 1125 "switch_1", ds); 1126 if (ret < 0) { 1127 pr_err("failed to request switch_1 IRQ\n"); 1128 goto out_mdio; 1129 } 1130 1131 /* Reset the MIB counters */ 1132 reg = core_readl(priv, CORE_GMNCFGCFG); 1133 reg |= RST_MIB_CNT; 1134 core_writel(priv, reg, CORE_GMNCFGCFG); 1135 reg &= ~RST_MIB_CNT; 1136 core_writel(priv, reg, CORE_GMNCFGCFG); 1137 1138 /* Get the maximum number of ports for this switch */ 1139 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1; 1140 if (priv->hw_params.num_ports > DSA_MAX_PORTS) 1141 priv->hw_params.num_ports = DSA_MAX_PORTS; 1142 1143 /* Assume a single GPHY setup if we can't read that property */ 1144 if (of_property_read_u32(dn, "brcm,num-gphy", 1145 &priv->hw_params.num_gphy)) 1146 priv->hw_params.num_gphy = 1; 1147 1148 rev = reg_readl(priv, REG_SWITCH_REVISION); 1149 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) & 1150 SWITCH_TOP_REV_MASK; 1151 priv->hw_params.core_rev = (rev & SF2_REV_MASK); 1152 1153 rev = reg_readl(priv, REG_PHY_REVISION); 1154 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK; 1155 1156 ret = b53_switch_register(dev); 1157 if (ret) 1158 goto out_mdio; 1159 1160 pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n", 1161 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff, 1162 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff, 1163 priv->core, priv->irq0, priv->irq1); 1164 1165 return 0; 1166 1167 out_mdio: 1168 bcm_sf2_mdio_unregister(priv); 1169 return ret; 1170 } 1171 1172 static int bcm_sf2_sw_remove(struct platform_device *pdev) 1173 { 1174 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1175 1176 priv->wol_ports_mask = 0; 1177 dsa_unregister_switch(priv->dev->ds); 1178 bcm_sf2_cfp_exit(priv->dev->ds); 1179 /* Disable all ports and interrupts */ 1180 bcm_sf2_sw_suspend(priv->dev->ds); 1181 bcm_sf2_mdio_unregister(priv); 1182 1183 return 0; 1184 } 1185 1186 static void bcm_sf2_sw_shutdown(struct platform_device *pdev) 1187 { 1188 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1189 1190 /* For a kernel about to be kexec'd we want to keep the GPHY on for a 1191 * successful MDIO bus scan to occur. If we did turn off the GPHY 1192 * before (e.g: port_disable), this will also power it back on. 1193 * 1194 * Do not rely on kexec_in_progress, just power the PHY on. 1195 */ 1196 if (priv->hw_params.num_gphy == 1) 1197 bcm_sf2_gphy_enable_set(priv->dev->ds, true); 1198 } 1199 1200 #ifdef CONFIG_PM_SLEEP 1201 static int bcm_sf2_suspend(struct device *dev) 1202 { 1203 struct bcm_sf2_priv *priv = dev_get_drvdata(dev); 1204 1205 return dsa_switch_suspend(priv->dev->ds); 1206 } 1207 1208 static int bcm_sf2_resume(struct device *dev) 1209 { 1210 struct bcm_sf2_priv *priv = dev_get_drvdata(dev); 1211 1212 return dsa_switch_resume(priv->dev->ds); 1213 } 1214 #endif /* CONFIG_PM_SLEEP */ 1215 1216 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops, 1217 bcm_sf2_suspend, bcm_sf2_resume); 1218 1219 1220 static struct platform_driver bcm_sf2_driver = { 1221 .probe = bcm_sf2_sw_probe, 1222 .remove = bcm_sf2_sw_remove, 1223 .shutdown = bcm_sf2_sw_shutdown, 1224 .driver = { 1225 .name = "brcm-sf2", 1226 .of_match_table = bcm_sf2_of_match, 1227 .pm = &bcm_sf2_pm_ops, 1228 }, 1229 }; 1230 module_platform_driver(bcm_sf2_driver); 1231 1232 MODULE_AUTHOR("Broadcom Corporation"); 1233 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip"); 1234 MODULE_LICENSE("GPL"); 1235 MODULE_ALIAS("platform:brcm-sf2"); 1236