1 /* 2 * B53 register definitions 3 * 4 * Copyright (C) 2004 Broadcom Corporation 5 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org> 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef __B53_REGS_H 21 #define __B53_REGS_H 22 23 /* Management Port (SMP) Page offsets */ 24 #define B53_CTRL_PAGE 0x00 /* Control */ 25 #define B53_STAT_PAGE 0x01 /* Status */ 26 #define B53_MGMT_PAGE 0x02 /* Management Mode */ 27 #define B53_MIB_AC_PAGE 0x03 /* MIB Autocast */ 28 #define B53_ARLCTRL_PAGE 0x04 /* ARL Control */ 29 #define B53_ARLIO_PAGE 0x05 /* ARL Access */ 30 #define B53_FRAMEBUF_PAGE 0x06 /* Management frame access */ 31 #define B53_MEM_ACCESS_PAGE 0x08 /* Memory access */ 32 #define B53_IEEE_PAGE 0x0a /* IEEE 802.1X */ 33 34 /* PHY Registers */ 35 #define B53_PORT_MII_PAGE(i) (0x10 + (i)) /* Port i MII Registers */ 36 #define B53_IM_PORT_PAGE 0x18 /* Inverse MII Port (to EMAC) */ 37 #define B53_ALL_PORT_PAGE 0x19 /* All ports MII (broadcast) */ 38 39 /* MIB registers */ 40 #define B53_MIB_PAGE(i) (0x20 + (i)) 41 42 /* Quality of Service (QoS) Registers */ 43 #define B53_QOS_PAGE 0x30 44 45 /* Port VLAN Page */ 46 #define B53_PVLAN_PAGE 0x31 47 48 /* VLAN Registers */ 49 #define B53_VLAN_PAGE 0x34 50 51 /* Jumbo Frame Registers */ 52 #define B53_JUMBO_PAGE 0x40 53 54 /* EAP Registers */ 55 #define B53_EAP_PAGE 0x42 56 57 /* EEE Control Registers Page */ 58 #define B53_EEE_PAGE 0x92 59 60 /* CFP Configuration Registers Page */ 61 #define B53_CFP_PAGE 0xa1 62 63 /************************************************************************* 64 * Control Page registers 65 *************************************************************************/ 66 67 /* Port Control Register (8 bit) */ 68 #define B53_PORT_CTRL(i) (0x00 + (i)) 69 #define PORT_CTRL_RX_DISABLE BIT(0) 70 #define PORT_CTRL_TX_DISABLE BIT(1) 71 #define PORT_CTRL_RX_BCST_EN BIT(2) /* Broadcast RX (P8 only) */ 72 #define PORT_CTRL_RX_MCST_EN BIT(3) /* Multicast RX (P8 only) */ 73 #define PORT_CTRL_RX_UCST_EN BIT(4) /* Unicast RX (P8 only) */ 74 #define PORT_CTRL_STP_STATE_S 5 75 #define PORT_CTRL_NO_STP (0 << PORT_CTRL_STP_STATE_S) 76 #define PORT_CTRL_DIS_STATE (1 << PORT_CTRL_STP_STATE_S) 77 #define PORT_CTRL_BLOCK_STATE (2 << PORT_CTRL_STP_STATE_S) 78 #define PORT_CTRL_LISTEN_STATE (3 << PORT_CTRL_STP_STATE_S) 79 #define PORT_CTRL_LEARN_STATE (4 << PORT_CTRL_STP_STATE_S) 80 #define PORT_CTRL_FWD_STATE (5 << PORT_CTRL_STP_STATE_S) 81 #define PORT_CTRL_STP_STATE_MASK (0x7 << PORT_CTRL_STP_STATE_S) 82 83 /* SMP Control Register (8 bit) */ 84 #define B53_SMP_CTRL 0x0a 85 86 /* Switch Mode Control Register (8 bit) */ 87 #define B53_SWITCH_MODE 0x0b 88 #define SM_SW_FWD_MODE BIT(0) /* 1 = Managed Mode */ 89 #define SM_SW_FWD_EN BIT(1) /* Forwarding Enable */ 90 91 /* IMP Port state override register (8 bit) */ 92 #define B53_PORT_OVERRIDE_CTRL 0x0e 93 #define PORT_OVERRIDE_LINK BIT(0) 94 #define PORT_OVERRIDE_FULL_DUPLEX BIT(1) /* 0 = Half Duplex */ 95 #define PORT_OVERRIDE_SPEED_S 2 96 #define PORT_OVERRIDE_SPEED_10M (0 << PORT_OVERRIDE_SPEED_S) 97 #define PORT_OVERRIDE_SPEED_100M (1 << PORT_OVERRIDE_SPEED_S) 98 #define PORT_OVERRIDE_SPEED_1000M (2 << PORT_OVERRIDE_SPEED_S) 99 #define PORT_OVERRIDE_LP_FLOW_25 BIT(3) /* BCM5325 only */ 100 #define PORT_OVERRIDE_RV_MII_25 BIT(4) /* BCM5325 only */ 101 #define PORT_OVERRIDE_RX_FLOW BIT(4) 102 #define PORT_OVERRIDE_TX_FLOW BIT(5) 103 #define PORT_OVERRIDE_SPEED_2000M BIT(6) /* BCM5301X only, requires setting 1000M */ 104 #define PORT_OVERRIDE_EN BIT(7) /* Use the register contents */ 105 106 /* Power-down mode control (8 bit) */ 107 #define B53_PD_MODE_CTRL_25 0x0f 108 #define PD_MODE_PORT_MASK 0x1f 109 /* Bit 0 also powers down the switch. */ 110 #define PD_MODE_POWER_DOWN_PORT(i) BIT(i) 111 112 /* IP Multicast control (8 bit) */ 113 #define B53_IP_MULTICAST_CTRL 0x21 114 #define B53_IP_MCAST_25 BIT(0) 115 #define B53_IPMC_FWD_EN BIT(1) 116 #define B53_UC_FWD_EN BIT(6) 117 #define B53_MC_FWD_EN BIT(7) 118 119 /* Switch control (8 bit) */ 120 #define B53_SWITCH_CTRL 0x22 121 #define B53_MII_DUMB_FWDG_EN BIT(6) 122 123 /* Protected Port Selection (16 bit) */ 124 #define B53_PROTECTED_PORT_SEL 0x24 125 #define B53_PROTECTED_PORT_SEL_25 0x26 126 127 /* (16 bit) */ 128 #define B53_UC_FLOOD_MASK 0x32 129 #define B53_MC_FLOOD_MASK 0x34 130 #define B53_IPMC_FLOOD_MASK 0x36 131 #define B53_DIS_LEARNING 0x3c 132 133 /* 134 * Override Ports 0-7 State on devices with xMII interfaces (8 bit) 135 * 136 * For port 8 still use B53_PORT_OVERRIDE_CTRL 137 * Please note that not all ports are available on every hardware, e.g. BCM5301X 138 * don't include overriding port 6, BCM63xx also have some limitations. 139 */ 140 #define B53_GMII_PORT_OVERRIDE_CTRL(i) (0x58 + (i)) 141 #define GMII_PO_LINK BIT(0) 142 #define GMII_PO_FULL_DUPLEX BIT(1) /* 0 = Half Duplex */ 143 #define GMII_PO_SPEED_S 2 144 #define GMII_PO_SPEED_10M (0 << GMII_PO_SPEED_S) 145 #define GMII_PO_SPEED_100M (1 << GMII_PO_SPEED_S) 146 #define GMII_PO_SPEED_1000M (2 << GMII_PO_SPEED_S) 147 #define GMII_PO_RX_FLOW BIT(4) 148 #define GMII_PO_TX_FLOW BIT(5) 149 #define GMII_PO_EN BIT(6) /* Use the register contents */ 150 #define GMII_PO_SPEED_2000M BIT(7) /* BCM5301X only, requires setting 1000M */ 151 152 #define B53_RGMII_CTRL_IMP 0x60 153 #define RGMII_CTRL_ENABLE_GMII BIT(7) 154 #define RGMII_CTRL_MII_OVERRIDE BIT(6) 155 #define RGMII_CTRL_TIMING_SEL BIT(2) 156 #define RGMII_CTRL_DLL_RXC BIT(1) 157 #define RGMII_CTRL_DLL_TXC BIT(0) 158 159 #define B53_RGMII_CTRL_P(i) (B53_RGMII_CTRL_IMP + (i)) 160 161 /* Software reset register (8 bit) */ 162 #define B53_SOFTRESET 0x79 163 #define SW_RST BIT(7) 164 #define EN_CH_RST BIT(6) 165 #define EN_SW_RST BIT(4) 166 167 /* Fast Aging Control register (8 bit) */ 168 #define B53_FAST_AGE_CTRL 0x88 169 #define FAST_AGE_STATIC BIT(0) 170 #define FAST_AGE_DYNAMIC BIT(1) 171 #define FAST_AGE_PORT BIT(2) 172 #define FAST_AGE_VLAN BIT(3) 173 #define FAST_AGE_STP BIT(4) 174 #define FAST_AGE_MC BIT(5) 175 #define FAST_AGE_DONE BIT(7) 176 177 /* Fast Aging Port Control register (8 bit) */ 178 #define B53_FAST_AGE_PORT_CTRL 0x89 179 180 /* Fast Aging VID Control register (16 bit) */ 181 #define B53_FAST_AGE_VID_CTRL 0x8a 182 183 /************************************************************************* 184 * Status Page registers 185 *************************************************************************/ 186 187 /* Link Status Summary Register (16bit) */ 188 #define B53_LINK_STAT 0x00 189 190 /* Link Status Change Register (16 bit) */ 191 #define B53_LINK_STAT_CHANGE 0x02 192 193 /* Port Speed Summary Register (16 bit for FE, 32 bit for GE) */ 194 #define B53_SPEED_STAT 0x04 195 #define SPEED_PORT_FE(reg, port) (((reg) >> (port)) & 1) 196 #define SPEED_PORT_GE(reg, port) (((reg) >> 2 * (port)) & 3) 197 #define SPEED_STAT_10M 0 198 #define SPEED_STAT_100M 1 199 #define SPEED_STAT_1000M 2 200 201 /* Duplex Status Summary (16 bit) */ 202 #define B53_DUPLEX_STAT_FE 0x06 203 #define B53_DUPLEX_STAT_GE 0x08 204 #define B53_DUPLEX_STAT_63XX 0x0c 205 206 /* Revision ID register for BCM5325 */ 207 #define B53_REV_ID_25 0x50 208 209 /* Strap Value (48 bit) */ 210 #define B53_STRAP_VALUE 0x70 211 #define SV_GMII_CTRL_115 BIT(27) 212 213 /************************************************************************* 214 * Management Mode Page Registers 215 *************************************************************************/ 216 217 /* Global Management Config Register (8 bit) */ 218 #define B53_GLOBAL_CONFIG 0x00 219 #define GC_RESET_MIB 0x01 220 #define GC_RX_BPDU_EN 0x02 221 #define GC_MIB_AC_HDR_EN 0x10 222 #define GC_MIB_AC_EN 0x20 223 #define GC_FRM_MGMT_PORT_M 0xC0 224 #define GC_FRM_MGMT_PORT_04 0x00 225 #define GC_FRM_MGMT_PORT_MII 0x80 226 227 /* Broadcom Header control register (8 bit) */ 228 #define B53_BRCM_HDR 0x03 229 #define BRCM_HDR_P8_EN BIT(0) /* Enable tagging on port 8 */ 230 #define BRCM_HDR_P5_EN BIT(1) /* Enable tagging on port 5 */ 231 #define BRCM_HDR_P7_EN BIT(2) /* Enable tagging on port 7 */ 232 233 /* Aging Time control register (32 bit) */ 234 #define B53_AGING_TIME_CONTROL 0x06 235 #define B53_AGING_TIME_CONTROL_63XX 0x08 236 #define AGE_CHANGE BIT(20) 237 #define AGE_TIME_MASK 0x7ffff 238 #define AGE_TIME_MAX 1048575 239 240 /* Mirror capture control register (16 bit) */ 241 #define B53_MIR_CAP_CTL 0x10 242 #define CAP_PORT_MASK 0xf 243 #define BLK_NOT_MIR BIT(14) 244 #define MIRROR_EN BIT(15) 245 246 /* Ingress mirror control register (16 bit) */ 247 #define B53_IG_MIR_CTL 0x12 248 #define MIRROR_MASK 0x1ff 249 #define DIV_EN BIT(13) 250 #define MIRROR_FILTER_MASK 0x3 251 #define MIRROR_FILTER_SHIFT 14 252 #define MIRROR_ALL 0 253 #define MIRROR_DA 1 254 #define MIRROR_SA 2 255 256 /* Ingress mirror divider register (16 bit) */ 257 #define B53_IG_MIR_DIV 0x14 258 #define IN_MIRROR_DIV_MASK 0x3ff 259 260 /* Ingress mirror MAC address register (48 bit) */ 261 #define B53_IG_MIR_MAC 0x16 262 263 /* Egress mirror control register (16 bit) */ 264 #define B53_EG_MIR_CTL 0x1C 265 266 /* Egress mirror divider register (16 bit) */ 267 #define B53_EG_MIR_DIV 0x1E 268 269 /* Egress mirror MAC address register (48 bit) */ 270 #define B53_EG_MIR_MAC 0x20 271 272 /* Device ID register (8 or 32 bit) */ 273 #define B53_DEVICE_ID 0x30 274 275 /* Revision ID register (8 bit) */ 276 #define B53_REV_ID 0x40 277 278 /* Broadcom header RX control (16 bit) */ 279 #define B53_BRCM_HDR_RX_DIS 0x60 280 281 /* Broadcom header TX control (16 bit) */ 282 #define B53_BRCM_HDR_TX_DIS 0x62 283 284 /************************************************************************* 285 * ARL Access Page Registers 286 *************************************************************************/ 287 288 /* VLAN Table Access Register (8 bit) */ 289 #define B53_VT_ACCESS 0x80 290 #define B53_VT_ACCESS_9798 0x60 /* for BCM5397/BCM5398 */ 291 #define B53_VT_ACCESS_63XX 0x60 /* for BCM6328/62/68 */ 292 #define VTA_CMD_WRITE 0 293 #define VTA_CMD_READ 1 294 #define VTA_CMD_CLEAR 2 295 #define VTA_START_CMD BIT(7) 296 297 /* VLAN Table Index Register (16 bit) */ 298 #define B53_VT_INDEX 0x81 299 #define B53_VT_INDEX_9798 0x61 300 #define B53_VT_INDEX_63XX 0x62 301 302 /* VLAN Table Entry Register (32 bit) */ 303 #define B53_VT_ENTRY 0x83 304 #define B53_VT_ENTRY_9798 0x63 305 #define B53_VT_ENTRY_63XX 0x64 306 #define VTE_MEMBERS 0x1ff 307 #define VTE_UNTAG_S 9 308 #define VTE_UNTAG (0x1ff << 9) 309 310 /************************************************************************* 311 * ARL I/O Registers 312 *************************************************************************/ 313 314 /* ARL Table Read/Write Register (8 bit) */ 315 #define B53_ARLTBL_RW_CTRL 0x00 316 #define ARLTBL_RW BIT(0) 317 #define ARLTBL_IVL_SVL_SELECT BIT(6) 318 #define ARLTBL_START_DONE BIT(7) 319 320 /* MAC Address Index Register (48 bit) */ 321 #define B53_MAC_ADDR_IDX 0x02 322 323 /* VLAN ID Index Register (16 bit) */ 324 #define B53_VLAN_ID_IDX 0x08 325 326 /* ARL Table MAC/VID Entry N Registers (64 bit) 327 * 328 * BCM5325 and BCM5365 share most definitions below 329 */ 330 #define B53_ARLTBL_MAC_VID_ENTRY(n) ((0x10 * (n)) + 0x10) 331 #define ARLTBL_MAC_MASK 0xffffffffffffULL 332 #define ARLTBL_VID_S 48 333 #define ARLTBL_VID_MASK_25 0xff 334 #define ARLTBL_VID_MASK 0xfff 335 #define ARLTBL_DATA_PORT_ID_S_25 48 336 #define ARLTBL_DATA_PORT_ID_MASK_25 0xf 337 #define ARLTBL_VID_S_65 53 338 #define ARLTBL_AGE_25 BIT_ULL(61) 339 #define ARLTBL_STATIC_25 BIT_ULL(62) 340 #define ARLTBL_VALID_25 BIT_ULL(63) 341 342 /* ARL Table Data Entry N Registers (32 bit) */ 343 #define B53_ARLTBL_DATA_ENTRY(n) ((0x10 * (n)) + 0x18) 344 #define ARLTBL_DATA_PORT_ID_MASK 0x1ff 345 #define ARLTBL_TC(tc) ((3 & tc) << 11) 346 #define ARLTBL_AGE BIT(14) 347 #define ARLTBL_STATIC BIT(15) 348 #define ARLTBL_VALID BIT(16) 349 350 /* Maximum number of bin entries in the ARL for all switches */ 351 #define B53_ARLTBL_MAX_BIN_ENTRIES 4 352 353 /* ARL Search Control Register (8 bit) */ 354 #define B53_ARL_SRCH_CTL 0x50 355 #define B53_ARL_SRCH_CTL_25 0x20 356 #define ARL_SRCH_VLID BIT(0) 357 #define ARL_SRCH_STDN BIT(7) 358 359 /* ARL Search Address Register (16 bit) */ 360 #define B53_ARL_SRCH_ADDR 0x51 361 #define B53_ARL_SRCH_ADDR_25 0x22 362 #define B53_ARL_SRCH_ADDR_65 0x24 363 #define ARL_ADDR_MASK GENMASK(14, 0) 364 365 /* ARL Search MAC/VID Result (64 bit) */ 366 #define B53_ARL_SRCH_RSTL_0_MACVID 0x60 367 368 /* Single register search result on 5325 */ 369 #define B53_ARL_SRCH_RSTL_0_MACVID_25 0x24 370 /* Single register search result on 5365 */ 371 #define B53_ARL_SRCH_RSTL_0_MACVID_65 0x30 372 373 /* ARL Search Data Result (32 bit) */ 374 #define B53_ARL_SRCH_RSTL_0 0x68 375 376 #define B53_ARL_SRCH_RSTL_MACVID(x) (B53_ARL_SRCH_RSTL_0_MACVID + ((x) * 0x10)) 377 #define B53_ARL_SRCH_RSTL(x) (B53_ARL_SRCH_RSTL_0 + ((x) * 0x10)) 378 379 /************************************************************************* 380 * IEEE 802.1X Registers 381 *************************************************************************/ 382 383 /* Multicast DLF Drop Control register (16 bit) */ 384 #define B53_IEEE_MCAST_DLF 0x94 385 #define B53_IEEE_MCAST_DROP_EN BIT(11) 386 387 /* Unicast DLF Drop Control register (16 bit) */ 388 #define B53_IEEE_UCAST_DLF 0x96 389 #define B53_IEEE_UCAST_DROP_EN BIT(11) 390 391 /************************************************************************* 392 * Port VLAN Registers 393 *************************************************************************/ 394 395 /* Port VLAN mask (16 bit) IMP port is always 8, also on 5325 & co */ 396 #define B53_PVLAN_PORT_MASK(i) ((i) * 2) 397 398 /* Join all VLANs register (16 bit) */ 399 #define B53_JOIN_ALL_VLAN_EN 0x50 400 401 /************************************************************************* 402 * 802.1Q Page Registers 403 *************************************************************************/ 404 405 /* Global QoS Control (8 bit) */ 406 #define B53_QOS_GLOBAL_CTL 0x00 407 408 /* Enable 802.1Q for individual Ports (16 bit) */ 409 #define B53_802_1P_EN 0x04 410 411 /************************************************************************* 412 * VLAN Page Registers 413 *************************************************************************/ 414 415 /* VLAN Control 0 (8 bit) */ 416 #define B53_VLAN_CTRL0 0x00 417 #define VC0_8021PF_CTRL_MASK 0x3 418 #define VC0_8021PF_CTRL_NONE 0x0 419 #define VC0_8021PF_CTRL_CHANGE_PRI 0x1 420 #define VC0_8021PF_CTRL_CHANGE_VID 0x2 421 #define VC0_8021PF_CTRL_CHANGE_BOTH 0x3 422 #define VC0_8021QF_CTRL_MASK 0xc 423 #define VC0_8021QF_CTRL_CHANGE_PRI 0x1 424 #define VC0_8021QF_CTRL_CHANGE_VID 0x2 425 #define VC0_8021QF_CTRL_CHANGE_BOTH 0x3 426 #define VC0_RESERVED_1 BIT(1) 427 #define VC0_DROP_VID_MISS BIT(4) 428 #define VC0_VID_HASH_VID BIT(5) 429 #define VC0_VID_CHK_EN BIT(6) /* Use VID,DA or VID,SA */ 430 #define VC0_VLAN_EN BIT(7) /* 802.1Q VLAN Enabled */ 431 432 /* VLAN Control 1 (8 bit) */ 433 #define B53_VLAN_CTRL1 0x01 434 #define VC1_RX_MCST_TAG_EN BIT(1) 435 #define VC1_RX_MCST_FWD_EN BIT(2) 436 #define VC1_RX_MCST_UNTAG_EN BIT(3) 437 438 /* VLAN Control 2 (8 bit) */ 439 #define B53_VLAN_CTRL2 0x02 440 441 /* VLAN Control 3 (8 bit when BCM5325, 16 bit else) */ 442 #define B53_VLAN_CTRL3 0x03 443 #define B53_VLAN_CTRL3_63XX 0x04 444 #define VC3_MAXSIZE_1532 BIT(6) /* 5325 only */ 445 #define VC3_HIGH_8BIT_EN BIT(7) /* 5325 only */ 446 447 /* VLAN Control 4 (8 bit) */ 448 #define B53_VLAN_CTRL4 0x05 449 #define B53_VLAN_CTRL4_25 0x04 450 #define B53_VLAN_CTRL4_63XX 0x06 451 #define VC4_ING_VID_CHECK_S 6 452 #define VC4_ING_VID_CHECK_MASK (0x3 << VC4_ING_VID_CHECK_S) 453 #define VC4_ING_VID_VIO_FWD 0 /* forward, but do not learn */ 454 #define VC4_ING_VID_VIO_DROP 1 /* drop VID violations */ 455 #define VC4_NO_ING_VID_CHK 2 /* do not check */ 456 #define VC4_ING_VID_VIO_TO_IMP 3 /* redirect to MII port */ 457 458 /* VLAN Control 5 (8 bit) */ 459 #define B53_VLAN_CTRL5 0x06 460 #define B53_VLAN_CTRL5_25 0x05 461 #define B53_VLAN_CTRL5_63XX 0x07 462 #define VC5_VID_FFF_EN BIT(2) 463 #define VC5_DROP_VTABLE_MISS BIT(3) 464 465 /* VLAN Control 6 (8 bit) */ 466 #define B53_VLAN_CTRL6 0x07 467 #define B53_VLAN_CTRL6_63XX 0x08 468 469 /* VLAN Table Access Register (16 bit) */ 470 #define B53_VLAN_TABLE_ACCESS_25 0x06 /* BCM5325E/5350 */ 471 #define B53_VLAN_TABLE_ACCESS_65 0x08 /* BCM5365 */ 472 #define VTA_VID_LOW_MASK_25 0xf 473 #define VTA_VID_LOW_MASK_65 0xff 474 #define VTA_VID_HIGH_S_25 4 475 #define VTA_VID_HIGH_S_65 8 476 #define VTA_VID_HIGH_MASK_25 (0xff << VTA_VID_HIGH_S_25E) 477 #define VTA_VID_HIGH_MASK_65 (0xf << VTA_VID_HIGH_S_65) 478 #define VTA_RW_STATE BIT(12) 479 #define VTA_RW_STATE_RD 0 480 #define VTA_RW_STATE_WR BIT(12) 481 #define VTA_RW_OP_EN BIT(13) 482 483 /* VLAN Read/Write Registers for (16/32 bit) */ 484 #define B53_VLAN_WRITE_25 0x08 485 #define B53_VLAN_WRITE_65 0x0a 486 #define B53_VLAN_READ 0x0c 487 #define VA_MEMBER_MASK 0x3f 488 #define VA_UNTAG_S_25 6 489 #define VA_UNTAG_MASK_25 0x3f 490 #define VA_UNTAG_S_65 7 491 #define VA_UNTAG_MASK_65 0x1f 492 #define VA_VID_HIGH_S 12 493 #define VA_VID_HIGH_MASK (0xffff << VA_VID_HIGH_S) 494 #define VA_VALID_25 BIT(20) 495 #define VA_VALID_25_R4 BIT(24) 496 #define VA_VALID_65 BIT(14) 497 498 /* VLAN Port Default Tag (16 bit) */ 499 #define B53_VLAN_PORT_DEF_TAG(i) (0x10 + 2 * (i)) 500 501 /************************************************************************* 502 * Jumbo Frame Page Registers 503 *************************************************************************/ 504 505 /* Jumbo Enable Port Mask (bit i == port i enabled) (32 bit) */ 506 #define B53_JUMBO_PORT_MASK 0x01 507 #define B53_JUMBO_PORT_MASK_63XX 0x04 508 #define JPM_10_100_JUMBO_EN BIT(24) /* GigE always enabled */ 509 510 /* Good Frame Max Size without 802.1Q TAG (16 bit) */ 511 #define B53_JUMBO_MAX_SIZE 0x05 512 #define B53_JUMBO_MAX_SIZE_63XX 0x08 513 #define JMS_MIN_SIZE 1518 514 #define JMS_MAX_SIZE 9724 515 516 /************************************************************************* 517 * EAP Page Registers 518 *************************************************************************/ 519 #define B53_PORT_EAP_CONF(i) (0x20 + 8 * (i)) 520 #define EAP_MODE_SHIFT 51 521 #define EAP_MODE_SHIFT_63XX 50 522 #define EAP_MODE_MASK (0x3ull << EAP_MODE_SHIFT) 523 #define EAP_MODE_MASK_63XX (0x3ull << EAP_MODE_SHIFT_63XX) 524 #define EAP_MODE_BASIC 0 525 #define EAP_MODE_SIMPLIFIED 3 526 527 /************************************************************************* 528 * EEE Configuration Page Registers 529 *************************************************************************/ 530 531 /* EEE Enable control register (16 bit) */ 532 #define B53_EEE_EN_CTRL 0x00 533 534 /* EEE LPI assert status register (16 bit) */ 535 #define B53_EEE_LPI_ASSERT_STS 0x02 536 537 /* EEE LPI indicate status register (16 bit) */ 538 #define B53_EEE_LPI_INDICATE 0x4 539 540 /* EEE Receiving idle symbols status register (16 bit) */ 541 #define B53_EEE_RX_IDLE_SYM_STS 0x6 542 543 /* EEE Pipeline timer register (32 bit) */ 544 #define B53_EEE_PIP_TIMER 0xC 545 546 /* EEE Sleep timer Gig register (32 bit) */ 547 #define B53_EEE_SLEEP_TIMER_GIG(i) (0x10 + 4 * (i)) 548 549 /* EEE Sleep timer FE register (32 bit) */ 550 #define B53_EEE_SLEEP_TIMER_FE(i) (0x34 + 4 * (i)) 551 552 /* EEE Minimum LP timer Gig register (32 bit) */ 553 #define B53_EEE_MIN_LP_TIMER_GIG(i) (0x58 + 4 * (i)) 554 555 /* EEE Minimum LP timer FE register (32 bit) */ 556 #define B53_EEE_MIN_LP_TIMER_FE(i) (0x7c + 4 * (i)) 557 558 /* EEE Wake timer Gig register (16 bit) */ 559 #define B53_EEE_WAKE_TIMER_GIG(i) (0xa0 + 2 * (i)) 560 561 /* EEE Wake timer FE register (16 bit) */ 562 #define B53_EEE_WAKE_TIMER_FE(i) (0xb2 + 2 * (i)) 563 564 565 /************************************************************************* 566 * CFP Configuration Page Registers 567 *************************************************************************/ 568 569 /* CFP Control Register with ports map (8 bit) */ 570 #define B53_CFP_CTRL 0x00 571 572 #endif /* !__B53_REGS_H */ 573