1 /* 2 * B53 switch driver main logic 3 * 4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org> 5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com> 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <linux/delay.h> 21 #include <linux/export.h> 22 #include <linux/gpio.h> 23 #include <linux/kernel.h> 24 #include <linux/math.h> 25 #include <linux/minmax.h> 26 #include <linux/module.h> 27 #include <linux/platform_data/b53.h> 28 #include <linux/phy.h> 29 #include <linux/phylink.h> 30 #include <linux/etherdevice.h> 31 #include <linux/if_bridge.h> 32 #include <linux/if_vlan.h> 33 #include <net/dsa.h> 34 35 #include "b53_regs.h" 36 #include "b53_priv.h" 37 38 struct b53_mib_desc { 39 u8 size; 40 u8 offset; 41 const char *name; 42 }; 43 44 /* BCM5365 MIB counters */ 45 static const struct b53_mib_desc b53_mibs_65[] = { 46 { 8, 0x00, "TxOctets" }, 47 { 4, 0x08, "TxDropPkts" }, 48 { 4, 0x10, "TxBroadcastPkts" }, 49 { 4, 0x14, "TxMulticastPkts" }, 50 { 4, 0x18, "TxUnicastPkts" }, 51 { 4, 0x1c, "TxCollisions" }, 52 { 4, 0x20, "TxSingleCollision" }, 53 { 4, 0x24, "TxMultipleCollision" }, 54 { 4, 0x28, "TxDeferredTransmit" }, 55 { 4, 0x2c, "TxLateCollision" }, 56 { 4, 0x30, "TxExcessiveCollision" }, 57 { 4, 0x38, "TxPausePkts" }, 58 { 8, 0x44, "RxOctets" }, 59 { 4, 0x4c, "RxUndersizePkts" }, 60 { 4, 0x50, "RxPausePkts" }, 61 { 4, 0x54, "Pkts64Octets" }, 62 { 4, 0x58, "Pkts65to127Octets" }, 63 { 4, 0x5c, "Pkts128to255Octets" }, 64 { 4, 0x60, "Pkts256to511Octets" }, 65 { 4, 0x64, "Pkts512to1023Octets" }, 66 { 4, 0x68, "Pkts1024to1522Octets" }, 67 { 4, 0x6c, "RxOversizePkts" }, 68 { 4, 0x70, "RxJabbers" }, 69 { 4, 0x74, "RxAlignmentErrors" }, 70 { 4, 0x78, "RxFCSErrors" }, 71 { 8, 0x7c, "RxGoodOctets" }, 72 { 4, 0x84, "RxDropPkts" }, 73 { 4, 0x88, "RxUnicastPkts" }, 74 { 4, 0x8c, "RxMulticastPkts" }, 75 { 4, 0x90, "RxBroadcastPkts" }, 76 { 4, 0x94, "RxSAChanges" }, 77 { 4, 0x98, "RxFragments" }, 78 }; 79 80 #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65) 81 82 /* BCM63xx MIB counters */ 83 static const struct b53_mib_desc b53_mibs_63xx[] = { 84 { 8, 0x00, "TxOctets" }, 85 { 4, 0x08, "TxDropPkts" }, 86 { 4, 0x0c, "TxQoSPkts" }, 87 { 4, 0x10, "TxBroadcastPkts" }, 88 { 4, 0x14, "TxMulticastPkts" }, 89 { 4, 0x18, "TxUnicastPkts" }, 90 { 4, 0x1c, "TxCollisions" }, 91 { 4, 0x20, "TxSingleCollision" }, 92 { 4, 0x24, "TxMultipleCollision" }, 93 { 4, 0x28, "TxDeferredTransmit" }, 94 { 4, 0x2c, "TxLateCollision" }, 95 { 4, 0x30, "TxExcessiveCollision" }, 96 { 4, 0x38, "TxPausePkts" }, 97 { 8, 0x3c, "TxQoSOctets" }, 98 { 8, 0x44, "RxOctets" }, 99 { 4, 0x4c, "RxUndersizePkts" }, 100 { 4, 0x50, "RxPausePkts" }, 101 { 4, 0x54, "Pkts64Octets" }, 102 { 4, 0x58, "Pkts65to127Octets" }, 103 { 4, 0x5c, "Pkts128to255Octets" }, 104 { 4, 0x60, "Pkts256to511Octets" }, 105 { 4, 0x64, "Pkts512to1023Octets" }, 106 { 4, 0x68, "Pkts1024to1522Octets" }, 107 { 4, 0x6c, "RxOversizePkts" }, 108 { 4, 0x70, "RxJabbers" }, 109 { 4, 0x74, "RxAlignmentErrors" }, 110 { 4, 0x78, "RxFCSErrors" }, 111 { 8, 0x7c, "RxGoodOctets" }, 112 { 4, 0x84, "RxDropPkts" }, 113 { 4, 0x88, "RxUnicastPkts" }, 114 { 4, 0x8c, "RxMulticastPkts" }, 115 { 4, 0x90, "RxBroadcastPkts" }, 116 { 4, 0x94, "RxSAChanges" }, 117 { 4, 0x98, "RxFragments" }, 118 { 4, 0xa0, "RxSymbolErrors" }, 119 { 4, 0xa4, "RxQoSPkts" }, 120 { 8, 0xa8, "RxQoSOctets" }, 121 { 4, 0xb0, "Pkts1523to2047Octets" }, 122 { 4, 0xb4, "Pkts2048to4095Octets" }, 123 { 4, 0xb8, "Pkts4096to8191Octets" }, 124 { 4, 0xbc, "Pkts8192to9728Octets" }, 125 { 4, 0xc0, "RxDiscarded" }, 126 }; 127 128 #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx) 129 130 /* MIB counters */ 131 static const struct b53_mib_desc b53_mibs[] = { 132 { 8, 0x00, "TxOctets" }, 133 { 4, 0x08, "TxDropPkts" }, 134 { 4, 0x10, "TxBroadcastPkts" }, 135 { 4, 0x14, "TxMulticastPkts" }, 136 { 4, 0x18, "TxUnicastPkts" }, 137 { 4, 0x1c, "TxCollisions" }, 138 { 4, 0x20, "TxSingleCollision" }, 139 { 4, 0x24, "TxMultipleCollision" }, 140 { 4, 0x28, "TxDeferredTransmit" }, 141 { 4, 0x2c, "TxLateCollision" }, 142 { 4, 0x30, "TxExcessiveCollision" }, 143 { 4, 0x38, "TxPausePkts" }, 144 { 8, 0x50, "RxOctets" }, 145 { 4, 0x58, "RxUndersizePkts" }, 146 { 4, 0x5c, "RxPausePkts" }, 147 { 4, 0x60, "Pkts64Octets" }, 148 { 4, 0x64, "Pkts65to127Octets" }, 149 { 4, 0x68, "Pkts128to255Octets" }, 150 { 4, 0x6c, "Pkts256to511Octets" }, 151 { 4, 0x70, "Pkts512to1023Octets" }, 152 { 4, 0x74, "Pkts1024to1522Octets" }, 153 { 4, 0x78, "RxOversizePkts" }, 154 { 4, 0x7c, "RxJabbers" }, 155 { 4, 0x80, "RxAlignmentErrors" }, 156 { 4, 0x84, "RxFCSErrors" }, 157 { 8, 0x88, "RxGoodOctets" }, 158 { 4, 0x90, "RxDropPkts" }, 159 { 4, 0x94, "RxUnicastPkts" }, 160 { 4, 0x98, "RxMulticastPkts" }, 161 { 4, 0x9c, "RxBroadcastPkts" }, 162 { 4, 0xa0, "RxSAChanges" }, 163 { 4, 0xa4, "RxFragments" }, 164 { 4, 0xa8, "RxJumboPkts" }, 165 { 4, 0xac, "RxSymbolErrors" }, 166 { 4, 0xc0, "RxDiscarded" }, 167 }; 168 169 #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs) 170 171 static const struct b53_mib_desc b53_mibs_58xx[] = { 172 { 8, 0x00, "TxOctets" }, 173 { 4, 0x08, "TxDropPkts" }, 174 { 4, 0x0c, "TxQPKTQ0" }, 175 { 4, 0x10, "TxBroadcastPkts" }, 176 { 4, 0x14, "TxMulticastPkts" }, 177 { 4, 0x18, "TxUnicastPKts" }, 178 { 4, 0x1c, "TxCollisions" }, 179 { 4, 0x20, "TxSingleCollision" }, 180 { 4, 0x24, "TxMultipleCollision" }, 181 { 4, 0x28, "TxDeferredCollision" }, 182 { 4, 0x2c, "TxLateCollision" }, 183 { 4, 0x30, "TxExcessiveCollision" }, 184 { 4, 0x34, "TxFrameInDisc" }, 185 { 4, 0x38, "TxPausePkts" }, 186 { 4, 0x3c, "TxQPKTQ1" }, 187 { 4, 0x40, "TxQPKTQ2" }, 188 { 4, 0x44, "TxQPKTQ3" }, 189 { 4, 0x48, "TxQPKTQ4" }, 190 { 4, 0x4c, "TxQPKTQ5" }, 191 { 8, 0x50, "RxOctets" }, 192 { 4, 0x58, "RxUndersizePkts" }, 193 { 4, 0x5c, "RxPausePkts" }, 194 { 4, 0x60, "RxPkts64Octets" }, 195 { 4, 0x64, "RxPkts65to127Octets" }, 196 { 4, 0x68, "RxPkts128to255Octets" }, 197 { 4, 0x6c, "RxPkts256to511Octets" }, 198 { 4, 0x70, "RxPkts512to1023Octets" }, 199 { 4, 0x74, "RxPkts1024toMaxPktsOctets" }, 200 { 4, 0x78, "RxOversizePkts" }, 201 { 4, 0x7c, "RxJabbers" }, 202 { 4, 0x80, "RxAlignmentErrors" }, 203 { 4, 0x84, "RxFCSErrors" }, 204 { 8, 0x88, "RxGoodOctets" }, 205 { 4, 0x90, "RxDropPkts" }, 206 { 4, 0x94, "RxUnicastPkts" }, 207 { 4, 0x98, "RxMulticastPkts" }, 208 { 4, 0x9c, "RxBroadcastPkts" }, 209 { 4, 0xa0, "RxSAChanges" }, 210 { 4, 0xa4, "RxFragments" }, 211 { 4, 0xa8, "RxJumboPkt" }, 212 { 4, 0xac, "RxSymblErr" }, 213 { 4, 0xb0, "InRangeErrCount" }, 214 { 4, 0xb4, "OutRangeErrCount" }, 215 { 4, 0xb8, "EEELpiEvent" }, 216 { 4, 0xbc, "EEELpiDuration" }, 217 { 4, 0xc0, "RxDiscard" }, 218 { 4, 0xc8, "TxQPKTQ6" }, 219 { 4, 0xcc, "TxQPKTQ7" }, 220 { 4, 0xd0, "TxPkts64Octets" }, 221 { 4, 0xd4, "TxPkts65to127Octets" }, 222 { 4, 0xd8, "TxPkts128to255Octets" }, 223 { 4, 0xdc, "TxPkts256to511Ocets" }, 224 { 4, 0xe0, "TxPkts512to1023Ocets" }, 225 { 4, 0xe4, "TxPkts1024toMaxPktOcets" }, 226 }; 227 228 #define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx) 229 230 #define B53_MAX_MTU_25 (1536 - ETH_HLEN - VLAN_HLEN - ETH_FCS_LEN) 231 #define B53_MAX_MTU (9720 - ETH_HLEN - VLAN_HLEN - ETH_FCS_LEN) 232 233 static int b53_do_vlan_op(struct b53_device *dev, u8 op) 234 { 235 unsigned int i; 236 237 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op); 238 239 for (i = 0; i < 10; i++) { 240 u8 vta; 241 242 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta); 243 if (!(vta & VTA_START_CMD)) 244 return 0; 245 246 usleep_range(100, 200); 247 } 248 249 return -EIO; 250 } 251 252 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, 253 struct b53_vlan *vlan) 254 { 255 if (is5325(dev)) { 256 u32 entry = 0; 257 258 if (vlan->members) { 259 entry = ((vlan->untag & VA_UNTAG_MASK_25) << 260 VA_UNTAG_S_25) | vlan->members; 261 if (dev->core_rev >= 3) 262 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S; 263 else 264 entry |= VA_VALID_25; 265 } 266 267 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry); 268 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 269 VTA_RW_STATE_WR | VTA_RW_OP_EN); 270 } else if (is5365(dev)) { 271 u16 entry = 0; 272 273 if (vlan->members) 274 entry = ((vlan->untag & VA_UNTAG_MASK_65) << 275 VA_UNTAG_S_65) | vlan->members | VA_VALID_65; 276 277 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry); 278 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 279 VTA_RW_STATE_WR | VTA_RW_OP_EN); 280 } else { 281 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 282 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], 283 (vlan->untag << VTE_UNTAG_S) | vlan->members); 284 285 b53_do_vlan_op(dev, VTA_CMD_WRITE); 286 } 287 288 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n", 289 vid, vlan->members, vlan->untag); 290 } 291 292 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid, 293 struct b53_vlan *vlan) 294 { 295 if (is5325(dev)) { 296 u32 entry = 0; 297 298 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 299 VTA_RW_STATE_RD | VTA_RW_OP_EN); 300 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry); 301 302 if (dev->core_rev >= 3) 303 vlan->valid = !!(entry & VA_VALID_25_R4); 304 else 305 vlan->valid = !!(entry & VA_VALID_25); 306 vlan->members = entry & VA_MEMBER_MASK; 307 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25; 308 309 } else if (is5365(dev)) { 310 u16 entry = 0; 311 312 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 313 VTA_RW_STATE_WR | VTA_RW_OP_EN); 314 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry); 315 316 vlan->valid = !!(entry & VA_VALID_65); 317 vlan->members = entry & VA_MEMBER_MASK; 318 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65; 319 } else { 320 u32 entry = 0; 321 322 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 323 b53_do_vlan_op(dev, VTA_CMD_READ); 324 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry); 325 vlan->members = entry & VTE_MEMBERS; 326 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS; 327 vlan->valid = true; 328 } 329 } 330 331 static void b53_set_eap_mode(struct b53_device *dev, int port, int mode) 332 { 333 u64 eap_conf; 334 335 if (is5325(dev) || is5365(dev) || dev->chip_id == BCM5389_DEVICE_ID) 336 return; 337 338 b53_read64(dev, B53_EAP_PAGE, B53_PORT_EAP_CONF(port), &eap_conf); 339 340 if (is63xx(dev)) { 341 eap_conf &= ~EAP_MODE_MASK_63XX; 342 eap_conf |= (u64)mode << EAP_MODE_SHIFT_63XX; 343 } else { 344 eap_conf &= ~EAP_MODE_MASK; 345 eap_conf |= (u64)mode << EAP_MODE_SHIFT; 346 } 347 348 b53_write64(dev, B53_EAP_PAGE, B53_PORT_EAP_CONF(port), eap_conf); 349 } 350 351 static void b53_set_forwarding(struct b53_device *dev, int enable) 352 { 353 u8 mgmt; 354 355 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 356 357 if (enable) 358 mgmt |= SM_SW_FWD_EN; 359 else 360 mgmt &= ~SM_SW_FWD_EN; 361 362 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 363 364 if (!is5325(dev)) { 365 /* Include IMP port in dumb forwarding mode */ 366 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt); 367 mgmt |= B53_MII_DUMB_FWDG_EN; 368 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt); 369 370 /* Look at B53_UC_FWD_EN and B53_MC_FWD_EN to decide whether 371 * frames should be flooded or not. 372 */ 373 b53_read8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, &mgmt); 374 mgmt |= B53_UC_FWD_EN | B53_MC_FWD_EN | B53_IPMC_FWD_EN; 375 b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt); 376 } else { 377 b53_read8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, &mgmt); 378 mgmt |= B53_IP_MCAST_25; 379 b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt); 380 } 381 } 382 383 static void b53_enable_vlan(struct b53_device *dev, int port, bool enable, 384 bool enable_filtering) 385 { 386 u8 mgmt, vc0, vc1, vc4 = 0, vc5; 387 388 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 389 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0); 390 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1); 391 392 if (is5325(dev) || is5365(dev)) { 393 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 394 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5); 395 } else if (is63xx(dev)) { 396 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4); 397 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5); 398 } else { 399 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4); 400 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5); 401 } 402 403 vc1 &= ~VC1_RX_MCST_FWD_EN; 404 405 if (enable) { 406 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID; 407 vc1 |= VC1_RX_MCST_UNTAG_EN; 408 vc4 &= ~VC4_ING_VID_CHECK_MASK; 409 if (enable_filtering) { 410 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S; 411 vc5 |= VC5_DROP_VTABLE_MISS; 412 } else { 413 vc4 |= VC4_NO_ING_VID_CHK << VC4_ING_VID_CHECK_S; 414 vc5 &= ~VC5_DROP_VTABLE_MISS; 415 } 416 417 if (is5325(dev)) 418 vc0 &= ~VC0_RESERVED_1; 419 420 if (is5325(dev) || is5365(dev)) 421 vc1 |= VC1_RX_MCST_TAG_EN; 422 423 } else { 424 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID); 425 vc1 &= ~VC1_RX_MCST_UNTAG_EN; 426 vc4 &= ~VC4_ING_VID_CHECK_MASK; 427 vc5 &= ~VC5_DROP_VTABLE_MISS; 428 429 if (is5325(dev) || is5365(dev)) 430 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 431 else 432 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S; 433 434 if (is5325(dev) || is5365(dev)) 435 vc1 &= ~VC1_RX_MCST_TAG_EN; 436 } 437 438 if (!is5325(dev) && !is5365(dev)) 439 vc5 &= ~VC5_VID_FFF_EN; 440 441 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0); 442 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1); 443 444 if (is5325(dev) || is5365(dev)) { 445 /* enable the high 8 bit vid check on 5325 */ 446 if (is5325(dev) && enable) 447 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 448 VC3_HIGH_8BIT_EN); 449 else 450 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 451 452 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4); 453 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5); 454 } else if (is63xx(dev)) { 455 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0); 456 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4); 457 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5); 458 } else { 459 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 460 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4); 461 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5); 462 } 463 464 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 465 466 dev->vlan_enabled = enable; 467 468 dev_dbg(dev->dev, "Port %d VLAN enabled: %d, filtering: %d\n", 469 port, enable, enable_filtering); 470 } 471 472 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100) 473 { 474 u32 port_mask = 0; 475 u16 max_size = JMS_MIN_SIZE; 476 477 if (is5325(dev) || is5365(dev)) 478 return -EINVAL; 479 480 if (enable) { 481 port_mask = dev->enabled_ports; 482 max_size = JMS_MAX_SIZE; 483 if (allow_10_100) 484 port_mask |= JPM_10_100_JUMBO_EN; 485 } 486 487 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask); 488 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size); 489 } 490 491 static int b53_flush_arl(struct b53_device *dev, u8 mask) 492 { 493 unsigned int i; 494 495 if (is5325(dev)) 496 return 0; 497 498 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 499 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask); 500 501 for (i = 0; i < 10; i++) { 502 u8 fast_age_ctrl; 503 504 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 505 &fast_age_ctrl); 506 507 if (!(fast_age_ctrl & FAST_AGE_DONE)) 508 goto out; 509 510 msleep(1); 511 } 512 513 return -ETIMEDOUT; 514 out: 515 /* Only age dynamic entries (default behavior) */ 516 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC); 517 return 0; 518 } 519 520 static int b53_fast_age_port(struct b53_device *dev, int port) 521 { 522 if (is5325(dev)) 523 return 0; 524 525 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port); 526 527 return b53_flush_arl(dev, FAST_AGE_PORT); 528 } 529 530 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid) 531 { 532 if (is5325(dev)) 533 return 0; 534 535 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid); 536 537 return b53_flush_arl(dev, FAST_AGE_VLAN); 538 } 539 540 void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port) 541 { 542 struct b53_device *dev = ds->priv; 543 unsigned int i; 544 u16 pvlan; 545 546 /* BCM5325 CPU port is at 8 */ 547 if ((is5325(dev) || is5365(dev)) && cpu_port == B53_CPU_PORT_25) 548 cpu_port = B53_CPU_PORT; 549 550 /* Enable the IMP port to be in the same VLAN as the other ports 551 * on a per-port basis such that we only have Port i and IMP in 552 * the same VLAN. 553 */ 554 b53_for_each_port(dev, i) { 555 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan); 556 pvlan |= BIT(cpu_port); 557 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan); 558 } 559 } 560 EXPORT_SYMBOL(b53_imp_vlan_setup); 561 562 static void b53_port_set_ucast_flood(struct b53_device *dev, int port, 563 bool unicast) 564 { 565 u16 uc; 566 567 if (is5325(dev)) { 568 if (port == B53_CPU_PORT_25) 569 port = B53_CPU_PORT; 570 571 b53_read16(dev, B53_IEEE_PAGE, B53_IEEE_UCAST_DLF, &uc); 572 if (unicast) 573 uc |= BIT(port) | B53_IEEE_UCAST_DROP_EN; 574 else 575 uc &= ~BIT(port); 576 b53_write16(dev, B53_IEEE_PAGE, B53_IEEE_UCAST_DLF, uc); 577 } else { 578 b53_read16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, &uc); 579 if (unicast) 580 uc |= BIT(port); 581 else 582 uc &= ~BIT(port); 583 b53_write16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, uc); 584 } 585 } 586 587 static void b53_port_set_mcast_flood(struct b53_device *dev, int port, 588 bool multicast) 589 { 590 u16 mc; 591 592 if (is5325(dev)) { 593 if (port == B53_CPU_PORT_25) 594 port = B53_CPU_PORT; 595 596 b53_read16(dev, B53_IEEE_PAGE, B53_IEEE_MCAST_DLF, &mc); 597 if (multicast) 598 mc |= BIT(port) | B53_IEEE_MCAST_DROP_EN; 599 else 600 mc &= ~BIT(port); 601 b53_write16(dev, B53_IEEE_PAGE, B53_IEEE_MCAST_DLF, mc); 602 } else { 603 b53_read16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, &mc); 604 if (multicast) 605 mc |= BIT(port); 606 else 607 mc &= ~BIT(port); 608 b53_write16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, mc); 609 610 b53_read16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, &mc); 611 if (multicast) 612 mc |= BIT(port); 613 else 614 mc &= ~BIT(port); 615 b53_write16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, mc); 616 } 617 } 618 619 static void b53_port_set_learning(struct b53_device *dev, int port, 620 bool learning) 621 { 622 u16 reg; 623 624 if (is5325(dev)) 625 return; 626 627 b53_read16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, ®); 628 if (learning) 629 reg &= ~BIT(port); 630 else 631 reg |= BIT(port); 632 b53_write16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, reg); 633 } 634 635 static void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable) 636 { 637 struct b53_device *dev = ds->priv; 638 u16 reg; 639 640 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, ®); 641 if (enable) 642 reg |= BIT(port); 643 else 644 reg &= ~BIT(port); 645 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg); 646 } 647 648 int b53_setup_port(struct dsa_switch *ds, int port) 649 { 650 struct b53_device *dev = ds->priv; 651 652 b53_port_set_ucast_flood(dev, port, true); 653 b53_port_set_mcast_flood(dev, port, true); 654 b53_port_set_learning(dev, port, false); 655 656 /* Force all traffic to go to the CPU port to prevent the ASIC from 657 * trying to forward to bridged ports on matching FDB entries, then 658 * dropping frames because it isn't allowed to forward there. 659 */ 660 if (dsa_is_user_port(ds, port)) 661 b53_set_eap_mode(dev, port, EAP_MODE_SIMPLIFIED); 662 663 if (is5325(dev) && 664 in_range(port, 1, 4)) { 665 u8 reg; 666 667 b53_read8(dev, B53_CTRL_PAGE, B53_PD_MODE_CTRL_25, ®); 668 reg &= ~PD_MODE_POWER_DOWN_PORT(0); 669 if (dsa_is_unused_port(ds, port)) 670 reg |= PD_MODE_POWER_DOWN_PORT(port); 671 else 672 reg &= ~PD_MODE_POWER_DOWN_PORT(port); 673 b53_write8(dev, B53_CTRL_PAGE, B53_PD_MODE_CTRL_25, reg); 674 } 675 676 return 0; 677 } 678 EXPORT_SYMBOL(b53_setup_port); 679 680 int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy) 681 { 682 struct b53_device *dev = ds->priv; 683 unsigned int cpu_port; 684 int ret = 0; 685 u16 pvlan; 686 687 if (!dsa_is_user_port(ds, port)) 688 return 0; 689 690 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 691 692 if (dev->ops->phy_enable) 693 dev->ops->phy_enable(dev, port); 694 695 if (dev->ops->irq_enable) 696 ret = dev->ops->irq_enable(dev, port); 697 if (ret) 698 return ret; 699 700 /* Clear the Rx and Tx disable bits and set to no spanning tree */ 701 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0); 702 703 /* Set this port, and only this one to be in the default VLAN, 704 * if member of a bridge, restore its membership prior to 705 * bringing down this port. 706 */ 707 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 708 pvlan &= ~0x1ff; 709 pvlan |= BIT(port); 710 pvlan |= dev->ports[port].vlan_ctl_mask; 711 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 712 713 b53_imp_vlan_setup(ds, cpu_port); 714 715 /* If EEE was enabled, restore it */ 716 if (dev->ports[port].eee.eee_enabled) 717 b53_eee_enable_set(ds, port, true); 718 719 return 0; 720 } 721 EXPORT_SYMBOL(b53_enable_port); 722 723 void b53_disable_port(struct dsa_switch *ds, int port) 724 { 725 struct b53_device *dev = ds->priv; 726 u8 reg; 727 728 /* Disable Tx/Rx for the port */ 729 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 730 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE; 731 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 732 733 if (dev->ops->phy_disable) 734 dev->ops->phy_disable(dev, port); 735 736 if (dev->ops->irq_disable) 737 dev->ops->irq_disable(dev, port); 738 } 739 EXPORT_SYMBOL(b53_disable_port); 740 741 void b53_brcm_hdr_setup(struct dsa_switch *ds, int port) 742 { 743 struct b53_device *dev = ds->priv; 744 bool tag_en = !(dev->tag_protocol == DSA_TAG_PROTO_NONE); 745 u8 hdr_ctl, val; 746 u16 reg; 747 748 /* Resolve which bit controls the Broadcom tag */ 749 switch (port) { 750 case 8: 751 val = BRCM_HDR_P8_EN; 752 break; 753 case 7: 754 val = BRCM_HDR_P7_EN; 755 break; 756 case 5: 757 val = BRCM_HDR_P5_EN; 758 break; 759 default: 760 val = 0; 761 break; 762 } 763 764 /* Enable management mode if tagging is requested */ 765 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &hdr_ctl); 766 if (tag_en) 767 hdr_ctl |= SM_SW_FWD_MODE; 768 else 769 hdr_ctl &= ~SM_SW_FWD_MODE; 770 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, hdr_ctl); 771 772 /* Configure the appropriate IMP port */ 773 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &hdr_ctl); 774 if (port == 8) 775 hdr_ctl |= GC_FRM_MGMT_PORT_MII; 776 else if (port == 5) 777 hdr_ctl |= GC_FRM_MGMT_PORT_M; 778 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, hdr_ctl); 779 780 /* B53_BRCM_HDR not present on devices with legacy tags */ 781 if (dev->tag_protocol == DSA_TAG_PROTO_BRCM_LEGACY || 782 dev->tag_protocol == DSA_TAG_PROTO_BRCM_LEGACY_FCS) 783 return; 784 785 /* Enable Broadcom tags for IMP port */ 786 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl); 787 if (tag_en) 788 hdr_ctl |= val; 789 else 790 hdr_ctl &= ~val; 791 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl); 792 793 /* Registers below are only accessible on newer devices */ 794 if (!is58xx(dev)) 795 return; 796 797 /* Enable reception Broadcom tag for CPU TX (switch RX) to 798 * allow us to tag outgoing frames 799 */ 800 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, ®); 801 if (tag_en) 802 reg &= ~BIT(port); 803 else 804 reg |= BIT(port); 805 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg); 806 807 /* Enable transmission of Broadcom tags from the switch (CPU RX) to 808 * allow delivering frames to the per-port net_devices 809 */ 810 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, ®); 811 if (tag_en) 812 reg &= ~BIT(port); 813 else 814 reg |= BIT(port); 815 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg); 816 } 817 EXPORT_SYMBOL(b53_brcm_hdr_setup); 818 819 static void b53_enable_cpu_port(struct b53_device *dev, int port) 820 { 821 u8 port_ctrl; 822 823 /* BCM5325 CPU port is at 8 */ 824 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25) 825 port = B53_CPU_PORT; 826 827 port_ctrl = PORT_CTRL_RX_BCST_EN | 828 PORT_CTRL_RX_MCST_EN | 829 PORT_CTRL_RX_UCST_EN; 830 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl); 831 832 b53_brcm_hdr_setup(dev->ds, port); 833 } 834 835 static void b53_enable_mib(struct b53_device *dev) 836 { 837 u8 gc; 838 839 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 840 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN); 841 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc); 842 } 843 844 static void b53_enable_stp(struct b53_device *dev) 845 { 846 u8 gc; 847 848 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 849 gc |= GC_RX_BPDU_EN; 850 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc); 851 } 852 853 static u16 b53_default_pvid(struct b53_device *dev) 854 { 855 if (is5325(dev) || is5365(dev)) 856 return 1; 857 else 858 return 0; 859 } 860 861 static bool b53_vlan_port_needs_forced_tagged(struct dsa_switch *ds, int port) 862 { 863 struct b53_device *dev = ds->priv; 864 865 return dev->tag_protocol == DSA_TAG_PROTO_NONE && dsa_is_cpu_port(ds, port); 866 } 867 868 static bool b53_vlan_port_may_join_untagged(struct dsa_switch *ds, int port) 869 { 870 struct b53_device *dev = ds->priv; 871 struct dsa_port *dp; 872 873 if (!dev->vlan_filtering) 874 return true; 875 876 dp = dsa_to_port(ds, port); 877 878 if (dsa_port_is_cpu(dp)) 879 return true; 880 881 return dp->bridge == NULL; 882 } 883 884 int b53_configure_vlan(struct dsa_switch *ds) 885 { 886 struct b53_device *dev = ds->priv; 887 struct b53_vlan vl = { 0 }; 888 struct b53_vlan *v; 889 int i, def_vid; 890 u16 vid; 891 892 def_vid = b53_default_pvid(dev); 893 894 /* clear all vlan entries */ 895 if (is5325(dev) || is5365(dev)) { 896 for (i = def_vid; i < dev->num_vlans; i++) 897 b53_set_vlan_entry(dev, i, &vl); 898 } else { 899 b53_do_vlan_op(dev, VTA_CMD_CLEAR); 900 } 901 902 b53_enable_vlan(dev, -1, dev->vlan_enabled, dev->vlan_filtering); 903 904 /* Create an untagged VLAN entry for the default PVID in case 905 * CONFIG_VLAN_8021Q is disabled and there are no calls to 906 * dsa_user_vlan_rx_add_vid() to create the default VLAN 907 * entry. Do this only when the tagging protocol is not 908 * DSA_TAG_PROTO_NONE 909 */ 910 v = &dev->vlans[def_vid]; 911 b53_for_each_port(dev, i) { 912 if (!b53_vlan_port_may_join_untagged(ds, i)) 913 continue; 914 915 vl.members |= BIT(i); 916 if (!b53_vlan_port_needs_forced_tagged(ds, i)) 917 vl.untag = vl.members; 918 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(i), 919 def_vid); 920 } 921 b53_set_vlan_entry(dev, def_vid, &vl); 922 923 if (dev->vlan_filtering) { 924 /* Upon initial call we have not set-up any VLANs, but upon 925 * system resume, we need to restore all VLAN entries. 926 */ 927 for (vid = def_vid + 1; vid < dev->num_vlans; vid++) { 928 v = &dev->vlans[vid]; 929 930 if (!v->members) 931 continue; 932 933 b53_set_vlan_entry(dev, vid, v); 934 b53_fast_age_vlan(dev, vid); 935 } 936 937 b53_for_each_port(dev, i) { 938 if (!dsa_is_cpu_port(ds, i)) 939 b53_write16(dev, B53_VLAN_PAGE, 940 B53_VLAN_PORT_DEF_TAG(i), 941 dev->ports[i].pvid); 942 } 943 } 944 945 return 0; 946 } 947 EXPORT_SYMBOL(b53_configure_vlan); 948 949 static void b53_switch_reset_gpio(struct b53_device *dev) 950 { 951 int gpio = dev->reset_gpio; 952 953 if (gpio < 0) 954 return; 955 956 /* Reset sequence: RESET low(50ms)->high(20ms) 957 */ 958 gpio_set_value(gpio, 0); 959 mdelay(50); 960 961 gpio_set_value(gpio, 1); 962 mdelay(20); 963 964 dev->current_page = 0xff; 965 } 966 967 static int b53_switch_reset(struct b53_device *dev) 968 { 969 unsigned int timeout = 1000; 970 u8 mgmt, reg; 971 972 b53_switch_reset_gpio(dev); 973 974 if (is539x(dev)) { 975 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83); 976 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00); 977 } 978 979 /* This is specific to 58xx devices here, do not use is58xx() which 980 * covers the larger Starfigther 2 family, including 7445/7278 which 981 * still use this driver as a library and need to perform the reset 982 * earlier. 983 */ 984 if (dev->chip_id == BCM58XX_DEVICE_ID || 985 dev->chip_id == BCM583XX_DEVICE_ID) { 986 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 987 reg |= SW_RST | EN_SW_RST | EN_CH_RST; 988 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg); 989 990 do { 991 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 992 if (!(reg & SW_RST)) 993 break; 994 995 usleep_range(1000, 2000); 996 } while (timeout-- > 0); 997 998 if (timeout == 0) { 999 dev_err(dev->dev, 1000 "Timeout waiting for SW_RST to clear!\n"); 1001 return -ETIMEDOUT; 1002 } 1003 } 1004 1005 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 1006 1007 if (!(mgmt & SM_SW_FWD_EN)) { 1008 mgmt &= ~SM_SW_FWD_MODE; 1009 mgmt |= SM_SW_FWD_EN; 1010 1011 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 1012 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 1013 1014 if (!(mgmt & SM_SW_FWD_EN)) { 1015 dev_err(dev->dev, "Failed to enable switch!\n"); 1016 return -EINVAL; 1017 } 1018 } 1019 1020 b53_enable_mib(dev); 1021 b53_enable_stp(dev); 1022 1023 return b53_flush_arl(dev, FAST_AGE_STATIC); 1024 } 1025 1026 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg) 1027 { 1028 struct b53_device *priv = ds->priv; 1029 u16 value = 0; 1030 int ret; 1031 1032 if (priv->ops->phy_read16) 1033 ret = priv->ops->phy_read16(priv, addr, reg, &value); 1034 else 1035 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr), 1036 reg * 2, &value); 1037 1038 return ret ? ret : value; 1039 } 1040 1041 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 1042 { 1043 struct b53_device *priv = ds->priv; 1044 1045 if (priv->ops->phy_write16) 1046 return priv->ops->phy_write16(priv, addr, reg, val); 1047 1048 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val); 1049 } 1050 1051 static int b53_reset_switch(struct b53_device *priv) 1052 { 1053 /* reset vlans */ 1054 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans); 1055 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports); 1056 1057 priv->serdes_lane = B53_INVALID_LANE; 1058 1059 return b53_switch_reset(priv); 1060 } 1061 1062 static int b53_apply_config(struct b53_device *priv) 1063 { 1064 /* disable switching */ 1065 b53_set_forwarding(priv, 0); 1066 1067 b53_configure_vlan(priv->ds); 1068 1069 /* enable switching */ 1070 b53_set_forwarding(priv, 1); 1071 1072 return 0; 1073 } 1074 1075 static void b53_reset_mib(struct b53_device *priv) 1076 { 1077 u8 gc; 1078 1079 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 1080 1081 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB); 1082 msleep(1); 1083 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB); 1084 msleep(1); 1085 } 1086 1087 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev) 1088 { 1089 if (is5365(dev)) 1090 return b53_mibs_65; 1091 else if (is63xx(dev)) 1092 return b53_mibs_63xx; 1093 else if (is58xx(dev)) 1094 return b53_mibs_58xx; 1095 else 1096 return b53_mibs; 1097 } 1098 1099 static unsigned int b53_get_mib_size(struct b53_device *dev) 1100 { 1101 if (is5365(dev)) 1102 return B53_MIBS_65_SIZE; 1103 else if (is63xx(dev)) 1104 return B53_MIBS_63XX_SIZE; 1105 else if (is58xx(dev)) 1106 return B53_MIBS_58XX_SIZE; 1107 else 1108 return B53_MIBS_SIZE; 1109 } 1110 1111 static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port) 1112 { 1113 /* These ports typically do not have built-in PHYs */ 1114 switch (port) { 1115 case B53_CPU_PORT_25: 1116 case 7: 1117 case B53_CPU_PORT: 1118 return NULL; 1119 } 1120 1121 return mdiobus_get_phy(ds->user_mii_bus, port); 1122 } 1123 1124 void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset, 1125 uint8_t *data) 1126 { 1127 struct b53_device *dev = ds->priv; 1128 const struct b53_mib_desc *mibs = b53_get_mib(dev); 1129 unsigned int mib_size = b53_get_mib_size(dev); 1130 struct phy_device *phydev; 1131 unsigned int i; 1132 1133 if (stringset == ETH_SS_STATS) { 1134 for (i = 0; i < mib_size; i++) 1135 ethtool_puts(&data, mibs[i].name); 1136 } else if (stringset == ETH_SS_PHY_STATS) { 1137 phydev = b53_get_phy_device(ds, port); 1138 if (!phydev) 1139 return; 1140 1141 phy_ethtool_get_strings(phydev, data); 1142 } 1143 } 1144 EXPORT_SYMBOL(b53_get_strings); 1145 1146 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) 1147 { 1148 struct b53_device *dev = ds->priv; 1149 const struct b53_mib_desc *mibs = b53_get_mib(dev); 1150 unsigned int mib_size = b53_get_mib_size(dev); 1151 const struct b53_mib_desc *s; 1152 unsigned int i; 1153 u64 val = 0; 1154 1155 if (is5365(dev) && port == 5) 1156 port = 8; 1157 1158 mutex_lock(&dev->stats_mutex); 1159 1160 for (i = 0; i < mib_size; i++) { 1161 s = &mibs[i]; 1162 1163 if (s->size == 8) { 1164 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val); 1165 } else { 1166 u32 val32; 1167 1168 b53_read32(dev, B53_MIB_PAGE(port), s->offset, 1169 &val32); 1170 val = val32; 1171 } 1172 data[i] = (u64)val; 1173 } 1174 1175 mutex_unlock(&dev->stats_mutex); 1176 } 1177 EXPORT_SYMBOL(b53_get_ethtool_stats); 1178 1179 void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data) 1180 { 1181 struct phy_device *phydev; 1182 1183 phydev = b53_get_phy_device(ds, port); 1184 if (!phydev) 1185 return; 1186 1187 phy_ethtool_get_stats(phydev, NULL, data); 1188 } 1189 EXPORT_SYMBOL(b53_get_ethtool_phy_stats); 1190 1191 int b53_get_sset_count(struct dsa_switch *ds, int port, int sset) 1192 { 1193 struct b53_device *dev = ds->priv; 1194 struct phy_device *phydev; 1195 1196 if (sset == ETH_SS_STATS) { 1197 return b53_get_mib_size(dev); 1198 } else if (sset == ETH_SS_PHY_STATS) { 1199 phydev = b53_get_phy_device(ds, port); 1200 if (!phydev) 1201 return 0; 1202 1203 return phy_ethtool_get_sset_count(phydev); 1204 } 1205 1206 return 0; 1207 } 1208 EXPORT_SYMBOL(b53_get_sset_count); 1209 1210 enum b53_devlink_resource_id { 1211 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1212 }; 1213 1214 static u64 b53_devlink_vlan_table_get(void *priv) 1215 { 1216 struct b53_device *dev = priv; 1217 struct b53_vlan *vl; 1218 unsigned int i; 1219 u64 count = 0; 1220 1221 for (i = 0; i < dev->num_vlans; i++) { 1222 vl = &dev->vlans[i]; 1223 if (vl->members) 1224 count++; 1225 } 1226 1227 return count; 1228 } 1229 1230 int b53_setup_devlink_resources(struct dsa_switch *ds) 1231 { 1232 struct devlink_resource_size_params size_params; 1233 struct b53_device *dev = ds->priv; 1234 int err; 1235 1236 devlink_resource_size_params_init(&size_params, dev->num_vlans, 1237 dev->num_vlans, 1238 1, DEVLINK_RESOURCE_UNIT_ENTRY); 1239 1240 err = dsa_devlink_resource_register(ds, "VLAN", dev->num_vlans, 1241 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1242 DEVLINK_RESOURCE_ID_PARENT_TOP, 1243 &size_params); 1244 if (err) 1245 goto out; 1246 1247 dsa_devlink_resource_occ_get_register(ds, 1248 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1249 b53_devlink_vlan_table_get, dev); 1250 1251 return 0; 1252 out: 1253 dsa_devlink_resources_unregister(ds); 1254 return err; 1255 } 1256 EXPORT_SYMBOL(b53_setup_devlink_resources); 1257 1258 static int b53_setup(struct dsa_switch *ds) 1259 { 1260 struct b53_device *dev = ds->priv; 1261 struct b53_vlan *vl; 1262 unsigned int port; 1263 u16 pvid; 1264 int ret; 1265 1266 /* Request bridge PVID untagged when DSA_TAG_PROTO_NONE is set 1267 * which forces the CPU port to be tagged in all VLANs. 1268 */ 1269 ds->untag_bridge_pvid = dev->tag_protocol == DSA_TAG_PROTO_NONE; 1270 1271 /* The switch does not tell us the original VLAN for untagged 1272 * packets, so keep the CPU port always tagged. 1273 */ 1274 ds->untag_vlan_aware_bridge_pvid = true; 1275 1276 if (dev->chip_id == BCM53101_DEVICE_ID) { 1277 /* BCM53101 uses 0.5 second increments */ 1278 ds->ageing_time_min = 1 * 500; 1279 ds->ageing_time_max = AGE_TIME_MAX * 500; 1280 } else { 1281 /* Everything else uses 1 second increments */ 1282 ds->ageing_time_min = 1 * 1000; 1283 ds->ageing_time_max = AGE_TIME_MAX * 1000; 1284 } 1285 1286 ret = b53_reset_switch(dev); 1287 if (ret) { 1288 dev_err(ds->dev, "failed to reset switch\n"); 1289 return ret; 1290 } 1291 1292 /* setup default vlan for filtering mode */ 1293 pvid = b53_default_pvid(dev); 1294 vl = &dev->vlans[pvid]; 1295 b53_for_each_port(dev, port) { 1296 vl->members |= BIT(port); 1297 if (!b53_vlan_port_needs_forced_tagged(ds, port)) 1298 vl->untag |= BIT(port); 1299 } 1300 1301 b53_reset_mib(dev); 1302 1303 ret = b53_apply_config(dev); 1304 if (ret) { 1305 dev_err(ds->dev, "failed to apply configuration\n"); 1306 return ret; 1307 } 1308 1309 /* Configure IMP/CPU port, disable all other ports. Enabled 1310 * ports will be configured with .port_enable 1311 */ 1312 for (port = 0; port < dev->num_ports; port++) { 1313 if (dsa_is_cpu_port(ds, port)) 1314 b53_enable_cpu_port(dev, port); 1315 else 1316 b53_disable_port(ds, port); 1317 } 1318 1319 return b53_setup_devlink_resources(ds); 1320 } 1321 1322 static void b53_teardown(struct dsa_switch *ds) 1323 { 1324 dsa_devlink_resources_unregister(ds); 1325 } 1326 1327 static void b53_force_link(struct b53_device *dev, int port, int link) 1328 { 1329 u8 reg, val, off; 1330 1331 /* Override the port settings */ 1332 if (port == dev->imp_port) { 1333 off = B53_PORT_OVERRIDE_CTRL; 1334 val = PORT_OVERRIDE_EN; 1335 } else if (is5325(dev)) { 1336 return; 1337 } else { 1338 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 1339 val = GMII_PO_EN; 1340 } 1341 1342 b53_read8(dev, B53_CTRL_PAGE, off, ®); 1343 reg |= val; 1344 if (link) 1345 reg |= PORT_OVERRIDE_LINK; 1346 else 1347 reg &= ~PORT_OVERRIDE_LINK; 1348 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1349 } 1350 1351 static void b53_force_port_config(struct b53_device *dev, int port, 1352 int speed, int duplex, 1353 bool tx_pause, bool rx_pause) 1354 { 1355 u8 reg, val, off; 1356 1357 /* Override the port settings */ 1358 if (port == dev->imp_port) { 1359 off = B53_PORT_OVERRIDE_CTRL; 1360 val = PORT_OVERRIDE_EN; 1361 } else if (is5325(dev)) { 1362 return; 1363 } else { 1364 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 1365 val = GMII_PO_EN; 1366 } 1367 1368 b53_read8(dev, B53_CTRL_PAGE, off, ®); 1369 reg |= val; 1370 if (duplex == DUPLEX_FULL) 1371 reg |= PORT_OVERRIDE_FULL_DUPLEX; 1372 else 1373 reg &= ~PORT_OVERRIDE_FULL_DUPLEX; 1374 1375 switch (speed) { 1376 case 2000: 1377 reg |= PORT_OVERRIDE_SPEED_2000M; 1378 fallthrough; 1379 case SPEED_1000: 1380 reg |= PORT_OVERRIDE_SPEED_1000M; 1381 break; 1382 case SPEED_100: 1383 reg |= PORT_OVERRIDE_SPEED_100M; 1384 break; 1385 case SPEED_10: 1386 reg |= PORT_OVERRIDE_SPEED_10M; 1387 break; 1388 default: 1389 dev_err(dev->dev, "unknown speed: %d\n", speed); 1390 return; 1391 } 1392 1393 if (rx_pause) { 1394 if (is5325(dev)) 1395 reg |= PORT_OVERRIDE_LP_FLOW_25; 1396 else 1397 reg |= PORT_OVERRIDE_RX_FLOW; 1398 } 1399 1400 if (tx_pause) { 1401 if (is5325(dev)) 1402 reg |= PORT_OVERRIDE_LP_FLOW_25; 1403 else 1404 reg |= PORT_OVERRIDE_TX_FLOW; 1405 } 1406 1407 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1408 } 1409 1410 static void b53_adjust_63xx_rgmii(struct dsa_switch *ds, int port, 1411 phy_interface_t interface) 1412 { 1413 struct b53_device *dev = ds->priv; 1414 u8 rgmii_ctrl = 0; 1415 1416 b53_read8(dev, B53_CTRL_PAGE, B53_RGMII_CTRL_P(port), &rgmii_ctrl); 1417 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC); 1418 1419 if (is6318_268(dev)) 1420 rgmii_ctrl |= RGMII_CTRL_MII_OVERRIDE; 1421 1422 rgmii_ctrl |= RGMII_CTRL_ENABLE_GMII; 1423 1424 b53_write8(dev, B53_CTRL_PAGE, B53_RGMII_CTRL_P(port), rgmii_ctrl); 1425 1426 dev_dbg(ds->dev, "Configured port %d for %s\n", port, 1427 phy_modes(interface)); 1428 } 1429 1430 static void b53_adjust_531x5_rgmii(struct dsa_switch *ds, int port, 1431 phy_interface_t interface) 1432 { 1433 struct b53_device *dev = ds->priv; 1434 u8 rgmii_ctrl = 0, off; 1435 1436 if (port == dev->imp_port) 1437 off = B53_RGMII_CTRL_IMP; 1438 else 1439 off = B53_RGMII_CTRL_P(port); 1440 1441 /* Configure the port RGMII clock delay by DLL disabled and 1442 * tx_clk aligned timing (restoring to reset defaults) 1443 */ 1444 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl); 1445 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC); 1446 1447 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make 1448 * sure that we enable the port TX clock internal delay to 1449 * account for this internal delay that is inserted, otherwise 1450 * the switch won't be able to receive correctly. 1451 * 1452 * PHY_INTERFACE_MODE_RGMII means that we are not introducing 1453 * any delay neither on transmission nor reception, so the 1454 * BCM53125 must also be configured accordingly to account for 1455 * the lack of delay and introduce 1456 * 1457 * The BCM53125 switch has its RX clock and TX clock control 1458 * swapped, hence the reason why we modify the TX clock path in 1459 * the "RGMII" case 1460 */ 1461 if (interface == PHY_INTERFACE_MODE_RGMII_TXID) 1462 rgmii_ctrl |= RGMII_CTRL_DLL_TXC; 1463 if (interface == PHY_INTERFACE_MODE_RGMII) 1464 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC; 1465 1466 if (dev->chip_id != BCM53115_DEVICE_ID) 1467 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL; 1468 1469 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl); 1470 1471 dev_info(ds->dev, "Configured port %d for %s\n", port, 1472 phy_modes(interface)); 1473 } 1474 1475 static void b53_adjust_5325_mii(struct dsa_switch *ds, int port) 1476 { 1477 struct b53_device *dev = ds->priv; 1478 u8 reg = 0; 1479 1480 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1481 ®); 1482 1483 /* reverse mii needs to be enabled */ 1484 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1485 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1486 reg | PORT_OVERRIDE_RV_MII_25); 1487 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1488 ®); 1489 1490 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1491 dev_err(ds->dev, 1492 "Failed to enable reverse MII mode\n"); 1493 return; 1494 } 1495 } 1496 } 1497 1498 void b53_port_event(struct dsa_switch *ds, int port) 1499 { 1500 struct b53_device *dev = ds->priv; 1501 bool link; 1502 u16 sts; 1503 1504 b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts); 1505 link = !!(sts & BIT(port)); 1506 dsa_port_phylink_mac_change(ds, port, link); 1507 } 1508 EXPORT_SYMBOL(b53_port_event); 1509 1510 static void b53_phylink_get_caps(struct dsa_switch *ds, int port, 1511 struct phylink_config *config) 1512 { 1513 struct b53_device *dev = ds->priv; 1514 1515 /* Internal ports need GMII for PHYLIB */ 1516 __set_bit(PHY_INTERFACE_MODE_GMII, config->supported_interfaces); 1517 1518 /* These switches appear to support MII and RevMII too, but beyond 1519 * this, the code gives very few clues. FIXME: We probably need more 1520 * interface modes here. 1521 * 1522 * According to b53_srab_mux_init(), ports 3..5 can support: 1523 * SGMII, MII, GMII, RGMII or INTERNAL depending on the MUX setting. 1524 * However, the interface mode read from the MUX configuration is 1525 * not passed back to DSA, so phylink uses NA. 1526 * DT can specify RGMII for ports 0, 1. 1527 * For MDIO, port 8 can be RGMII_TXID. 1528 */ 1529 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 1530 __set_bit(PHY_INTERFACE_MODE_REVMII, config->supported_interfaces); 1531 1532 /* BCM63xx RGMII ports support RGMII */ 1533 if (is63xx(dev) && in_range(port, B53_63XX_RGMII0, 4)) 1534 phy_interface_set_rgmii(config->supported_interfaces); 1535 1536 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 1537 MAC_10 | MAC_100; 1538 1539 /* 5325/5365 are not capable of gigabit speeds, everything else is. 1540 * Note: the original code also exclulded Gigagbit for MII, RevMII 1541 * and 802.3z modes. MII and RevMII are not able to work above 100M, 1542 * so will be excluded by the generic validator implementation. 1543 * However, the exclusion of Gigabit for 802.3z just seems wrong. 1544 */ 1545 if (!(is5325(dev) || is5365(dev))) 1546 config->mac_capabilities |= MAC_1000; 1547 1548 /* Get the implementation specific capabilities */ 1549 if (dev->ops->phylink_get_caps) 1550 dev->ops->phylink_get_caps(dev, port, config); 1551 } 1552 1553 static struct phylink_pcs *b53_phylink_mac_select_pcs(struct phylink_config *config, 1554 phy_interface_t interface) 1555 { 1556 struct dsa_port *dp = dsa_phylink_to_port(config); 1557 struct b53_device *dev = dp->ds->priv; 1558 1559 if (!dev->ops->phylink_mac_select_pcs) 1560 return NULL; 1561 1562 return dev->ops->phylink_mac_select_pcs(dev, dp->index, interface); 1563 } 1564 1565 static void b53_phylink_mac_config(struct phylink_config *config, 1566 unsigned int mode, 1567 const struct phylink_link_state *state) 1568 { 1569 struct dsa_port *dp = dsa_phylink_to_port(config); 1570 phy_interface_t interface = state->interface; 1571 struct dsa_switch *ds = dp->ds; 1572 struct b53_device *dev = ds->priv; 1573 int port = dp->index; 1574 1575 if (is63xx(dev) && in_range(port, B53_63XX_RGMII0, 4)) 1576 b53_adjust_63xx_rgmii(ds, port, interface); 1577 1578 if (mode == MLO_AN_FIXED) { 1579 if (is531x5(dev) && phy_interface_mode_is_rgmii(interface)) 1580 b53_adjust_531x5_rgmii(ds, port, interface); 1581 1582 /* configure MII port if necessary */ 1583 if (is5325(dev)) 1584 b53_adjust_5325_mii(ds, port); 1585 } 1586 } 1587 1588 static void b53_phylink_mac_link_down(struct phylink_config *config, 1589 unsigned int mode, 1590 phy_interface_t interface) 1591 { 1592 struct dsa_port *dp = dsa_phylink_to_port(config); 1593 struct b53_device *dev = dp->ds->priv; 1594 int port = dp->index; 1595 1596 if (mode == MLO_AN_PHY) 1597 return; 1598 1599 if (mode == MLO_AN_FIXED) { 1600 b53_force_link(dev, port, false); 1601 return; 1602 } 1603 1604 if (phy_interface_mode_is_8023z(interface) && 1605 dev->ops->serdes_link_set) 1606 dev->ops->serdes_link_set(dev, port, mode, interface, false); 1607 } 1608 1609 static void b53_phylink_mac_link_up(struct phylink_config *config, 1610 struct phy_device *phydev, 1611 unsigned int mode, 1612 phy_interface_t interface, 1613 int speed, int duplex, 1614 bool tx_pause, bool rx_pause) 1615 { 1616 struct dsa_port *dp = dsa_phylink_to_port(config); 1617 struct dsa_switch *ds = dp->ds; 1618 struct b53_device *dev = ds->priv; 1619 struct ethtool_keee *p = &dev->ports[dp->index].eee; 1620 int port = dp->index; 1621 1622 if (mode == MLO_AN_PHY) { 1623 /* Re-negotiate EEE if it was enabled already */ 1624 p->eee_enabled = b53_eee_init(ds, port, phydev); 1625 return; 1626 } 1627 1628 if (mode == MLO_AN_FIXED) { 1629 /* Force flow control on BCM5301x's CPU port */ 1630 if (is5301x(dev) && dsa_is_cpu_port(ds, port)) 1631 tx_pause = rx_pause = true; 1632 1633 b53_force_port_config(dev, port, speed, duplex, 1634 tx_pause, rx_pause); 1635 b53_force_link(dev, port, true); 1636 return; 1637 } 1638 1639 if (phy_interface_mode_is_8023z(interface) && 1640 dev->ops->serdes_link_set) 1641 dev->ops->serdes_link_set(dev, port, mode, interface, true); 1642 } 1643 1644 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1645 struct netlink_ext_ack *extack) 1646 { 1647 struct b53_device *dev = ds->priv; 1648 1649 if (dev->vlan_filtering != vlan_filtering) { 1650 dev->vlan_filtering = vlan_filtering; 1651 b53_apply_config(dev); 1652 } 1653 1654 return 0; 1655 } 1656 EXPORT_SYMBOL(b53_vlan_filtering); 1657 1658 static int b53_vlan_prepare(struct dsa_switch *ds, int port, 1659 const struct switchdev_obj_port_vlan *vlan) 1660 { 1661 struct b53_device *dev = ds->priv; 1662 1663 if ((is5325(dev) || is5365(dev)) && vlan->vid == 0) 1664 return -EOPNOTSUPP; 1665 1666 /* Port 7 on 7278 connects to the ASP's UniMAC which is not capable of 1667 * receiving VLAN tagged frames at all, we can still allow the port to 1668 * be configured for egress untagged. 1669 */ 1670 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7 && 1671 !(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)) 1672 return -EINVAL; 1673 1674 if (vlan->vid >= dev->num_vlans) 1675 return -ERANGE; 1676 1677 b53_enable_vlan(dev, port, true, dev->vlan_filtering); 1678 1679 return 0; 1680 } 1681 1682 int b53_vlan_add(struct dsa_switch *ds, int port, 1683 const struct switchdev_obj_port_vlan *vlan, 1684 struct netlink_ext_ack *extack) 1685 { 1686 struct b53_device *dev = ds->priv; 1687 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1688 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1689 struct b53_vlan *vl; 1690 u16 old_pvid, new_pvid; 1691 int err; 1692 1693 err = b53_vlan_prepare(ds, port, vlan); 1694 if (err) 1695 return err; 1696 1697 if (vlan->vid == 0) 1698 return 0; 1699 1700 old_pvid = dev->ports[port].pvid; 1701 if (pvid) 1702 new_pvid = vlan->vid; 1703 else if (!pvid && vlan->vid == old_pvid) 1704 new_pvid = b53_default_pvid(dev); 1705 else 1706 new_pvid = old_pvid; 1707 dev->ports[port].pvid = new_pvid; 1708 1709 vl = &dev->vlans[vlan->vid]; 1710 1711 if (dsa_is_cpu_port(ds, port)) 1712 untagged = false; 1713 1714 vl->members |= BIT(port); 1715 if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port)) 1716 vl->untag |= BIT(port); 1717 else 1718 vl->untag &= ~BIT(port); 1719 1720 if (!dev->vlan_filtering) 1721 return 0; 1722 1723 b53_set_vlan_entry(dev, vlan->vid, vl); 1724 b53_fast_age_vlan(dev, vlan->vid); 1725 1726 if (!dsa_is_cpu_port(ds, port) && new_pvid != old_pvid) { 1727 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), 1728 new_pvid); 1729 b53_fast_age_vlan(dev, old_pvid); 1730 } 1731 1732 return 0; 1733 } 1734 EXPORT_SYMBOL(b53_vlan_add); 1735 1736 int b53_vlan_del(struct dsa_switch *ds, int port, 1737 const struct switchdev_obj_port_vlan *vlan) 1738 { 1739 struct b53_device *dev = ds->priv; 1740 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1741 struct b53_vlan *vl; 1742 u16 pvid; 1743 1744 if (vlan->vid == 0) 1745 return 0; 1746 1747 pvid = dev->ports[port].pvid; 1748 1749 vl = &dev->vlans[vlan->vid]; 1750 1751 vl->members &= ~BIT(port); 1752 1753 if (pvid == vlan->vid) 1754 pvid = b53_default_pvid(dev); 1755 dev->ports[port].pvid = pvid; 1756 1757 if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port)) 1758 vl->untag &= ~(BIT(port)); 1759 1760 if (!dev->vlan_filtering) 1761 return 0; 1762 1763 b53_set_vlan_entry(dev, vlan->vid, vl); 1764 b53_fast_age_vlan(dev, vlan->vid); 1765 1766 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid); 1767 b53_fast_age_vlan(dev, pvid); 1768 1769 return 0; 1770 } 1771 EXPORT_SYMBOL(b53_vlan_del); 1772 1773 /* Address Resolution Logic routines. Caller must hold &dev->arl_mutex. */ 1774 static int b53_arl_op_wait(struct b53_device *dev) 1775 { 1776 unsigned int timeout = 10; 1777 u8 reg; 1778 1779 do { 1780 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1781 if (!(reg & ARLTBL_START_DONE)) 1782 return 0; 1783 1784 usleep_range(1000, 2000); 1785 } while (timeout--); 1786 1787 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg); 1788 1789 return -ETIMEDOUT; 1790 } 1791 1792 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op) 1793 { 1794 u8 reg; 1795 1796 if (op > ARLTBL_RW) 1797 return -EINVAL; 1798 1799 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1800 reg |= ARLTBL_START_DONE; 1801 if (op) 1802 reg |= ARLTBL_RW; 1803 else 1804 reg &= ~ARLTBL_RW; 1805 if (dev->vlan_enabled) 1806 reg &= ~ARLTBL_IVL_SVL_SELECT; 1807 else 1808 reg |= ARLTBL_IVL_SVL_SELECT; 1809 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg); 1810 1811 return b53_arl_op_wait(dev); 1812 } 1813 1814 static int b53_arl_read(struct b53_device *dev, u64 mac, 1815 u16 vid, struct b53_arl_entry *ent, u8 *idx) 1816 { 1817 DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES); 1818 unsigned int i; 1819 int ret; 1820 1821 ret = b53_arl_op_wait(dev); 1822 if (ret) 1823 return ret; 1824 1825 bitmap_zero(free_bins, dev->num_arl_bins); 1826 1827 /* Read the bins */ 1828 for (i = 0; i < dev->num_arl_bins; i++) { 1829 u64 mac_vid; 1830 u32 fwd_entry; 1831 1832 b53_read64(dev, B53_ARLIO_PAGE, 1833 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid); 1834 b53_read32(dev, B53_ARLIO_PAGE, 1835 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry); 1836 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1837 1838 if (!(fwd_entry & ARLTBL_VALID)) { 1839 set_bit(i, free_bins); 1840 continue; 1841 } 1842 if ((mac_vid & ARLTBL_MAC_MASK) != mac) 1843 continue; 1844 if (dev->vlan_enabled && 1845 ((mac_vid >> ARLTBL_VID_S) & ARLTBL_VID_MASK) != vid) 1846 continue; 1847 *idx = i; 1848 return 0; 1849 } 1850 1851 *idx = find_first_bit(free_bins, dev->num_arl_bins); 1852 return *idx >= dev->num_arl_bins ? -ENOSPC : -ENOENT; 1853 } 1854 1855 static int b53_arl_read_25(struct b53_device *dev, u64 mac, 1856 u16 vid, struct b53_arl_entry *ent, u8 *idx) 1857 { 1858 DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES); 1859 unsigned int i; 1860 int ret; 1861 1862 ret = b53_arl_op_wait(dev); 1863 if (ret) 1864 return ret; 1865 1866 bitmap_zero(free_bins, dev->num_arl_bins); 1867 1868 /* Read the bins */ 1869 for (i = 0; i < dev->num_arl_bins; i++) { 1870 u64 mac_vid; 1871 1872 b53_read64(dev, B53_ARLIO_PAGE, 1873 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid); 1874 1875 b53_arl_to_entry_25(ent, mac_vid); 1876 1877 if (!(mac_vid & ARLTBL_VALID_25)) { 1878 set_bit(i, free_bins); 1879 continue; 1880 } 1881 if ((mac_vid & ARLTBL_MAC_MASK) != mac) 1882 continue; 1883 if (dev->vlan_enabled && 1884 ((mac_vid >> ARLTBL_VID_S_65) & ARLTBL_VID_MASK_25) != vid) 1885 continue; 1886 *idx = i; 1887 return 0; 1888 } 1889 1890 *idx = find_first_bit(free_bins, dev->num_arl_bins); 1891 return *idx >= dev->num_arl_bins ? -ENOSPC : -ENOENT; 1892 } 1893 1894 static int b53_arl_op(struct b53_device *dev, int op, int port, 1895 const unsigned char *addr, u16 vid, bool is_valid) 1896 { 1897 struct b53_arl_entry ent; 1898 u32 fwd_entry; 1899 u64 mac, mac_vid = 0; 1900 u8 idx = 0; 1901 int ret; 1902 1903 /* Convert the array into a 64-bit MAC */ 1904 mac = ether_addr_to_u64(addr); 1905 1906 /* Perform a read for the given MAC and VID */ 1907 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac); 1908 if (!is5325m(dev)) 1909 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid); 1910 1911 /* Issue a read operation for this MAC */ 1912 ret = b53_arl_rw_op(dev, 1); 1913 if (ret) 1914 return ret; 1915 1916 if (is5325(dev) || is5365(dev)) 1917 ret = b53_arl_read_25(dev, mac, vid, &ent, &idx); 1918 else 1919 ret = b53_arl_read(dev, mac, vid, &ent, &idx); 1920 1921 /* If this is a read, just finish now */ 1922 if (op) 1923 return ret; 1924 1925 switch (ret) { 1926 case -ETIMEDOUT: 1927 return ret; 1928 case -ENOSPC: 1929 dev_dbg(dev->dev, "{%pM,%.4d} no space left in ARL\n", 1930 addr, vid); 1931 return is_valid ? ret : 0; 1932 case -ENOENT: 1933 /* We could not find a matching MAC, so reset to a new entry */ 1934 dev_dbg(dev->dev, "{%pM,%.4d} not found, using idx: %d\n", 1935 addr, vid, idx); 1936 fwd_entry = 0; 1937 break; 1938 default: 1939 dev_dbg(dev->dev, "{%pM,%.4d} found, using idx: %d\n", 1940 addr, vid, idx); 1941 break; 1942 } 1943 1944 /* For multicast address, the port is a bitmask and the validity 1945 * is determined by having at least one port being still active 1946 */ 1947 if (!is_multicast_ether_addr(addr)) { 1948 ent.port = port; 1949 ent.is_valid = is_valid; 1950 } else { 1951 if (is_valid) 1952 ent.port |= BIT(port); 1953 else 1954 ent.port &= ~BIT(port); 1955 1956 ent.is_valid = !!(ent.port); 1957 } 1958 1959 ent.vid = vid; 1960 ent.is_static = true; 1961 ent.is_age = false; 1962 memcpy(ent.mac, addr, ETH_ALEN); 1963 if (is5325(dev) || is5365(dev)) 1964 b53_arl_from_entry_25(&mac_vid, &ent); 1965 else 1966 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent); 1967 1968 b53_write64(dev, B53_ARLIO_PAGE, 1969 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid); 1970 1971 if (!is5325(dev) && !is5365(dev)) 1972 b53_write32(dev, B53_ARLIO_PAGE, 1973 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry); 1974 1975 return b53_arl_rw_op(dev, 0); 1976 } 1977 1978 int b53_fdb_add(struct dsa_switch *ds, int port, 1979 const unsigned char *addr, u16 vid, 1980 struct dsa_db db) 1981 { 1982 struct b53_device *priv = ds->priv; 1983 int ret; 1984 1985 mutex_lock(&priv->arl_mutex); 1986 ret = b53_arl_op(priv, 0, port, addr, vid, true); 1987 mutex_unlock(&priv->arl_mutex); 1988 1989 return ret; 1990 } 1991 EXPORT_SYMBOL(b53_fdb_add); 1992 1993 int b53_fdb_del(struct dsa_switch *ds, int port, 1994 const unsigned char *addr, u16 vid, 1995 struct dsa_db db) 1996 { 1997 struct b53_device *priv = ds->priv; 1998 int ret; 1999 2000 mutex_lock(&priv->arl_mutex); 2001 ret = b53_arl_op(priv, 0, port, addr, vid, false); 2002 mutex_unlock(&priv->arl_mutex); 2003 2004 return ret; 2005 } 2006 EXPORT_SYMBOL(b53_fdb_del); 2007 2008 static int b53_arl_search_wait(struct b53_device *dev) 2009 { 2010 unsigned int timeout = 1000; 2011 u8 reg, offset; 2012 2013 if (is5325(dev) || is5365(dev)) 2014 offset = B53_ARL_SRCH_CTL_25; 2015 else 2016 offset = B53_ARL_SRCH_CTL; 2017 2018 do { 2019 b53_read8(dev, B53_ARLIO_PAGE, offset, ®); 2020 if (!(reg & ARL_SRCH_STDN)) 2021 return 0; 2022 2023 if (reg & ARL_SRCH_VLID) 2024 return 0; 2025 2026 usleep_range(1000, 2000); 2027 } while (timeout--); 2028 2029 return -ETIMEDOUT; 2030 } 2031 2032 static void b53_arl_search_rd(struct b53_device *dev, u8 idx, 2033 struct b53_arl_entry *ent) 2034 { 2035 u64 mac_vid; 2036 2037 if (is5325(dev)) { 2038 b53_read64(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSTL_0_MACVID_25, 2039 &mac_vid); 2040 b53_arl_to_entry_25(ent, mac_vid); 2041 } else if (is5365(dev)) { 2042 b53_read64(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSTL_0_MACVID_65, 2043 &mac_vid); 2044 b53_arl_to_entry_25(ent, mac_vid); 2045 } else { 2046 u32 fwd_entry; 2047 2048 b53_read64(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSTL_MACVID(idx), 2049 &mac_vid); 2050 b53_read32(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSTL(idx), 2051 &fwd_entry); 2052 b53_arl_to_entry(ent, mac_vid, fwd_entry); 2053 } 2054 } 2055 2056 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent, 2057 dsa_fdb_dump_cb_t *cb, void *data) 2058 { 2059 if (!ent->is_valid) 2060 return 0; 2061 2062 if (port != ent->port) 2063 return 0; 2064 2065 return cb(ent->mac, ent->vid, ent->is_static, data); 2066 } 2067 2068 int b53_fdb_dump(struct dsa_switch *ds, int port, 2069 dsa_fdb_dump_cb_t *cb, void *data) 2070 { 2071 struct b53_device *priv = ds->priv; 2072 struct b53_arl_entry results[2]; 2073 unsigned int count = 0; 2074 u8 offset; 2075 int ret; 2076 u8 reg; 2077 2078 mutex_lock(&priv->arl_mutex); 2079 2080 if (is5325(priv) || is5365(priv)) 2081 offset = B53_ARL_SRCH_CTL_25; 2082 else 2083 offset = B53_ARL_SRCH_CTL; 2084 2085 /* Start search operation */ 2086 reg = ARL_SRCH_STDN; 2087 b53_write8(priv, B53_ARLIO_PAGE, offset, reg); 2088 2089 do { 2090 ret = b53_arl_search_wait(priv); 2091 if (ret) 2092 break; 2093 2094 b53_arl_search_rd(priv, 0, &results[0]); 2095 ret = b53_fdb_copy(port, &results[0], cb, data); 2096 if (ret) 2097 break; 2098 2099 if (priv->num_arl_bins > 2) { 2100 b53_arl_search_rd(priv, 1, &results[1]); 2101 ret = b53_fdb_copy(port, &results[1], cb, data); 2102 if (ret) 2103 break; 2104 2105 if (!results[0].is_valid && !results[1].is_valid) 2106 break; 2107 } 2108 2109 } while (count++ < b53_max_arl_entries(priv) / 2); 2110 2111 mutex_unlock(&priv->arl_mutex); 2112 2113 return 0; 2114 } 2115 EXPORT_SYMBOL(b53_fdb_dump); 2116 2117 int b53_mdb_add(struct dsa_switch *ds, int port, 2118 const struct switchdev_obj_port_mdb *mdb, 2119 struct dsa_db db) 2120 { 2121 struct b53_device *priv = ds->priv; 2122 int ret; 2123 2124 /* 5325 and 5365 require some more massaging, but could 2125 * be supported eventually 2126 */ 2127 if (is5325(priv) || is5365(priv)) 2128 return -EOPNOTSUPP; 2129 2130 mutex_lock(&priv->arl_mutex); 2131 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, true); 2132 mutex_unlock(&priv->arl_mutex); 2133 2134 return ret; 2135 } 2136 EXPORT_SYMBOL(b53_mdb_add); 2137 2138 int b53_mdb_del(struct dsa_switch *ds, int port, 2139 const struct switchdev_obj_port_mdb *mdb, 2140 struct dsa_db db) 2141 { 2142 struct b53_device *priv = ds->priv; 2143 int ret; 2144 2145 mutex_lock(&priv->arl_mutex); 2146 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, false); 2147 mutex_unlock(&priv->arl_mutex); 2148 if (ret) 2149 dev_err(ds->dev, "failed to delete MDB entry\n"); 2150 2151 return ret; 2152 } 2153 EXPORT_SYMBOL(b53_mdb_del); 2154 2155 int b53_br_join(struct dsa_switch *ds, int port, struct dsa_bridge bridge, 2156 bool *tx_fwd_offload, struct netlink_ext_ack *extack) 2157 { 2158 struct b53_device *dev = ds->priv; 2159 struct b53_vlan *vl; 2160 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 2161 u16 pvlan, reg, pvid; 2162 unsigned int i; 2163 2164 /* On 7278, port 7 which connects to the ASP should only receive 2165 * traffic from matching CFP rules. 2166 */ 2167 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7) 2168 return -EINVAL; 2169 2170 pvid = b53_default_pvid(dev); 2171 vl = &dev->vlans[pvid]; 2172 2173 if (dev->vlan_filtering) { 2174 /* Make this port leave the all VLANs join since we will have 2175 * proper VLAN entries from now on 2176 */ 2177 if (is58xx(dev)) { 2178 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, 2179 ®); 2180 reg &= ~BIT(port); 2181 if ((reg & BIT(cpu_port)) == BIT(cpu_port)) 2182 reg &= ~BIT(cpu_port); 2183 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, 2184 reg); 2185 } 2186 2187 b53_get_vlan_entry(dev, pvid, vl); 2188 vl->members &= ~BIT(port); 2189 b53_set_vlan_entry(dev, pvid, vl); 2190 } 2191 2192 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 2193 2194 b53_for_each_port(dev, i) { 2195 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge)) 2196 continue; 2197 2198 /* Add this local port to the remote port VLAN control 2199 * membership and update the remote port bitmask 2200 */ 2201 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 2202 reg |= BIT(port); 2203 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 2204 dev->ports[i].vlan_ctl_mask = reg; 2205 2206 pvlan |= BIT(i); 2207 } 2208 2209 /* Disable redirection of unknown SA to the CPU port */ 2210 b53_set_eap_mode(dev, port, EAP_MODE_BASIC); 2211 2212 /* Configure the local port VLAN control membership to include 2213 * remote ports and update the local port bitmask 2214 */ 2215 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 2216 dev->ports[port].vlan_ctl_mask = pvlan; 2217 2218 return 0; 2219 } 2220 EXPORT_SYMBOL(b53_br_join); 2221 2222 void b53_br_leave(struct dsa_switch *ds, int port, struct dsa_bridge bridge) 2223 { 2224 struct b53_device *dev = ds->priv; 2225 struct b53_vlan *vl; 2226 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 2227 unsigned int i; 2228 u16 pvlan, reg, pvid; 2229 2230 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 2231 2232 b53_for_each_port(dev, i) { 2233 /* Don't touch the remaining ports */ 2234 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge)) 2235 continue; 2236 2237 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 2238 reg &= ~BIT(port); 2239 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 2240 dev->ports[port].vlan_ctl_mask = reg; 2241 2242 /* Prevent self removal to preserve isolation */ 2243 if (port != i) 2244 pvlan &= ~BIT(i); 2245 } 2246 2247 /* Enable redirection of unknown SA to the CPU port */ 2248 b53_set_eap_mode(dev, port, EAP_MODE_SIMPLIFIED); 2249 2250 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 2251 dev->ports[port].vlan_ctl_mask = pvlan; 2252 2253 pvid = b53_default_pvid(dev); 2254 vl = &dev->vlans[pvid]; 2255 2256 if (dev->vlan_filtering) { 2257 /* Make this port join all VLANs without VLAN entries */ 2258 if (is58xx(dev)) { 2259 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 2260 reg |= BIT(port); 2261 if (!(reg & BIT(cpu_port))) 2262 reg |= BIT(cpu_port); 2263 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 2264 } 2265 2266 b53_get_vlan_entry(dev, pvid, vl); 2267 vl->members |= BIT(port); 2268 b53_set_vlan_entry(dev, pvid, vl); 2269 } 2270 } 2271 EXPORT_SYMBOL(b53_br_leave); 2272 2273 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state) 2274 { 2275 struct b53_device *dev = ds->priv; 2276 u8 hw_state; 2277 u8 reg; 2278 2279 switch (state) { 2280 case BR_STATE_DISABLED: 2281 hw_state = PORT_CTRL_DIS_STATE; 2282 break; 2283 case BR_STATE_LISTENING: 2284 hw_state = PORT_CTRL_LISTEN_STATE; 2285 break; 2286 case BR_STATE_LEARNING: 2287 hw_state = PORT_CTRL_LEARN_STATE; 2288 break; 2289 case BR_STATE_FORWARDING: 2290 hw_state = PORT_CTRL_FWD_STATE; 2291 break; 2292 case BR_STATE_BLOCKING: 2293 hw_state = PORT_CTRL_BLOCK_STATE; 2294 break; 2295 default: 2296 dev_err(ds->dev, "invalid STP state: %d\n", state); 2297 return; 2298 } 2299 2300 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 2301 reg &= ~PORT_CTRL_STP_STATE_MASK; 2302 reg |= hw_state; 2303 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 2304 } 2305 EXPORT_SYMBOL(b53_br_set_stp_state); 2306 2307 void b53_br_fast_age(struct dsa_switch *ds, int port) 2308 { 2309 struct b53_device *dev = ds->priv; 2310 2311 if (b53_fast_age_port(dev, port)) 2312 dev_err(ds->dev, "fast ageing failed\n"); 2313 } 2314 EXPORT_SYMBOL(b53_br_fast_age); 2315 2316 int b53_br_flags_pre(struct dsa_switch *ds, int port, 2317 struct switchdev_brport_flags flags, 2318 struct netlink_ext_ack *extack) 2319 { 2320 struct b53_device *dev = ds->priv; 2321 unsigned long mask = (BR_FLOOD | BR_MCAST_FLOOD); 2322 2323 if (!is5325(dev)) 2324 mask |= BR_LEARNING; 2325 2326 if (flags.mask & ~mask) 2327 return -EINVAL; 2328 2329 return 0; 2330 } 2331 EXPORT_SYMBOL(b53_br_flags_pre); 2332 2333 int b53_br_flags(struct dsa_switch *ds, int port, 2334 struct switchdev_brport_flags flags, 2335 struct netlink_ext_ack *extack) 2336 { 2337 if (flags.mask & BR_FLOOD) 2338 b53_port_set_ucast_flood(ds->priv, port, 2339 !!(flags.val & BR_FLOOD)); 2340 if (flags.mask & BR_MCAST_FLOOD) 2341 b53_port_set_mcast_flood(ds->priv, port, 2342 !!(flags.val & BR_MCAST_FLOOD)); 2343 if (flags.mask & BR_LEARNING) 2344 b53_port_set_learning(ds->priv, port, 2345 !!(flags.val & BR_LEARNING)); 2346 2347 return 0; 2348 } 2349 EXPORT_SYMBOL(b53_br_flags); 2350 2351 static bool b53_possible_cpu_port(struct dsa_switch *ds, int port) 2352 { 2353 /* Broadcom switches will accept enabling Broadcom tags on the 2354 * following ports: 5, 7 and 8, any other port is not supported 2355 */ 2356 switch (port) { 2357 case B53_CPU_PORT_25: 2358 case 7: 2359 case B53_CPU_PORT: 2360 return true; 2361 } 2362 2363 return false; 2364 } 2365 2366 static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port, 2367 enum dsa_tag_protocol tag_protocol) 2368 { 2369 bool ret = b53_possible_cpu_port(ds, port); 2370 2371 if (!ret) { 2372 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n", 2373 port); 2374 return ret; 2375 } 2376 2377 switch (tag_protocol) { 2378 case DSA_TAG_PROTO_BRCM: 2379 case DSA_TAG_PROTO_BRCM_PREPEND: 2380 dev_warn(ds->dev, 2381 "Port %d is stacked to Broadcom tag switch\n", port); 2382 ret = false; 2383 break; 2384 default: 2385 ret = true; 2386 break; 2387 } 2388 2389 return ret; 2390 } 2391 2392 enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port, 2393 enum dsa_tag_protocol mprot) 2394 { 2395 struct b53_device *dev = ds->priv; 2396 2397 if (!b53_can_enable_brcm_tags(ds, port, mprot)) { 2398 dev->tag_protocol = DSA_TAG_PROTO_NONE; 2399 goto out; 2400 } 2401 2402 /* Older models require different 6 byte tags */ 2403 if (is5325(dev) || is5365(dev)) { 2404 dev->tag_protocol = DSA_TAG_PROTO_BRCM_LEGACY_FCS; 2405 goto out; 2406 } else if (is63xx(dev)) { 2407 dev->tag_protocol = DSA_TAG_PROTO_BRCM_LEGACY; 2408 goto out; 2409 } 2410 2411 /* Broadcom BCM58xx chips have a flow accelerator on Port 8 2412 * which requires us to use the prepended Broadcom tag type 2413 */ 2414 if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT) { 2415 dev->tag_protocol = DSA_TAG_PROTO_BRCM_PREPEND; 2416 goto out; 2417 } 2418 2419 dev->tag_protocol = DSA_TAG_PROTO_BRCM; 2420 out: 2421 return dev->tag_protocol; 2422 } 2423 EXPORT_SYMBOL(b53_get_tag_protocol); 2424 2425 int b53_mirror_add(struct dsa_switch *ds, int port, 2426 struct dsa_mall_mirror_tc_entry *mirror, bool ingress, 2427 struct netlink_ext_ack *extack) 2428 { 2429 struct b53_device *dev = ds->priv; 2430 u16 reg, loc; 2431 2432 if (ingress) 2433 loc = B53_IG_MIR_CTL; 2434 else 2435 loc = B53_EG_MIR_CTL; 2436 2437 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 2438 reg |= BIT(port); 2439 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 2440 2441 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 2442 reg &= ~CAP_PORT_MASK; 2443 reg |= mirror->to_local_port; 2444 reg |= MIRROR_EN; 2445 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 2446 2447 return 0; 2448 } 2449 EXPORT_SYMBOL(b53_mirror_add); 2450 2451 void b53_mirror_del(struct dsa_switch *ds, int port, 2452 struct dsa_mall_mirror_tc_entry *mirror) 2453 { 2454 struct b53_device *dev = ds->priv; 2455 bool loc_disable = false, other_loc_disable = false; 2456 u16 reg, loc; 2457 2458 if (mirror->ingress) 2459 loc = B53_IG_MIR_CTL; 2460 else 2461 loc = B53_EG_MIR_CTL; 2462 2463 /* Update the desired ingress/egress register */ 2464 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 2465 reg &= ~BIT(port); 2466 if (!(reg & MIRROR_MASK)) 2467 loc_disable = true; 2468 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 2469 2470 /* Now look at the other one to know if we can disable mirroring 2471 * entirely 2472 */ 2473 if (mirror->ingress) 2474 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, ®); 2475 else 2476 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, ®); 2477 if (!(reg & MIRROR_MASK)) 2478 other_loc_disable = true; 2479 2480 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 2481 /* Both no longer have ports, let's disable mirroring */ 2482 if (loc_disable && other_loc_disable) { 2483 reg &= ~MIRROR_EN; 2484 reg &= ~mirror->to_local_port; 2485 } 2486 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 2487 } 2488 EXPORT_SYMBOL(b53_mirror_del); 2489 2490 /* Returns 0 if EEE was not enabled, or 1 otherwise 2491 */ 2492 int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy) 2493 { 2494 int ret; 2495 2496 if (!b53_support_eee(ds, port)) 2497 return 0; 2498 2499 ret = phy_init_eee(phy, false); 2500 if (ret) 2501 return 0; 2502 2503 b53_eee_enable_set(ds, port, true); 2504 2505 return 1; 2506 } 2507 EXPORT_SYMBOL(b53_eee_init); 2508 2509 bool b53_support_eee(struct dsa_switch *ds, int port) 2510 { 2511 struct b53_device *dev = ds->priv; 2512 2513 return !is5325(dev) && !is5365(dev) && !is63xx(dev); 2514 } 2515 EXPORT_SYMBOL(b53_support_eee); 2516 2517 int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_keee *e) 2518 { 2519 struct b53_device *dev = ds->priv; 2520 struct ethtool_keee *p = &dev->ports[port].eee; 2521 2522 p->eee_enabled = e->eee_enabled; 2523 b53_eee_enable_set(ds, port, e->eee_enabled); 2524 2525 return 0; 2526 } 2527 EXPORT_SYMBOL(b53_set_mac_eee); 2528 2529 static int b53_change_mtu(struct dsa_switch *ds, int port, int mtu) 2530 { 2531 struct b53_device *dev = ds->priv; 2532 bool enable_jumbo; 2533 bool allow_10_100; 2534 2535 if (is5325(dev) || is5365(dev)) 2536 return 0; 2537 2538 if (!dsa_is_cpu_port(ds, port)) 2539 return 0; 2540 2541 enable_jumbo = (mtu > ETH_DATA_LEN); 2542 allow_10_100 = !is63xx(dev); 2543 2544 return b53_set_jumbo(dev, enable_jumbo, allow_10_100); 2545 } 2546 2547 static int b53_get_max_mtu(struct dsa_switch *ds, int port) 2548 { 2549 struct b53_device *dev = ds->priv; 2550 2551 if (is5325(dev) || is5365(dev)) 2552 return B53_MAX_MTU_25; 2553 2554 return B53_MAX_MTU; 2555 } 2556 2557 int b53_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 2558 { 2559 struct b53_device *dev = ds->priv; 2560 u32 atc; 2561 int reg; 2562 2563 if (is63xx(dev)) 2564 reg = B53_AGING_TIME_CONTROL_63XX; 2565 else 2566 reg = B53_AGING_TIME_CONTROL; 2567 2568 if (dev->chip_id == BCM53101_DEVICE_ID) 2569 atc = DIV_ROUND_CLOSEST(msecs, 500); 2570 else 2571 atc = DIV_ROUND_CLOSEST(msecs, 1000); 2572 2573 if (!is5325(dev) && !is5365(dev)) 2574 atc |= AGE_CHANGE; 2575 2576 b53_write32(dev, B53_MGMT_PAGE, reg, atc); 2577 2578 return 0; 2579 } 2580 EXPORT_SYMBOL_GPL(b53_set_ageing_time); 2581 2582 static const struct phylink_mac_ops b53_phylink_mac_ops = { 2583 .mac_select_pcs = b53_phylink_mac_select_pcs, 2584 .mac_config = b53_phylink_mac_config, 2585 .mac_link_down = b53_phylink_mac_link_down, 2586 .mac_link_up = b53_phylink_mac_link_up, 2587 }; 2588 2589 static const struct dsa_switch_ops b53_switch_ops = { 2590 .get_tag_protocol = b53_get_tag_protocol, 2591 .setup = b53_setup, 2592 .teardown = b53_teardown, 2593 .get_strings = b53_get_strings, 2594 .get_ethtool_stats = b53_get_ethtool_stats, 2595 .get_sset_count = b53_get_sset_count, 2596 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 2597 .phy_read = b53_phy_read16, 2598 .phy_write = b53_phy_write16, 2599 .phylink_get_caps = b53_phylink_get_caps, 2600 .port_setup = b53_setup_port, 2601 .port_enable = b53_enable_port, 2602 .port_disable = b53_disable_port, 2603 .support_eee = b53_support_eee, 2604 .set_mac_eee = b53_set_mac_eee, 2605 .set_ageing_time = b53_set_ageing_time, 2606 .port_bridge_join = b53_br_join, 2607 .port_bridge_leave = b53_br_leave, 2608 .port_pre_bridge_flags = b53_br_flags_pre, 2609 .port_bridge_flags = b53_br_flags, 2610 .port_stp_state_set = b53_br_set_stp_state, 2611 .port_fast_age = b53_br_fast_age, 2612 .port_vlan_filtering = b53_vlan_filtering, 2613 .port_vlan_add = b53_vlan_add, 2614 .port_vlan_del = b53_vlan_del, 2615 .port_fdb_dump = b53_fdb_dump, 2616 .port_fdb_add = b53_fdb_add, 2617 .port_fdb_del = b53_fdb_del, 2618 .port_mirror_add = b53_mirror_add, 2619 .port_mirror_del = b53_mirror_del, 2620 .port_mdb_add = b53_mdb_add, 2621 .port_mdb_del = b53_mdb_del, 2622 .port_max_mtu = b53_get_max_mtu, 2623 .port_change_mtu = b53_change_mtu, 2624 }; 2625 2626 struct b53_chip_data { 2627 u32 chip_id; 2628 const char *dev_name; 2629 u16 vlans; 2630 u16 enabled_ports; 2631 u8 imp_port; 2632 u8 cpu_port; 2633 u8 vta_regs[3]; 2634 u8 arl_bins; 2635 u16 arl_buckets; 2636 u8 duplex_reg; 2637 u8 jumbo_pm_reg; 2638 u8 jumbo_size_reg; 2639 }; 2640 2641 #define B53_VTA_REGS \ 2642 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY } 2643 #define B53_VTA_REGS_9798 \ 2644 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 } 2645 #define B53_VTA_REGS_63XX \ 2646 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX } 2647 2648 static const struct b53_chip_data b53_switch_chips[] = { 2649 { 2650 .chip_id = BCM5325_DEVICE_ID, 2651 .dev_name = "BCM5325", 2652 .vlans = 16, 2653 .enabled_ports = 0x3f, 2654 .arl_bins = 2, 2655 .arl_buckets = 1024, 2656 .imp_port = 5, 2657 .duplex_reg = B53_DUPLEX_STAT_FE, 2658 }, 2659 { 2660 .chip_id = BCM5365_DEVICE_ID, 2661 .dev_name = "BCM5365", 2662 .vlans = 256, 2663 .enabled_ports = 0x3f, 2664 .arl_bins = 2, 2665 .arl_buckets = 1024, 2666 .imp_port = 5, 2667 .duplex_reg = B53_DUPLEX_STAT_FE, 2668 }, 2669 { 2670 .chip_id = BCM5389_DEVICE_ID, 2671 .dev_name = "BCM5389", 2672 .vlans = 4096, 2673 .enabled_ports = 0x11f, 2674 .arl_bins = 4, 2675 .arl_buckets = 1024, 2676 .imp_port = 8, 2677 .vta_regs = B53_VTA_REGS, 2678 .duplex_reg = B53_DUPLEX_STAT_GE, 2679 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2680 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2681 }, 2682 { 2683 .chip_id = BCM5395_DEVICE_ID, 2684 .dev_name = "BCM5395", 2685 .vlans = 4096, 2686 .enabled_ports = 0x11f, 2687 .arl_bins = 4, 2688 .arl_buckets = 1024, 2689 .imp_port = 8, 2690 .vta_regs = B53_VTA_REGS, 2691 .duplex_reg = B53_DUPLEX_STAT_GE, 2692 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2693 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2694 }, 2695 { 2696 .chip_id = BCM5397_DEVICE_ID, 2697 .dev_name = "BCM5397", 2698 .vlans = 4096, 2699 .enabled_ports = 0x11f, 2700 .arl_bins = 4, 2701 .arl_buckets = 1024, 2702 .imp_port = 8, 2703 .vta_regs = B53_VTA_REGS_9798, 2704 .duplex_reg = B53_DUPLEX_STAT_GE, 2705 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2706 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2707 }, 2708 { 2709 .chip_id = BCM5398_DEVICE_ID, 2710 .dev_name = "BCM5398", 2711 .vlans = 4096, 2712 .enabled_ports = 0x17f, 2713 .arl_bins = 4, 2714 .arl_buckets = 1024, 2715 .imp_port = 8, 2716 .vta_regs = B53_VTA_REGS_9798, 2717 .duplex_reg = B53_DUPLEX_STAT_GE, 2718 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2719 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2720 }, 2721 { 2722 .chip_id = BCM53101_DEVICE_ID, 2723 .dev_name = "BCM53101", 2724 .vlans = 4096, 2725 .enabled_ports = 0x11f, 2726 .arl_bins = 4, 2727 .arl_buckets = 512, 2728 .vta_regs = B53_VTA_REGS, 2729 .imp_port = 8, 2730 .duplex_reg = B53_DUPLEX_STAT_GE, 2731 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2732 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2733 }, 2734 { 2735 .chip_id = BCM53115_DEVICE_ID, 2736 .dev_name = "BCM53115", 2737 .vlans = 4096, 2738 .enabled_ports = 0x11f, 2739 .arl_bins = 4, 2740 .arl_buckets = 1024, 2741 .vta_regs = B53_VTA_REGS, 2742 .imp_port = 8, 2743 .duplex_reg = B53_DUPLEX_STAT_GE, 2744 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2745 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2746 }, 2747 { 2748 .chip_id = BCM53125_DEVICE_ID, 2749 .dev_name = "BCM53125", 2750 .vlans = 4096, 2751 .enabled_ports = 0x1ff, 2752 .arl_bins = 4, 2753 .arl_buckets = 1024, 2754 .imp_port = 8, 2755 .vta_regs = B53_VTA_REGS, 2756 .duplex_reg = B53_DUPLEX_STAT_GE, 2757 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2758 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2759 }, 2760 { 2761 .chip_id = BCM53128_DEVICE_ID, 2762 .dev_name = "BCM53128", 2763 .vlans = 4096, 2764 .enabled_ports = 0x1ff, 2765 .arl_bins = 4, 2766 .arl_buckets = 1024, 2767 .imp_port = 8, 2768 .vta_regs = B53_VTA_REGS, 2769 .duplex_reg = B53_DUPLEX_STAT_GE, 2770 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2771 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2772 }, 2773 { 2774 .chip_id = BCM63XX_DEVICE_ID, 2775 .dev_name = "BCM63xx", 2776 .vlans = 4096, 2777 .enabled_ports = 0, /* pdata must provide them */ 2778 .arl_bins = 4, 2779 .arl_buckets = 1024, 2780 .imp_port = 8, 2781 .vta_regs = B53_VTA_REGS_63XX, 2782 .duplex_reg = B53_DUPLEX_STAT_63XX, 2783 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, 2784 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, 2785 }, 2786 { 2787 .chip_id = BCM53010_DEVICE_ID, 2788 .dev_name = "BCM53010", 2789 .vlans = 4096, 2790 .enabled_ports = 0x1bf, 2791 .arl_bins = 4, 2792 .arl_buckets = 1024, 2793 .imp_port = 8, 2794 .vta_regs = B53_VTA_REGS, 2795 .duplex_reg = B53_DUPLEX_STAT_GE, 2796 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2797 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2798 }, 2799 { 2800 .chip_id = BCM53011_DEVICE_ID, 2801 .dev_name = "BCM53011", 2802 .vlans = 4096, 2803 .enabled_ports = 0x1bf, 2804 .arl_bins = 4, 2805 .arl_buckets = 1024, 2806 .imp_port = 8, 2807 .vta_regs = B53_VTA_REGS, 2808 .duplex_reg = B53_DUPLEX_STAT_GE, 2809 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2810 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2811 }, 2812 { 2813 .chip_id = BCM53012_DEVICE_ID, 2814 .dev_name = "BCM53012", 2815 .vlans = 4096, 2816 .enabled_ports = 0x1bf, 2817 .arl_bins = 4, 2818 .arl_buckets = 1024, 2819 .imp_port = 8, 2820 .vta_regs = B53_VTA_REGS, 2821 .duplex_reg = B53_DUPLEX_STAT_GE, 2822 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2823 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2824 }, 2825 { 2826 .chip_id = BCM53018_DEVICE_ID, 2827 .dev_name = "BCM53018", 2828 .vlans = 4096, 2829 .enabled_ports = 0x1bf, 2830 .arl_bins = 4, 2831 .arl_buckets = 1024, 2832 .imp_port = 8, 2833 .vta_regs = B53_VTA_REGS, 2834 .duplex_reg = B53_DUPLEX_STAT_GE, 2835 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2836 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2837 }, 2838 { 2839 .chip_id = BCM53019_DEVICE_ID, 2840 .dev_name = "BCM53019", 2841 .vlans = 4096, 2842 .enabled_ports = 0x1bf, 2843 .arl_bins = 4, 2844 .arl_buckets = 1024, 2845 .imp_port = 8, 2846 .vta_regs = B53_VTA_REGS, 2847 .duplex_reg = B53_DUPLEX_STAT_GE, 2848 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2849 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2850 }, 2851 { 2852 .chip_id = BCM58XX_DEVICE_ID, 2853 .dev_name = "BCM585xx/586xx/88312", 2854 .vlans = 4096, 2855 .enabled_ports = 0x1ff, 2856 .arl_bins = 4, 2857 .arl_buckets = 1024, 2858 .imp_port = 8, 2859 .vta_regs = B53_VTA_REGS, 2860 .duplex_reg = B53_DUPLEX_STAT_GE, 2861 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2862 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2863 }, 2864 { 2865 .chip_id = BCM583XX_DEVICE_ID, 2866 .dev_name = "BCM583xx/11360", 2867 .vlans = 4096, 2868 .enabled_ports = 0x103, 2869 .arl_bins = 4, 2870 .arl_buckets = 1024, 2871 .imp_port = 8, 2872 .vta_regs = B53_VTA_REGS, 2873 .duplex_reg = B53_DUPLEX_STAT_GE, 2874 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2875 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2876 }, 2877 /* Starfighter 2 */ 2878 { 2879 .chip_id = BCM4908_DEVICE_ID, 2880 .dev_name = "BCM4908", 2881 .vlans = 4096, 2882 .enabled_ports = 0x1bf, 2883 .arl_bins = 4, 2884 .arl_buckets = 256, 2885 .imp_port = 8, 2886 .vta_regs = B53_VTA_REGS, 2887 .duplex_reg = B53_DUPLEX_STAT_GE, 2888 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2889 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2890 }, 2891 { 2892 .chip_id = BCM7445_DEVICE_ID, 2893 .dev_name = "BCM7445", 2894 .vlans = 4096, 2895 .enabled_ports = 0x1ff, 2896 .arl_bins = 4, 2897 .arl_buckets = 1024, 2898 .imp_port = 8, 2899 .vta_regs = B53_VTA_REGS, 2900 .duplex_reg = B53_DUPLEX_STAT_GE, 2901 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2902 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2903 }, 2904 { 2905 .chip_id = BCM7278_DEVICE_ID, 2906 .dev_name = "BCM7278", 2907 .vlans = 4096, 2908 .enabled_ports = 0x1ff, 2909 .arl_bins = 4, 2910 .arl_buckets = 256, 2911 .imp_port = 8, 2912 .vta_regs = B53_VTA_REGS, 2913 .duplex_reg = B53_DUPLEX_STAT_GE, 2914 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2915 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2916 }, 2917 { 2918 .chip_id = BCM53134_DEVICE_ID, 2919 .dev_name = "BCM53134", 2920 .vlans = 4096, 2921 .enabled_ports = 0x12f, 2922 .imp_port = 8, 2923 .cpu_port = B53_CPU_PORT, 2924 .vta_regs = B53_VTA_REGS, 2925 .arl_bins = 4, 2926 .arl_buckets = 1024, 2927 .duplex_reg = B53_DUPLEX_STAT_GE, 2928 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2929 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2930 }, 2931 }; 2932 2933 static int b53_switch_init(struct b53_device *dev) 2934 { 2935 u32 chip_id = dev->chip_id; 2936 unsigned int i; 2937 int ret; 2938 2939 if (is63xx(dev)) 2940 chip_id = BCM63XX_DEVICE_ID; 2941 2942 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) { 2943 const struct b53_chip_data *chip = &b53_switch_chips[i]; 2944 2945 if (chip->chip_id == chip_id) { 2946 if (!dev->enabled_ports) 2947 dev->enabled_ports = chip->enabled_ports; 2948 dev->name = chip->dev_name; 2949 dev->duplex_reg = chip->duplex_reg; 2950 dev->vta_regs[0] = chip->vta_regs[0]; 2951 dev->vta_regs[1] = chip->vta_regs[1]; 2952 dev->vta_regs[2] = chip->vta_regs[2]; 2953 dev->jumbo_pm_reg = chip->jumbo_pm_reg; 2954 dev->imp_port = chip->imp_port; 2955 dev->num_vlans = chip->vlans; 2956 dev->num_arl_bins = chip->arl_bins; 2957 dev->num_arl_buckets = chip->arl_buckets; 2958 break; 2959 } 2960 } 2961 2962 /* check which BCM5325x version we have */ 2963 if (is5325(dev)) { 2964 u8 vc4; 2965 2966 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 2967 2968 /* check reserved bits */ 2969 switch (vc4 & 3) { 2970 case 1: 2971 /* BCM5325E */ 2972 break; 2973 case 3: 2974 /* BCM5325F - do not use port 4 */ 2975 dev->enabled_ports &= ~BIT(4); 2976 break; 2977 default: 2978 /* On the BCM47XX SoCs this is the supported internal switch.*/ 2979 #ifndef CONFIG_BCM47XX 2980 /* BCM5325M */ 2981 return -EINVAL; 2982 #else 2983 break; 2984 #endif 2985 } 2986 } 2987 2988 if (is5325e(dev)) 2989 dev->num_arl_buckets = 512; 2990 2991 dev->num_ports = fls(dev->enabled_ports); 2992 2993 dev->ds->num_ports = min_t(unsigned int, dev->num_ports, DSA_MAX_PORTS); 2994 2995 /* Include non standard CPU port built-in PHYs to be probed */ 2996 if (is539x(dev) || is531x5(dev)) { 2997 for (i = 0; i < dev->num_ports; i++) { 2998 if (!(dev->ds->phys_mii_mask & BIT(i)) && 2999 !b53_possible_cpu_port(dev->ds, i)) 3000 dev->ds->phys_mii_mask |= BIT(i); 3001 } 3002 } 3003 3004 dev->ports = devm_kcalloc(dev->dev, 3005 dev->num_ports, sizeof(struct b53_port), 3006 GFP_KERNEL); 3007 if (!dev->ports) 3008 return -ENOMEM; 3009 3010 dev->vlans = devm_kcalloc(dev->dev, 3011 dev->num_vlans, sizeof(struct b53_vlan), 3012 GFP_KERNEL); 3013 if (!dev->vlans) 3014 return -ENOMEM; 3015 3016 dev->reset_gpio = b53_switch_get_reset_gpio(dev); 3017 if (dev->reset_gpio >= 0) { 3018 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio, 3019 GPIOF_OUT_INIT_HIGH, "robo_reset"); 3020 if (ret) 3021 return ret; 3022 } 3023 3024 return 0; 3025 } 3026 3027 struct b53_device *b53_switch_alloc(struct device *base, 3028 const struct b53_io_ops *ops, 3029 void *priv) 3030 { 3031 struct dsa_switch *ds; 3032 struct b53_device *dev; 3033 3034 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 3035 if (!ds) 3036 return NULL; 3037 3038 ds->dev = base; 3039 3040 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL); 3041 if (!dev) 3042 return NULL; 3043 3044 ds->priv = dev; 3045 dev->dev = base; 3046 3047 dev->ds = ds; 3048 dev->priv = priv; 3049 dev->ops = ops; 3050 ds->ops = &b53_switch_ops; 3051 ds->phylink_mac_ops = &b53_phylink_mac_ops; 3052 dev->vlan_enabled = true; 3053 dev->vlan_filtering = false; 3054 /* Let DSA handle the case were multiple bridges span the same switch 3055 * device and different VLAN awareness settings are requested, which 3056 * would be breaking filtering semantics for any of the other bridge 3057 * devices. (not hardware supported) 3058 */ 3059 ds->vlan_filtering_is_global = true; 3060 3061 mutex_init(&dev->reg_mutex); 3062 mutex_init(&dev->stats_mutex); 3063 mutex_init(&dev->arl_mutex); 3064 3065 return dev; 3066 } 3067 EXPORT_SYMBOL(b53_switch_alloc); 3068 3069 int b53_switch_detect(struct b53_device *dev) 3070 { 3071 u32 id32; 3072 u16 tmp; 3073 u8 id8; 3074 int ret; 3075 3076 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8); 3077 if (ret) 3078 return ret; 3079 3080 switch (id8) { 3081 case 0: 3082 /* BCM5325 and BCM5365 do not have this register so reads 3083 * return 0. But the read operation did succeed, so assume this 3084 * is one of them. 3085 * 3086 * Next check if we can write to the 5325's VTA register; for 3087 * 5365 it is read only. 3088 */ 3089 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf); 3090 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp); 3091 3092 if (tmp == 0xf) { 3093 u32 phy_id; 3094 int val; 3095 3096 dev->chip_id = BCM5325_DEVICE_ID; 3097 3098 val = b53_phy_read16(dev->ds, 0, MII_PHYSID1); 3099 phy_id = (val & 0xffff) << 16; 3100 val = b53_phy_read16(dev->ds, 0, MII_PHYSID2); 3101 phy_id |= (val & 0xfff0); 3102 3103 if (phy_id == 0x00406330) 3104 dev->variant_id = B53_VARIANT_5325M; 3105 else if (phy_id == 0x0143bc30) 3106 dev->variant_id = B53_VARIANT_5325E; 3107 } else { 3108 dev->chip_id = BCM5365_DEVICE_ID; 3109 } 3110 break; 3111 case BCM5389_DEVICE_ID: 3112 case BCM5395_DEVICE_ID: 3113 case BCM5397_DEVICE_ID: 3114 case BCM5398_DEVICE_ID: 3115 dev->chip_id = id8; 3116 break; 3117 default: 3118 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32); 3119 if (ret) 3120 return ret; 3121 3122 switch (id32) { 3123 case BCM53101_DEVICE_ID: 3124 case BCM53115_DEVICE_ID: 3125 case BCM53125_DEVICE_ID: 3126 case BCM53128_DEVICE_ID: 3127 case BCM53010_DEVICE_ID: 3128 case BCM53011_DEVICE_ID: 3129 case BCM53012_DEVICE_ID: 3130 case BCM53018_DEVICE_ID: 3131 case BCM53019_DEVICE_ID: 3132 case BCM53134_DEVICE_ID: 3133 dev->chip_id = id32; 3134 break; 3135 default: 3136 dev_err(dev->dev, 3137 "unsupported switch detected (BCM53%02x/BCM%x)\n", 3138 id8, id32); 3139 return -ENODEV; 3140 } 3141 } 3142 3143 if (dev->chip_id == BCM5325_DEVICE_ID) 3144 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25, 3145 &dev->core_rev); 3146 else 3147 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID, 3148 &dev->core_rev); 3149 } 3150 EXPORT_SYMBOL(b53_switch_detect); 3151 3152 int b53_switch_register(struct b53_device *dev) 3153 { 3154 int ret; 3155 3156 if (dev->pdata) { 3157 dev->chip_id = dev->pdata->chip_id; 3158 dev->enabled_ports = dev->pdata->enabled_ports; 3159 } 3160 3161 if (!dev->chip_id && b53_switch_detect(dev)) 3162 return -EINVAL; 3163 3164 ret = b53_switch_init(dev); 3165 if (ret) 3166 return ret; 3167 3168 dev_info(dev->dev, "found switch: %s, rev %i\n", 3169 dev->name, dev->core_rev); 3170 3171 return dsa_register_switch(dev->ds); 3172 } 3173 EXPORT_SYMBOL(b53_switch_register); 3174 3175 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>"); 3176 MODULE_DESCRIPTION("B53 switch library"); 3177 MODULE_LICENSE("Dual BSD/GPL"); 3178