1 /* 2 * B53 switch driver main logic 3 * 4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org> 5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com> 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21 22 #include <linux/delay.h> 23 #include <linux/export.h> 24 #include <linux/gpio.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/platform_data/b53.h> 28 #include <linux/phy.h> 29 #include <linux/etherdevice.h> 30 #include <linux/if_bridge.h> 31 #include <net/dsa.h> 32 33 #include "b53_regs.h" 34 #include "b53_priv.h" 35 36 struct b53_mib_desc { 37 u8 size; 38 u8 offset; 39 const char *name; 40 }; 41 42 /* BCM5365 MIB counters */ 43 static const struct b53_mib_desc b53_mibs_65[] = { 44 { 8, 0x00, "TxOctets" }, 45 { 4, 0x08, "TxDropPkts" }, 46 { 4, 0x10, "TxBroadcastPkts" }, 47 { 4, 0x14, "TxMulticastPkts" }, 48 { 4, 0x18, "TxUnicastPkts" }, 49 { 4, 0x1c, "TxCollisions" }, 50 { 4, 0x20, "TxSingleCollision" }, 51 { 4, 0x24, "TxMultipleCollision" }, 52 { 4, 0x28, "TxDeferredTransmit" }, 53 { 4, 0x2c, "TxLateCollision" }, 54 { 4, 0x30, "TxExcessiveCollision" }, 55 { 4, 0x38, "TxPausePkts" }, 56 { 8, 0x44, "RxOctets" }, 57 { 4, 0x4c, "RxUndersizePkts" }, 58 { 4, 0x50, "RxPausePkts" }, 59 { 4, 0x54, "Pkts64Octets" }, 60 { 4, 0x58, "Pkts65to127Octets" }, 61 { 4, 0x5c, "Pkts128to255Octets" }, 62 { 4, 0x60, "Pkts256to511Octets" }, 63 { 4, 0x64, "Pkts512to1023Octets" }, 64 { 4, 0x68, "Pkts1024to1522Octets" }, 65 { 4, 0x6c, "RxOversizePkts" }, 66 { 4, 0x70, "RxJabbers" }, 67 { 4, 0x74, "RxAlignmentErrors" }, 68 { 4, 0x78, "RxFCSErrors" }, 69 { 8, 0x7c, "RxGoodOctets" }, 70 { 4, 0x84, "RxDropPkts" }, 71 { 4, 0x88, "RxUnicastPkts" }, 72 { 4, 0x8c, "RxMulticastPkts" }, 73 { 4, 0x90, "RxBroadcastPkts" }, 74 { 4, 0x94, "RxSAChanges" }, 75 { 4, 0x98, "RxFragments" }, 76 }; 77 78 #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65) 79 80 /* BCM63xx MIB counters */ 81 static const struct b53_mib_desc b53_mibs_63xx[] = { 82 { 8, 0x00, "TxOctets" }, 83 { 4, 0x08, "TxDropPkts" }, 84 { 4, 0x0c, "TxQoSPkts" }, 85 { 4, 0x10, "TxBroadcastPkts" }, 86 { 4, 0x14, "TxMulticastPkts" }, 87 { 4, 0x18, "TxUnicastPkts" }, 88 { 4, 0x1c, "TxCollisions" }, 89 { 4, 0x20, "TxSingleCollision" }, 90 { 4, 0x24, "TxMultipleCollision" }, 91 { 4, 0x28, "TxDeferredTransmit" }, 92 { 4, 0x2c, "TxLateCollision" }, 93 { 4, 0x30, "TxExcessiveCollision" }, 94 { 4, 0x38, "TxPausePkts" }, 95 { 8, 0x3c, "TxQoSOctets" }, 96 { 8, 0x44, "RxOctets" }, 97 { 4, 0x4c, "RxUndersizePkts" }, 98 { 4, 0x50, "RxPausePkts" }, 99 { 4, 0x54, "Pkts64Octets" }, 100 { 4, 0x58, "Pkts65to127Octets" }, 101 { 4, 0x5c, "Pkts128to255Octets" }, 102 { 4, 0x60, "Pkts256to511Octets" }, 103 { 4, 0x64, "Pkts512to1023Octets" }, 104 { 4, 0x68, "Pkts1024to1522Octets" }, 105 { 4, 0x6c, "RxOversizePkts" }, 106 { 4, 0x70, "RxJabbers" }, 107 { 4, 0x74, "RxAlignmentErrors" }, 108 { 4, 0x78, "RxFCSErrors" }, 109 { 8, 0x7c, "RxGoodOctets" }, 110 { 4, 0x84, "RxDropPkts" }, 111 { 4, 0x88, "RxUnicastPkts" }, 112 { 4, 0x8c, "RxMulticastPkts" }, 113 { 4, 0x90, "RxBroadcastPkts" }, 114 { 4, 0x94, "RxSAChanges" }, 115 { 4, 0x98, "RxFragments" }, 116 { 4, 0xa0, "RxSymbolErrors" }, 117 { 4, 0xa4, "RxQoSPkts" }, 118 { 8, 0xa8, "RxQoSOctets" }, 119 { 4, 0xb0, "Pkts1523to2047Octets" }, 120 { 4, 0xb4, "Pkts2048to4095Octets" }, 121 { 4, 0xb8, "Pkts4096to8191Octets" }, 122 { 4, 0xbc, "Pkts8192to9728Octets" }, 123 { 4, 0xc0, "RxDiscarded" }, 124 }; 125 126 #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx) 127 128 /* MIB counters */ 129 static const struct b53_mib_desc b53_mibs[] = { 130 { 8, 0x00, "TxOctets" }, 131 { 4, 0x08, "TxDropPkts" }, 132 { 4, 0x10, "TxBroadcastPkts" }, 133 { 4, 0x14, "TxMulticastPkts" }, 134 { 4, 0x18, "TxUnicastPkts" }, 135 { 4, 0x1c, "TxCollisions" }, 136 { 4, 0x20, "TxSingleCollision" }, 137 { 4, 0x24, "TxMultipleCollision" }, 138 { 4, 0x28, "TxDeferredTransmit" }, 139 { 4, 0x2c, "TxLateCollision" }, 140 { 4, 0x30, "TxExcessiveCollision" }, 141 { 4, 0x38, "TxPausePkts" }, 142 { 8, 0x50, "RxOctets" }, 143 { 4, 0x58, "RxUndersizePkts" }, 144 { 4, 0x5c, "RxPausePkts" }, 145 { 4, 0x60, "Pkts64Octets" }, 146 { 4, 0x64, "Pkts65to127Octets" }, 147 { 4, 0x68, "Pkts128to255Octets" }, 148 { 4, 0x6c, "Pkts256to511Octets" }, 149 { 4, 0x70, "Pkts512to1023Octets" }, 150 { 4, 0x74, "Pkts1024to1522Octets" }, 151 { 4, 0x78, "RxOversizePkts" }, 152 { 4, 0x7c, "RxJabbers" }, 153 { 4, 0x80, "RxAlignmentErrors" }, 154 { 4, 0x84, "RxFCSErrors" }, 155 { 8, 0x88, "RxGoodOctets" }, 156 { 4, 0x90, "RxDropPkts" }, 157 { 4, 0x94, "RxUnicastPkts" }, 158 { 4, 0x98, "RxMulticastPkts" }, 159 { 4, 0x9c, "RxBroadcastPkts" }, 160 { 4, 0xa0, "RxSAChanges" }, 161 { 4, 0xa4, "RxFragments" }, 162 { 4, 0xa8, "RxJumboPkts" }, 163 { 4, 0xac, "RxSymbolErrors" }, 164 { 4, 0xc0, "RxDiscarded" }, 165 }; 166 167 #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs) 168 169 static const struct b53_mib_desc b53_mibs_58xx[] = { 170 { 8, 0x00, "TxOctets" }, 171 { 4, 0x08, "TxDropPkts" }, 172 { 4, 0x0c, "TxQPKTQ0" }, 173 { 4, 0x10, "TxBroadcastPkts" }, 174 { 4, 0x14, "TxMulticastPkts" }, 175 { 4, 0x18, "TxUnicastPKts" }, 176 { 4, 0x1c, "TxCollisions" }, 177 { 4, 0x20, "TxSingleCollision" }, 178 { 4, 0x24, "TxMultipleCollision" }, 179 { 4, 0x28, "TxDeferredCollision" }, 180 { 4, 0x2c, "TxLateCollision" }, 181 { 4, 0x30, "TxExcessiveCollision" }, 182 { 4, 0x34, "TxFrameInDisc" }, 183 { 4, 0x38, "TxPausePkts" }, 184 { 4, 0x3c, "TxQPKTQ1" }, 185 { 4, 0x40, "TxQPKTQ2" }, 186 { 4, 0x44, "TxQPKTQ3" }, 187 { 4, 0x48, "TxQPKTQ4" }, 188 { 4, 0x4c, "TxQPKTQ5" }, 189 { 8, 0x50, "RxOctets" }, 190 { 4, 0x58, "RxUndersizePkts" }, 191 { 4, 0x5c, "RxPausePkts" }, 192 { 4, 0x60, "RxPkts64Octets" }, 193 { 4, 0x64, "RxPkts65to127Octets" }, 194 { 4, 0x68, "RxPkts128to255Octets" }, 195 { 4, 0x6c, "RxPkts256to511Octets" }, 196 { 4, 0x70, "RxPkts512to1023Octets" }, 197 { 4, 0x74, "RxPkts1024toMaxPktsOctets" }, 198 { 4, 0x78, "RxOversizePkts" }, 199 { 4, 0x7c, "RxJabbers" }, 200 { 4, 0x80, "RxAlignmentErrors" }, 201 { 4, 0x84, "RxFCSErrors" }, 202 { 8, 0x88, "RxGoodOctets" }, 203 { 4, 0x90, "RxDropPkts" }, 204 { 4, 0x94, "RxUnicastPkts" }, 205 { 4, 0x98, "RxMulticastPkts" }, 206 { 4, 0x9c, "RxBroadcastPkts" }, 207 { 4, 0xa0, "RxSAChanges" }, 208 { 4, 0xa4, "RxFragments" }, 209 { 4, 0xa8, "RxJumboPkt" }, 210 { 4, 0xac, "RxSymblErr" }, 211 { 4, 0xb0, "InRangeErrCount" }, 212 { 4, 0xb4, "OutRangeErrCount" }, 213 { 4, 0xb8, "EEELpiEvent" }, 214 { 4, 0xbc, "EEELpiDuration" }, 215 { 4, 0xc0, "RxDiscard" }, 216 { 4, 0xc8, "TxQPKTQ6" }, 217 { 4, 0xcc, "TxQPKTQ7" }, 218 { 4, 0xd0, "TxPkts64Octets" }, 219 { 4, 0xd4, "TxPkts65to127Octets" }, 220 { 4, 0xd8, "TxPkts128to255Octets" }, 221 { 4, 0xdc, "TxPkts256to511Ocets" }, 222 { 4, 0xe0, "TxPkts512to1023Ocets" }, 223 { 4, 0xe4, "TxPkts1024toMaxPktOcets" }, 224 }; 225 226 #define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx) 227 228 static int b53_do_vlan_op(struct b53_device *dev, u8 op) 229 { 230 unsigned int i; 231 232 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op); 233 234 for (i = 0; i < 10; i++) { 235 u8 vta; 236 237 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta); 238 if (!(vta & VTA_START_CMD)) 239 return 0; 240 241 usleep_range(100, 200); 242 } 243 244 return -EIO; 245 } 246 247 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, 248 struct b53_vlan *vlan) 249 { 250 if (is5325(dev)) { 251 u32 entry = 0; 252 253 if (vlan->members) { 254 entry = ((vlan->untag & VA_UNTAG_MASK_25) << 255 VA_UNTAG_S_25) | vlan->members; 256 if (dev->core_rev >= 3) 257 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S; 258 else 259 entry |= VA_VALID_25; 260 } 261 262 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry); 263 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 264 VTA_RW_STATE_WR | VTA_RW_OP_EN); 265 } else if (is5365(dev)) { 266 u16 entry = 0; 267 268 if (vlan->members) 269 entry = ((vlan->untag & VA_UNTAG_MASK_65) << 270 VA_UNTAG_S_65) | vlan->members | VA_VALID_65; 271 272 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry); 273 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 274 VTA_RW_STATE_WR | VTA_RW_OP_EN); 275 } else { 276 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 277 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], 278 (vlan->untag << VTE_UNTAG_S) | vlan->members); 279 280 b53_do_vlan_op(dev, VTA_CMD_WRITE); 281 } 282 283 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n", 284 vid, vlan->members, vlan->untag); 285 } 286 287 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid, 288 struct b53_vlan *vlan) 289 { 290 if (is5325(dev)) { 291 u32 entry = 0; 292 293 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 294 VTA_RW_STATE_RD | VTA_RW_OP_EN); 295 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry); 296 297 if (dev->core_rev >= 3) 298 vlan->valid = !!(entry & VA_VALID_25_R4); 299 else 300 vlan->valid = !!(entry & VA_VALID_25); 301 vlan->members = entry & VA_MEMBER_MASK; 302 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25; 303 304 } else if (is5365(dev)) { 305 u16 entry = 0; 306 307 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 308 VTA_RW_STATE_WR | VTA_RW_OP_EN); 309 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry); 310 311 vlan->valid = !!(entry & VA_VALID_65); 312 vlan->members = entry & VA_MEMBER_MASK; 313 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65; 314 } else { 315 u32 entry = 0; 316 317 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 318 b53_do_vlan_op(dev, VTA_CMD_READ); 319 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry); 320 vlan->members = entry & VTE_MEMBERS; 321 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS; 322 vlan->valid = true; 323 } 324 } 325 326 static void b53_set_forwarding(struct b53_device *dev, int enable) 327 { 328 struct dsa_switch *ds = dev->ds; 329 u8 mgmt; 330 331 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 332 333 if (enable) 334 mgmt |= SM_SW_FWD_EN; 335 else 336 mgmt &= ~SM_SW_FWD_EN; 337 338 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 339 340 /* Include IMP port in dumb forwarding mode when no tagging protocol is 341 * set 342 */ 343 if (ds->ops->get_tag_protocol(ds) == DSA_TAG_PROTO_NONE) { 344 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt); 345 mgmt |= B53_MII_DUMB_FWDG_EN; 346 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt); 347 } 348 } 349 350 static void b53_enable_vlan(struct b53_device *dev, bool enable) 351 { 352 u8 mgmt, vc0, vc1, vc4 = 0, vc5; 353 354 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 355 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0); 356 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1); 357 358 if (is5325(dev) || is5365(dev)) { 359 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 360 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5); 361 } else if (is63xx(dev)) { 362 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4); 363 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5); 364 } else { 365 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4); 366 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5); 367 } 368 369 mgmt &= ~SM_SW_FWD_MODE; 370 371 if (enable) { 372 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID; 373 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN; 374 vc4 &= ~VC4_ING_VID_CHECK_MASK; 375 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S; 376 vc5 |= VC5_DROP_VTABLE_MISS; 377 378 if (is5325(dev)) 379 vc0 &= ~VC0_RESERVED_1; 380 381 if (is5325(dev) || is5365(dev)) 382 vc1 |= VC1_RX_MCST_TAG_EN; 383 384 } else { 385 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID); 386 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN); 387 vc4 &= ~VC4_ING_VID_CHECK_MASK; 388 vc5 &= ~VC5_DROP_VTABLE_MISS; 389 390 if (is5325(dev) || is5365(dev)) 391 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 392 else 393 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S; 394 395 if (is5325(dev) || is5365(dev)) 396 vc1 &= ~VC1_RX_MCST_TAG_EN; 397 } 398 399 if (!is5325(dev) && !is5365(dev)) 400 vc5 &= ~VC5_VID_FFF_EN; 401 402 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0); 403 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1); 404 405 if (is5325(dev) || is5365(dev)) { 406 /* enable the high 8 bit vid check on 5325 */ 407 if (is5325(dev) && enable) 408 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 409 VC3_HIGH_8BIT_EN); 410 else 411 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 412 413 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4); 414 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5); 415 } else if (is63xx(dev)) { 416 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0); 417 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4); 418 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5); 419 } else { 420 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 421 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4); 422 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5); 423 } 424 425 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 426 } 427 428 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100) 429 { 430 u32 port_mask = 0; 431 u16 max_size = JMS_MIN_SIZE; 432 433 if (is5325(dev) || is5365(dev)) 434 return -EINVAL; 435 436 if (enable) { 437 port_mask = dev->enabled_ports; 438 max_size = JMS_MAX_SIZE; 439 if (allow_10_100) 440 port_mask |= JPM_10_100_JUMBO_EN; 441 } 442 443 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask); 444 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size); 445 } 446 447 static int b53_flush_arl(struct b53_device *dev, u8 mask) 448 { 449 unsigned int i; 450 451 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 452 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask); 453 454 for (i = 0; i < 10; i++) { 455 u8 fast_age_ctrl; 456 457 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 458 &fast_age_ctrl); 459 460 if (!(fast_age_ctrl & FAST_AGE_DONE)) 461 goto out; 462 463 msleep(1); 464 } 465 466 return -ETIMEDOUT; 467 out: 468 /* Only age dynamic entries (default behavior) */ 469 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC); 470 return 0; 471 } 472 473 static int b53_fast_age_port(struct b53_device *dev, int port) 474 { 475 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port); 476 477 return b53_flush_arl(dev, FAST_AGE_PORT); 478 } 479 480 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid) 481 { 482 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid); 483 484 return b53_flush_arl(dev, FAST_AGE_VLAN); 485 } 486 487 void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port) 488 { 489 struct b53_device *dev = ds->priv; 490 unsigned int i; 491 u16 pvlan; 492 493 /* Enable the IMP port to be in the same VLAN as the other ports 494 * on a per-port basis such that we only have Port i and IMP in 495 * the same VLAN. 496 */ 497 b53_for_each_port(dev, i) { 498 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan); 499 pvlan |= BIT(cpu_port); 500 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan); 501 } 502 } 503 EXPORT_SYMBOL(b53_imp_vlan_setup); 504 505 int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy) 506 { 507 struct b53_device *dev = ds->priv; 508 unsigned int cpu_port = dev->cpu_port; 509 u16 pvlan; 510 511 /* Clear the Rx and Tx disable bits and set to no spanning tree */ 512 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0); 513 514 /* Set this port, and only this one to be in the default VLAN, 515 * if member of a bridge, restore its membership prior to 516 * bringing down this port. 517 */ 518 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 519 pvlan &= ~0x1ff; 520 pvlan |= BIT(port); 521 pvlan |= dev->ports[port].vlan_ctl_mask; 522 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 523 524 b53_imp_vlan_setup(ds, cpu_port); 525 526 /* If EEE was enabled, restore it */ 527 if (dev->ports[port].eee.eee_enabled) 528 b53_eee_enable_set(ds, port, true); 529 530 return 0; 531 } 532 EXPORT_SYMBOL(b53_enable_port); 533 534 void b53_disable_port(struct dsa_switch *ds, int port, struct phy_device *phy) 535 { 536 struct b53_device *dev = ds->priv; 537 u8 reg; 538 539 /* Disable Tx/Rx for the port */ 540 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 541 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE; 542 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 543 } 544 EXPORT_SYMBOL(b53_disable_port); 545 546 void b53_brcm_hdr_setup(struct dsa_switch *ds, int port) 547 { 548 struct b53_device *dev = ds->priv; 549 u8 hdr_ctl, val; 550 u16 reg; 551 552 /* Resolve which bit controls the Broadcom tag */ 553 switch (port) { 554 case 8: 555 val = BRCM_HDR_P8_EN; 556 break; 557 case 7: 558 val = BRCM_HDR_P7_EN; 559 break; 560 case 5: 561 val = BRCM_HDR_P5_EN; 562 break; 563 default: 564 val = 0; 565 break; 566 } 567 568 /* Enable Broadcom tags for IMP port */ 569 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl); 570 hdr_ctl |= val; 571 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl); 572 573 /* Registers below are only accessible on newer devices */ 574 if (!is58xx(dev)) 575 return; 576 577 /* Enable reception Broadcom tag for CPU TX (switch RX) to 578 * allow us to tag outgoing frames 579 */ 580 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, ®); 581 reg &= ~BIT(port); 582 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg); 583 584 /* Enable transmission of Broadcom tags from the switch (CPU RX) to 585 * allow delivering frames to the per-port net_devices 586 */ 587 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, ®); 588 reg &= ~BIT(port); 589 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg); 590 } 591 EXPORT_SYMBOL(b53_brcm_hdr_setup); 592 593 static void b53_enable_cpu_port(struct b53_device *dev, int port) 594 { 595 u8 port_ctrl; 596 597 /* BCM5325 CPU port is at 8 */ 598 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25) 599 port = B53_CPU_PORT; 600 601 port_ctrl = PORT_CTRL_RX_BCST_EN | 602 PORT_CTRL_RX_MCST_EN | 603 PORT_CTRL_RX_UCST_EN; 604 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl); 605 } 606 607 static void b53_enable_mib(struct b53_device *dev) 608 { 609 u8 gc; 610 611 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 612 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN); 613 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc); 614 } 615 616 int b53_configure_vlan(struct dsa_switch *ds) 617 { 618 struct b53_device *dev = ds->priv; 619 struct b53_vlan vl = { 0 }; 620 int i; 621 622 /* clear all vlan entries */ 623 if (is5325(dev) || is5365(dev)) { 624 for (i = 1; i < dev->num_vlans; i++) 625 b53_set_vlan_entry(dev, i, &vl); 626 } else { 627 b53_do_vlan_op(dev, VTA_CMD_CLEAR); 628 } 629 630 b53_enable_vlan(dev, false); 631 632 b53_for_each_port(dev, i) 633 b53_write16(dev, B53_VLAN_PAGE, 634 B53_VLAN_PORT_DEF_TAG(i), 1); 635 636 if (!is5325(dev) && !is5365(dev)) 637 b53_set_jumbo(dev, dev->enable_jumbo, false); 638 639 return 0; 640 } 641 EXPORT_SYMBOL(b53_configure_vlan); 642 643 static void b53_switch_reset_gpio(struct b53_device *dev) 644 { 645 int gpio = dev->reset_gpio; 646 647 if (gpio < 0) 648 return; 649 650 /* Reset sequence: RESET low(50ms)->high(20ms) 651 */ 652 gpio_set_value(gpio, 0); 653 mdelay(50); 654 655 gpio_set_value(gpio, 1); 656 mdelay(20); 657 658 dev->current_page = 0xff; 659 } 660 661 static int b53_switch_reset(struct b53_device *dev) 662 { 663 unsigned int timeout = 1000; 664 u8 mgmt, reg; 665 666 b53_switch_reset_gpio(dev); 667 668 if (is539x(dev)) { 669 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83); 670 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00); 671 } 672 673 /* This is specific to 58xx devices here, do not use is58xx() which 674 * covers the larger Starfigther 2 family, including 7445/7278 which 675 * still use this driver as a library and need to perform the reset 676 * earlier. 677 */ 678 if (dev->chip_id == BCM58XX_DEVICE_ID) { 679 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 680 reg |= SW_RST | EN_SW_RST | EN_CH_RST; 681 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg); 682 683 do { 684 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 685 if (!(reg & SW_RST)) 686 break; 687 688 usleep_range(1000, 2000); 689 } while (timeout-- > 0); 690 691 if (timeout == 0) 692 return -ETIMEDOUT; 693 } 694 695 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 696 697 if (!(mgmt & SM_SW_FWD_EN)) { 698 mgmt &= ~SM_SW_FWD_MODE; 699 mgmt |= SM_SW_FWD_EN; 700 701 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 702 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 703 704 if (!(mgmt & SM_SW_FWD_EN)) { 705 dev_err(dev->dev, "Failed to enable switch!\n"); 706 return -EINVAL; 707 } 708 } 709 710 b53_enable_mib(dev); 711 712 return b53_flush_arl(dev, FAST_AGE_STATIC); 713 } 714 715 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg) 716 { 717 struct b53_device *priv = ds->priv; 718 u16 value = 0; 719 int ret; 720 721 if (priv->ops->phy_read16) 722 ret = priv->ops->phy_read16(priv, addr, reg, &value); 723 else 724 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr), 725 reg * 2, &value); 726 727 return ret ? ret : value; 728 } 729 730 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 731 { 732 struct b53_device *priv = ds->priv; 733 734 if (priv->ops->phy_write16) 735 return priv->ops->phy_write16(priv, addr, reg, val); 736 737 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val); 738 } 739 740 static int b53_reset_switch(struct b53_device *priv) 741 { 742 /* reset vlans */ 743 priv->enable_jumbo = false; 744 745 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans); 746 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports); 747 748 return b53_switch_reset(priv); 749 } 750 751 static int b53_apply_config(struct b53_device *priv) 752 { 753 /* disable switching */ 754 b53_set_forwarding(priv, 0); 755 756 b53_configure_vlan(priv->ds); 757 758 /* enable switching */ 759 b53_set_forwarding(priv, 1); 760 761 return 0; 762 } 763 764 static void b53_reset_mib(struct b53_device *priv) 765 { 766 u8 gc; 767 768 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 769 770 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB); 771 msleep(1); 772 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB); 773 msleep(1); 774 } 775 776 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev) 777 { 778 if (is5365(dev)) 779 return b53_mibs_65; 780 else if (is63xx(dev)) 781 return b53_mibs_63xx; 782 else if (is58xx(dev)) 783 return b53_mibs_58xx; 784 else 785 return b53_mibs; 786 } 787 788 static unsigned int b53_get_mib_size(struct b53_device *dev) 789 { 790 if (is5365(dev)) 791 return B53_MIBS_65_SIZE; 792 else if (is63xx(dev)) 793 return B53_MIBS_63XX_SIZE; 794 else if (is58xx(dev)) 795 return B53_MIBS_58XX_SIZE; 796 else 797 return B53_MIBS_SIZE; 798 } 799 800 void b53_get_strings(struct dsa_switch *ds, int port, uint8_t *data) 801 { 802 struct b53_device *dev = ds->priv; 803 const struct b53_mib_desc *mibs = b53_get_mib(dev); 804 unsigned int mib_size = b53_get_mib_size(dev); 805 unsigned int i; 806 807 for (i = 0; i < mib_size; i++) 808 memcpy(data + i * ETH_GSTRING_LEN, 809 mibs[i].name, ETH_GSTRING_LEN); 810 } 811 EXPORT_SYMBOL(b53_get_strings); 812 813 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) 814 { 815 struct b53_device *dev = ds->priv; 816 const struct b53_mib_desc *mibs = b53_get_mib(dev); 817 unsigned int mib_size = b53_get_mib_size(dev); 818 const struct b53_mib_desc *s; 819 unsigned int i; 820 u64 val = 0; 821 822 if (is5365(dev) && port == 5) 823 port = 8; 824 825 mutex_lock(&dev->stats_mutex); 826 827 for (i = 0; i < mib_size; i++) { 828 s = &mibs[i]; 829 830 if (s->size == 8) { 831 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val); 832 } else { 833 u32 val32; 834 835 b53_read32(dev, B53_MIB_PAGE(port), s->offset, 836 &val32); 837 val = val32; 838 } 839 data[i] = (u64)val; 840 } 841 842 mutex_unlock(&dev->stats_mutex); 843 } 844 EXPORT_SYMBOL(b53_get_ethtool_stats); 845 846 int b53_get_sset_count(struct dsa_switch *ds) 847 { 848 struct b53_device *dev = ds->priv; 849 850 return b53_get_mib_size(dev); 851 } 852 EXPORT_SYMBOL(b53_get_sset_count); 853 854 static int b53_setup(struct dsa_switch *ds) 855 { 856 struct b53_device *dev = ds->priv; 857 unsigned int port; 858 int ret; 859 860 ret = b53_reset_switch(dev); 861 if (ret) { 862 dev_err(ds->dev, "failed to reset switch\n"); 863 return ret; 864 } 865 866 b53_reset_mib(dev); 867 868 ret = b53_apply_config(dev); 869 if (ret) 870 dev_err(ds->dev, "failed to apply configuration\n"); 871 872 /* Configure IMP/CPU port, disable unused ports. Enabled 873 * ports will be configured with .port_enable 874 */ 875 for (port = 0; port < dev->num_ports; port++) { 876 if (dsa_is_cpu_port(ds, port)) 877 b53_enable_cpu_port(dev, port); 878 else if (dsa_is_unused_port(ds, port)) 879 b53_disable_port(ds, port, NULL); 880 } 881 882 return ret; 883 } 884 885 static void b53_adjust_link(struct dsa_switch *ds, int port, 886 struct phy_device *phydev) 887 { 888 struct b53_device *dev = ds->priv; 889 struct ethtool_eee *p = &dev->ports[port].eee; 890 u8 rgmii_ctrl = 0, reg = 0, off; 891 892 if (!phy_is_pseudo_fixed_link(phydev)) 893 return; 894 895 /* Override the port settings */ 896 if (port == dev->cpu_port) { 897 off = B53_PORT_OVERRIDE_CTRL; 898 reg = PORT_OVERRIDE_EN; 899 } else { 900 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 901 reg = GMII_PO_EN; 902 } 903 904 /* Set the link UP */ 905 if (phydev->link) 906 reg |= PORT_OVERRIDE_LINK; 907 908 if (phydev->duplex == DUPLEX_FULL) 909 reg |= PORT_OVERRIDE_FULL_DUPLEX; 910 911 switch (phydev->speed) { 912 case 2000: 913 reg |= PORT_OVERRIDE_SPEED_2000M; 914 /* fallthrough */ 915 case SPEED_1000: 916 reg |= PORT_OVERRIDE_SPEED_1000M; 917 break; 918 case SPEED_100: 919 reg |= PORT_OVERRIDE_SPEED_100M; 920 break; 921 case SPEED_10: 922 reg |= PORT_OVERRIDE_SPEED_10M; 923 break; 924 default: 925 dev_err(ds->dev, "unknown speed: %d\n", phydev->speed); 926 return; 927 } 928 929 /* Enable flow control on BCM5301x's CPU port */ 930 if (is5301x(dev) && port == dev->cpu_port) 931 reg |= PORT_OVERRIDE_RX_FLOW | PORT_OVERRIDE_TX_FLOW; 932 933 if (phydev->pause) { 934 if (phydev->asym_pause) 935 reg |= PORT_OVERRIDE_TX_FLOW; 936 reg |= PORT_OVERRIDE_RX_FLOW; 937 } 938 939 b53_write8(dev, B53_CTRL_PAGE, off, reg); 940 941 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) { 942 if (port == 8) 943 off = B53_RGMII_CTRL_IMP; 944 else 945 off = B53_RGMII_CTRL_P(port); 946 947 /* Configure the port RGMII clock delay by DLL disabled and 948 * tx_clk aligned timing (restoring to reset defaults) 949 */ 950 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl); 951 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC | 952 RGMII_CTRL_TIMING_SEL); 953 954 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make 955 * sure that we enable the port TX clock internal delay to 956 * account for this internal delay that is inserted, otherwise 957 * the switch won't be able to receive correctly. 958 * 959 * PHY_INTERFACE_MODE_RGMII means that we are not introducing 960 * any delay neither on transmission nor reception, so the 961 * BCM53125 must also be configured accordingly to account for 962 * the lack of delay and introduce 963 * 964 * The BCM53125 switch has its RX clock and TX clock control 965 * swapped, hence the reason why we modify the TX clock path in 966 * the "RGMII" case 967 */ 968 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 969 rgmii_ctrl |= RGMII_CTRL_DLL_TXC; 970 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) 971 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC; 972 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL; 973 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl); 974 975 dev_info(ds->dev, "Configured port %d for %s\n", port, 976 phy_modes(phydev->interface)); 977 } 978 979 /* configure MII port if necessary */ 980 if (is5325(dev)) { 981 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 982 ®); 983 984 /* reverse mii needs to be enabled */ 985 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 986 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 987 reg | PORT_OVERRIDE_RV_MII_25); 988 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 989 ®); 990 991 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 992 dev_err(ds->dev, 993 "Failed to enable reverse MII mode\n"); 994 return; 995 } 996 } 997 } else if (is5301x(dev)) { 998 if (port != dev->cpu_port) { 999 u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(dev->cpu_port); 1000 u8 gmii_po; 1001 1002 b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po); 1003 gmii_po |= GMII_PO_LINK | 1004 GMII_PO_RX_FLOW | 1005 GMII_PO_TX_FLOW | 1006 GMII_PO_EN | 1007 GMII_PO_SPEED_2000M; 1008 b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po); 1009 } 1010 } 1011 1012 /* Re-negotiate EEE if it was enabled already */ 1013 p->eee_enabled = b53_eee_init(ds, port, phydev); 1014 } 1015 1016 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering) 1017 { 1018 return 0; 1019 } 1020 EXPORT_SYMBOL(b53_vlan_filtering); 1021 1022 int b53_vlan_prepare(struct dsa_switch *ds, int port, 1023 const struct switchdev_obj_port_vlan *vlan, 1024 struct switchdev_trans *trans) 1025 { 1026 struct b53_device *dev = ds->priv; 1027 1028 if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0) 1029 return -EOPNOTSUPP; 1030 1031 if (vlan->vid_end > dev->num_vlans) 1032 return -ERANGE; 1033 1034 b53_enable_vlan(dev, true); 1035 1036 return 0; 1037 } 1038 EXPORT_SYMBOL(b53_vlan_prepare); 1039 1040 void b53_vlan_add(struct dsa_switch *ds, int port, 1041 const struct switchdev_obj_port_vlan *vlan, 1042 struct switchdev_trans *trans) 1043 { 1044 struct b53_device *dev = ds->priv; 1045 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1046 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1047 unsigned int cpu_port = dev->cpu_port; 1048 struct b53_vlan *vl; 1049 u16 vid; 1050 1051 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1052 vl = &dev->vlans[vid]; 1053 1054 b53_get_vlan_entry(dev, vid, vl); 1055 1056 vl->members |= BIT(port) | BIT(cpu_port); 1057 if (untagged) 1058 vl->untag |= BIT(port); 1059 else 1060 vl->untag &= ~BIT(port); 1061 vl->untag &= ~BIT(cpu_port); 1062 1063 b53_set_vlan_entry(dev, vid, vl); 1064 b53_fast_age_vlan(dev, vid); 1065 } 1066 1067 if (pvid) { 1068 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), 1069 vlan->vid_end); 1070 b53_fast_age_vlan(dev, vid); 1071 } 1072 } 1073 EXPORT_SYMBOL(b53_vlan_add); 1074 1075 int b53_vlan_del(struct dsa_switch *ds, int port, 1076 const struct switchdev_obj_port_vlan *vlan) 1077 { 1078 struct b53_device *dev = ds->priv; 1079 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1080 struct b53_vlan *vl; 1081 u16 vid; 1082 u16 pvid; 1083 1084 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid); 1085 1086 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1087 vl = &dev->vlans[vid]; 1088 1089 b53_get_vlan_entry(dev, vid, vl); 1090 1091 vl->members &= ~BIT(port); 1092 1093 if (pvid == vid) { 1094 if (is5325(dev) || is5365(dev)) 1095 pvid = 1; 1096 else 1097 pvid = 0; 1098 } 1099 1100 if (untagged) 1101 vl->untag &= ~(BIT(port)); 1102 1103 b53_set_vlan_entry(dev, vid, vl); 1104 b53_fast_age_vlan(dev, vid); 1105 } 1106 1107 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid); 1108 b53_fast_age_vlan(dev, pvid); 1109 1110 return 0; 1111 } 1112 EXPORT_SYMBOL(b53_vlan_del); 1113 1114 /* Address Resolution Logic routines */ 1115 static int b53_arl_op_wait(struct b53_device *dev) 1116 { 1117 unsigned int timeout = 10; 1118 u8 reg; 1119 1120 do { 1121 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1122 if (!(reg & ARLTBL_START_DONE)) 1123 return 0; 1124 1125 usleep_range(1000, 2000); 1126 } while (timeout--); 1127 1128 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg); 1129 1130 return -ETIMEDOUT; 1131 } 1132 1133 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op) 1134 { 1135 u8 reg; 1136 1137 if (op > ARLTBL_RW) 1138 return -EINVAL; 1139 1140 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1141 reg |= ARLTBL_START_DONE; 1142 if (op) 1143 reg |= ARLTBL_RW; 1144 else 1145 reg &= ~ARLTBL_RW; 1146 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg); 1147 1148 return b53_arl_op_wait(dev); 1149 } 1150 1151 static int b53_arl_read(struct b53_device *dev, u64 mac, 1152 u16 vid, struct b53_arl_entry *ent, u8 *idx, 1153 bool is_valid) 1154 { 1155 unsigned int i; 1156 int ret; 1157 1158 ret = b53_arl_op_wait(dev); 1159 if (ret) 1160 return ret; 1161 1162 /* Read the bins */ 1163 for (i = 0; i < dev->num_arl_entries; i++) { 1164 u64 mac_vid; 1165 u32 fwd_entry; 1166 1167 b53_read64(dev, B53_ARLIO_PAGE, 1168 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid); 1169 b53_read32(dev, B53_ARLIO_PAGE, 1170 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry); 1171 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1172 1173 if (!(fwd_entry & ARLTBL_VALID)) 1174 continue; 1175 if ((mac_vid & ARLTBL_MAC_MASK) != mac) 1176 continue; 1177 *idx = i; 1178 } 1179 1180 return -ENOENT; 1181 } 1182 1183 static int b53_arl_op(struct b53_device *dev, int op, int port, 1184 const unsigned char *addr, u16 vid, bool is_valid) 1185 { 1186 struct b53_arl_entry ent; 1187 u32 fwd_entry; 1188 u64 mac, mac_vid = 0; 1189 u8 idx = 0; 1190 int ret; 1191 1192 /* Convert the array into a 64-bit MAC */ 1193 mac = ether_addr_to_u64(addr); 1194 1195 /* Perform a read for the given MAC and VID */ 1196 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac); 1197 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid); 1198 1199 /* Issue a read operation for this MAC */ 1200 ret = b53_arl_rw_op(dev, 1); 1201 if (ret) 1202 return ret; 1203 1204 ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid); 1205 /* If this is a read, just finish now */ 1206 if (op) 1207 return ret; 1208 1209 /* We could not find a matching MAC, so reset to a new entry */ 1210 if (ret) { 1211 fwd_entry = 0; 1212 idx = 1; 1213 } 1214 1215 memset(&ent, 0, sizeof(ent)); 1216 ent.port = port; 1217 ent.is_valid = is_valid; 1218 ent.vid = vid; 1219 ent.is_static = true; 1220 memcpy(ent.mac, addr, ETH_ALEN); 1221 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent); 1222 1223 b53_write64(dev, B53_ARLIO_PAGE, 1224 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid); 1225 b53_write32(dev, B53_ARLIO_PAGE, 1226 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry); 1227 1228 return b53_arl_rw_op(dev, 0); 1229 } 1230 1231 int b53_fdb_add(struct dsa_switch *ds, int port, 1232 const unsigned char *addr, u16 vid) 1233 { 1234 struct b53_device *priv = ds->priv; 1235 1236 /* 5325 and 5365 require some more massaging, but could 1237 * be supported eventually 1238 */ 1239 if (is5325(priv) || is5365(priv)) 1240 return -EOPNOTSUPP; 1241 1242 return b53_arl_op(priv, 0, port, addr, vid, true); 1243 } 1244 EXPORT_SYMBOL(b53_fdb_add); 1245 1246 int b53_fdb_del(struct dsa_switch *ds, int port, 1247 const unsigned char *addr, u16 vid) 1248 { 1249 struct b53_device *priv = ds->priv; 1250 1251 return b53_arl_op(priv, 0, port, addr, vid, false); 1252 } 1253 EXPORT_SYMBOL(b53_fdb_del); 1254 1255 static int b53_arl_search_wait(struct b53_device *dev) 1256 { 1257 unsigned int timeout = 1000; 1258 u8 reg; 1259 1260 do { 1261 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®); 1262 if (!(reg & ARL_SRCH_STDN)) 1263 return 0; 1264 1265 if (reg & ARL_SRCH_VLID) 1266 return 0; 1267 1268 usleep_range(1000, 2000); 1269 } while (timeout--); 1270 1271 return -ETIMEDOUT; 1272 } 1273 1274 static void b53_arl_search_rd(struct b53_device *dev, u8 idx, 1275 struct b53_arl_entry *ent) 1276 { 1277 u64 mac_vid; 1278 u32 fwd_entry; 1279 1280 b53_read64(dev, B53_ARLIO_PAGE, 1281 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid); 1282 b53_read32(dev, B53_ARLIO_PAGE, 1283 B53_ARL_SRCH_RSTL(idx), &fwd_entry); 1284 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1285 } 1286 1287 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent, 1288 dsa_fdb_dump_cb_t *cb, void *data) 1289 { 1290 if (!ent->is_valid) 1291 return 0; 1292 1293 if (port != ent->port) 1294 return 0; 1295 1296 return cb(ent->mac, ent->vid, ent->is_static, data); 1297 } 1298 1299 int b53_fdb_dump(struct dsa_switch *ds, int port, 1300 dsa_fdb_dump_cb_t *cb, void *data) 1301 { 1302 struct b53_device *priv = ds->priv; 1303 struct b53_arl_entry results[2]; 1304 unsigned int count = 0; 1305 int ret; 1306 u8 reg; 1307 1308 /* Start search operation */ 1309 reg = ARL_SRCH_STDN; 1310 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg); 1311 1312 do { 1313 ret = b53_arl_search_wait(priv); 1314 if (ret) 1315 return ret; 1316 1317 b53_arl_search_rd(priv, 0, &results[0]); 1318 ret = b53_fdb_copy(port, &results[0], cb, data); 1319 if (ret) 1320 return ret; 1321 1322 if (priv->num_arl_entries > 2) { 1323 b53_arl_search_rd(priv, 1, &results[1]); 1324 ret = b53_fdb_copy(port, &results[1], cb, data); 1325 if (ret) 1326 return ret; 1327 1328 if (!results[0].is_valid && !results[1].is_valid) 1329 break; 1330 } 1331 1332 } while (count++ < 1024); 1333 1334 return 0; 1335 } 1336 EXPORT_SYMBOL(b53_fdb_dump); 1337 1338 int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br) 1339 { 1340 struct b53_device *dev = ds->priv; 1341 s8 cpu_port = ds->ports[port].cpu_dp->index; 1342 u16 pvlan, reg; 1343 unsigned int i; 1344 1345 /* Make this port leave the all VLANs join since we will have proper 1346 * VLAN entries from now on 1347 */ 1348 if (is58xx(dev)) { 1349 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1350 reg &= ~BIT(port); 1351 if ((reg & BIT(cpu_port)) == BIT(cpu_port)) 1352 reg &= ~BIT(cpu_port); 1353 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1354 } 1355 1356 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1357 1358 b53_for_each_port(dev, i) { 1359 if (dsa_to_port(ds, i)->bridge_dev != br) 1360 continue; 1361 1362 /* Add this local port to the remote port VLAN control 1363 * membership and update the remote port bitmask 1364 */ 1365 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1366 reg |= BIT(port); 1367 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1368 dev->ports[i].vlan_ctl_mask = reg; 1369 1370 pvlan |= BIT(i); 1371 } 1372 1373 /* Configure the local port VLAN control membership to include 1374 * remote ports and update the local port bitmask 1375 */ 1376 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1377 dev->ports[port].vlan_ctl_mask = pvlan; 1378 1379 return 0; 1380 } 1381 EXPORT_SYMBOL(b53_br_join); 1382 1383 void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br) 1384 { 1385 struct b53_device *dev = ds->priv; 1386 struct b53_vlan *vl = &dev->vlans[0]; 1387 s8 cpu_port = ds->ports[port].cpu_dp->index; 1388 unsigned int i; 1389 u16 pvlan, reg, pvid; 1390 1391 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1392 1393 b53_for_each_port(dev, i) { 1394 /* Don't touch the remaining ports */ 1395 if (dsa_to_port(ds, i)->bridge_dev != br) 1396 continue; 1397 1398 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1399 reg &= ~BIT(port); 1400 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1401 dev->ports[port].vlan_ctl_mask = reg; 1402 1403 /* Prevent self removal to preserve isolation */ 1404 if (port != i) 1405 pvlan &= ~BIT(i); 1406 } 1407 1408 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1409 dev->ports[port].vlan_ctl_mask = pvlan; 1410 1411 if (is5325(dev) || is5365(dev)) 1412 pvid = 1; 1413 else 1414 pvid = 0; 1415 1416 /* Make this port join all VLANs without VLAN entries */ 1417 if (is58xx(dev)) { 1418 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1419 reg |= BIT(port); 1420 if (!(reg & BIT(cpu_port))) 1421 reg |= BIT(cpu_port); 1422 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1423 } else { 1424 b53_get_vlan_entry(dev, pvid, vl); 1425 vl->members |= BIT(port) | BIT(dev->cpu_port); 1426 vl->untag |= BIT(port) | BIT(dev->cpu_port); 1427 b53_set_vlan_entry(dev, pvid, vl); 1428 } 1429 } 1430 EXPORT_SYMBOL(b53_br_leave); 1431 1432 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state) 1433 { 1434 struct b53_device *dev = ds->priv; 1435 u8 hw_state; 1436 u8 reg; 1437 1438 switch (state) { 1439 case BR_STATE_DISABLED: 1440 hw_state = PORT_CTRL_DIS_STATE; 1441 break; 1442 case BR_STATE_LISTENING: 1443 hw_state = PORT_CTRL_LISTEN_STATE; 1444 break; 1445 case BR_STATE_LEARNING: 1446 hw_state = PORT_CTRL_LEARN_STATE; 1447 break; 1448 case BR_STATE_FORWARDING: 1449 hw_state = PORT_CTRL_FWD_STATE; 1450 break; 1451 case BR_STATE_BLOCKING: 1452 hw_state = PORT_CTRL_BLOCK_STATE; 1453 break; 1454 default: 1455 dev_err(ds->dev, "invalid STP state: %d\n", state); 1456 return; 1457 } 1458 1459 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 1460 reg &= ~PORT_CTRL_STP_STATE_MASK; 1461 reg |= hw_state; 1462 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 1463 } 1464 EXPORT_SYMBOL(b53_br_set_stp_state); 1465 1466 void b53_br_fast_age(struct dsa_switch *ds, int port) 1467 { 1468 struct b53_device *dev = ds->priv; 1469 1470 if (b53_fast_age_port(dev, port)) 1471 dev_err(ds->dev, "fast ageing failed\n"); 1472 } 1473 EXPORT_SYMBOL(b53_br_fast_age); 1474 1475 static enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds) 1476 { 1477 return DSA_TAG_PROTO_NONE; 1478 } 1479 1480 int b53_mirror_add(struct dsa_switch *ds, int port, 1481 struct dsa_mall_mirror_tc_entry *mirror, bool ingress) 1482 { 1483 struct b53_device *dev = ds->priv; 1484 u16 reg, loc; 1485 1486 if (ingress) 1487 loc = B53_IG_MIR_CTL; 1488 else 1489 loc = B53_EG_MIR_CTL; 1490 1491 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 1492 reg &= ~MIRROR_MASK; 1493 reg |= BIT(port); 1494 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 1495 1496 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 1497 reg &= ~CAP_PORT_MASK; 1498 reg |= mirror->to_local_port; 1499 reg |= MIRROR_EN; 1500 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 1501 1502 return 0; 1503 } 1504 EXPORT_SYMBOL(b53_mirror_add); 1505 1506 void b53_mirror_del(struct dsa_switch *ds, int port, 1507 struct dsa_mall_mirror_tc_entry *mirror) 1508 { 1509 struct b53_device *dev = ds->priv; 1510 bool loc_disable = false, other_loc_disable = false; 1511 u16 reg, loc; 1512 1513 if (mirror->ingress) 1514 loc = B53_IG_MIR_CTL; 1515 else 1516 loc = B53_EG_MIR_CTL; 1517 1518 /* Update the desired ingress/egress register */ 1519 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 1520 reg &= ~BIT(port); 1521 if (!(reg & MIRROR_MASK)) 1522 loc_disable = true; 1523 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 1524 1525 /* Now look at the other one to know if we can disable mirroring 1526 * entirely 1527 */ 1528 if (mirror->ingress) 1529 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, ®); 1530 else 1531 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, ®); 1532 if (!(reg & MIRROR_MASK)) 1533 other_loc_disable = true; 1534 1535 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 1536 /* Both no longer have ports, let's disable mirroring */ 1537 if (loc_disable && other_loc_disable) { 1538 reg &= ~MIRROR_EN; 1539 reg &= ~mirror->to_local_port; 1540 } 1541 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 1542 } 1543 EXPORT_SYMBOL(b53_mirror_del); 1544 1545 void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable) 1546 { 1547 struct b53_device *dev = ds->priv; 1548 u16 reg; 1549 1550 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, ®); 1551 if (enable) 1552 reg |= BIT(port); 1553 else 1554 reg &= ~BIT(port); 1555 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg); 1556 } 1557 EXPORT_SYMBOL(b53_eee_enable_set); 1558 1559 1560 /* Returns 0 if EEE was not enabled, or 1 otherwise 1561 */ 1562 int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy) 1563 { 1564 int ret; 1565 1566 ret = phy_init_eee(phy, 0); 1567 if (ret) 1568 return 0; 1569 1570 b53_eee_enable_set(ds, port, true); 1571 1572 return 1; 1573 } 1574 EXPORT_SYMBOL(b53_eee_init); 1575 1576 int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) 1577 { 1578 struct b53_device *dev = ds->priv; 1579 struct ethtool_eee *p = &dev->ports[port].eee; 1580 u16 reg; 1581 1582 if (is5325(dev) || is5365(dev)) 1583 return -EOPNOTSUPP; 1584 1585 b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, ®); 1586 e->eee_enabled = p->eee_enabled; 1587 e->eee_active = !!(reg & BIT(port)); 1588 1589 return 0; 1590 } 1591 EXPORT_SYMBOL(b53_get_mac_eee); 1592 1593 int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) 1594 { 1595 struct b53_device *dev = ds->priv; 1596 struct ethtool_eee *p = &dev->ports[port].eee; 1597 1598 if (is5325(dev) || is5365(dev)) 1599 return -EOPNOTSUPP; 1600 1601 p->eee_enabled = e->eee_enabled; 1602 b53_eee_enable_set(ds, port, e->eee_enabled); 1603 1604 return 0; 1605 } 1606 EXPORT_SYMBOL(b53_set_mac_eee); 1607 1608 static const struct dsa_switch_ops b53_switch_ops = { 1609 .get_tag_protocol = b53_get_tag_protocol, 1610 .setup = b53_setup, 1611 .get_strings = b53_get_strings, 1612 .get_ethtool_stats = b53_get_ethtool_stats, 1613 .get_sset_count = b53_get_sset_count, 1614 .phy_read = b53_phy_read16, 1615 .phy_write = b53_phy_write16, 1616 .adjust_link = b53_adjust_link, 1617 .port_enable = b53_enable_port, 1618 .port_disable = b53_disable_port, 1619 .get_mac_eee = b53_get_mac_eee, 1620 .set_mac_eee = b53_set_mac_eee, 1621 .port_bridge_join = b53_br_join, 1622 .port_bridge_leave = b53_br_leave, 1623 .port_stp_state_set = b53_br_set_stp_state, 1624 .port_fast_age = b53_br_fast_age, 1625 .port_vlan_filtering = b53_vlan_filtering, 1626 .port_vlan_prepare = b53_vlan_prepare, 1627 .port_vlan_add = b53_vlan_add, 1628 .port_vlan_del = b53_vlan_del, 1629 .port_fdb_dump = b53_fdb_dump, 1630 .port_fdb_add = b53_fdb_add, 1631 .port_fdb_del = b53_fdb_del, 1632 .port_mirror_add = b53_mirror_add, 1633 .port_mirror_del = b53_mirror_del, 1634 }; 1635 1636 struct b53_chip_data { 1637 u32 chip_id; 1638 const char *dev_name; 1639 u16 vlans; 1640 u16 enabled_ports; 1641 u8 cpu_port; 1642 u8 vta_regs[3]; 1643 u8 arl_entries; 1644 u8 duplex_reg; 1645 u8 jumbo_pm_reg; 1646 u8 jumbo_size_reg; 1647 }; 1648 1649 #define B53_VTA_REGS \ 1650 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY } 1651 #define B53_VTA_REGS_9798 \ 1652 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 } 1653 #define B53_VTA_REGS_63XX \ 1654 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX } 1655 1656 static const struct b53_chip_data b53_switch_chips[] = { 1657 { 1658 .chip_id = BCM5325_DEVICE_ID, 1659 .dev_name = "BCM5325", 1660 .vlans = 16, 1661 .enabled_ports = 0x1f, 1662 .arl_entries = 2, 1663 .cpu_port = B53_CPU_PORT_25, 1664 .duplex_reg = B53_DUPLEX_STAT_FE, 1665 }, 1666 { 1667 .chip_id = BCM5365_DEVICE_ID, 1668 .dev_name = "BCM5365", 1669 .vlans = 256, 1670 .enabled_ports = 0x1f, 1671 .arl_entries = 2, 1672 .cpu_port = B53_CPU_PORT_25, 1673 .duplex_reg = B53_DUPLEX_STAT_FE, 1674 }, 1675 { 1676 .chip_id = BCM5395_DEVICE_ID, 1677 .dev_name = "BCM5395", 1678 .vlans = 4096, 1679 .enabled_ports = 0x1f, 1680 .arl_entries = 4, 1681 .cpu_port = B53_CPU_PORT, 1682 .vta_regs = B53_VTA_REGS, 1683 .duplex_reg = B53_DUPLEX_STAT_GE, 1684 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1685 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1686 }, 1687 { 1688 .chip_id = BCM5397_DEVICE_ID, 1689 .dev_name = "BCM5397", 1690 .vlans = 4096, 1691 .enabled_ports = 0x1f, 1692 .arl_entries = 4, 1693 .cpu_port = B53_CPU_PORT, 1694 .vta_regs = B53_VTA_REGS_9798, 1695 .duplex_reg = B53_DUPLEX_STAT_GE, 1696 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1697 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1698 }, 1699 { 1700 .chip_id = BCM5398_DEVICE_ID, 1701 .dev_name = "BCM5398", 1702 .vlans = 4096, 1703 .enabled_ports = 0x7f, 1704 .arl_entries = 4, 1705 .cpu_port = B53_CPU_PORT, 1706 .vta_regs = B53_VTA_REGS_9798, 1707 .duplex_reg = B53_DUPLEX_STAT_GE, 1708 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1709 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1710 }, 1711 { 1712 .chip_id = BCM53115_DEVICE_ID, 1713 .dev_name = "BCM53115", 1714 .vlans = 4096, 1715 .enabled_ports = 0x1f, 1716 .arl_entries = 4, 1717 .vta_regs = B53_VTA_REGS, 1718 .cpu_port = B53_CPU_PORT, 1719 .duplex_reg = B53_DUPLEX_STAT_GE, 1720 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1721 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1722 }, 1723 { 1724 .chip_id = BCM53125_DEVICE_ID, 1725 .dev_name = "BCM53125", 1726 .vlans = 4096, 1727 .enabled_ports = 0xff, 1728 .arl_entries = 4, 1729 .cpu_port = B53_CPU_PORT, 1730 .vta_regs = B53_VTA_REGS, 1731 .duplex_reg = B53_DUPLEX_STAT_GE, 1732 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1733 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1734 }, 1735 { 1736 .chip_id = BCM53128_DEVICE_ID, 1737 .dev_name = "BCM53128", 1738 .vlans = 4096, 1739 .enabled_ports = 0x1ff, 1740 .arl_entries = 4, 1741 .cpu_port = B53_CPU_PORT, 1742 .vta_regs = B53_VTA_REGS, 1743 .duplex_reg = B53_DUPLEX_STAT_GE, 1744 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1745 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1746 }, 1747 { 1748 .chip_id = BCM63XX_DEVICE_ID, 1749 .dev_name = "BCM63xx", 1750 .vlans = 4096, 1751 .enabled_ports = 0, /* pdata must provide them */ 1752 .arl_entries = 4, 1753 .cpu_port = B53_CPU_PORT, 1754 .vta_regs = B53_VTA_REGS_63XX, 1755 .duplex_reg = B53_DUPLEX_STAT_63XX, 1756 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, 1757 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, 1758 }, 1759 { 1760 .chip_id = BCM53010_DEVICE_ID, 1761 .dev_name = "BCM53010", 1762 .vlans = 4096, 1763 .enabled_ports = 0x1f, 1764 .arl_entries = 4, 1765 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 1766 .vta_regs = B53_VTA_REGS, 1767 .duplex_reg = B53_DUPLEX_STAT_GE, 1768 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1769 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1770 }, 1771 { 1772 .chip_id = BCM53011_DEVICE_ID, 1773 .dev_name = "BCM53011", 1774 .vlans = 4096, 1775 .enabled_ports = 0x1bf, 1776 .arl_entries = 4, 1777 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 1778 .vta_regs = B53_VTA_REGS, 1779 .duplex_reg = B53_DUPLEX_STAT_GE, 1780 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1781 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1782 }, 1783 { 1784 .chip_id = BCM53012_DEVICE_ID, 1785 .dev_name = "BCM53012", 1786 .vlans = 4096, 1787 .enabled_ports = 0x1bf, 1788 .arl_entries = 4, 1789 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 1790 .vta_regs = B53_VTA_REGS, 1791 .duplex_reg = B53_DUPLEX_STAT_GE, 1792 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1793 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1794 }, 1795 { 1796 .chip_id = BCM53018_DEVICE_ID, 1797 .dev_name = "BCM53018", 1798 .vlans = 4096, 1799 .enabled_ports = 0x1f, 1800 .arl_entries = 4, 1801 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 1802 .vta_regs = B53_VTA_REGS, 1803 .duplex_reg = B53_DUPLEX_STAT_GE, 1804 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1805 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1806 }, 1807 { 1808 .chip_id = BCM53019_DEVICE_ID, 1809 .dev_name = "BCM53019", 1810 .vlans = 4096, 1811 .enabled_ports = 0x1f, 1812 .arl_entries = 4, 1813 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 1814 .vta_regs = B53_VTA_REGS, 1815 .duplex_reg = B53_DUPLEX_STAT_GE, 1816 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1817 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1818 }, 1819 { 1820 .chip_id = BCM58XX_DEVICE_ID, 1821 .dev_name = "BCM585xx/586xx/88312", 1822 .vlans = 4096, 1823 .enabled_ports = 0x1ff, 1824 .arl_entries = 4, 1825 .cpu_port = B53_CPU_PORT, 1826 .vta_regs = B53_VTA_REGS, 1827 .duplex_reg = B53_DUPLEX_STAT_GE, 1828 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1829 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1830 }, 1831 { 1832 .chip_id = BCM7445_DEVICE_ID, 1833 .dev_name = "BCM7445", 1834 .vlans = 4096, 1835 .enabled_ports = 0x1ff, 1836 .arl_entries = 4, 1837 .cpu_port = B53_CPU_PORT, 1838 .vta_regs = B53_VTA_REGS, 1839 .duplex_reg = B53_DUPLEX_STAT_GE, 1840 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1841 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1842 }, 1843 { 1844 .chip_id = BCM7278_DEVICE_ID, 1845 .dev_name = "BCM7278", 1846 .vlans = 4096, 1847 .enabled_ports = 0x1ff, 1848 .arl_entries= 4, 1849 .cpu_port = B53_CPU_PORT, 1850 .vta_regs = B53_VTA_REGS, 1851 .duplex_reg = B53_DUPLEX_STAT_GE, 1852 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1853 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1854 }, 1855 }; 1856 1857 static int b53_switch_init(struct b53_device *dev) 1858 { 1859 unsigned int i; 1860 int ret; 1861 1862 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) { 1863 const struct b53_chip_data *chip = &b53_switch_chips[i]; 1864 1865 if (chip->chip_id == dev->chip_id) { 1866 if (!dev->enabled_ports) 1867 dev->enabled_ports = chip->enabled_ports; 1868 dev->name = chip->dev_name; 1869 dev->duplex_reg = chip->duplex_reg; 1870 dev->vta_regs[0] = chip->vta_regs[0]; 1871 dev->vta_regs[1] = chip->vta_regs[1]; 1872 dev->vta_regs[2] = chip->vta_regs[2]; 1873 dev->jumbo_pm_reg = chip->jumbo_pm_reg; 1874 dev->cpu_port = chip->cpu_port; 1875 dev->num_vlans = chip->vlans; 1876 dev->num_arl_entries = chip->arl_entries; 1877 break; 1878 } 1879 } 1880 1881 /* check which BCM5325x version we have */ 1882 if (is5325(dev)) { 1883 u8 vc4; 1884 1885 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 1886 1887 /* check reserved bits */ 1888 switch (vc4 & 3) { 1889 case 1: 1890 /* BCM5325E */ 1891 break; 1892 case 3: 1893 /* BCM5325F - do not use port 4 */ 1894 dev->enabled_ports &= ~BIT(4); 1895 break; 1896 default: 1897 /* On the BCM47XX SoCs this is the supported internal switch.*/ 1898 #ifndef CONFIG_BCM47XX 1899 /* BCM5325M */ 1900 return -EINVAL; 1901 #else 1902 break; 1903 #endif 1904 } 1905 } else if (dev->chip_id == BCM53115_DEVICE_ID) { 1906 u64 strap_value; 1907 1908 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value); 1909 /* use second IMP port if GMII is enabled */ 1910 if (strap_value & SV_GMII_CTRL_115) 1911 dev->cpu_port = 5; 1912 } 1913 1914 /* cpu port is always last */ 1915 dev->num_ports = dev->cpu_port + 1; 1916 dev->enabled_ports |= BIT(dev->cpu_port); 1917 1918 dev->ports = devm_kzalloc(dev->dev, 1919 sizeof(struct b53_port) * dev->num_ports, 1920 GFP_KERNEL); 1921 if (!dev->ports) 1922 return -ENOMEM; 1923 1924 dev->vlans = devm_kzalloc(dev->dev, 1925 sizeof(struct b53_vlan) * dev->num_vlans, 1926 GFP_KERNEL); 1927 if (!dev->vlans) 1928 return -ENOMEM; 1929 1930 dev->reset_gpio = b53_switch_get_reset_gpio(dev); 1931 if (dev->reset_gpio >= 0) { 1932 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio, 1933 GPIOF_OUT_INIT_HIGH, "robo_reset"); 1934 if (ret) 1935 return ret; 1936 } 1937 1938 return 0; 1939 } 1940 1941 struct b53_device *b53_switch_alloc(struct device *base, 1942 const struct b53_io_ops *ops, 1943 void *priv) 1944 { 1945 struct dsa_switch *ds; 1946 struct b53_device *dev; 1947 1948 ds = dsa_switch_alloc(base, DSA_MAX_PORTS); 1949 if (!ds) 1950 return NULL; 1951 1952 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL); 1953 if (!dev) 1954 return NULL; 1955 1956 ds->priv = dev; 1957 dev->dev = base; 1958 1959 dev->ds = ds; 1960 dev->priv = priv; 1961 dev->ops = ops; 1962 ds->ops = &b53_switch_ops; 1963 mutex_init(&dev->reg_mutex); 1964 mutex_init(&dev->stats_mutex); 1965 1966 return dev; 1967 } 1968 EXPORT_SYMBOL(b53_switch_alloc); 1969 1970 int b53_switch_detect(struct b53_device *dev) 1971 { 1972 u32 id32; 1973 u16 tmp; 1974 u8 id8; 1975 int ret; 1976 1977 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8); 1978 if (ret) 1979 return ret; 1980 1981 switch (id8) { 1982 case 0: 1983 /* BCM5325 and BCM5365 do not have this register so reads 1984 * return 0. But the read operation did succeed, so assume this 1985 * is one of them. 1986 * 1987 * Next check if we can write to the 5325's VTA register; for 1988 * 5365 it is read only. 1989 */ 1990 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf); 1991 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp); 1992 1993 if (tmp == 0xf) 1994 dev->chip_id = BCM5325_DEVICE_ID; 1995 else 1996 dev->chip_id = BCM5365_DEVICE_ID; 1997 break; 1998 case BCM5395_DEVICE_ID: 1999 case BCM5397_DEVICE_ID: 2000 case BCM5398_DEVICE_ID: 2001 dev->chip_id = id8; 2002 break; 2003 default: 2004 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32); 2005 if (ret) 2006 return ret; 2007 2008 switch (id32) { 2009 case BCM53115_DEVICE_ID: 2010 case BCM53125_DEVICE_ID: 2011 case BCM53128_DEVICE_ID: 2012 case BCM53010_DEVICE_ID: 2013 case BCM53011_DEVICE_ID: 2014 case BCM53012_DEVICE_ID: 2015 case BCM53018_DEVICE_ID: 2016 case BCM53019_DEVICE_ID: 2017 dev->chip_id = id32; 2018 break; 2019 default: 2020 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n", 2021 id8, id32); 2022 return -ENODEV; 2023 } 2024 } 2025 2026 if (dev->chip_id == BCM5325_DEVICE_ID) 2027 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25, 2028 &dev->core_rev); 2029 else 2030 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID, 2031 &dev->core_rev); 2032 } 2033 EXPORT_SYMBOL(b53_switch_detect); 2034 2035 int b53_switch_register(struct b53_device *dev) 2036 { 2037 int ret; 2038 2039 if (dev->pdata) { 2040 dev->chip_id = dev->pdata->chip_id; 2041 dev->enabled_ports = dev->pdata->enabled_ports; 2042 } 2043 2044 if (!dev->chip_id && b53_switch_detect(dev)) 2045 return -EINVAL; 2046 2047 ret = b53_switch_init(dev); 2048 if (ret) 2049 return ret; 2050 2051 pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev); 2052 2053 return dsa_register_switch(dev->ds); 2054 } 2055 EXPORT_SYMBOL(b53_switch_register); 2056 2057 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>"); 2058 MODULE_DESCRIPTION("B53 switch library"); 2059 MODULE_LICENSE("Dual BSD/GPL"); 2060