1 /* 2 * B53 switch driver main logic 3 * 4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org> 5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com> 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <linux/delay.h> 21 #include <linux/export.h> 22 #include <linux/gpio.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/platform_data/b53.h> 26 #include <linux/phy.h> 27 #include <linux/phylink.h> 28 #include <linux/etherdevice.h> 29 #include <linux/if_bridge.h> 30 #include <net/dsa.h> 31 32 #include "b53_regs.h" 33 #include "b53_priv.h" 34 35 struct b53_mib_desc { 36 u8 size; 37 u8 offset; 38 const char *name; 39 }; 40 41 /* BCM5365 MIB counters */ 42 static const struct b53_mib_desc b53_mibs_65[] = { 43 { 8, 0x00, "TxOctets" }, 44 { 4, 0x08, "TxDropPkts" }, 45 { 4, 0x10, "TxBroadcastPkts" }, 46 { 4, 0x14, "TxMulticastPkts" }, 47 { 4, 0x18, "TxUnicastPkts" }, 48 { 4, 0x1c, "TxCollisions" }, 49 { 4, 0x20, "TxSingleCollision" }, 50 { 4, 0x24, "TxMultipleCollision" }, 51 { 4, 0x28, "TxDeferredTransmit" }, 52 { 4, 0x2c, "TxLateCollision" }, 53 { 4, 0x30, "TxExcessiveCollision" }, 54 { 4, 0x38, "TxPausePkts" }, 55 { 8, 0x44, "RxOctets" }, 56 { 4, 0x4c, "RxUndersizePkts" }, 57 { 4, 0x50, "RxPausePkts" }, 58 { 4, 0x54, "Pkts64Octets" }, 59 { 4, 0x58, "Pkts65to127Octets" }, 60 { 4, 0x5c, "Pkts128to255Octets" }, 61 { 4, 0x60, "Pkts256to511Octets" }, 62 { 4, 0x64, "Pkts512to1023Octets" }, 63 { 4, 0x68, "Pkts1024to1522Octets" }, 64 { 4, 0x6c, "RxOversizePkts" }, 65 { 4, 0x70, "RxJabbers" }, 66 { 4, 0x74, "RxAlignmentErrors" }, 67 { 4, 0x78, "RxFCSErrors" }, 68 { 8, 0x7c, "RxGoodOctets" }, 69 { 4, 0x84, "RxDropPkts" }, 70 { 4, 0x88, "RxUnicastPkts" }, 71 { 4, 0x8c, "RxMulticastPkts" }, 72 { 4, 0x90, "RxBroadcastPkts" }, 73 { 4, 0x94, "RxSAChanges" }, 74 { 4, 0x98, "RxFragments" }, 75 }; 76 77 #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65) 78 79 /* BCM63xx MIB counters */ 80 static const struct b53_mib_desc b53_mibs_63xx[] = { 81 { 8, 0x00, "TxOctets" }, 82 { 4, 0x08, "TxDropPkts" }, 83 { 4, 0x0c, "TxQoSPkts" }, 84 { 4, 0x10, "TxBroadcastPkts" }, 85 { 4, 0x14, "TxMulticastPkts" }, 86 { 4, 0x18, "TxUnicastPkts" }, 87 { 4, 0x1c, "TxCollisions" }, 88 { 4, 0x20, "TxSingleCollision" }, 89 { 4, 0x24, "TxMultipleCollision" }, 90 { 4, 0x28, "TxDeferredTransmit" }, 91 { 4, 0x2c, "TxLateCollision" }, 92 { 4, 0x30, "TxExcessiveCollision" }, 93 { 4, 0x38, "TxPausePkts" }, 94 { 8, 0x3c, "TxQoSOctets" }, 95 { 8, 0x44, "RxOctets" }, 96 { 4, 0x4c, "RxUndersizePkts" }, 97 { 4, 0x50, "RxPausePkts" }, 98 { 4, 0x54, "Pkts64Octets" }, 99 { 4, 0x58, "Pkts65to127Octets" }, 100 { 4, 0x5c, "Pkts128to255Octets" }, 101 { 4, 0x60, "Pkts256to511Octets" }, 102 { 4, 0x64, "Pkts512to1023Octets" }, 103 { 4, 0x68, "Pkts1024to1522Octets" }, 104 { 4, 0x6c, "RxOversizePkts" }, 105 { 4, 0x70, "RxJabbers" }, 106 { 4, 0x74, "RxAlignmentErrors" }, 107 { 4, 0x78, "RxFCSErrors" }, 108 { 8, 0x7c, "RxGoodOctets" }, 109 { 4, 0x84, "RxDropPkts" }, 110 { 4, 0x88, "RxUnicastPkts" }, 111 { 4, 0x8c, "RxMulticastPkts" }, 112 { 4, 0x90, "RxBroadcastPkts" }, 113 { 4, 0x94, "RxSAChanges" }, 114 { 4, 0x98, "RxFragments" }, 115 { 4, 0xa0, "RxSymbolErrors" }, 116 { 4, 0xa4, "RxQoSPkts" }, 117 { 8, 0xa8, "RxQoSOctets" }, 118 { 4, 0xb0, "Pkts1523to2047Octets" }, 119 { 4, 0xb4, "Pkts2048to4095Octets" }, 120 { 4, 0xb8, "Pkts4096to8191Octets" }, 121 { 4, 0xbc, "Pkts8192to9728Octets" }, 122 { 4, 0xc0, "RxDiscarded" }, 123 }; 124 125 #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx) 126 127 /* MIB counters */ 128 static const struct b53_mib_desc b53_mibs[] = { 129 { 8, 0x00, "TxOctets" }, 130 { 4, 0x08, "TxDropPkts" }, 131 { 4, 0x10, "TxBroadcastPkts" }, 132 { 4, 0x14, "TxMulticastPkts" }, 133 { 4, 0x18, "TxUnicastPkts" }, 134 { 4, 0x1c, "TxCollisions" }, 135 { 4, 0x20, "TxSingleCollision" }, 136 { 4, 0x24, "TxMultipleCollision" }, 137 { 4, 0x28, "TxDeferredTransmit" }, 138 { 4, 0x2c, "TxLateCollision" }, 139 { 4, 0x30, "TxExcessiveCollision" }, 140 { 4, 0x38, "TxPausePkts" }, 141 { 8, 0x50, "RxOctets" }, 142 { 4, 0x58, "RxUndersizePkts" }, 143 { 4, 0x5c, "RxPausePkts" }, 144 { 4, 0x60, "Pkts64Octets" }, 145 { 4, 0x64, "Pkts65to127Octets" }, 146 { 4, 0x68, "Pkts128to255Octets" }, 147 { 4, 0x6c, "Pkts256to511Octets" }, 148 { 4, 0x70, "Pkts512to1023Octets" }, 149 { 4, 0x74, "Pkts1024to1522Octets" }, 150 { 4, 0x78, "RxOversizePkts" }, 151 { 4, 0x7c, "RxJabbers" }, 152 { 4, 0x80, "RxAlignmentErrors" }, 153 { 4, 0x84, "RxFCSErrors" }, 154 { 8, 0x88, "RxGoodOctets" }, 155 { 4, 0x90, "RxDropPkts" }, 156 { 4, 0x94, "RxUnicastPkts" }, 157 { 4, 0x98, "RxMulticastPkts" }, 158 { 4, 0x9c, "RxBroadcastPkts" }, 159 { 4, 0xa0, "RxSAChanges" }, 160 { 4, 0xa4, "RxFragments" }, 161 { 4, 0xa8, "RxJumboPkts" }, 162 { 4, 0xac, "RxSymbolErrors" }, 163 { 4, 0xc0, "RxDiscarded" }, 164 }; 165 166 #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs) 167 168 static const struct b53_mib_desc b53_mibs_58xx[] = { 169 { 8, 0x00, "TxOctets" }, 170 { 4, 0x08, "TxDropPkts" }, 171 { 4, 0x0c, "TxQPKTQ0" }, 172 { 4, 0x10, "TxBroadcastPkts" }, 173 { 4, 0x14, "TxMulticastPkts" }, 174 { 4, 0x18, "TxUnicastPKts" }, 175 { 4, 0x1c, "TxCollisions" }, 176 { 4, 0x20, "TxSingleCollision" }, 177 { 4, 0x24, "TxMultipleCollision" }, 178 { 4, 0x28, "TxDeferredCollision" }, 179 { 4, 0x2c, "TxLateCollision" }, 180 { 4, 0x30, "TxExcessiveCollision" }, 181 { 4, 0x34, "TxFrameInDisc" }, 182 { 4, 0x38, "TxPausePkts" }, 183 { 4, 0x3c, "TxQPKTQ1" }, 184 { 4, 0x40, "TxQPKTQ2" }, 185 { 4, 0x44, "TxQPKTQ3" }, 186 { 4, 0x48, "TxQPKTQ4" }, 187 { 4, 0x4c, "TxQPKTQ5" }, 188 { 8, 0x50, "RxOctets" }, 189 { 4, 0x58, "RxUndersizePkts" }, 190 { 4, 0x5c, "RxPausePkts" }, 191 { 4, 0x60, "RxPkts64Octets" }, 192 { 4, 0x64, "RxPkts65to127Octets" }, 193 { 4, 0x68, "RxPkts128to255Octets" }, 194 { 4, 0x6c, "RxPkts256to511Octets" }, 195 { 4, 0x70, "RxPkts512to1023Octets" }, 196 { 4, 0x74, "RxPkts1024toMaxPktsOctets" }, 197 { 4, 0x78, "RxOversizePkts" }, 198 { 4, 0x7c, "RxJabbers" }, 199 { 4, 0x80, "RxAlignmentErrors" }, 200 { 4, 0x84, "RxFCSErrors" }, 201 { 8, 0x88, "RxGoodOctets" }, 202 { 4, 0x90, "RxDropPkts" }, 203 { 4, 0x94, "RxUnicastPkts" }, 204 { 4, 0x98, "RxMulticastPkts" }, 205 { 4, 0x9c, "RxBroadcastPkts" }, 206 { 4, 0xa0, "RxSAChanges" }, 207 { 4, 0xa4, "RxFragments" }, 208 { 4, 0xa8, "RxJumboPkt" }, 209 { 4, 0xac, "RxSymblErr" }, 210 { 4, 0xb0, "InRangeErrCount" }, 211 { 4, 0xb4, "OutRangeErrCount" }, 212 { 4, 0xb8, "EEELpiEvent" }, 213 { 4, 0xbc, "EEELpiDuration" }, 214 { 4, 0xc0, "RxDiscard" }, 215 { 4, 0xc8, "TxQPKTQ6" }, 216 { 4, 0xcc, "TxQPKTQ7" }, 217 { 4, 0xd0, "TxPkts64Octets" }, 218 { 4, 0xd4, "TxPkts65to127Octets" }, 219 { 4, 0xd8, "TxPkts128to255Octets" }, 220 { 4, 0xdc, "TxPkts256to511Ocets" }, 221 { 4, 0xe0, "TxPkts512to1023Ocets" }, 222 { 4, 0xe4, "TxPkts1024toMaxPktOcets" }, 223 }; 224 225 #define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx) 226 227 static int b53_do_vlan_op(struct b53_device *dev, u8 op) 228 { 229 unsigned int i; 230 231 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op); 232 233 for (i = 0; i < 10; i++) { 234 u8 vta; 235 236 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta); 237 if (!(vta & VTA_START_CMD)) 238 return 0; 239 240 usleep_range(100, 200); 241 } 242 243 return -EIO; 244 } 245 246 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, 247 struct b53_vlan *vlan) 248 { 249 if (is5325(dev)) { 250 u32 entry = 0; 251 252 if (vlan->members) { 253 entry = ((vlan->untag & VA_UNTAG_MASK_25) << 254 VA_UNTAG_S_25) | vlan->members; 255 if (dev->core_rev >= 3) 256 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S; 257 else 258 entry |= VA_VALID_25; 259 } 260 261 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry); 262 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 263 VTA_RW_STATE_WR | VTA_RW_OP_EN); 264 } else if (is5365(dev)) { 265 u16 entry = 0; 266 267 if (vlan->members) 268 entry = ((vlan->untag & VA_UNTAG_MASK_65) << 269 VA_UNTAG_S_65) | vlan->members | VA_VALID_65; 270 271 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry); 272 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 273 VTA_RW_STATE_WR | VTA_RW_OP_EN); 274 } else { 275 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 276 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], 277 (vlan->untag << VTE_UNTAG_S) | vlan->members); 278 279 b53_do_vlan_op(dev, VTA_CMD_WRITE); 280 } 281 282 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n", 283 vid, vlan->members, vlan->untag); 284 } 285 286 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid, 287 struct b53_vlan *vlan) 288 { 289 if (is5325(dev)) { 290 u32 entry = 0; 291 292 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 293 VTA_RW_STATE_RD | VTA_RW_OP_EN); 294 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry); 295 296 if (dev->core_rev >= 3) 297 vlan->valid = !!(entry & VA_VALID_25_R4); 298 else 299 vlan->valid = !!(entry & VA_VALID_25); 300 vlan->members = entry & VA_MEMBER_MASK; 301 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25; 302 303 } else if (is5365(dev)) { 304 u16 entry = 0; 305 306 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 307 VTA_RW_STATE_WR | VTA_RW_OP_EN); 308 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry); 309 310 vlan->valid = !!(entry & VA_VALID_65); 311 vlan->members = entry & VA_MEMBER_MASK; 312 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65; 313 } else { 314 u32 entry = 0; 315 316 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 317 b53_do_vlan_op(dev, VTA_CMD_READ); 318 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry); 319 vlan->members = entry & VTE_MEMBERS; 320 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS; 321 vlan->valid = true; 322 } 323 } 324 325 static void b53_set_forwarding(struct b53_device *dev, int enable) 326 { 327 u8 mgmt; 328 329 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 330 331 if (enable) 332 mgmt |= SM_SW_FWD_EN; 333 else 334 mgmt &= ~SM_SW_FWD_EN; 335 336 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 337 338 /* Include IMP port in dumb forwarding mode 339 */ 340 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt); 341 mgmt |= B53_MII_DUMB_FWDG_EN; 342 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt); 343 344 /* Look at B53_UC_FWD_EN and B53_MC_FWD_EN to decide whether 345 * frames should be flooded or not. 346 */ 347 b53_read8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, &mgmt); 348 mgmt |= B53_UC_FWD_EN | B53_MC_FWD_EN | B53_IPMC_FWD_EN; 349 b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt); 350 } 351 352 static void b53_enable_vlan(struct b53_device *dev, int port, bool enable, 353 bool enable_filtering) 354 { 355 u8 mgmt, vc0, vc1, vc4 = 0, vc5; 356 357 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 358 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0); 359 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1); 360 361 if (is5325(dev) || is5365(dev)) { 362 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 363 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5); 364 } else if (is63xx(dev)) { 365 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4); 366 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5); 367 } else { 368 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4); 369 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5); 370 } 371 372 if (enable) { 373 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID; 374 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN; 375 vc4 &= ~VC4_ING_VID_CHECK_MASK; 376 if (enable_filtering) { 377 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S; 378 vc5 |= VC5_DROP_VTABLE_MISS; 379 } else { 380 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 381 vc5 &= ~VC5_DROP_VTABLE_MISS; 382 } 383 384 if (is5325(dev)) 385 vc0 &= ~VC0_RESERVED_1; 386 387 if (is5325(dev) || is5365(dev)) 388 vc1 |= VC1_RX_MCST_TAG_EN; 389 390 } else { 391 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID); 392 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN); 393 vc4 &= ~VC4_ING_VID_CHECK_MASK; 394 vc5 &= ~VC5_DROP_VTABLE_MISS; 395 396 if (is5325(dev) || is5365(dev)) 397 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 398 else 399 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S; 400 401 if (is5325(dev) || is5365(dev)) 402 vc1 &= ~VC1_RX_MCST_TAG_EN; 403 } 404 405 if (!is5325(dev) && !is5365(dev)) 406 vc5 &= ~VC5_VID_FFF_EN; 407 408 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0); 409 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1); 410 411 if (is5325(dev) || is5365(dev)) { 412 /* enable the high 8 bit vid check on 5325 */ 413 if (is5325(dev) && enable) 414 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 415 VC3_HIGH_8BIT_EN); 416 else 417 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 418 419 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4); 420 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5); 421 } else if (is63xx(dev)) { 422 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0); 423 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4); 424 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5); 425 } else { 426 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 427 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4); 428 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5); 429 } 430 431 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 432 433 dev->vlan_enabled = enable; 434 435 dev_dbg(dev->dev, "Port %d VLAN enabled: %d, filtering: %d\n", 436 port, enable, enable_filtering); 437 } 438 439 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100) 440 { 441 u32 port_mask = 0; 442 u16 max_size = JMS_MIN_SIZE; 443 444 if (is5325(dev) || is5365(dev)) 445 return -EINVAL; 446 447 if (enable) { 448 port_mask = dev->enabled_ports; 449 max_size = JMS_MAX_SIZE; 450 if (allow_10_100) 451 port_mask |= JPM_10_100_JUMBO_EN; 452 } 453 454 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask); 455 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size); 456 } 457 458 static int b53_flush_arl(struct b53_device *dev, u8 mask) 459 { 460 unsigned int i; 461 462 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 463 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask); 464 465 for (i = 0; i < 10; i++) { 466 u8 fast_age_ctrl; 467 468 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 469 &fast_age_ctrl); 470 471 if (!(fast_age_ctrl & FAST_AGE_DONE)) 472 goto out; 473 474 msleep(1); 475 } 476 477 return -ETIMEDOUT; 478 out: 479 /* Only age dynamic entries (default behavior) */ 480 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC); 481 return 0; 482 } 483 484 static int b53_fast_age_port(struct b53_device *dev, int port) 485 { 486 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port); 487 488 return b53_flush_arl(dev, FAST_AGE_PORT); 489 } 490 491 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid) 492 { 493 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid); 494 495 return b53_flush_arl(dev, FAST_AGE_VLAN); 496 } 497 498 void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port) 499 { 500 struct b53_device *dev = ds->priv; 501 unsigned int i; 502 u16 pvlan; 503 504 /* Enable the IMP port to be in the same VLAN as the other ports 505 * on a per-port basis such that we only have Port i and IMP in 506 * the same VLAN. 507 */ 508 b53_for_each_port(dev, i) { 509 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan); 510 pvlan |= BIT(cpu_port); 511 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan); 512 } 513 } 514 EXPORT_SYMBOL(b53_imp_vlan_setup); 515 516 static void b53_port_set_ucast_flood(struct b53_device *dev, int port, 517 bool unicast) 518 { 519 u16 uc; 520 521 b53_read16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, &uc); 522 if (unicast) 523 uc |= BIT(port); 524 else 525 uc &= ~BIT(port); 526 b53_write16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, uc); 527 } 528 529 static void b53_port_set_mcast_flood(struct b53_device *dev, int port, 530 bool multicast) 531 { 532 u16 mc; 533 534 b53_read16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, &mc); 535 if (multicast) 536 mc |= BIT(port); 537 else 538 mc &= ~BIT(port); 539 b53_write16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, mc); 540 541 b53_read16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, &mc); 542 if (multicast) 543 mc |= BIT(port); 544 else 545 mc &= ~BIT(port); 546 b53_write16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, mc); 547 } 548 549 static void b53_port_set_learning(struct b53_device *dev, int port, 550 bool learning) 551 { 552 u16 reg; 553 554 b53_read16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, ®); 555 if (learning) 556 reg &= ~BIT(port); 557 else 558 reg |= BIT(port); 559 b53_write16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, reg); 560 } 561 562 int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy) 563 { 564 struct b53_device *dev = ds->priv; 565 unsigned int cpu_port; 566 int ret = 0; 567 u16 pvlan; 568 569 if (!dsa_is_user_port(ds, port)) 570 return 0; 571 572 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 573 574 b53_port_set_ucast_flood(dev, port, true); 575 b53_port_set_mcast_flood(dev, port, true); 576 b53_port_set_learning(dev, port, false); 577 578 if (dev->ops->irq_enable) 579 ret = dev->ops->irq_enable(dev, port); 580 if (ret) 581 return ret; 582 583 /* Clear the Rx and Tx disable bits and set to no spanning tree */ 584 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0); 585 586 /* Set this port, and only this one to be in the default VLAN, 587 * if member of a bridge, restore its membership prior to 588 * bringing down this port. 589 */ 590 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 591 pvlan &= ~0x1ff; 592 pvlan |= BIT(port); 593 pvlan |= dev->ports[port].vlan_ctl_mask; 594 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 595 596 b53_imp_vlan_setup(ds, cpu_port); 597 598 /* If EEE was enabled, restore it */ 599 if (dev->ports[port].eee.eee_enabled) 600 b53_eee_enable_set(ds, port, true); 601 602 return 0; 603 } 604 EXPORT_SYMBOL(b53_enable_port); 605 606 void b53_disable_port(struct dsa_switch *ds, int port) 607 { 608 struct b53_device *dev = ds->priv; 609 u8 reg; 610 611 /* Disable Tx/Rx for the port */ 612 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 613 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE; 614 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 615 616 if (dev->ops->irq_disable) 617 dev->ops->irq_disable(dev, port); 618 } 619 EXPORT_SYMBOL(b53_disable_port); 620 621 void b53_brcm_hdr_setup(struct dsa_switch *ds, int port) 622 { 623 struct b53_device *dev = ds->priv; 624 bool tag_en = !(dev->tag_protocol == DSA_TAG_PROTO_NONE); 625 u8 hdr_ctl, val; 626 u16 reg; 627 628 /* Resolve which bit controls the Broadcom tag */ 629 switch (port) { 630 case 8: 631 val = BRCM_HDR_P8_EN; 632 break; 633 case 7: 634 val = BRCM_HDR_P7_EN; 635 break; 636 case 5: 637 val = BRCM_HDR_P5_EN; 638 break; 639 default: 640 val = 0; 641 break; 642 } 643 644 /* Enable management mode if tagging is requested */ 645 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &hdr_ctl); 646 if (tag_en) 647 hdr_ctl |= SM_SW_FWD_MODE; 648 else 649 hdr_ctl &= ~SM_SW_FWD_MODE; 650 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, hdr_ctl); 651 652 /* Configure the appropriate IMP port */ 653 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &hdr_ctl); 654 if (port == 8) 655 hdr_ctl |= GC_FRM_MGMT_PORT_MII; 656 else if (port == 5) 657 hdr_ctl |= GC_FRM_MGMT_PORT_M; 658 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, hdr_ctl); 659 660 /* Enable Broadcom tags for IMP port */ 661 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl); 662 if (tag_en) 663 hdr_ctl |= val; 664 else 665 hdr_ctl &= ~val; 666 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl); 667 668 /* Registers below are only accessible on newer devices */ 669 if (!is58xx(dev)) 670 return; 671 672 /* Enable reception Broadcom tag for CPU TX (switch RX) to 673 * allow us to tag outgoing frames 674 */ 675 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, ®); 676 if (tag_en) 677 reg &= ~BIT(port); 678 else 679 reg |= BIT(port); 680 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg); 681 682 /* Enable transmission of Broadcom tags from the switch (CPU RX) to 683 * allow delivering frames to the per-port net_devices 684 */ 685 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, ®); 686 if (tag_en) 687 reg &= ~BIT(port); 688 else 689 reg |= BIT(port); 690 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg); 691 } 692 EXPORT_SYMBOL(b53_brcm_hdr_setup); 693 694 static void b53_enable_cpu_port(struct b53_device *dev, int port) 695 { 696 u8 port_ctrl; 697 698 /* BCM5325 CPU port is at 8 */ 699 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25) 700 port = B53_CPU_PORT; 701 702 port_ctrl = PORT_CTRL_RX_BCST_EN | 703 PORT_CTRL_RX_MCST_EN | 704 PORT_CTRL_RX_UCST_EN; 705 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl); 706 707 b53_brcm_hdr_setup(dev->ds, port); 708 709 b53_port_set_ucast_flood(dev, port, true); 710 b53_port_set_mcast_flood(dev, port, true); 711 b53_port_set_learning(dev, port, false); 712 } 713 714 static void b53_enable_mib(struct b53_device *dev) 715 { 716 u8 gc; 717 718 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 719 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN); 720 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc); 721 } 722 723 static u16 b53_default_pvid(struct b53_device *dev) 724 { 725 if (is5325(dev) || is5365(dev)) 726 return 1; 727 else 728 return 0; 729 } 730 731 static bool b53_vlan_port_needs_forced_tagged(struct dsa_switch *ds, int port) 732 { 733 struct b53_device *dev = ds->priv; 734 735 return dev->tag_protocol == DSA_TAG_PROTO_NONE && dsa_is_cpu_port(ds, port); 736 } 737 738 int b53_configure_vlan(struct dsa_switch *ds) 739 { 740 struct b53_device *dev = ds->priv; 741 struct b53_vlan vl = { 0 }; 742 struct b53_vlan *v; 743 int i, def_vid; 744 u16 vid; 745 746 def_vid = b53_default_pvid(dev); 747 748 /* clear all vlan entries */ 749 if (is5325(dev) || is5365(dev)) { 750 for (i = def_vid; i < dev->num_vlans; i++) 751 b53_set_vlan_entry(dev, i, &vl); 752 } else { 753 b53_do_vlan_op(dev, VTA_CMD_CLEAR); 754 } 755 756 b53_enable_vlan(dev, -1, dev->vlan_enabled, ds->vlan_filtering); 757 758 /* Create an untagged VLAN entry for the default PVID in case 759 * CONFIG_VLAN_8021Q is disabled and there are no calls to 760 * dsa_slave_vlan_rx_add_vid() to create the default VLAN 761 * entry. Do this only when the tagging protocol is not 762 * DSA_TAG_PROTO_NONE 763 */ 764 b53_for_each_port(dev, i) { 765 v = &dev->vlans[def_vid]; 766 v->members |= BIT(i); 767 if (!b53_vlan_port_needs_forced_tagged(ds, i)) 768 v->untag = v->members; 769 b53_write16(dev, B53_VLAN_PAGE, 770 B53_VLAN_PORT_DEF_TAG(i), def_vid); 771 } 772 773 /* Upon initial call we have not set-up any VLANs, but upon 774 * system resume, we need to restore all VLAN entries. 775 */ 776 for (vid = def_vid; vid < dev->num_vlans; vid++) { 777 v = &dev->vlans[vid]; 778 779 if (!v->members) 780 continue; 781 782 b53_set_vlan_entry(dev, vid, v); 783 b53_fast_age_vlan(dev, vid); 784 } 785 786 return 0; 787 } 788 EXPORT_SYMBOL(b53_configure_vlan); 789 790 static void b53_switch_reset_gpio(struct b53_device *dev) 791 { 792 int gpio = dev->reset_gpio; 793 794 if (gpio < 0) 795 return; 796 797 /* Reset sequence: RESET low(50ms)->high(20ms) 798 */ 799 gpio_set_value(gpio, 0); 800 mdelay(50); 801 802 gpio_set_value(gpio, 1); 803 mdelay(20); 804 805 dev->current_page = 0xff; 806 } 807 808 static int b53_switch_reset(struct b53_device *dev) 809 { 810 unsigned int timeout = 1000; 811 u8 mgmt, reg; 812 813 b53_switch_reset_gpio(dev); 814 815 if (is539x(dev)) { 816 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83); 817 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00); 818 } 819 820 /* This is specific to 58xx devices here, do not use is58xx() which 821 * covers the larger Starfigther 2 family, including 7445/7278 which 822 * still use this driver as a library and need to perform the reset 823 * earlier. 824 */ 825 if (dev->chip_id == BCM58XX_DEVICE_ID || 826 dev->chip_id == BCM583XX_DEVICE_ID) { 827 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 828 reg |= SW_RST | EN_SW_RST | EN_CH_RST; 829 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg); 830 831 do { 832 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 833 if (!(reg & SW_RST)) 834 break; 835 836 usleep_range(1000, 2000); 837 } while (timeout-- > 0); 838 839 if (timeout == 0) { 840 dev_err(dev->dev, 841 "Timeout waiting for SW_RST to clear!\n"); 842 return -ETIMEDOUT; 843 } 844 } 845 846 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 847 848 if (!(mgmt & SM_SW_FWD_EN)) { 849 mgmt &= ~SM_SW_FWD_MODE; 850 mgmt |= SM_SW_FWD_EN; 851 852 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 853 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 854 855 if (!(mgmt & SM_SW_FWD_EN)) { 856 dev_err(dev->dev, "Failed to enable switch!\n"); 857 return -EINVAL; 858 } 859 } 860 861 b53_enable_mib(dev); 862 863 return b53_flush_arl(dev, FAST_AGE_STATIC); 864 } 865 866 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg) 867 { 868 struct b53_device *priv = ds->priv; 869 u16 value = 0; 870 int ret; 871 872 if (priv->ops->phy_read16) 873 ret = priv->ops->phy_read16(priv, addr, reg, &value); 874 else 875 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr), 876 reg * 2, &value); 877 878 return ret ? ret : value; 879 } 880 881 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 882 { 883 struct b53_device *priv = ds->priv; 884 885 if (priv->ops->phy_write16) 886 return priv->ops->phy_write16(priv, addr, reg, val); 887 888 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val); 889 } 890 891 static int b53_reset_switch(struct b53_device *priv) 892 { 893 /* reset vlans */ 894 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans); 895 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports); 896 897 priv->serdes_lane = B53_INVALID_LANE; 898 899 return b53_switch_reset(priv); 900 } 901 902 static int b53_apply_config(struct b53_device *priv) 903 { 904 /* disable switching */ 905 b53_set_forwarding(priv, 0); 906 907 b53_configure_vlan(priv->ds); 908 909 /* enable switching */ 910 b53_set_forwarding(priv, 1); 911 912 return 0; 913 } 914 915 static void b53_reset_mib(struct b53_device *priv) 916 { 917 u8 gc; 918 919 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 920 921 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB); 922 msleep(1); 923 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB); 924 msleep(1); 925 } 926 927 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev) 928 { 929 if (is5365(dev)) 930 return b53_mibs_65; 931 else if (is63xx(dev)) 932 return b53_mibs_63xx; 933 else if (is58xx(dev)) 934 return b53_mibs_58xx; 935 else 936 return b53_mibs; 937 } 938 939 static unsigned int b53_get_mib_size(struct b53_device *dev) 940 { 941 if (is5365(dev)) 942 return B53_MIBS_65_SIZE; 943 else if (is63xx(dev)) 944 return B53_MIBS_63XX_SIZE; 945 else if (is58xx(dev)) 946 return B53_MIBS_58XX_SIZE; 947 else 948 return B53_MIBS_SIZE; 949 } 950 951 static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port) 952 { 953 /* These ports typically do not have built-in PHYs */ 954 switch (port) { 955 case B53_CPU_PORT_25: 956 case 7: 957 case B53_CPU_PORT: 958 return NULL; 959 } 960 961 return mdiobus_get_phy(ds->slave_mii_bus, port); 962 } 963 964 void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset, 965 uint8_t *data) 966 { 967 struct b53_device *dev = ds->priv; 968 const struct b53_mib_desc *mibs = b53_get_mib(dev); 969 unsigned int mib_size = b53_get_mib_size(dev); 970 struct phy_device *phydev; 971 unsigned int i; 972 973 if (stringset == ETH_SS_STATS) { 974 for (i = 0; i < mib_size; i++) 975 strlcpy(data + i * ETH_GSTRING_LEN, 976 mibs[i].name, ETH_GSTRING_LEN); 977 } else if (stringset == ETH_SS_PHY_STATS) { 978 phydev = b53_get_phy_device(ds, port); 979 if (!phydev) 980 return; 981 982 phy_ethtool_get_strings(phydev, data); 983 } 984 } 985 EXPORT_SYMBOL(b53_get_strings); 986 987 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) 988 { 989 struct b53_device *dev = ds->priv; 990 const struct b53_mib_desc *mibs = b53_get_mib(dev); 991 unsigned int mib_size = b53_get_mib_size(dev); 992 const struct b53_mib_desc *s; 993 unsigned int i; 994 u64 val = 0; 995 996 if (is5365(dev) && port == 5) 997 port = 8; 998 999 mutex_lock(&dev->stats_mutex); 1000 1001 for (i = 0; i < mib_size; i++) { 1002 s = &mibs[i]; 1003 1004 if (s->size == 8) { 1005 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val); 1006 } else { 1007 u32 val32; 1008 1009 b53_read32(dev, B53_MIB_PAGE(port), s->offset, 1010 &val32); 1011 val = val32; 1012 } 1013 data[i] = (u64)val; 1014 } 1015 1016 mutex_unlock(&dev->stats_mutex); 1017 } 1018 EXPORT_SYMBOL(b53_get_ethtool_stats); 1019 1020 void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data) 1021 { 1022 struct phy_device *phydev; 1023 1024 phydev = b53_get_phy_device(ds, port); 1025 if (!phydev) 1026 return; 1027 1028 phy_ethtool_get_stats(phydev, NULL, data); 1029 } 1030 EXPORT_SYMBOL(b53_get_ethtool_phy_stats); 1031 1032 int b53_get_sset_count(struct dsa_switch *ds, int port, int sset) 1033 { 1034 struct b53_device *dev = ds->priv; 1035 struct phy_device *phydev; 1036 1037 if (sset == ETH_SS_STATS) { 1038 return b53_get_mib_size(dev); 1039 } else if (sset == ETH_SS_PHY_STATS) { 1040 phydev = b53_get_phy_device(ds, port); 1041 if (!phydev) 1042 return 0; 1043 1044 return phy_ethtool_get_sset_count(phydev); 1045 } 1046 1047 return 0; 1048 } 1049 EXPORT_SYMBOL(b53_get_sset_count); 1050 1051 enum b53_devlink_resource_id { 1052 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1053 }; 1054 1055 static u64 b53_devlink_vlan_table_get(void *priv) 1056 { 1057 struct b53_device *dev = priv; 1058 struct b53_vlan *vl; 1059 unsigned int i; 1060 u64 count = 0; 1061 1062 for (i = 0; i < dev->num_vlans; i++) { 1063 vl = &dev->vlans[i]; 1064 if (vl->members) 1065 count++; 1066 } 1067 1068 return count; 1069 } 1070 1071 int b53_setup_devlink_resources(struct dsa_switch *ds) 1072 { 1073 struct devlink_resource_size_params size_params; 1074 struct b53_device *dev = ds->priv; 1075 int err; 1076 1077 devlink_resource_size_params_init(&size_params, dev->num_vlans, 1078 dev->num_vlans, 1079 1, DEVLINK_RESOURCE_UNIT_ENTRY); 1080 1081 err = dsa_devlink_resource_register(ds, "VLAN", dev->num_vlans, 1082 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1083 DEVLINK_RESOURCE_ID_PARENT_TOP, 1084 &size_params); 1085 if (err) 1086 goto out; 1087 1088 dsa_devlink_resource_occ_get_register(ds, 1089 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1090 b53_devlink_vlan_table_get, dev); 1091 1092 return 0; 1093 out: 1094 dsa_devlink_resources_unregister(ds); 1095 return err; 1096 } 1097 EXPORT_SYMBOL(b53_setup_devlink_resources); 1098 1099 static int b53_setup(struct dsa_switch *ds) 1100 { 1101 struct b53_device *dev = ds->priv; 1102 unsigned int port; 1103 int ret; 1104 1105 /* Request bridge PVID untagged when DSA_TAG_PROTO_NONE is set 1106 * which forces the CPU port to be tagged in all VLANs. 1107 */ 1108 ds->untag_bridge_pvid = dev->tag_protocol == DSA_TAG_PROTO_NONE; 1109 1110 ret = b53_reset_switch(dev); 1111 if (ret) { 1112 dev_err(ds->dev, "failed to reset switch\n"); 1113 return ret; 1114 } 1115 1116 b53_reset_mib(dev); 1117 1118 ret = b53_apply_config(dev); 1119 if (ret) { 1120 dev_err(ds->dev, "failed to apply configuration\n"); 1121 return ret; 1122 } 1123 1124 /* Configure IMP/CPU port, disable all other ports. Enabled 1125 * ports will be configured with .port_enable 1126 */ 1127 for (port = 0; port < dev->num_ports; port++) { 1128 if (dsa_is_cpu_port(ds, port)) 1129 b53_enable_cpu_port(dev, port); 1130 else 1131 b53_disable_port(ds, port); 1132 } 1133 1134 return b53_setup_devlink_resources(ds); 1135 } 1136 1137 static void b53_teardown(struct dsa_switch *ds) 1138 { 1139 dsa_devlink_resources_unregister(ds); 1140 } 1141 1142 static void b53_force_link(struct b53_device *dev, int port, int link) 1143 { 1144 u8 reg, val, off; 1145 1146 /* Override the port settings */ 1147 if (port == dev->imp_port) { 1148 off = B53_PORT_OVERRIDE_CTRL; 1149 val = PORT_OVERRIDE_EN; 1150 } else { 1151 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 1152 val = GMII_PO_EN; 1153 } 1154 1155 b53_read8(dev, B53_CTRL_PAGE, off, ®); 1156 reg |= val; 1157 if (link) 1158 reg |= PORT_OVERRIDE_LINK; 1159 else 1160 reg &= ~PORT_OVERRIDE_LINK; 1161 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1162 } 1163 1164 static void b53_force_port_config(struct b53_device *dev, int port, 1165 int speed, int duplex, 1166 bool tx_pause, bool rx_pause) 1167 { 1168 u8 reg, val, off; 1169 1170 /* Override the port settings */ 1171 if (port == dev->imp_port) { 1172 off = B53_PORT_OVERRIDE_CTRL; 1173 val = PORT_OVERRIDE_EN; 1174 } else { 1175 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 1176 val = GMII_PO_EN; 1177 } 1178 1179 b53_read8(dev, B53_CTRL_PAGE, off, ®); 1180 reg |= val; 1181 if (duplex == DUPLEX_FULL) 1182 reg |= PORT_OVERRIDE_FULL_DUPLEX; 1183 else 1184 reg &= ~PORT_OVERRIDE_FULL_DUPLEX; 1185 1186 switch (speed) { 1187 case 2000: 1188 reg |= PORT_OVERRIDE_SPEED_2000M; 1189 fallthrough; 1190 case SPEED_1000: 1191 reg |= PORT_OVERRIDE_SPEED_1000M; 1192 break; 1193 case SPEED_100: 1194 reg |= PORT_OVERRIDE_SPEED_100M; 1195 break; 1196 case SPEED_10: 1197 reg |= PORT_OVERRIDE_SPEED_10M; 1198 break; 1199 default: 1200 dev_err(dev->dev, "unknown speed: %d\n", speed); 1201 return; 1202 } 1203 1204 if (rx_pause) 1205 reg |= PORT_OVERRIDE_RX_FLOW; 1206 if (tx_pause) 1207 reg |= PORT_OVERRIDE_TX_FLOW; 1208 1209 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1210 } 1211 1212 static void b53_adjust_link(struct dsa_switch *ds, int port, 1213 struct phy_device *phydev) 1214 { 1215 struct b53_device *dev = ds->priv; 1216 struct ethtool_eee *p = &dev->ports[port].eee; 1217 u8 rgmii_ctrl = 0, reg = 0, off; 1218 bool tx_pause = false; 1219 bool rx_pause = false; 1220 1221 if (!phy_is_pseudo_fixed_link(phydev)) 1222 return; 1223 1224 /* Enable flow control on BCM5301x's CPU port */ 1225 if (is5301x(dev) && dsa_is_cpu_port(ds, port)) 1226 tx_pause = rx_pause = true; 1227 1228 if (phydev->pause) { 1229 if (phydev->asym_pause) 1230 tx_pause = true; 1231 rx_pause = true; 1232 } 1233 1234 b53_force_port_config(dev, port, phydev->speed, phydev->duplex, 1235 tx_pause, rx_pause); 1236 b53_force_link(dev, port, phydev->link); 1237 1238 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) { 1239 if (port == dev->imp_port) 1240 off = B53_RGMII_CTRL_IMP; 1241 else 1242 off = B53_RGMII_CTRL_P(port); 1243 1244 /* Configure the port RGMII clock delay by DLL disabled and 1245 * tx_clk aligned timing (restoring to reset defaults) 1246 */ 1247 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl); 1248 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC | 1249 RGMII_CTRL_TIMING_SEL); 1250 1251 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make 1252 * sure that we enable the port TX clock internal delay to 1253 * account for this internal delay that is inserted, otherwise 1254 * the switch won't be able to receive correctly. 1255 * 1256 * PHY_INTERFACE_MODE_RGMII means that we are not introducing 1257 * any delay neither on transmission nor reception, so the 1258 * BCM53125 must also be configured accordingly to account for 1259 * the lack of delay and introduce 1260 * 1261 * The BCM53125 switch has its RX clock and TX clock control 1262 * swapped, hence the reason why we modify the TX clock path in 1263 * the "RGMII" case 1264 */ 1265 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 1266 rgmii_ctrl |= RGMII_CTRL_DLL_TXC; 1267 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) 1268 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC; 1269 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL; 1270 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl); 1271 1272 dev_info(ds->dev, "Configured port %d for %s\n", port, 1273 phy_modes(phydev->interface)); 1274 } 1275 1276 /* configure MII port if necessary */ 1277 if (is5325(dev)) { 1278 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1279 ®); 1280 1281 /* reverse mii needs to be enabled */ 1282 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1283 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1284 reg | PORT_OVERRIDE_RV_MII_25); 1285 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1286 ®); 1287 1288 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1289 dev_err(ds->dev, 1290 "Failed to enable reverse MII mode\n"); 1291 return; 1292 } 1293 } 1294 } 1295 1296 /* Re-negotiate EEE if it was enabled already */ 1297 p->eee_enabled = b53_eee_init(ds, port, phydev); 1298 } 1299 1300 void b53_port_event(struct dsa_switch *ds, int port) 1301 { 1302 struct b53_device *dev = ds->priv; 1303 bool link; 1304 u16 sts; 1305 1306 b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts); 1307 link = !!(sts & BIT(port)); 1308 dsa_port_phylink_mac_change(ds, port, link); 1309 } 1310 EXPORT_SYMBOL(b53_port_event); 1311 1312 static void b53_phylink_get_caps(struct dsa_switch *ds, int port, 1313 struct phylink_config *config) 1314 { 1315 struct b53_device *dev = ds->priv; 1316 1317 /* Internal ports need GMII for PHYLIB */ 1318 __set_bit(PHY_INTERFACE_MODE_GMII, config->supported_interfaces); 1319 1320 /* These switches appear to support MII and RevMII too, but beyond 1321 * this, the code gives very few clues. FIXME: We probably need more 1322 * interface modes here. 1323 * 1324 * According to b53_srab_mux_init(), ports 3..5 can support: 1325 * SGMII, MII, GMII, RGMII or INTERNAL depending on the MUX setting. 1326 * However, the interface mode read from the MUX configuration is 1327 * not passed back to DSA, so phylink uses NA. 1328 * DT can specify RGMII for ports 0, 1. 1329 * For MDIO, port 8 can be RGMII_TXID. 1330 */ 1331 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 1332 __set_bit(PHY_INTERFACE_MODE_REVMII, config->supported_interfaces); 1333 1334 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 1335 MAC_10 | MAC_100; 1336 1337 /* 5325/5365 are not capable of gigabit speeds, everything else is. 1338 * Note: the original code also exclulded Gigagbit for MII, RevMII 1339 * and 802.3z modes. MII and RevMII are not able to work above 100M, 1340 * so will be excluded by the generic validator implementation. 1341 * However, the exclusion of Gigabit for 802.3z just seems wrong. 1342 */ 1343 if (!(is5325(dev) || is5365(dev))) 1344 config->mac_capabilities |= MAC_1000; 1345 1346 /* Get the implementation specific capabilities */ 1347 if (dev->ops->phylink_get_caps) 1348 dev->ops->phylink_get_caps(dev, port, config); 1349 1350 /* This driver does not make use of the speed, duplex, pause or the 1351 * advertisement in its mac_config, so it is safe to mark this driver 1352 * as non-legacy. 1353 */ 1354 config->legacy_pre_march2020 = false; 1355 } 1356 1357 static struct phylink_pcs *b53_phylink_mac_select_pcs(struct dsa_switch *ds, 1358 int port, 1359 phy_interface_t interface) 1360 { 1361 struct b53_device *dev = ds->priv; 1362 1363 if (!dev->ops->phylink_mac_select_pcs) 1364 return NULL; 1365 1366 return dev->ops->phylink_mac_select_pcs(dev, port, interface); 1367 } 1368 1369 void b53_phylink_mac_config(struct dsa_switch *ds, int port, 1370 unsigned int mode, 1371 const struct phylink_link_state *state) 1372 { 1373 } 1374 EXPORT_SYMBOL(b53_phylink_mac_config); 1375 1376 void b53_phylink_mac_link_down(struct dsa_switch *ds, int port, 1377 unsigned int mode, 1378 phy_interface_t interface) 1379 { 1380 struct b53_device *dev = ds->priv; 1381 1382 if (mode == MLO_AN_PHY) 1383 return; 1384 1385 if (mode == MLO_AN_FIXED) { 1386 b53_force_link(dev, port, false); 1387 return; 1388 } 1389 1390 if (phy_interface_mode_is_8023z(interface) && 1391 dev->ops->serdes_link_set) 1392 dev->ops->serdes_link_set(dev, port, mode, interface, false); 1393 } 1394 EXPORT_SYMBOL(b53_phylink_mac_link_down); 1395 1396 void b53_phylink_mac_link_up(struct dsa_switch *ds, int port, 1397 unsigned int mode, 1398 phy_interface_t interface, 1399 struct phy_device *phydev, 1400 int speed, int duplex, 1401 bool tx_pause, bool rx_pause) 1402 { 1403 struct b53_device *dev = ds->priv; 1404 1405 if (mode == MLO_AN_PHY) 1406 return; 1407 1408 if (mode == MLO_AN_FIXED) { 1409 b53_force_port_config(dev, port, speed, duplex, 1410 tx_pause, rx_pause); 1411 b53_force_link(dev, port, true); 1412 return; 1413 } 1414 1415 if (phy_interface_mode_is_8023z(interface) && 1416 dev->ops->serdes_link_set) 1417 dev->ops->serdes_link_set(dev, port, mode, interface, true); 1418 } 1419 EXPORT_SYMBOL(b53_phylink_mac_link_up); 1420 1421 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1422 struct netlink_ext_ack *extack) 1423 { 1424 struct b53_device *dev = ds->priv; 1425 1426 b53_enable_vlan(dev, port, dev->vlan_enabled, vlan_filtering); 1427 1428 return 0; 1429 } 1430 EXPORT_SYMBOL(b53_vlan_filtering); 1431 1432 static int b53_vlan_prepare(struct dsa_switch *ds, int port, 1433 const struct switchdev_obj_port_vlan *vlan) 1434 { 1435 struct b53_device *dev = ds->priv; 1436 1437 if ((is5325(dev) || is5365(dev)) && vlan->vid == 0) 1438 return -EOPNOTSUPP; 1439 1440 /* Port 7 on 7278 connects to the ASP's UniMAC which is not capable of 1441 * receiving VLAN tagged frames at all, we can still allow the port to 1442 * be configured for egress untagged. 1443 */ 1444 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7 && 1445 !(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)) 1446 return -EINVAL; 1447 1448 if (vlan->vid >= dev->num_vlans) 1449 return -ERANGE; 1450 1451 b53_enable_vlan(dev, port, true, ds->vlan_filtering); 1452 1453 return 0; 1454 } 1455 1456 int b53_vlan_add(struct dsa_switch *ds, int port, 1457 const struct switchdev_obj_port_vlan *vlan, 1458 struct netlink_ext_ack *extack) 1459 { 1460 struct b53_device *dev = ds->priv; 1461 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1462 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1463 struct b53_vlan *vl; 1464 int err; 1465 1466 err = b53_vlan_prepare(ds, port, vlan); 1467 if (err) 1468 return err; 1469 1470 vl = &dev->vlans[vlan->vid]; 1471 1472 b53_get_vlan_entry(dev, vlan->vid, vl); 1473 1474 if (vlan->vid == 0 && vlan->vid == b53_default_pvid(dev)) 1475 untagged = true; 1476 1477 vl->members |= BIT(port); 1478 if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port)) 1479 vl->untag |= BIT(port); 1480 else 1481 vl->untag &= ~BIT(port); 1482 1483 b53_set_vlan_entry(dev, vlan->vid, vl); 1484 b53_fast_age_vlan(dev, vlan->vid); 1485 1486 if (pvid && !dsa_is_cpu_port(ds, port)) { 1487 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), 1488 vlan->vid); 1489 b53_fast_age_vlan(dev, vlan->vid); 1490 } 1491 1492 return 0; 1493 } 1494 EXPORT_SYMBOL(b53_vlan_add); 1495 1496 int b53_vlan_del(struct dsa_switch *ds, int port, 1497 const struct switchdev_obj_port_vlan *vlan) 1498 { 1499 struct b53_device *dev = ds->priv; 1500 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1501 struct b53_vlan *vl; 1502 u16 pvid; 1503 1504 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid); 1505 1506 vl = &dev->vlans[vlan->vid]; 1507 1508 b53_get_vlan_entry(dev, vlan->vid, vl); 1509 1510 vl->members &= ~BIT(port); 1511 1512 if (pvid == vlan->vid) 1513 pvid = b53_default_pvid(dev); 1514 1515 if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port)) 1516 vl->untag &= ~(BIT(port)); 1517 1518 b53_set_vlan_entry(dev, vlan->vid, vl); 1519 b53_fast_age_vlan(dev, vlan->vid); 1520 1521 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid); 1522 b53_fast_age_vlan(dev, pvid); 1523 1524 return 0; 1525 } 1526 EXPORT_SYMBOL(b53_vlan_del); 1527 1528 /* Address Resolution Logic routines. Caller must hold &dev->arl_mutex. */ 1529 static int b53_arl_op_wait(struct b53_device *dev) 1530 { 1531 unsigned int timeout = 10; 1532 u8 reg; 1533 1534 do { 1535 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1536 if (!(reg & ARLTBL_START_DONE)) 1537 return 0; 1538 1539 usleep_range(1000, 2000); 1540 } while (timeout--); 1541 1542 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg); 1543 1544 return -ETIMEDOUT; 1545 } 1546 1547 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op) 1548 { 1549 u8 reg; 1550 1551 if (op > ARLTBL_RW) 1552 return -EINVAL; 1553 1554 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1555 reg |= ARLTBL_START_DONE; 1556 if (op) 1557 reg |= ARLTBL_RW; 1558 else 1559 reg &= ~ARLTBL_RW; 1560 if (dev->vlan_enabled) 1561 reg &= ~ARLTBL_IVL_SVL_SELECT; 1562 else 1563 reg |= ARLTBL_IVL_SVL_SELECT; 1564 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg); 1565 1566 return b53_arl_op_wait(dev); 1567 } 1568 1569 static int b53_arl_read(struct b53_device *dev, u64 mac, 1570 u16 vid, struct b53_arl_entry *ent, u8 *idx) 1571 { 1572 DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES); 1573 unsigned int i; 1574 int ret; 1575 1576 ret = b53_arl_op_wait(dev); 1577 if (ret) 1578 return ret; 1579 1580 bitmap_zero(free_bins, dev->num_arl_bins); 1581 1582 /* Read the bins */ 1583 for (i = 0; i < dev->num_arl_bins; i++) { 1584 u64 mac_vid; 1585 u32 fwd_entry; 1586 1587 b53_read64(dev, B53_ARLIO_PAGE, 1588 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid); 1589 b53_read32(dev, B53_ARLIO_PAGE, 1590 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry); 1591 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1592 1593 if (!(fwd_entry & ARLTBL_VALID)) { 1594 set_bit(i, free_bins); 1595 continue; 1596 } 1597 if ((mac_vid & ARLTBL_MAC_MASK) != mac) 1598 continue; 1599 if (dev->vlan_enabled && 1600 ((mac_vid >> ARLTBL_VID_S) & ARLTBL_VID_MASK) != vid) 1601 continue; 1602 *idx = i; 1603 return 0; 1604 } 1605 1606 if (bitmap_weight(free_bins, dev->num_arl_bins) == 0) 1607 return -ENOSPC; 1608 1609 *idx = find_first_bit(free_bins, dev->num_arl_bins); 1610 1611 return -ENOENT; 1612 } 1613 1614 static int b53_arl_op(struct b53_device *dev, int op, int port, 1615 const unsigned char *addr, u16 vid, bool is_valid) 1616 { 1617 struct b53_arl_entry ent; 1618 u32 fwd_entry; 1619 u64 mac, mac_vid = 0; 1620 u8 idx = 0; 1621 int ret; 1622 1623 /* Convert the array into a 64-bit MAC */ 1624 mac = ether_addr_to_u64(addr); 1625 1626 /* Perform a read for the given MAC and VID */ 1627 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac); 1628 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid); 1629 1630 /* Issue a read operation for this MAC */ 1631 ret = b53_arl_rw_op(dev, 1); 1632 if (ret) 1633 return ret; 1634 1635 ret = b53_arl_read(dev, mac, vid, &ent, &idx); 1636 1637 /* If this is a read, just finish now */ 1638 if (op) 1639 return ret; 1640 1641 switch (ret) { 1642 case -ETIMEDOUT: 1643 return ret; 1644 case -ENOSPC: 1645 dev_dbg(dev->dev, "{%pM,%.4d} no space left in ARL\n", 1646 addr, vid); 1647 return is_valid ? ret : 0; 1648 case -ENOENT: 1649 /* We could not find a matching MAC, so reset to a new entry */ 1650 dev_dbg(dev->dev, "{%pM,%.4d} not found, using idx: %d\n", 1651 addr, vid, idx); 1652 fwd_entry = 0; 1653 break; 1654 default: 1655 dev_dbg(dev->dev, "{%pM,%.4d} found, using idx: %d\n", 1656 addr, vid, idx); 1657 break; 1658 } 1659 1660 /* For multicast address, the port is a bitmask and the validity 1661 * is determined by having at least one port being still active 1662 */ 1663 if (!is_multicast_ether_addr(addr)) { 1664 ent.port = port; 1665 ent.is_valid = is_valid; 1666 } else { 1667 if (is_valid) 1668 ent.port |= BIT(port); 1669 else 1670 ent.port &= ~BIT(port); 1671 1672 ent.is_valid = !!(ent.port); 1673 } 1674 1675 ent.vid = vid; 1676 ent.is_static = true; 1677 ent.is_age = false; 1678 memcpy(ent.mac, addr, ETH_ALEN); 1679 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent); 1680 1681 b53_write64(dev, B53_ARLIO_PAGE, 1682 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid); 1683 b53_write32(dev, B53_ARLIO_PAGE, 1684 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry); 1685 1686 return b53_arl_rw_op(dev, 0); 1687 } 1688 1689 int b53_fdb_add(struct dsa_switch *ds, int port, 1690 const unsigned char *addr, u16 vid, 1691 struct dsa_db db) 1692 { 1693 struct b53_device *priv = ds->priv; 1694 int ret; 1695 1696 /* 5325 and 5365 require some more massaging, but could 1697 * be supported eventually 1698 */ 1699 if (is5325(priv) || is5365(priv)) 1700 return -EOPNOTSUPP; 1701 1702 mutex_lock(&priv->arl_mutex); 1703 ret = b53_arl_op(priv, 0, port, addr, vid, true); 1704 mutex_unlock(&priv->arl_mutex); 1705 1706 return ret; 1707 } 1708 EXPORT_SYMBOL(b53_fdb_add); 1709 1710 int b53_fdb_del(struct dsa_switch *ds, int port, 1711 const unsigned char *addr, u16 vid, 1712 struct dsa_db db) 1713 { 1714 struct b53_device *priv = ds->priv; 1715 int ret; 1716 1717 mutex_lock(&priv->arl_mutex); 1718 ret = b53_arl_op(priv, 0, port, addr, vid, false); 1719 mutex_unlock(&priv->arl_mutex); 1720 1721 return ret; 1722 } 1723 EXPORT_SYMBOL(b53_fdb_del); 1724 1725 static int b53_arl_search_wait(struct b53_device *dev) 1726 { 1727 unsigned int timeout = 1000; 1728 u8 reg; 1729 1730 do { 1731 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®); 1732 if (!(reg & ARL_SRCH_STDN)) 1733 return 0; 1734 1735 if (reg & ARL_SRCH_VLID) 1736 return 0; 1737 1738 usleep_range(1000, 2000); 1739 } while (timeout--); 1740 1741 return -ETIMEDOUT; 1742 } 1743 1744 static void b53_arl_search_rd(struct b53_device *dev, u8 idx, 1745 struct b53_arl_entry *ent) 1746 { 1747 u64 mac_vid; 1748 u32 fwd_entry; 1749 1750 b53_read64(dev, B53_ARLIO_PAGE, 1751 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid); 1752 b53_read32(dev, B53_ARLIO_PAGE, 1753 B53_ARL_SRCH_RSTL(idx), &fwd_entry); 1754 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1755 } 1756 1757 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent, 1758 dsa_fdb_dump_cb_t *cb, void *data) 1759 { 1760 if (!ent->is_valid) 1761 return 0; 1762 1763 if (port != ent->port) 1764 return 0; 1765 1766 return cb(ent->mac, ent->vid, ent->is_static, data); 1767 } 1768 1769 int b53_fdb_dump(struct dsa_switch *ds, int port, 1770 dsa_fdb_dump_cb_t *cb, void *data) 1771 { 1772 struct b53_device *priv = ds->priv; 1773 struct b53_arl_entry results[2]; 1774 unsigned int count = 0; 1775 int ret; 1776 u8 reg; 1777 1778 mutex_lock(&priv->arl_mutex); 1779 1780 /* Start search operation */ 1781 reg = ARL_SRCH_STDN; 1782 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg); 1783 1784 do { 1785 ret = b53_arl_search_wait(priv); 1786 if (ret) 1787 break; 1788 1789 b53_arl_search_rd(priv, 0, &results[0]); 1790 ret = b53_fdb_copy(port, &results[0], cb, data); 1791 if (ret) 1792 break; 1793 1794 if (priv->num_arl_bins > 2) { 1795 b53_arl_search_rd(priv, 1, &results[1]); 1796 ret = b53_fdb_copy(port, &results[1], cb, data); 1797 if (ret) 1798 break; 1799 1800 if (!results[0].is_valid && !results[1].is_valid) 1801 break; 1802 } 1803 1804 } while (count++ < b53_max_arl_entries(priv) / 2); 1805 1806 mutex_unlock(&priv->arl_mutex); 1807 1808 return 0; 1809 } 1810 EXPORT_SYMBOL(b53_fdb_dump); 1811 1812 int b53_mdb_add(struct dsa_switch *ds, int port, 1813 const struct switchdev_obj_port_mdb *mdb, 1814 struct dsa_db db) 1815 { 1816 struct b53_device *priv = ds->priv; 1817 int ret; 1818 1819 /* 5325 and 5365 require some more massaging, but could 1820 * be supported eventually 1821 */ 1822 if (is5325(priv) || is5365(priv)) 1823 return -EOPNOTSUPP; 1824 1825 mutex_lock(&priv->arl_mutex); 1826 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, true); 1827 mutex_unlock(&priv->arl_mutex); 1828 1829 return ret; 1830 } 1831 EXPORT_SYMBOL(b53_mdb_add); 1832 1833 int b53_mdb_del(struct dsa_switch *ds, int port, 1834 const struct switchdev_obj_port_mdb *mdb, 1835 struct dsa_db db) 1836 { 1837 struct b53_device *priv = ds->priv; 1838 int ret; 1839 1840 mutex_lock(&priv->arl_mutex); 1841 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, false); 1842 mutex_unlock(&priv->arl_mutex); 1843 if (ret) 1844 dev_err(ds->dev, "failed to delete MDB entry\n"); 1845 1846 return ret; 1847 } 1848 EXPORT_SYMBOL(b53_mdb_del); 1849 1850 int b53_br_join(struct dsa_switch *ds, int port, struct dsa_bridge bridge, 1851 bool *tx_fwd_offload, struct netlink_ext_ack *extack) 1852 { 1853 struct b53_device *dev = ds->priv; 1854 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 1855 u16 pvlan, reg; 1856 unsigned int i; 1857 1858 /* On 7278, port 7 which connects to the ASP should only receive 1859 * traffic from matching CFP rules. 1860 */ 1861 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7) 1862 return -EINVAL; 1863 1864 /* Make this port leave the all VLANs join since we will have proper 1865 * VLAN entries from now on 1866 */ 1867 if (is58xx(dev)) { 1868 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1869 reg &= ~BIT(port); 1870 if ((reg & BIT(cpu_port)) == BIT(cpu_port)) 1871 reg &= ~BIT(cpu_port); 1872 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1873 } 1874 1875 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1876 1877 b53_for_each_port(dev, i) { 1878 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge)) 1879 continue; 1880 1881 /* Add this local port to the remote port VLAN control 1882 * membership and update the remote port bitmask 1883 */ 1884 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1885 reg |= BIT(port); 1886 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1887 dev->ports[i].vlan_ctl_mask = reg; 1888 1889 pvlan |= BIT(i); 1890 } 1891 1892 /* Configure the local port VLAN control membership to include 1893 * remote ports and update the local port bitmask 1894 */ 1895 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1896 dev->ports[port].vlan_ctl_mask = pvlan; 1897 1898 return 0; 1899 } 1900 EXPORT_SYMBOL(b53_br_join); 1901 1902 void b53_br_leave(struct dsa_switch *ds, int port, struct dsa_bridge bridge) 1903 { 1904 struct b53_device *dev = ds->priv; 1905 struct b53_vlan *vl = &dev->vlans[0]; 1906 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 1907 unsigned int i; 1908 u16 pvlan, reg, pvid; 1909 1910 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1911 1912 b53_for_each_port(dev, i) { 1913 /* Don't touch the remaining ports */ 1914 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge)) 1915 continue; 1916 1917 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1918 reg &= ~BIT(port); 1919 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1920 dev->ports[port].vlan_ctl_mask = reg; 1921 1922 /* Prevent self removal to preserve isolation */ 1923 if (port != i) 1924 pvlan &= ~BIT(i); 1925 } 1926 1927 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1928 dev->ports[port].vlan_ctl_mask = pvlan; 1929 1930 pvid = b53_default_pvid(dev); 1931 1932 /* Make this port join all VLANs without VLAN entries */ 1933 if (is58xx(dev)) { 1934 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1935 reg |= BIT(port); 1936 if (!(reg & BIT(cpu_port))) 1937 reg |= BIT(cpu_port); 1938 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1939 } else { 1940 b53_get_vlan_entry(dev, pvid, vl); 1941 vl->members |= BIT(port) | BIT(cpu_port); 1942 vl->untag |= BIT(port) | BIT(cpu_port); 1943 b53_set_vlan_entry(dev, pvid, vl); 1944 } 1945 } 1946 EXPORT_SYMBOL(b53_br_leave); 1947 1948 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state) 1949 { 1950 struct b53_device *dev = ds->priv; 1951 u8 hw_state; 1952 u8 reg; 1953 1954 switch (state) { 1955 case BR_STATE_DISABLED: 1956 hw_state = PORT_CTRL_DIS_STATE; 1957 break; 1958 case BR_STATE_LISTENING: 1959 hw_state = PORT_CTRL_LISTEN_STATE; 1960 break; 1961 case BR_STATE_LEARNING: 1962 hw_state = PORT_CTRL_LEARN_STATE; 1963 break; 1964 case BR_STATE_FORWARDING: 1965 hw_state = PORT_CTRL_FWD_STATE; 1966 break; 1967 case BR_STATE_BLOCKING: 1968 hw_state = PORT_CTRL_BLOCK_STATE; 1969 break; 1970 default: 1971 dev_err(ds->dev, "invalid STP state: %d\n", state); 1972 return; 1973 } 1974 1975 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 1976 reg &= ~PORT_CTRL_STP_STATE_MASK; 1977 reg |= hw_state; 1978 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 1979 } 1980 EXPORT_SYMBOL(b53_br_set_stp_state); 1981 1982 void b53_br_fast_age(struct dsa_switch *ds, int port) 1983 { 1984 struct b53_device *dev = ds->priv; 1985 1986 if (b53_fast_age_port(dev, port)) 1987 dev_err(ds->dev, "fast ageing failed\n"); 1988 } 1989 EXPORT_SYMBOL(b53_br_fast_age); 1990 1991 int b53_br_flags_pre(struct dsa_switch *ds, int port, 1992 struct switchdev_brport_flags flags, 1993 struct netlink_ext_ack *extack) 1994 { 1995 if (flags.mask & ~(BR_FLOOD | BR_MCAST_FLOOD | BR_LEARNING)) 1996 return -EINVAL; 1997 1998 return 0; 1999 } 2000 EXPORT_SYMBOL(b53_br_flags_pre); 2001 2002 int b53_br_flags(struct dsa_switch *ds, int port, 2003 struct switchdev_brport_flags flags, 2004 struct netlink_ext_ack *extack) 2005 { 2006 if (flags.mask & BR_FLOOD) 2007 b53_port_set_ucast_flood(ds->priv, port, 2008 !!(flags.val & BR_FLOOD)); 2009 if (flags.mask & BR_MCAST_FLOOD) 2010 b53_port_set_mcast_flood(ds->priv, port, 2011 !!(flags.val & BR_MCAST_FLOOD)); 2012 if (flags.mask & BR_LEARNING) 2013 b53_port_set_learning(ds->priv, port, 2014 !!(flags.val & BR_LEARNING)); 2015 2016 return 0; 2017 } 2018 EXPORT_SYMBOL(b53_br_flags); 2019 2020 static bool b53_possible_cpu_port(struct dsa_switch *ds, int port) 2021 { 2022 /* Broadcom switches will accept enabling Broadcom tags on the 2023 * following ports: 5, 7 and 8, any other port is not supported 2024 */ 2025 switch (port) { 2026 case B53_CPU_PORT_25: 2027 case 7: 2028 case B53_CPU_PORT: 2029 return true; 2030 } 2031 2032 return false; 2033 } 2034 2035 static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port, 2036 enum dsa_tag_protocol tag_protocol) 2037 { 2038 bool ret = b53_possible_cpu_port(ds, port); 2039 2040 if (!ret) { 2041 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n", 2042 port); 2043 return ret; 2044 } 2045 2046 switch (tag_protocol) { 2047 case DSA_TAG_PROTO_BRCM: 2048 case DSA_TAG_PROTO_BRCM_PREPEND: 2049 dev_warn(ds->dev, 2050 "Port %d is stacked to Broadcom tag switch\n", port); 2051 ret = false; 2052 break; 2053 default: 2054 ret = true; 2055 break; 2056 } 2057 2058 return ret; 2059 } 2060 2061 enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port, 2062 enum dsa_tag_protocol mprot) 2063 { 2064 struct b53_device *dev = ds->priv; 2065 2066 if (!b53_can_enable_brcm_tags(ds, port, mprot)) { 2067 dev->tag_protocol = DSA_TAG_PROTO_NONE; 2068 goto out; 2069 } 2070 2071 /* Older models require a different 6 byte tag */ 2072 if (is5325(dev) || is5365(dev) || is63xx(dev)) { 2073 dev->tag_protocol = DSA_TAG_PROTO_BRCM_LEGACY; 2074 goto out; 2075 } 2076 2077 /* Broadcom BCM58xx chips have a flow accelerator on Port 8 2078 * which requires us to use the prepended Broadcom tag type 2079 */ 2080 if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT) { 2081 dev->tag_protocol = DSA_TAG_PROTO_BRCM_PREPEND; 2082 goto out; 2083 } 2084 2085 dev->tag_protocol = DSA_TAG_PROTO_BRCM; 2086 out: 2087 return dev->tag_protocol; 2088 } 2089 EXPORT_SYMBOL(b53_get_tag_protocol); 2090 2091 int b53_mirror_add(struct dsa_switch *ds, int port, 2092 struct dsa_mall_mirror_tc_entry *mirror, bool ingress, 2093 struct netlink_ext_ack *extack) 2094 { 2095 struct b53_device *dev = ds->priv; 2096 u16 reg, loc; 2097 2098 if (ingress) 2099 loc = B53_IG_MIR_CTL; 2100 else 2101 loc = B53_EG_MIR_CTL; 2102 2103 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 2104 reg |= BIT(port); 2105 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 2106 2107 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 2108 reg &= ~CAP_PORT_MASK; 2109 reg |= mirror->to_local_port; 2110 reg |= MIRROR_EN; 2111 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 2112 2113 return 0; 2114 } 2115 EXPORT_SYMBOL(b53_mirror_add); 2116 2117 void b53_mirror_del(struct dsa_switch *ds, int port, 2118 struct dsa_mall_mirror_tc_entry *mirror) 2119 { 2120 struct b53_device *dev = ds->priv; 2121 bool loc_disable = false, other_loc_disable = false; 2122 u16 reg, loc; 2123 2124 if (mirror->ingress) 2125 loc = B53_IG_MIR_CTL; 2126 else 2127 loc = B53_EG_MIR_CTL; 2128 2129 /* Update the desired ingress/egress register */ 2130 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 2131 reg &= ~BIT(port); 2132 if (!(reg & MIRROR_MASK)) 2133 loc_disable = true; 2134 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 2135 2136 /* Now look at the other one to know if we can disable mirroring 2137 * entirely 2138 */ 2139 if (mirror->ingress) 2140 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, ®); 2141 else 2142 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, ®); 2143 if (!(reg & MIRROR_MASK)) 2144 other_loc_disable = true; 2145 2146 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 2147 /* Both no longer have ports, let's disable mirroring */ 2148 if (loc_disable && other_loc_disable) { 2149 reg &= ~MIRROR_EN; 2150 reg &= ~mirror->to_local_port; 2151 } 2152 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 2153 } 2154 EXPORT_SYMBOL(b53_mirror_del); 2155 2156 void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable) 2157 { 2158 struct b53_device *dev = ds->priv; 2159 u16 reg; 2160 2161 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, ®); 2162 if (enable) 2163 reg |= BIT(port); 2164 else 2165 reg &= ~BIT(port); 2166 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg); 2167 } 2168 EXPORT_SYMBOL(b53_eee_enable_set); 2169 2170 2171 /* Returns 0 if EEE was not enabled, or 1 otherwise 2172 */ 2173 int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy) 2174 { 2175 int ret; 2176 2177 ret = phy_init_eee(phy, false); 2178 if (ret) 2179 return 0; 2180 2181 b53_eee_enable_set(ds, port, true); 2182 2183 return 1; 2184 } 2185 EXPORT_SYMBOL(b53_eee_init); 2186 2187 int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) 2188 { 2189 struct b53_device *dev = ds->priv; 2190 struct ethtool_eee *p = &dev->ports[port].eee; 2191 u16 reg; 2192 2193 if (is5325(dev) || is5365(dev)) 2194 return -EOPNOTSUPP; 2195 2196 b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, ®); 2197 e->eee_enabled = p->eee_enabled; 2198 e->eee_active = !!(reg & BIT(port)); 2199 2200 return 0; 2201 } 2202 EXPORT_SYMBOL(b53_get_mac_eee); 2203 2204 int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) 2205 { 2206 struct b53_device *dev = ds->priv; 2207 struct ethtool_eee *p = &dev->ports[port].eee; 2208 2209 if (is5325(dev) || is5365(dev)) 2210 return -EOPNOTSUPP; 2211 2212 p->eee_enabled = e->eee_enabled; 2213 b53_eee_enable_set(ds, port, e->eee_enabled); 2214 2215 return 0; 2216 } 2217 EXPORT_SYMBOL(b53_set_mac_eee); 2218 2219 static int b53_change_mtu(struct dsa_switch *ds, int port, int mtu) 2220 { 2221 struct b53_device *dev = ds->priv; 2222 bool enable_jumbo; 2223 bool allow_10_100; 2224 2225 if (is5325(dev) || is5365(dev)) 2226 return -EOPNOTSUPP; 2227 2228 enable_jumbo = (mtu >= JMS_MIN_SIZE); 2229 allow_10_100 = (dev->chip_id == BCM583XX_DEVICE_ID); 2230 2231 return b53_set_jumbo(dev, enable_jumbo, allow_10_100); 2232 } 2233 2234 static int b53_get_max_mtu(struct dsa_switch *ds, int port) 2235 { 2236 return JMS_MAX_SIZE; 2237 } 2238 2239 static const struct dsa_switch_ops b53_switch_ops = { 2240 .get_tag_protocol = b53_get_tag_protocol, 2241 .setup = b53_setup, 2242 .teardown = b53_teardown, 2243 .get_strings = b53_get_strings, 2244 .get_ethtool_stats = b53_get_ethtool_stats, 2245 .get_sset_count = b53_get_sset_count, 2246 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 2247 .phy_read = b53_phy_read16, 2248 .phy_write = b53_phy_write16, 2249 .adjust_link = b53_adjust_link, 2250 .phylink_get_caps = b53_phylink_get_caps, 2251 .phylink_mac_select_pcs = b53_phylink_mac_select_pcs, 2252 .phylink_mac_config = b53_phylink_mac_config, 2253 .phylink_mac_link_down = b53_phylink_mac_link_down, 2254 .phylink_mac_link_up = b53_phylink_mac_link_up, 2255 .port_enable = b53_enable_port, 2256 .port_disable = b53_disable_port, 2257 .get_mac_eee = b53_get_mac_eee, 2258 .set_mac_eee = b53_set_mac_eee, 2259 .port_bridge_join = b53_br_join, 2260 .port_bridge_leave = b53_br_leave, 2261 .port_pre_bridge_flags = b53_br_flags_pre, 2262 .port_bridge_flags = b53_br_flags, 2263 .port_stp_state_set = b53_br_set_stp_state, 2264 .port_fast_age = b53_br_fast_age, 2265 .port_vlan_filtering = b53_vlan_filtering, 2266 .port_vlan_add = b53_vlan_add, 2267 .port_vlan_del = b53_vlan_del, 2268 .port_fdb_dump = b53_fdb_dump, 2269 .port_fdb_add = b53_fdb_add, 2270 .port_fdb_del = b53_fdb_del, 2271 .port_mirror_add = b53_mirror_add, 2272 .port_mirror_del = b53_mirror_del, 2273 .port_mdb_add = b53_mdb_add, 2274 .port_mdb_del = b53_mdb_del, 2275 .port_max_mtu = b53_get_max_mtu, 2276 .port_change_mtu = b53_change_mtu, 2277 }; 2278 2279 struct b53_chip_data { 2280 u32 chip_id; 2281 const char *dev_name; 2282 u16 vlans; 2283 u16 enabled_ports; 2284 u8 imp_port; 2285 u8 cpu_port; 2286 u8 vta_regs[3]; 2287 u8 arl_bins; 2288 u16 arl_buckets; 2289 u8 duplex_reg; 2290 u8 jumbo_pm_reg; 2291 u8 jumbo_size_reg; 2292 }; 2293 2294 #define B53_VTA_REGS \ 2295 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY } 2296 #define B53_VTA_REGS_9798 \ 2297 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 } 2298 #define B53_VTA_REGS_63XX \ 2299 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX } 2300 2301 static const struct b53_chip_data b53_switch_chips[] = { 2302 { 2303 .chip_id = BCM5325_DEVICE_ID, 2304 .dev_name = "BCM5325", 2305 .vlans = 16, 2306 .enabled_ports = 0x3f, 2307 .arl_bins = 2, 2308 .arl_buckets = 1024, 2309 .imp_port = 5, 2310 .duplex_reg = B53_DUPLEX_STAT_FE, 2311 }, 2312 { 2313 .chip_id = BCM5365_DEVICE_ID, 2314 .dev_name = "BCM5365", 2315 .vlans = 256, 2316 .enabled_ports = 0x3f, 2317 .arl_bins = 2, 2318 .arl_buckets = 1024, 2319 .imp_port = 5, 2320 .duplex_reg = B53_DUPLEX_STAT_FE, 2321 }, 2322 { 2323 .chip_id = BCM5389_DEVICE_ID, 2324 .dev_name = "BCM5389", 2325 .vlans = 4096, 2326 .enabled_ports = 0x11f, 2327 .arl_bins = 4, 2328 .arl_buckets = 1024, 2329 .imp_port = 8, 2330 .vta_regs = B53_VTA_REGS, 2331 .duplex_reg = B53_DUPLEX_STAT_GE, 2332 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2333 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2334 }, 2335 { 2336 .chip_id = BCM5395_DEVICE_ID, 2337 .dev_name = "BCM5395", 2338 .vlans = 4096, 2339 .enabled_ports = 0x11f, 2340 .arl_bins = 4, 2341 .arl_buckets = 1024, 2342 .imp_port = 8, 2343 .vta_regs = B53_VTA_REGS, 2344 .duplex_reg = B53_DUPLEX_STAT_GE, 2345 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2346 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2347 }, 2348 { 2349 .chip_id = BCM5397_DEVICE_ID, 2350 .dev_name = "BCM5397", 2351 .vlans = 4096, 2352 .enabled_ports = 0x11f, 2353 .arl_bins = 4, 2354 .arl_buckets = 1024, 2355 .imp_port = 8, 2356 .vta_regs = B53_VTA_REGS_9798, 2357 .duplex_reg = B53_DUPLEX_STAT_GE, 2358 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2359 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2360 }, 2361 { 2362 .chip_id = BCM5398_DEVICE_ID, 2363 .dev_name = "BCM5398", 2364 .vlans = 4096, 2365 .enabled_ports = 0x17f, 2366 .arl_bins = 4, 2367 .arl_buckets = 1024, 2368 .imp_port = 8, 2369 .vta_regs = B53_VTA_REGS_9798, 2370 .duplex_reg = B53_DUPLEX_STAT_GE, 2371 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2372 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2373 }, 2374 { 2375 .chip_id = BCM53115_DEVICE_ID, 2376 .dev_name = "BCM53115", 2377 .vlans = 4096, 2378 .enabled_ports = 0x11f, 2379 .arl_bins = 4, 2380 .arl_buckets = 1024, 2381 .vta_regs = B53_VTA_REGS, 2382 .imp_port = 8, 2383 .duplex_reg = B53_DUPLEX_STAT_GE, 2384 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2385 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2386 }, 2387 { 2388 .chip_id = BCM53125_DEVICE_ID, 2389 .dev_name = "BCM53125", 2390 .vlans = 4096, 2391 .enabled_ports = 0x1ff, 2392 .arl_bins = 4, 2393 .arl_buckets = 1024, 2394 .imp_port = 8, 2395 .vta_regs = B53_VTA_REGS, 2396 .duplex_reg = B53_DUPLEX_STAT_GE, 2397 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2398 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2399 }, 2400 { 2401 .chip_id = BCM53128_DEVICE_ID, 2402 .dev_name = "BCM53128", 2403 .vlans = 4096, 2404 .enabled_ports = 0x1ff, 2405 .arl_bins = 4, 2406 .arl_buckets = 1024, 2407 .imp_port = 8, 2408 .vta_regs = B53_VTA_REGS, 2409 .duplex_reg = B53_DUPLEX_STAT_GE, 2410 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2411 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2412 }, 2413 { 2414 .chip_id = BCM63XX_DEVICE_ID, 2415 .dev_name = "BCM63xx", 2416 .vlans = 4096, 2417 .enabled_ports = 0, /* pdata must provide them */ 2418 .arl_bins = 4, 2419 .arl_buckets = 1024, 2420 .imp_port = 8, 2421 .vta_regs = B53_VTA_REGS_63XX, 2422 .duplex_reg = B53_DUPLEX_STAT_63XX, 2423 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, 2424 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, 2425 }, 2426 { 2427 .chip_id = BCM53010_DEVICE_ID, 2428 .dev_name = "BCM53010", 2429 .vlans = 4096, 2430 .enabled_ports = 0x1bf, 2431 .arl_bins = 4, 2432 .arl_buckets = 1024, 2433 .imp_port = 8, 2434 .vta_regs = B53_VTA_REGS, 2435 .duplex_reg = B53_DUPLEX_STAT_GE, 2436 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2437 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2438 }, 2439 { 2440 .chip_id = BCM53011_DEVICE_ID, 2441 .dev_name = "BCM53011", 2442 .vlans = 4096, 2443 .enabled_ports = 0x1bf, 2444 .arl_bins = 4, 2445 .arl_buckets = 1024, 2446 .imp_port = 8, 2447 .vta_regs = B53_VTA_REGS, 2448 .duplex_reg = B53_DUPLEX_STAT_GE, 2449 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2450 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2451 }, 2452 { 2453 .chip_id = BCM53012_DEVICE_ID, 2454 .dev_name = "BCM53012", 2455 .vlans = 4096, 2456 .enabled_ports = 0x1bf, 2457 .arl_bins = 4, 2458 .arl_buckets = 1024, 2459 .imp_port = 8, 2460 .vta_regs = B53_VTA_REGS, 2461 .duplex_reg = B53_DUPLEX_STAT_GE, 2462 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2463 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2464 }, 2465 { 2466 .chip_id = BCM53018_DEVICE_ID, 2467 .dev_name = "BCM53018", 2468 .vlans = 4096, 2469 .enabled_ports = 0x1bf, 2470 .arl_bins = 4, 2471 .arl_buckets = 1024, 2472 .imp_port = 8, 2473 .vta_regs = B53_VTA_REGS, 2474 .duplex_reg = B53_DUPLEX_STAT_GE, 2475 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2476 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2477 }, 2478 { 2479 .chip_id = BCM53019_DEVICE_ID, 2480 .dev_name = "BCM53019", 2481 .vlans = 4096, 2482 .enabled_ports = 0x1bf, 2483 .arl_bins = 4, 2484 .arl_buckets = 1024, 2485 .imp_port = 8, 2486 .vta_regs = B53_VTA_REGS, 2487 .duplex_reg = B53_DUPLEX_STAT_GE, 2488 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2489 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2490 }, 2491 { 2492 .chip_id = BCM58XX_DEVICE_ID, 2493 .dev_name = "BCM585xx/586xx/88312", 2494 .vlans = 4096, 2495 .enabled_ports = 0x1ff, 2496 .arl_bins = 4, 2497 .arl_buckets = 1024, 2498 .imp_port = 8, 2499 .vta_regs = B53_VTA_REGS, 2500 .duplex_reg = B53_DUPLEX_STAT_GE, 2501 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2502 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2503 }, 2504 { 2505 .chip_id = BCM583XX_DEVICE_ID, 2506 .dev_name = "BCM583xx/11360", 2507 .vlans = 4096, 2508 .enabled_ports = 0x103, 2509 .arl_bins = 4, 2510 .arl_buckets = 1024, 2511 .imp_port = 8, 2512 .vta_regs = B53_VTA_REGS, 2513 .duplex_reg = B53_DUPLEX_STAT_GE, 2514 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2515 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2516 }, 2517 /* Starfighter 2 */ 2518 { 2519 .chip_id = BCM4908_DEVICE_ID, 2520 .dev_name = "BCM4908", 2521 .vlans = 4096, 2522 .enabled_ports = 0x1bf, 2523 .arl_bins = 4, 2524 .arl_buckets = 256, 2525 .imp_port = 8, 2526 .vta_regs = B53_VTA_REGS, 2527 .duplex_reg = B53_DUPLEX_STAT_GE, 2528 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2529 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2530 }, 2531 { 2532 .chip_id = BCM7445_DEVICE_ID, 2533 .dev_name = "BCM7445", 2534 .vlans = 4096, 2535 .enabled_ports = 0x1ff, 2536 .arl_bins = 4, 2537 .arl_buckets = 1024, 2538 .imp_port = 8, 2539 .vta_regs = B53_VTA_REGS, 2540 .duplex_reg = B53_DUPLEX_STAT_GE, 2541 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2542 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2543 }, 2544 { 2545 .chip_id = BCM7278_DEVICE_ID, 2546 .dev_name = "BCM7278", 2547 .vlans = 4096, 2548 .enabled_ports = 0x1ff, 2549 .arl_bins = 4, 2550 .arl_buckets = 256, 2551 .imp_port = 8, 2552 .vta_regs = B53_VTA_REGS, 2553 .duplex_reg = B53_DUPLEX_STAT_GE, 2554 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2555 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2556 }, 2557 }; 2558 2559 static int b53_switch_init(struct b53_device *dev) 2560 { 2561 unsigned int i; 2562 int ret; 2563 2564 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) { 2565 const struct b53_chip_data *chip = &b53_switch_chips[i]; 2566 2567 if (chip->chip_id == dev->chip_id) { 2568 if (!dev->enabled_ports) 2569 dev->enabled_ports = chip->enabled_ports; 2570 dev->name = chip->dev_name; 2571 dev->duplex_reg = chip->duplex_reg; 2572 dev->vta_regs[0] = chip->vta_regs[0]; 2573 dev->vta_regs[1] = chip->vta_regs[1]; 2574 dev->vta_regs[2] = chip->vta_regs[2]; 2575 dev->jumbo_pm_reg = chip->jumbo_pm_reg; 2576 dev->imp_port = chip->imp_port; 2577 dev->num_vlans = chip->vlans; 2578 dev->num_arl_bins = chip->arl_bins; 2579 dev->num_arl_buckets = chip->arl_buckets; 2580 break; 2581 } 2582 } 2583 2584 /* check which BCM5325x version we have */ 2585 if (is5325(dev)) { 2586 u8 vc4; 2587 2588 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 2589 2590 /* check reserved bits */ 2591 switch (vc4 & 3) { 2592 case 1: 2593 /* BCM5325E */ 2594 break; 2595 case 3: 2596 /* BCM5325F - do not use port 4 */ 2597 dev->enabled_ports &= ~BIT(4); 2598 break; 2599 default: 2600 /* On the BCM47XX SoCs this is the supported internal switch.*/ 2601 #ifndef CONFIG_BCM47XX 2602 /* BCM5325M */ 2603 return -EINVAL; 2604 #else 2605 break; 2606 #endif 2607 } 2608 } 2609 2610 dev->num_ports = fls(dev->enabled_ports); 2611 2612 dev->ds->num_ports = min_t(unsigned int, dev->num_ports, DSA_MAX_PORTS); 2613 2614 /* Include non standard CPU port built-in PHYs to be probed */ 2615 if (is539x(dev) || is531x5(dev)) { 2616 for (i = 0; i < dev->num_ports; i++) { 2617 if (!(dev->ds->phys_mii_mask & BIT(i)) && 2618 !b53_possible_cpu_port(dev->ds, i)) 2619 dev->ds->phys_mii_mask |= BIT(i); 2620 } 2621 } 2622 2623 dev->ports = devm_kcalloc(dev->dev, 2624 dev->num_ports, sizeof(struct b53_port), 2625 GFP_KERNEL); 2626 if (!dev->ports) 2627 return -ENOMEM; 2628 2629 dev->vlans = devm_kcalloc(dev->dev, 2630 dev->num_vlans, sizeof(struct b53_vlan), 2631 GFP_KERNEL); 2632 if (!dev->vlans) 2633 return -ENOMEM; 2634 2635 dev->reset_gpio = b53_switch_get_reset_gpio(dev); 2636 if (dev->reset_gpio >= 0) { 2637 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio, 2638 GPIOF_OUT_INIT_HIGH, "robo_reset"); 2639 if (ret) 2640 return ret; 2641 } 2642 2643 return 0; 2644 } 2645 2646 struct b53_device *b53_switch_alloc(struct device *base, 2647 const struct b53_io_ops *ops, 2648 void *priv) 2649 { 2650 struct dsa_switch *ds; 2651 struct b53_device *dev; 2652 2653 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 2654 if (!ds) 2655 return NULL; 2656 2657 ds->dev = base; 2658 2659 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL); 2660 if (!dev) 2661 return NULL; 2662 2663 ds->priv = dev; 2664 dev->dev = base; 2665 2666 dev->ds = ds; 2667 dev->priv = priv; 2668 dev->ops = ops; 2669 ds->ops = &b53_switch_ops; 2670 dev->vlan_enabled = true; 2671 /* Let DSA handle the case were multiple bridges span the same switch 2672 * device and different VLAN awareness settings are requested, which 2673 * would be breaking filtering semantics for any of the other bridge 2674 * devices. (not hardware supported) 2675 */ 2676 ds->vlan_filtering_is_global = true; 2677 2678 mutex_init(&dev->reg_mutex); 2679 mutex_init(&dev->stats_mutex); 2680 mutex_init(&dev->arl_mutex); 2681 2682 return dev; 2683 } 2684 EXPORT_SYMBOL(b53_switch_alloc); 2685 2686 int b53_switch_detect(struct b53_device *dev) 2687 { 2688 u32 id32; 2689 u16 tmp; 2690 u8 id8; 2691 int ret; 2692 2693 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8); 2694 if (ret) 2695 return ret; 2696 2697 switch (id8) { 2698 case 0: 2699 /* BCM5325 and BCM5365 do not have this register so reads 2700 * return 0. But the read operation did succeed, so assume this 2701 * is one of them. 2702 * 2703 * Next check if we can write to the 5325's VTA register; for 2704 * 5365 it is read only. 2705 */ 2706 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf); 2707 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp); 2708 2709 if (tmp == 0xf) 2710 dev->chip_id = BCM5325_DEVICE_ID; 2711 else 2712 dev->chip_id = BCM5365_DEVICE_ID; 2713 break; 2714 case BCM5389_DEVICE_ID: 2715 case BCM5395_DEVICE_ID: 2716 case BCM5397_DEVICE_ID: 2717 case BCM5398_DEVICE_ID: 2718 dev->chip_id = id8; 2719 break; 2720 default: 2721 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32); 2722 if (ret) 2723 return ret; 2724 2725 switch (id32) { 2726 case BCM53115_DEVICE_ID: 2727 case BCM53125_DEVICE_ID: 2728 case BCM53128_DEVICE_ID: 2729 case BCM53010_DEVICE_ID: 2730 case BCM53011_DEVICE_ID: 2731 case BCM53012_DEVICE_ID: 2732 case BCM53018_DEVICE_ID: 2733 case BCM53019_DEVICE_ID: 2734 dev->chip_id = id32; 2735 break; 2736 default: 2737 dev_err(dev->dev, 2738 "unsupported switch detected (BCM53%02x/BCM%x)\n", 2739 id8, id32); 2740 return -ENODEV; 2741 } 2742 } 2743 2744 if (dev->chip_id == BCM5325_DEVICE_ID) 2745 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25, 2746 &dev->core_rev); 2747 else 2748 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID, 2749 &dev->core_rev); 2750 } 2751 EXPORT_SYMBOL(b53_switch_detect); 2752 2753 int b53_switch_register(struct b53_device *dev) 2754 { 2755 int ret; 2756 2757 if (dev->pdata) { 2758 dev->chip_id = dev->pdata->chip_id; 2759 dev->enabled_ports = dev->pdata->enabled_ports; 2760 } 2761 2762 if (!dev->chip_id && b53_switch_detect(dev)) 2763 return -EINVAL; 2764 2765 ret = b53_switch_init(dev); 2766 if (ret) 2767 return ret; 2768 2769 dev_info(dev->dev, "found switch: %s, rev %i\n", 2770 dev->name, dev->core_rev); 2771 2772 return dsa_register_switch(dev->ds); 2773 } 2774 EXPORT_SYMBOL(b53_switch_register); 2775 2776 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>"); 2777 MODULE_DESCRIPTION("B53 switch library"); 2778 MODULE_LICENSE("Dual BSD/GPL"); 2779