1 /* 2 * B53 switch driver main logic 3 * 4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org> 5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com> 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <linux/delay.h> 21 #include <linux/export.h> 22 #include <linux/gpio.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/platform_data/b53.h> 26 #include <linux/phy.h> 27 #include <linux/phylink.h> 28 #include <linux/etherdevice.h> 29 #include <linux/if_bridge.h> 30 #include <linux/if_vlan.h> 31 #include <net/dsa.h> 32 33 #include "b53_regs.h" 34 #include "b53_priv.h" 35 36 struct b53_mib_desc { 37 u8 size; 38 u8 offset; 39 const char *name; 40 }; 41 42 /* BCM5365 MIB counters */ 43 static const struct b53_mib_desc b53_mibs_65[] = { 44 { 8, 0x00, "TxOctets" }, 45 { 4, 0x08, "TxDropPkts" }, 46 { 4, 0x10, "TxBroadcastPkts" }, 47 { 4, 0x14, "TxMulticastPkts" }, 48 { 4, 0x18, "TxUnicastPkts" }, 49 { 4, 0x1c, "TxCollisions" }, 50 { 4, 0x20, "TxSingleCollision" }, 51 { 4, 0x24, "TxMultipleCollision" }, 52 { 4, 0x28, "TxDeferredTransmit" }, 53 { 4, 0x2c, "TxLateCollision" }, 54 { 4, 0x30, "TxExcessiveCollision" }, 55 { 4, 0x38, "TxPausePkts" }, 56 { 8, 0x44, "RxOctets" }, 57 { 4, 0x4c, "RxUndersizePkts" }, 58 { 4, 0x50, "RxPausePkts" }, 59 { 4, 0x54, "Pkts64Octets" }, 60 { 4, 0x58, "Pkts65to127Octets" }, 61 { 4, 0x5c, "Pkts128to255Octets" }, 62 { 4, 0x60, "Pkts256to511Octets" }, 63 { 4, 0x64, "Pkts512to1023Octets" }, 64 { 4, 0x68, "Pkts1024to1522Octets" }, 65 { 4, 0x6c, "RxOversizePkts" }, 66 { 4, 0x70, "RxJabbers" }, 67 { 4, 0x74, "RxAlignmentErrors" }, 68 { 4, 0x78, "RxFCSErrors" }, 69 { 8, 0x7c, "RxGoodOctets" }, 70 { 4, 0x84, "RxDropPkts" }, 71 { 4, 0x88, "RxUnicastPkts" }, 72 { 4, 0x8c, "RxMulticastPkts" }, 73 { 4, 0x90, "RxBroadcastPkts" }, 74 { 4, 0x94, "RxSAChanges" }, 75 { 4, 0x98, "RxFragments" }, 76 }; 77 78 #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65) 79 80 /* BCM63xx MIB counters */ 81 static const struct b53_mib_desc b53_mibs_63xx[] = { 82 { 8, 0x00, "TxOctets" }, 83 { 4, 0x08, "TxDropPkts" }, 84 { 4, 0x0c, "TxQoSPkts" }, 85 { 4, 0x10, "TxBroadcastPkts" }, 86 { 4, 0x14, "TxMulticastPkts" }, 87 { 4, 0x18, "TxUnicastPkts" }, 88 { 4, 0x1c, "TxCollisions" }, 89 { 4, 0x20, "TxSingleCollision" }, 90 { 4, 0x24, "TxMultipleCollision" }, 91 { 4, 0x28, "TxDeferredTransmit" }, 92 { 4, 0x2c, "TxLateCollision" }, 93 { 4, 0x30, "TxExcessiveCollision" }, 94 { 4, 0x38, "TxPausePkts" }, 95 { 8, 0x3c, "TxQoSOctets" }, 96 { 8, 0x44, "RxOctets" }, 97 { 4, 0x4c, "RxUndersizePkts" }, 98 { 4, 0x50, "RxPausePkts" }, 99 { 4, 0x54, "Pkts64Octets" }, 100 { 4, 0x58, "Pkts65to127Octets" }, 101 { 4, 0x5c, "Pkts128to255Octets" }, 102 { 4, 0x60, "Pkts256to511Octets" }, 103 { 4, 0x64, "Pkts512to1023Octets" }, 104 { 4, 0x68, "Pkts1024to1522Octets" }, 105 { 4, 0x6c, "RxOversizePkts" }, 106 { 4, 0x70, "RxJabbers" }, 107 { 4, 0x74, "RxAlignmentErrors" }, 108 { 4, 0x78, "RxFCSErrors" }, 109 { 8, 0x7c, "RxGoodOctets" }, 110 { 4, 0x84, "RxDropPkts" }, 111 { 4, 0x88, "RxUnicastPkts" }, 112 { 4, 0x8c, "RxMulticastPkts" }, 113 { 4, 0x90, "RxBroadcastPkts" }, 114 { 4, 0x94, "RxSAChanges" }, 115 { 4, 0x98, "RxFragments" }, 116 { 4, 0xa0, "RxSymbolErrors" }, 117 { 4, 0xa4, "RxQoSPkts" }, 118 { 8, 0xa8, "RxQoSOctets" }, 119 { 4, 0xb0, "Pkts1523to2047Octets" }, 120 { 4, 0xb4, "Pkts2048to4095Octets" }, 121 { 4, 0xb8, "Pkts4096to8191Octets" }, 122 { 4, 0xbc, "Pkts8192to9728Octets" }, 123 { 4, 0xc0, "RxDiscarded" }, 124 }; 125 126 #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx) 127 128 /* MIB counters */ 129 static const struct b53_mib_desc b53_mibs[] = { 130 { 8, 0x00, "TxOctets" }, 131 { 4, 0x08, "TxDropPkts" }, 132 { 4, 0x10, "TxBroadcastPkts" }, 133 { 4, 0x14, "TxMulticastPkts" }, 134 { 4, 0x18, "TxUnicastPkts" }, 135 { 4, 0x1c, "TxCollisions" }, 136 { 4, 0x20, "TxSingleCollision" }, 137 { 4, 0x24, "TxMultipleCollision" }, 138 { 4, 0x28, "TxDeferredTransmit" }, 139 { 4, 0x2c, "TxLateCollision" }, 140 { 4, 0x30, "TxExcessiveCollision" }, 141 { 4, 0x38, "TxPausePkts" }, 142 { 8, 0x50, "RxOctets" }, 143 { 4, 0x58, "RxUndersizePkts" }, 144 { 4, 0x5c, "RxPausePkts" }, 145 { 4, 0x60, "Pkts64Octets" }, 146 { 4, 0x64, "Pkts65to127Octets" }, 147 { 4, 0x68, "Pkts128to255Octets" }, 148 { 4, 0x6c, "Pkts256to511Octets" }, 149 { 4, 0x70, "Pkts512to1023Octets" }, 150 { 4, 0x74, "Pkts1024to1522Octets" }, 151 { 4, 0x78, "RxOversizePkts" }, 152 { 4, 0x7c, "RxJabbers" }, 153 { 4, 0x80, "RxAlignmentErrors" }, 154 { 4, 0x84, "RxFCSErrors" }, 155 { 8, 0x88, "RxGoodOctets" }, 156 { 4, 0x90, "RxDropPkts" }, 157 { 4, 0x94, "RxUnicastPkts" }, 158 { 4, 0x98, "RxMulticastPkts" }, 159 { 4, 0x9c, "RxBroadcastPkts" }, 160 { 4, 0xa0, "RxSAChanges" }, 161 { 4, 0xa4, "RxFragments" }, 162 { 4, 0xa8, "RxJumboPkts" }, 163 { 4, 0xac, "RxSymbolErrors" }, 164 { 4, 0xc0, "RxDiscarded" }, 165 }; 166 167 #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs) 168 169 static const struct b53_mib_desc b53_mibs_58xx[] = { 170 { 8, 0x00, "TxOctets" }, 171 { 4, 0x08, "TxDropPkts" }, 172 { 4, 0x0c, "TxQPKTQ0" }, 173 { 4, 0x10, "TxBroadcastPkts" }, 174 { 4, 0x14, "TxMulticastPkts" }, 175 { 4, 0x18, "TxUnicastPKts" }, 176 { 4, 0x1c, "TxCollisions" }, 177 { 4, 0x20, "TxSingleCollision" }, 178 { 4, 0x24, "TxMultipleCollision" }, 179 { 4, 0x28, "TxDeferredCollision" }, 180 { 4, 0x2c, "TxLateCollision" }, 181 { 4, 0x30, "TxExcessiveCollision" }, 182 { 4, 0x34, "TxFrameInDisc" }, 183 { 4, 0x38, "TxPausePkts" }, 184 { 4, 0x3c, "TxQPKTQ1" }, 185 { 4, 0x40, "TxQPKTQ2" }, 186 { 4, 0x44, "TxQPKTQ3" }, 187 { 4, 0x48, "TxQPKTQ4" }, 188 { 4, 0x4c, "TxQPKTQ5" }, 189 { 8, 0x50, "RxOctets" }, 190 { 4, 0x58, "RxUndersizePkts" }, 191 { 4, 0x5c, "RxPausePkts" }, 192 { 4, 0x60, "RxPkts64Octets" }, 193 { 4, 0x64, "RxPkts65to127Octets" }, 194 { 4, 0x68, "RxPkts128to255Octets" }, 195 { 4, 0x6c, "RxPkts256to511Octets" }, 196 { 4, 0x70, "RxPkts512to1023Octets" }, 197 { 4, 0x74, "RxPkts1024toMaxPktsOctets" }, 198 { 4, 0x78, "RxOversizePkts" }, 199 { 4, 0x7c, "RxJabbers" }, 200 { 4, 0x80, "RxAlignmentErrors" }, 201 { 4, 0x84, "RxFCSErrors" }, 202 { 8, 0x88, "RxGoodOctets" }, 203 { 4, 0x90, "RxDropPkts" }, 204 { 4, 0x94, "RxUnicastPkts" }, 205 { 4, 0x98, "RxMulticastPkts" }, 206 { 4, 0x9c, "RxBroadcastPkts" }, 207 { 4, 0xa0, "RxSAChanges" }, 208 { 4, 0xa4, "RxFragments" }, 209 { 4, 0xa8, "RxJumboPkt" }, 210 { 4, 0xac, "RxSymblErr" }, 211 { 4, 0xb0, "InRangeErrCount" }, 212 { 4, 0xb4, "OutRangeErrCount" }, 213 { 4, 0xb8, "EEELpiEvent" }, 214 { 4, 0xbc, "EEELpiDuration" }, 215 { 4, 0xc0, "RxDiscard" }, 216 { 4, 0xc8, "TxQPKTQ6" }, 217 { 4, 0xcc, "TxQPKTQ7" }, 218 { 4, 0xd0, "TxPkts64Octets" }, 219 { 4, 0xd4, "TxPkts65to127Octets" }, 220 { 4, 0xd8, "TxPkts128to255Octets" }, 221 { 4, 0xdc, "TxPkts256to511Ocets" }, 222 { 4, 0xe0, "TxPkts512to1023Ocets" }, 223 { 4, 0xe4, "TxPkts1024toMaxPktOcets" }, 224 }; 225 226 #define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx) 227 228 #define B53_MAX_MTU_25 (1536 - ETH_HLEN - VLAN_HLEN - ETH_FCS_LEN) 229 #define B53_MAX_MTU (9720 - ETH_HLEN - VLAN_HLEN - ETH_FCS_LEN) 230 231 static int b53_do_vlan_op(struct b53_device *dev, u8 op) 232 { 233 unsigned int i; 234 235 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op); 236 237 for (i = 0; i < 10; i++) { 238 u8 vta; 239 240 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta); 241 if (!(vta & VTA_START_CMD)) 242 return 0; 243 244 usleep_range(100, 200); 245 } 246 247 return -EIO; 248 } 249 250 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, 251 struct b53_vlan *vlan) 252 { 253 if (is5325(dev)) { 254 u32 entry = 0; 255 256 if (vlan->members) { 257 entry = ((vlan->untag & VA_UNTAG_MASK_25) << 258 VA_UNTAG_S_25) | vlan->members; 259 if (dev->core_rev >= 3) 260 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S; 261 else 262 entry |= VA_VALID_25; 263 } 264 265 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry); 266 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 267 VTA_RW_STATE_WR | VTA_RW_OP_EN); 268 } else if (is5365(dev)) { 269 u16 entry = 0; 270 271 if (vlan->members) 272 entry = ((vlan->untag & VA_UNTAG_MASK_65) << 273 VA_UNTAG_S_65) | vlan->members | VA_VALID_65; 274 275 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry); 276 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 277 VTA_RW_STATE_WR | VTA_RW_OP_EN); 278 } else { 279 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 280 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], 281 (vlan->untag << VTE_UNTAG_S) | vlan->members); 282 283 b53_do_vlan_op(dev, VTA_CMD_WRITE); 284 } 285 286 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n", 287 vid, vlan->members, vlan->untag); 288 } 289 290 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid, 291 struct b53_vlan *vlan) 292 { 293 if (is5325(dev)) { 294 u32 entry = 0; 295 296 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 297 VTA_RW_STATE_RD | VTA_RW_OP_EN); 298 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry); 299 300 if (dev->core_rev >= 3) 301 vlan->valid = !!(entry & VA_VALID_25_R4); 302 else 303 vlan->valid = !!(entry & VA_VALID_25); 304 vlan->members = entry & VA_MEMBER_MASK; 305 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25; 306 307 } else if (is5365(dev)) { 308 u16 entry = 0; 309 310 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 311 VTA_RW_STATE_WR | VTA_RW_OP_EN); 312 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry); 313 314 vlan->valid = !!(entry & VA_VALID_65); 315 vlan->members = entry & VA_MEMBER_MASK; 316 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65; 317 } else { 318 u32 entry = 0; 319 320 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 321 b53_do_vlan_op(dev, VTA_CMD_READ); 322 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry); 323 vlan->members = entry & VTE_MEMBERS; 324 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS; 325 vlan->valid = true; 326 } 327 } 328 329 static void b53_set_forwarding(struct b53_device *dev, int enable) 330 { 331 u8 mgmt; 332 333 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 334 335 if (enable) 336 mgmt |= SM_SW_FWD_EN; 337 else 338 mgmt &= ~SM_SW_FWD_EN; 339 340 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 341 342 /* Include IMP port in dumb forwarding mode 343 */ 344 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt); 345 mgmt |= B53_MII_DUMB_FWDG_EN; 346 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt); 347 348 /* Look at B53_UC_FWD_EN and B53_MC_FWD_EN to decide whether 349 * frames should be flooded or not. 350 */ 351 b53_read8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, &mgmt); 352 mgmt |= B53_UC_FWD_EN | B53_MC_FWD_EN | B53_IPMC_FWD_EN; 353 b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt); 354 } 355 356 static void b53_enable_vlan(struct b53_device *dev, int port, bool enable, 357 bool enable_filtering) 358 { 359 u8 mgmt, vc0, vc1, vc4 = 0, vc5; 360 361 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 362 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0); 363 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1); 364 365 if (is5325(dev) || is5365(dev)) { 366 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 367 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5); 368 } else if (is63xx(dev)) { 369 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4); 370 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5); 371 } else { 372 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4); 373 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5); 374 } 375 376 if (enable) { 377 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID; 378 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN; 379 vc4 &= ~VC4_ING_VID_CHECK_MASK; 380 if (enable_filtering) { 381 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S; 382 vc5 |= VC5_DROP_VTABLE_MISS; 383 } else { 384 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 385 vc5 &= ~VC5_DROP_VTABLE_MISS; 386 } 387 388 if (is5325(dev)) 389 vc0 &= ~VC0_RESERVED_1; 390 391 if (is5325(dev) || is5365(dev)) 392 vc1 |= VC1_RX_MCST_TAG_EN; 393 394 } else { 395 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID); 396 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN); 397 vc4 &= ~VC4_ING_VID_CHECK_MASK; 398 vc5 &= ~VC5_DROP_VTABLE_MISS; 399 400 if (is5325(dev) || is5365(dev)) 401 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 402 else 403 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S; 404 405 if (is5325(dev) || is5365(dev)) 406 vc1 &= ~VC1_RX_MCST_TAG_EN; 407 } 408 409 if (!is5325(dev) && !is5365(dev)) 410 vc5 &= ~VC5_VID_FFF_EN; 411 412 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0); 413 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1); 414 415 if (is5325(dev) || is5365(dev)) { 416 /* enable the high 8 bit vid check on 5325 */ 417 if (is5325(dev) && enable) 418 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 419 VC3_HIGH_8BIT_EN); 420 else 421 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 422 423 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4); 424 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5); 425 } else if (is63xx(dev)) { 426 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0); 427 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4); 428 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5); 429 } else { 430 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 431 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4); 432 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5); 433 } 434 435 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 436 437 dev->vlan_enabled = enable; 438 439 dev_dbg(dev->dev, "Port %d VLAN enabled: %d, filtering: %d\n", 440 port, enable, enable_filtering); 441 } 442 443 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100) 444 { 445 u32 port_mask = 0; 446 u16 max_size = JMS_MIN_SIZE; 447 448 if (is5325(dev) || is5365(dev)) 449 return -EINVAL; 450 451 if (enable) { 452 port_mask = dev->enabled_ports; 453 max_size = JMS_MAX_SIZE; 454 if (allow_10_100) 455 port_mask |= JPM_10_100_JUMBO_EN; 456 } 457 458 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask); 459 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size); 460 } 461 462 static int b53_flush_arl(struct b53_device *dev, u8 mask) 463 { 464 unsigned int i; 465 466 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 467 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask); 468 469 for (i = 0; i < 10; i++) { 470 u8 fast_age_ctrl; 471 472 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 473 &fast_age_ctrl); 474 475 if (!(fast_age_ctrl & FAST_AGE_DONE)) 476 goto out; 477 478 msleep(1); 479 } 480 481 return -ETIMEDOUT; 482 out: 483 /* Only age dynamic entries (default behavior) */ 484 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC); 485 return 0; 486 } 487 488 static int b53_fast_age_port(struct b53_device *dev, int port) 489 { 490 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port); 491 492 return b53_flush_arl(dev, FAST_AGE_PORT); 493 } 494 495 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid) 496 { 497 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid); 498 499 return b53_flush_arl(dev, FAST_AGE_VLAN); 500 } 501 502 void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port) 503 { 504 struct b53_device *dev = ds->priv; 505 unsigned int i; 506 u16 pvlan; 507 508 /* Enable the IMP port to be in the same VLAN as the other ports 509 * on a per-port basis such that we only have Port i and IMP in 510 * the same VLAN. 511 */ 512 b53_for_each_port(dev, i) { 513 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan); 514 pvlan |= BIT(cpu_port); 515 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan); 516 } 517 } 518 EXPORT_SYMBOL(b53_imp_vlan_setup); 519 520 static void b53_port_set_ucast_flood(struct b53_device *dev, int port, 521 bool unicast) 522 { 523 u16 uc; 524 525 b53_read16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, &uc); 526 if (unicast) 527 uc |= BIT(port); 528 else 529 uc &= ~BIT(port); 530 b53_write16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, uc); 531 } 532 533 static void b53_port_set_mcast_flood(struct b53_device *dev, int port, 534 bool multicast) 535 { 536 u16 mc; 537 538 b53_read16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, &mc); 539 if (multicast) 540 mc |= BIT(port); 541 else 542 mc &= ~BIT(port); 543 b53_write16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, mc); 544 545 b53_read16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, &mc); 546 if (multicast) 547 mc |= BIT(port); 548 else 549 mc &= ~BIT(port); 550 b53_write16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, mc); 551 } 552 553 static void b53_port_set_learning(struct b53_device *dev, int port, 554 bool learning) 555 { 556 u16 reg; 557 558 b53_read16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, ®); 559 if (learning) 560 reg &= ~BIT(port); 561 else 562 reg |= BIT(port); 563 b53_write16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, reg); 564 } 565 566 static void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable) 567 { 568 struct b53_device *dev = ds->priv; 569 u16 reg; 570 571 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, ®); 572 if (enable) 573 reg |= BIT(port); 574 else 575 reg &= ~BIT(port); 576 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg); 577 } 578 579 int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy) 580 { 581 struct b53_device *dev = ds->priv; 582 unsigned int cpu_port; 583 int ret = 0; 584 u16 pvlan; 585 586 if (!dsa_is_user_port(ds, port)) 587 return 0; 588 589 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 590 591 b53_port_set_ucast_flood(dev, port, true); 592 b53_port_set_mcast_flood(dev, port, true); 593 b53_port_set_learning(dev, port, false); 594 595 if (dev->ops->irq_enable) 596 ret = dev->ops->irq_enable(dev, port); 597 if (ret) 598 return ret; 599 600 /* Clear the Rx and Tx disable bits and set to no spanning tree */ 601 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0); 602 603 /* Set this port, and only this one to be in the default VLAN, 604 * if member of a bridge, restore its membership prior to 605 * bringing down this port. 606 */ 607 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 608 pvlan &= ~0x1ff; 609 pvlan |= BIT(port); 610 pvlan |= dev->ports[port].vlan_ctl_mask; 611 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 612 613 b53_imp_vlan_setup(ds, cpu_port); 614 615 /* If EEE was enabled, restore it */ 616 if (dev->ports[port].eee.eee_enabled) 617 b53_eee_enable_set(ds, port, true); 618 619 return 0; 620 } 621 EXPORT_SYMBOL(b53_enable_port); 622 623 void b53_disable_port(struct dsa_switch *ds, int port) 624 { 625 struct b53_device *dev = ds->priv; 626 u8 reg; 627 628 /* Disable Tx/Rx for the port */ 629 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 630 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE; 631 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 632 633 if (dev->ops->irq_disable) 634 dev->ops->irq_disable(dev, port); 635 } 636 EXPORT_SYMBOL(b53_disable_port); 637 638 void b53_brcm_hdr_setup(struct dsa_switch *ds, int port) 639 { 640 struct b53_device *dev = ds->priv; 641 bool tag_en = !(dev->tag_protocol == DSA_TAG_PROTO_NONE); 642 u8 hdr_ctl, val; 643 u16 reg; 644 645 /* Resolve which bit controls the Broadcom tag */ 646 switch (port) { 647 case 8: 648 val = BRCM_HDR_P8_EN; 649 break; 650 case 7: 651 val = BRCM_HDR_P7_EN; 652 break; 653 case 5: 654 val = BRCM_HDR_P5_EN; 655 break; 656 default: 657 val = 0; 658 break; 659 } 660 661 /* Enable management mode if tagging is requested */ 662 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &hdr_ctl); 663 if (tag_en) 664 hdr_ctl |= SM_SW_FWD_MODE; 665 else 666 hdr_ctl &= ~SM_SW_FWD_MODE; 667 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, hdr_ctl); 668 669 /* Configure the appropriate IMP port */ 670 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &hdr_ctl); 671 if (port == 8) 672 hdr_ctl |= GC_FRM_MGMT_PORT_MII; 673 else if (port == 5) 674 hdr_ctl |= GC_FRM_MGMT_PORT_M; 675 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, hdr_ctl); 676 677 /* Enable Broadcom tags for IMP port */ 678 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl); 679 if (tag_en) 680 hdr_ctl |= val; 681 else 682 hdr_ctl &= ~val; 683 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl); 684 685 /* Registers below are only accessible on newer devices */ 686 if (!is58xx(dev)) 687 return; 688 689 /* Enable reception Broadcom tag for CPU TX (switch RX) to 690 * allow us to tag outgoing frames 691 */ 692 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, ®); 693 if (tag_en) 694 reg &= ~BIT(port); 695 else 696 reg |= BIT(port); 697 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg); 698 699 /* Enable transmission of Broadcom tags from the switch (CPU RX) to 700 * allow delivering frames to the per-port net_devices 701 */ 702 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, ®); 703 if (tag_en) 704 reg &= ~BIT(port); 705 else 706 reg |= BIT(port); 707 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg); 708 } 709 EXPORT_SYMBOL(b53_brcm_hdr_setup); 710 711 static void b53_enable_cpu_port(struct b53_device *dev, int port) 712 { 713 u8 port_ctrl; 714 715 /* BCM5325 CPU port is at 8 */ 716 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25) 717 port = B53_CPU_PORT; 718 719 port_ctrl = PORT_CTRL_RX_BCST_EN | 720 PORT_CTRL_RX_MCST_EN | 721 PORT_CTRL_RX_UCST_EN; 722 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl); 723 724 b53_brcm_hdr_setup(dev->ds, port); 725 726 b53_port_set_ucast_flood(dev, port, true); 727 b53_port_set_mcast_flood(dev, port, true); 728 b53_port_set_learning(dev, port, false); 729 } 730 731 static void b53_enable_mib(struct b53_device *dev) 732 { 733 u8 gc; 734 735 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 736 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN); 737 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc); 738 } 739 740 static void b53_enable_stp(struct b53_device *dev) 741 { 742 u8 gc; 743 744 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 745 gc |= GC_RX_BPDU_EN; 746 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc); 747 } 748 749 static u16 b53_default_pvid(struct b53_device *dev) 750 { 751 if (is5325(dev) || is5365(dev)) 752 return 1; 753 else 754 return 0; 755 } 756 757 static bool b53_vlan_port_needs_forced_tagged(struct dsa_switch *ds, int port) 758 { 759 struct b53_device *dev = ds->priv; 760 761 return dev->tag_protocol == DSA_TAG_PROTO_NONE && dsa_is_cpu_port(ds, port); 762 } 763 764 int b53_configure_vlan(struct dsa_switch *ds) 765 { 766 struct b53_device *dev = ds->priv; 767 struct b53_vlan vl = { 0 }; 768 struct b53_vlan *v; 769 int i, def_vid; 770 u16 vid; 771 772 def_vid = b53_default_pvid(dev); 773 774 /* clear all vlan entries */ 775 if (is5325(dev) || is5365(dev)) { 776 for (i = def_vid; i < dev->num_vlans; i++) 777 b53_set_vlan_entry(dev, i, &vl); 778 } else { 779 b53_do_vlan_op(dev, VTA_CMD_CLEAR); 780 } 781 782 b53_enable_vlan(dev, -1, dev->vlan_enabled, ds->vlan_filtering); 783 784 /* Create an untagged VLAN entry for the default PVID in case 785 * CONFIG_VLAN_8021Q is disabled and there are no calls to 786 * dsa_user_vlan_rx_add_vid() to create the default VLAN 787 * entry. Do this only when the tagging protocol is not 788 * DSA_TAG_PROTO_NONE 789 */ 790 b53_for_each_port(dev, i) { 791 v = &dev->vlans[def_vid]; 792 v->members |= BIT(i); 793 if (!b53_vlan_port_needs_forced_tagged(ds, i)) 794 v->untag = v->members; 795 b53_write16(dev, B53_VLAN_PAGE, 796 B53_VLAN_PORT_DEF_TAG(i), def_vid); 797 } 798 799 /* Upon initial call we have not set-up any VLANs, but upon 800 * system resume, we need to restore all VLAN entries. 801 */ 802 for (vid = def_vid; vid < dev->num_vlans; vid++) { 803 v = &dev->vlans[vid]; 804 805 if (!v->members) 806 continue; 807 808 b53_set_vlan_entry(dev, vid, v); 809 b53_fast_age_vlan(dev, vid); 810 } 811 812 return 0; 813 } 814 EXPORT_SYMBOL(b53_configure_vlan); 815 816 static void b53_switch_reset_gpio(struct b53_device *dev) 817 { 818 int gpio = dev->reset_gpio; 819 820 if (gpio < 0) 821 return; 822 823 /* Reset sequence: RESET low(50ms)->high(20ms) 824 */ 825 gpio_set_value(gpio, 0); 826 mdelay(50); 827 828 gpio_set_value(gpio, 1); 829 mdelay(20); 830 831 dev->current_page = 0xff; 832 } 833 834 static int b53_switch_reset(struct b53_device *dev) 835 { 836 unsigned int timeout = 1000; 837 u8 mgmt, reg; 838 839 b53_switch_reset_gpio(dev); 840 841 if (is539x(dev)) { 842 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83); 843 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00); 844 } 845 846 /* This is specific to 58xx devices here, do not use is58xx() which 847 * covers the larger Starfigther 2 family, including 7445/7278 which 848 * still use this driver as a library and need to perform the reset 849 * earlier. 850 */ 851 if (dev->chip_id == BCM58XX_DEVICE_ID || 852 dev->chip_id == BCM583XX_DEVICE_ID) { 853 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 854 reg |= SW_RST | EN_SW_RST | EN_CH_RST; 855 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg); 856 857 do { 858 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 859 if (!(reg & SW_RST)) 860 break; 861 862 usleep_range(1000, 2000); 863 } while (timeout-- > 0); 864 865 if (timeout == 0) { 866 dev_err(dev->dev, 867 "Timeout waiting for SW_RST to clear!\n"); 868 return -ETIMEDOUT; 869 } 870 } 871 872 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 873 874 if (!(mgmt & SM_SW_FWD_EN)) { 875 mgmt &= ~SM_SW_FWD_MODE; 876 mgmt |= SM_SW_FWD_EN; 877 878 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 879 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 880 881 if (!(mgmt & SM_SW_FWD_EN)) { 882 dev_err(dev->dev, "Failed to enable switch!\n"); 883 return -EINVAL; 884 } 885 } 886 887 b53_enable_mib(dev); 888 b53_enable_stp(dev); 889 890 return b53_flush_arl(dev, FAST_AGE_STATIC); 891 } 892 893 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg) 894 { 895 struct b53_device *priv = ds->priv; 896 u16 value = 0; 897 int ret; 898 899 if (priv->ops->phy_read16) 900 ret = priv->ops->phy_read16(priv, addr, reg, &value); 901 else 902 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr), 903 reg * 2, &value); 904 905 return ret ? ret : value; 906 } 907 908 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 909 { 910 struct b53_device *priv = ds->priv; 911 912 if (priv->ops->phy_write16) 913 return priv->ops->phy_write16(priv, addr, reg, val); 914 915 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val); 916 } 917 918 static int b53_reset_switch(struct b53_device *priv) 919 { 920 /* reset vlans */ 921 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans); 922 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports); 923 924 priv->serdes_lane = B53_INVALID_LANE; 925 926 return b53_switch_reset(priv); 927 } 928 929 static int b53_apply_config(struct b53_device *priv) 930 { 931 /* disable switching */ 932 b53_set_forwarding(priv, 0); 933 934 b53_configure_vlan(priv->ds); 935 936 /* enable switching */ 937 b53_set_forwarding(priv, 1); 938 939 return 0; 940 } 941 942 static void b53_reset_mib(struct b53_device *priv) 943 { 944 u8 gc; 945 946 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 947 948 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB); 949 msleep(1); 950 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB); 951 msleep(1); 952 } 953 954 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev) 955 { 956 if (is5365(dev)) 957 return b53_mibs_65; 958 else if (is63xx(dev)) 959 return b53_mibs_63xx; 960 else if (is58xx(dev)) 961 return b53_mibs_58xx; 962 else 963 return b53_mibs; 964 } 965 966 static unsigned int b53_get_mib_size(struct b53_device *dev) 967 { 968 if (is5365(dev)) 969 return B53_MIBS_65_SIZE; 970 else if (is63xx(dev)) 971 return B53_MIBS_63XX_SIZE; 972 else if (is58xx(dev)) 973 return B53_MIBS_58XX_SIZE; 974 else 975 return B53_MIBS_SIZE; 976 } 977 978 static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port) 979 { 980 /* These ports typically do not have built-in PHYs */ 981 switch (port) { 982 case B53_CPU_PORT_25: 983 case 7: 984 case B53_CPU_PORT: 985 return NULL; 986 } 987 988 return mdiobus_get_phy(ds->user_mii_bus, port); 989 } 990 991 void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset, 992 uint8_t *data) 993 { 994 struct b53_device *dev = ds->priv; 995 const struct b53_mib_desc *mibs = b53_get_mib(dev); 996 unsigned int mib_size = b53_get_mib_size(dev); 997 struct phy_device *phydev; 998 unsigned int i; 999 1000 if (stringset == ETH_SS_STATS) { 1001 for (i = 0; i < mib_size; i++) 1002 ethtool_puts(&data, mibs[i].name); 1003 } else if (stringset == ETH_SS_PHY_STATS) { 1004 phydev = b53_get_phy_device(ds, port); 1005 if (!phydev) 1006 return; 1007 1008 phy_ethtool_get_strings(phydev, data); 1009 } 1010 } 1011 EXPORT_SYMBOL(b53_get_strings); 1012 1013 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) 1014 { 1015 struct b53_device *dev = ds->priv; 1016 const struct b53_mib_desc *mibs = b53_get_mib(dev); 1017 unsigned int mib_size = b53_get_mib_size(dev); 1018 const struct b53_mib_desc *s; 1019 unsigned int i; 1020 u64 val = 0; 1021 1022 if (is5365(dev) && port == 5) 1023 port = 8; 1024 1025 mutex_lock(&dev->stats_mutex); 1026 1027 for (i = 0; i < mib_size; i++) { 1028 s = &mibs[i]; 1029 1030 if (s->size == 8) { 1031 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val); 1032 } else { 1033 u32 val32; 1034 1035 b53_read32(dev, B53_MIB_PAGE(port), s->offset, 1036 &val32); 1037 val = val32; 1038 } 1039 data[i] = (u64)val; 1040 } 1041 1042 mutex_unlock(&dev->stats_mutex); 1043 } 1044 EXPORT_SYMBOL(b53_get_ethtool_stats); 1045 1046 void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data) 1047 { 1048 struct phy_device *phydev; 1049 1050 phydev = b53_get_phy_device(ds, port); 1051 if (!phydev) 1052 return; 1053 1054 phy_ethtool_get_stats(phydev, NULL, data); 1055 } 1056 EXPORT_SYMBOL(b53_get_ethtool_phy_stats); 1057 1058 int b53_get_sset_count(struct dsa_switch *ds, int port, int sset) 1059 { 1060 struct b53_device *dev = ds->priv; 1061 struct phy_device *phydev; 1062 1063 if (sset == ETH_SS_STATS) { 1064 return b53_get_mib_size(dev); 1065 } else if (sset == ETH_SS_PHY_STATS) { 1066 phydev = b53_get_phy_device(ds, port); 1067 if (!phydev) 1068 return 0; 1069 1070 return phy_ethtool_get_sset_count(phydev); 1071 } 1072 1073 return 0; 1074 } 1075 EXPORT_SYMBOL(b53_get_sset_count); 1076 1077 enum b53_devlink_resource_id { 1078 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1079 }; 1080 1081 static u64 b53_devlink_vlan_table_get(void *priv) 1082 { 1083 struct b53_device *dev = priv; 1084 struct b53_vlan *vl; 1085 unsigned int i; 1086 u64 count = 0; 1087 1088 for (i = 0; i < dev->num_vlans; i++) { 1089 vl = &dev->vlans[i]; 1090 if (vl->members) 1091 count++; 1092 } 1093 1094 return count; 1095 } 1096 1097 int b53_setup_devlink_resources(struct dsa_switch *ds) 1098 { 1099 struct devlink_resource_size_params size_params; 1100 struct b53_device *dev = ds->priv; 1101 int err; 1102 1103 devlink_resource_size_params_init(&size_params, dev->num_vlans, 1104 dev->num_vlans, 1105 1, DEVLINK_RESOURCE_UNIT_ENTRY); 1106 1107 err = dsa_devlink_resource_register(ds, "VLAN", dev->num_vlans, 1108 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1109 DEVLINK_RESOURCE_ID_PARENT_TOP, 1110 &size_params); 1111 if (err) 1112 goto out; 1113 1114 dsa_devlink_resource_occ_get_register(ds, 1115 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1116 b53_devlink_vlan_table_get, dev); 1117 1118 return 0; 1119 out: 1120 dsa_devlink_resources_unregister(ds); 1121 return err; 1122 } 1123 EXPORT_SYMBOL(b53_setup_devlink_resources); 1124 1125 static int b53_setup(struct dsa_switch *ds) 1126 { 1127 struct b53_device *dev = ds->priv; 1128 unsigned int port; 1129 int ret; 1130 1131 /* Request bridge PVID untagged when DSA_TAG_PROTO_NONE is set 1132 * which forces the CPU port to be tagged in all VLANs. 1133 */ 1134 ds->untag_bridge_pvid = dev->tag_protocol == DSA_TAG_PROTO_NONE; 1135 1136 ret = b53_reset_switch(dev); 1137 if (ret) { 1138 dev_err(ds->dev, "failed to reset switch\n"); 1139 return ret; 1140 } 1141 1142 b53_reset_mib(dev); 1143 1144 ret = b53_apply_config(dev); 1145 if (ret) { 1146 dev_err(ds->dev, "failed to apply configuration\n"); 1147 return ret; 1148 } 1149 1150 /* Configure IMP/CPU port, disable all other ports. Enabled 1151 * ports will be configured with .port_enable 1152 */ 1153 for (port = 0; port < dev->num_ports; port++) { 1154 if (dsa_is_cpu_port(ds, port)) 1155 b53_enable_cpu_port(dev, port); 1156 else 1157 b53_disable_port(ds, port); 1158 } 1159 1160 return b53_setup_devlink_resources(ds); 1161 } 1162 1163 static void b53_teardown(struct dsa_switch *ds) 1164 { 1165 dsa_devlink_resources_unregister(ds); 1166 } 1167 1168 static void b53_force_link(struct b53_device *dev, int port, int link) 1169 { 1170 u8 reg, val, off; 1171 1172 /* Override the port settings */ 1173 if (port == dev->imp_port) { 1174 off = B53_PORT_OVERRIDE_CTRL; 1175 val = PORT_OVERRIDE_EN; 1176 } else { 1177 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 1178 val = GMII_PO_EN; 1179 } 1180 1181 b53_read8(dev, B53_CTRL_PAGE, off, ®); 1182 reg |= val; 1183 if (link) 1184 reg |= PORT_OVERRIDE_LINK; 1185 else 1186 reg &= ~PORT_OVERRIDE_LINK; 1187 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1188 } 1189 1190 static void b53_force_port_config(struct b53_device *dev, int port, 1191 int speed, int duplex, 1192 bool tx_pause, bool rx_pause) 1193 { 1194 u8 reg, val, off; 1195 1196 /* Override the port settings */ 1197 if (port == dev->imp_port) { 1198 off = B53_PORT_OVERRIDE_CTRL; 1199 val = PORT_OVERRIDE_EN; 1200 } else { 1201 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 1202 val = GMII_PO_EN; 1203 } 1204 1205 b53_read8(dev, B53_CTRL_PAGE, off, ®); 1206 reg |= val; 1207 if (duplex == DUPLEX_FULL) 1208 reg |= PORT_OVERRIDE_FULL_DUPLEX; 1209 else 1210 reg &= ~PORT_OVERRIDE_FULL_DUPLEX; 1211 1212 switch (speed) { 1213 case 2000: 1214 reg |= PORT_OVERRIDE_SPEED_2000M; 1215 fallthrough; 1216 case SPEED_1000: 1217 reg |= PORT_OVERRIDE_SPEED_1000M; 1218 break; 1219 case SPEED_100: 1220 reg |= PORT_OVERRIDE_SPEED_100M; 1221 break; 1222 case SPEED_10: 1223 reg |= PORT_OVERRIDE_SPEED_10M; 1224 break; 1225 default: 1226 dev_err(dev->dev, "unknown speed: %d\n", speed); 1227 return; 1228 } 1229 1230 if (rx_pause) 1231 reg |= PORT_OVERRIDE_RX_FLOW; 1232 if (tx_pause) 1233 reg |= PORT_OVERRIDE_TX_FLOW; 1234 1235 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1236 } 1237 1238 static void b53_adjust_63xx_rgmii(struct dsa_switch *ds, int port, 1239 phy_interface_t interface) 1240 { 1241 struct b53_device *dev = ds->priv; 1242 u8 rgmii_ctrl = 0, off; 1243 1244 if (port == dev->imp_port) 1245 off = B53_RGMII_CTRL_IMP; 1246 else 1247 off = B53_RGMII_CTRL_P(port); 1248 1249 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl); 1250 1251 switch (interface) { 1252 case PHY_INTERFACE_MODE_RGMII_ID: 1253 rgmii_ctrl |= (RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC); 1254 break; 1255 case PHY_INTERFACE_MODE_RGMII_RXID: 1256 rgmii_ctrl &= ~(RGMII_CTRL_DLL_TXC); 1257 rgmii_ctrl |= RGMII_CTRL_DLL_RXC; 1258 break; 1259 case PHY_INTERFACE_MODE_RGMII_TXID: 1260 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC); 1261 rgmii_ctrl |= RGMII_CTRL_DLL_TXC; 1262 break; 1263 case PHY_INTERFACE_MODE_RGMII: 1264 default: 1265 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC); 1266 break; 1267 } 1268 1269 if (port != dev->imp_port) { 1270 if (is63268(dev)) 1271 rgmii_ctrl |= RGMII_CTRL_MII_OVERRIDE; 1272 1273 rgmii_ctrl |= RGMII_CTRL_ENABLE_GMII; 1274 } 1275 1276 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl); 1277 1278 dev_dbg(ds->dev, "Configured port %d for %s\n", port, 1279 phy_modes(interface)); 1280 } 1281 1282 static void b53_adjust_531x5_rgmii(struct dsa_switch *ds, int port, 1283 phy_interface_t interface) 1284 { 1285 struct b53_device *dev = ds->priv; 1286 u8 rgmii_ctrl = 0, off; 1287 1288 if (port == dev->imp_port) 1289 off = B53_RGMII_CTRL_IMP; 1290 else 1291 off = B53_RGMII_CTRL_P(port); 1292 1293 /* Configure the port RGMII clock delay by DLL disabled and 1294 * tx_clk aligned timing (restoring to reset defaults) 1295 */ 1296 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl); 1297 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC | 1298 RGMII_CTRL_TIMING_SEL); 1299 1300 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make 1301 * sure that we enable the port TX clock internal delay to 1302 * account for this internal delay that is inserted, otherwise 1303 * the switch won't be able to receive correctly. 1304 * 1305 * PHY_INTERFACE_MODE_RGMII means that we are not introducing 1306 * any delay neither on transmission nor reception, so the 1307 * BCM53125 must also be configured accordingly to account for 1308 * the lack of delay and introduce 1309 * 1310 * The BCM53125 switch has its RX clock and TX clock control 1311 * swapped, hence the reason why we modify the TX clock path in 1312 * the "RGMII" case 1313 */ 1314 if (interface == PHY_INTERFACE_MODE_RGMII_TXID) 1315 rgmii_ctrl |= RGMII_CTRL_DLL_TXC; 1316 if (interface == PHY_INTERFACE_MODE_RGMII) 1317 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC; 1318 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL; 1319 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl); 1320 1321 dev_info(ds->dev, "Configured port %d for %s\n", port, 1322 phy_modes(interface)); 1323 } 1324 1325 static void b53_adjust_5325_mii(struct dsa_switch *ds, int port) 1326 { 1327 struct b53_device *dev = ds->priv; 1328 u8 reg = 0; 1329 1330 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1331 ®); 1332 1333 /* reverse mii needs to be enabled */ 1334 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1335 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1336 reg | PORT_OVERRIDE_RV_MII_25); 1337 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1338 ®); 1339 1340 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1341 dev_err(ds->dev, 1342 "Failed to enable reverse MII mode\n"); 1343 return; 1344 } 1345 } 1346 } 1347 1348 void b53_port_event(struct dsa_switch *ds, int port) 1349 { 1350 struct b53_device *dev = ds->priv; 1351 bool link; 1352 u16 sts; 1353 1354 b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts); 1355 link = !!(sts & BIT(port)); 1356 dsa_port_phylink_mac_change(ds, port, link); 1357 } 1358 EXPORT_SYMBOL(b53_port_event); 1359 1360 static void b53_phylink_get_caps(struct dsa_switch *ds, int port, 1361 struct phylink_config *config) 1362 { 1363 struct b53_device *dev = ds->priv; 1364 1365 /* Internal ports need GMII for PHYLIB */ 1366 __set_bit(PHY_INTERFACE_MODE_GMII, config->supported_interfaces); 1367 1368 /* These switches appear to support MII and RevMII too, but beyond 1369 * this, the code gives very few clues. FIXME: We probably need more 1370 * interface modes here. 1371 * 1372 * According to b53_srab_mux_init(), ports 3..5 can support: 1373 * SGMII, MII, GMII, RGMII or INTERNAL depending on the MUX setting. 1374 * However, the interface mode read from the MUX configuration is 1375 * not passed back to DSA, so phylink uses NA. 1376 * DT can specify RGMII for ports 0, 1. 1377 * For MDIO, port 8 can be RGMII_TXID. 1378 */ 1379 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 1380 __set_bit(PHY_INTERFACE_MODE_REVMII, config->supported_interfaces); 1381 1382 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 1383 MAC_10 | MAC_100; 1384 1385 /* 5325/5365 are not capable of gigabit speeds, everything else is. 1386 * Note: the original code also exclulded Gigagbit for MII, RevMII 1387 * and 802.3z modes. MII and RevMII are not able to work above 100M, 1388 * so will be excluded by the generic validator implementation. 1389 * However, the exclusion of Gigabit for 802.3z just seems wrong. 1390 */ 1391 if (!(is5325(dev) || is5365(dev))) 1392 config->mac_capabilities |= MAC_1000; 1393 1394 /* Get the implementation specific capabilities */ 1395 if (dev->ops->phylink_get_caps) 1396 dev->ops->phylink_get_caps(dev, port, config); 1397 } 1398 1399 static struct phylink_pcs *b53_phylink_mac_select_pcs(struct phylink_config *config, 1400 phy_interface_t interface) 1401 { 1402 struct dsa_port *dp = dsa_phylink_to_port(config); 1403 struct b53_device *dev = dp->ds->priv; 1404 1405 if (!dev->ops->phylink_mac_select_pcs) 1406 return NULL; 1407 1408 return dev->ops->phylink_mac_select_pcs(dev, dp->index, interface); 1409 } 1410 1411 static void b53_phylink_mac_config(struct phylink_config *config, 1412 unsigned int mode, 1413 const struct phylink_link_state *state) 1414 { 1415 struct dsa_port *dp = dsa_phylink_to_port(config); 1416 phy_interface_t interface = state->interface; 1417 struct dsa_switch *ds = dp->ds; 1418 struct b53_device *dev = ds->priv; 1419 int port = dp->index; 1420 1421 if (is63xx(dev) && port >= B53_63XX_RGMII0) 1422 b53_adjust_63xx_rgmii(ds, port, interface); 1423 1424 if (mode == MLO_AN_FIXED) { 1425 if (is531x5(dev) && phy_interface_mode_is_rgmii(interface)) 1426 b53_adjust_531x5_rgmii(ds, port, interface); 1427 1428 /* configure MII port if necessary */ 1429 if (is5325(dev)) 1430 b53_adjust_5325_mii(ds, port); 1431 } 1432 } 1433 1434 static void b53_phylink_mac_link_down(struct phylink_config *config, 1435 unsigned int mode, 1436 phy_interface_t interface) 1437 { 1438 struct dsa_port *dp = dsa_phylink_to_port(config); 1439 struct b53_device *dev = dp->ds->priv; 1440 int port = dp->index; 1441 1442 if (mode == MLO_AN_PHY) 1443 return; 1444 1445 if (mode == MLO_AN_FIXED) { 1446 b53_force_link(dev, port, false); 1447 return; 1448 } 1449 1450 if (phy_interface_mode_is_8023z(interface) && 1451 dev->ops->serdes_link_set) 1452 dev->ops->serdes_link_set(dev, port, mode, interface, false); 1453 } 1454 1455 static void b53_phylink_mac_link_up(struct phylink_config *config, 1456 struct phy_device *phydev, 1457 unsigned int mode, 1458 phy_interface_t interface, 1459 int speed, int duplex, 1460 bool tx_pause, bool rx_pause) 1461 { 1462 struct dsa_port *dp = dsa_phylink_to_port(config); 1463 struct dsa_switch *ds = dp->ds; 1464 struct b53_device *dev = ds->priv; 1465 struct ethtool_keee *p = &dev->ports[dp->index].eee; 1466 int port = dp->index; 1467 1468 if (mode == MLO_AN_PHY) { 1469 /* Re-negotiate EEE if it was enabled already */ 1470 p->eee_enabled = b53_eee_init(ds, port, phydev); 1471 return; 1472 } 1473 1474 if (mode == MLO_AN_FIXED) { 1475 /* Force flow control on BCM5301x's CPU port */ 1476 if (is5301x(dev) && dsa_is_cpu_port(ds, port)) 1477 tx_pause = rx_pause = true; 1478 1479 b53_force_port_config(dev, port, speed, duplex, 1480 tx_pause, rx_pause); 1481 b53_force_link(dev, port, true); 1482 return; 1483 } 1484 1485 if (phy_interface_mode_is_8023z(interface) && 1486 dev->ops->serdes_link_set) 1487 dev->ops->serdes_link_set(dev, port, mode, interface, true); 1488 } 1489 1490 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1491 struct netlink_ext_ack *extack) 1492 { 1493 struct b53_device *dev = ds->priv; 1494 1495 b53_enable_vlan(dev, port, dev->vlan_enabled, vlan_filtering); 1496 1497 return 0; 1498 } 1499 EXPORT_SYMBOL(b53_vlan_filtering); 1500 1501 static int b53_vlan_prepare(struct dsa_switch *ds, int port, 1502 const struct switchdev_obj_port_vlan *vlan) 1503 { 1504 struct b53_device *dev = ds->priv; 1505 1506 if ((is5325(dev) || is5365(dev)) && vlan->vid == 0) 1507 return -EOPNOTSUPP; 1508 1509 /* Port 7 on 7278 connects to the ASP's UniMAC which is not capable of 1510 * receiving VLAN tagged frames at all, we can still allow the port to 1511 * be configured for egress untagged. 1512 */ 1513 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7 && 1514 !(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)) 1515 return -EINVAL; 1516 1517 if (vlan->vid >= dev->num_vlans) 1518 return -ERANGE; 1519 1520 b53_enable_vlan(dev, port, true, ds->vlan_filtering); 1521 1522 return 0; 1523 } 1524 1525 int b53_vlan_add(struct dsa_switch *ds, int port, 1526 const struct switchdev_obj_port_vlan *vlan, 1527 struct netlink_ext_ack *extack) 1528 { 1529 struct b53_device *dev = ds->priv; 1530 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1531 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1532 struct b53_vlan *vl; 1533 int err; 1534 1535 err = b53_vlan_prepare(ds, port, vlan); 1536 if (err) 1537 return err; 1538 1539 vl = &dev->vlans[vlan->vid]; 1540 1541 b53_get_vlan_entry(dev, vlan->vid, vl); 1542 1543 if (vlan->vid == 0 && vlan->vid == b53_default_pvid(dev)) 1544 untagged = true; 1545 1546 vl->members |= BIT(port); 1547 if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port)) 1548 vl->untag |= BIT(port); 1549 else 1550 vl->untag &= ~BIT(port); 1551 1552 b53_set_vlan_entry(dev, vlan->vid, vl); 1553 b53_fast_age_vlan(dev, vlan->vid); 1554 1555 if (pvid && !dsa_is_cpu_port(ds, port)) { 1556 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), 1557 vlan->vid); 1558 b53_fast_age_vlan(dev, vlan->vid); 1559 } 1560 1561 return 0; 1562 } 1563 EXPORT_SYMBOL(b53_vlan_add); 1564 1565 int b53_vlan_del(struct dsa_switch *ds, int port, 1566 const struct switchdev_obj_port_vlan *vlan) 1567 { 1568 struct b53_device *dev = ds->priv; 1569 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1570 struct b53_vlan *vl; 1571 u16 pvid; 1572 1573 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid); 1574 1575 vl = &dev->vlans[vlan->vid]; 1576 1577 b53_get_vlan_entry(dev, vlan->vid, vl); 1578 1579 vl->members &= ~BIT(port); 1580 1581 if (pvid == vlan->vid) 1582 pvid = b53_default_pvid(dev); 1583 1584 if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port)) 1585 vl->untag &= ~(BIT(port)); 1586 1587 b53_set_vlan_entry(dev, vlan->vid, vl); 1588 b53_fast_age_vlan(dev, vlan->vid); 1589 1590 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid); 1591 b53_fast_age_vlan(dev, pvid); 1592 1593 return 0; 1594 } 1595 EXPORT_SYMBOL(b53_vlan_del); 1596 1597 /* Address Resolution Logic routines. Caller must hold &dev->arl_mutex. */ 1598 static int b53_arl_op_wait(struct b53_device *dev) 1599 { 1600 unsigned int timeout = 10; 1601 u8 reg; 1602 1603 do { 1604 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1605 if (!(reg & ARLTBL_START_DONE)) 1606 return 0; 1607 1608 usleep_range(1000, 2000); 1609 } while (timeout--); 1610 1611 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg); 1612 1613 return -ETIMEDOUT; 1614 } 1615 1616 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op) 1617 { 1618 u8 reg; 1619 1620 if (op > ARLTBL_RW) 1621 return -EINVAL; 1622 1623 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1624 reg |= ARLTBL_START_DONE; 1625 if (op) 1626 reg |= ARLTBL_RW; 1627 else 1628 reg &= ~ARLTBL_RW; 1629 if (dev->vlan_enabled) 1630 reg &= ~ARLTBL_IVL_SVL_SELECT; 1631 else 1632 reg |= ARLTBL_IVL_SVL_SELECT; 1633 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg); 1634 1635 return b53_arl_op_wait(dev); 1636 } 1637 1638 static int b53_arl_read(struct b53_device *dev, u64 mac, 1639 u16 vid, struct b53_arl_entry *ent, u8 *idx) 1640 { 1641 DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES); 1642 unsigned int i; 1643 int ret; 1644 1645 ret = b53_arl_op_wait(dev); 1646 if (ret) 1647 return ret; 1648 1649 bitmap_zero(free_bins, dev->num_arl_bins); 1650 1651 /* Read the bins */ 1652 for (i = 0; i < dev->num_arl_bins; i++) { 1653 u64 mac_vid; 1654 u32 fwd_entry; 1655 1656 b53_read64(dev, B53_ARLIO_PAGE, 1657 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid); 1658 b53_read32(dev, B53_ARLIO_PAGE, 1659 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry); 1660 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1661 1662 if (!(fwd_entry & ARLTBL_VALID)) { 1663 set_bit(i, free_bins); 1664 continue; 1665 } 1666 if ((mac_vid & ARLTBL_MAC_MASK) != mac) 1667 continue; 1668 if (dev->vlan_enabled && 1669 ((mac_vid >> ARLTBL_VID_S) & ARLTBL_VID_MASK) != vid) 1670 continue; 1671 *idx = i; 1672 return 0; 1673 } 1674 1675 *idx = find_first_bit(free_bins, dev->num_arl_bins); 1676 return *idx >= dev->num_arl_bins ? -ENOSPC : -ENOENT; 1677 } 1678 1679 static int b53_arl_op(struct b53_device *dev, int op, int port, 1680 const unsigned char *addr, u16 vid, bool is_valid) 1681 { 1682 struct b53_arl_entry ent; 1683 u32 fwd_entry; 1684 u64 mac, mac_vid = 0; 1685 u8 idx = 0; 1686 int ret; 1687 1688 /* Convert the array into a 64-bit MAC */ 1689 mac = ether_addr_to_u64(addr); 1690 1691 /* Perform a read for the given MAC and VID */ 1692 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac); 1693 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid); 1694 1695 /* Issue a read operation for this MAC */ 1696 ret = b53_arl_rw_op(dev, 1); 1697 if (ret) 1698 return ret; 1699 1700 ret = b53_arl_read(dev, mac, vid, &ent, &idx); 1701 1702 /* If this is a read, just finish now */ 1703 if (op) 1704 return ret; 1705 1706 switch (ret) { 1707 case -ETIMEDOUT: 1708 return ret; 1709 case -ENOSPC: 1710 dev_dbg(dev->dev, "{%pM,%.4d} no space left in ARL\n", 1711 addr, vid); 1712 return is_valid ? ret : 0; 1713 case -ENOENT: 1714 /* We could not find a matching MAC, so reset to a new entry */ 1715 dev_dbg(dev->dev, "{%pM,%.4d} not found, using idx: %d\n", 1716 addr, vid, idx); 1717 fwd_entry = 0; 1718 break; 1719 default: 1720 dev_dbg(dev->dev, "{%pM,%.4d} found, using idx: %d\n", 1721 addr, vid, idx); 1722 break; 1723 } 1724 1725 /* For multicast address, the port is a bitmask and the validity 1726 * is determined by having at least one port being still active 1727 */ 1728 if (!is_multicast_ether_addr(addr)) { 1729 ent.port = port; 1730 ent.is_valid = is_valid; 1731 } else { 1732 if (is_valid) 1733 ent.port |= BIT(port); 1734 else 1735 ent.port &= ~BIT(port); 1736 1737 ent.is_valid = !!(ent.port); 1738 } 1739 1740 ent.vid = vid; 1741 ent.is_static = true; 1742 ent.is_age = false; 1743 memcpy(ent.mac, addr, ETH_ALEN); 1744 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent); 1745 1746 b53_write64(dev, B53_ARLIO_PAGE, 1747 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid); 1748 b53_write32(dev, B53_ARLIO_PAGE, 1749 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry); 1750 1751 return b53_arl_rw_op(dev, 0); 1752 } 1753 1754 int b53_fdb_add(struct dsa_switch *ds, int port, 1755 const unsigned char *addr, u16 vid, 1756 struct dsa_db db) 1757 { 1758 struct b53_device *priv = ds->priv; 1759 int ret; 1760 1761 /* 5325 and 5365 require some more massaging, but could 1762 * be supported eventually 1763 */ 1764 if (is5325(priv) || is5365(priv)) 1765 return -EOPNOTSUPP; 1766 1767 mutex_lock(&priv->arl_mutex); 1768 ret = b53_arl_op(priv, 0, port, addr, vid, true); 1769 mutex_unlock(&priv->arl_mutex); 1770 1771 return ret; 1772 } 1773 EXPORT_SYMBOL(b53_fdb_add); 1774 1775 int b53_fdb_del(struct dsa_switch *ds, int port, 1776 const unsigned char *addr, u16 vid, 1777 struct dsa_db db) 1778 { 1779 struct b53_device *priv = ds->priv; 1780 int ret; 1781 1782 mutex_lock(&priv->arl_mutex); 1783 ret = b53_arl_op(priv, 0, port, addr, vid, false); 1784 mutex_unlock(&priv->arl_mutex); 1785 1786 return ret; 1787 } 1788 EXPORT_SYMBOL(b53_fdb_del); 1789 1790 static int b53_arl_search_wait(struct b53_device *dev) 1791 { 1792 unsigned int timeout = 1000; 1793 u8 reg; 1794 1795 do { 1796 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®); 1797 if (!(reg & ARL_SRCH_STDN)) 1798 return 0; 1799 1800 if (reg & ARL_SRCH_VLID) 1801 return 0; 1802 1803 usleep_range(1000, 2000); 1804 } while (timeout--); 1805 1806 return -ETIMEDOUT; 1807 } 1808 1809 static void b53_arl_search_rd(struct b53_device *dev, u8 idx, 1810 struct b53_arl_entry *ent) 1811 { 1812 u64 mac_vid; 1813 u32 fwd_entry; 1814 1815 b53_read64(dev, B53_ARLIO_PAGE, 1816 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid); 1817 b53_read32(dev, B53_ARLIO_PAGE, 1818 B53_ARL_SRCH_RSTL(idx), &fwd_entry); 1819 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1820 } 1821 1822 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent, 1823 dsa_fdb_dump_cb_t *cb, void *data) 1824 { 1825 if (!ent->is_valid) 1826 return 0; 1827 1828 if (port != ent->port) 1829 return 0; 1830 1831 return cb(ent->mac, ent->vid, ent->is_static, data); 1832 } 1833 1834 int b53_fdb_dump(struct dsa_switch *ds, int port, 1835 dsa_fdb_dump_cb_t *cb, void *data) 1836 { 1837 struct b53_device *priv = ds->priv; 1838 struct b53_arl_entry results[2]; 1839 unsigned int count = 0; 1840 int ret; 1841 u8 reg; 1842 1843 mutex_lock(&priv->arl_mutex); 1844 1845 /* Start search operation */ 1846 reg = ARL_SRCH_STDN; 1847 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg); 1848 1849 do { 1850 ret = b53_arl_search_wait(priv); 1851 if (ret) 1852 break; 1853 1854 b53_arl_search_rd(priv, 0, &results[0]); 1855 ret = b53_fdb_copy(port, &results[0], cb, data); 1856 if (ret) 1857 break; 1858 1859 if (priv->num_arl_bins > 2) { 1860 b53_arl_search_rd(priv, 1, &results[1]); 1861 ret = b53_fdb_copy(port, &results[1], cb, data); 1862 if (ret) 1863 break; 1864 1865 if (!results[0].is_valid && !results[1].is_valid) 1866 break; 1867 } 1868 1869 } while (count++ < b53_max_arl_entries(priv) / 2); 1870 1871 mutex_unlock(&priv->arl_mutex); 1872 1873 return 0; 1874 } 1875 EXPORT_SYMBOL(b53_fdb_dump); 1876 1877 int b53_mdb_add(struct dsa_switch *ds, int port, 1878 const struct switchdev_obj_port_mdb *mdb, 1879 struct dsa_db db) 1880 { 1881 struct b53_device *priv = ds->priv; 1882 int ret; 1883 1884 /* 5325 and 5365 require some more massaging, but could 1885 * be supported eventually 1886 */ 1887 if (is5325(priv) || is5365(priv)) 1888 return -EOPNOTSUPP; 1889 1890 mutex_lock(&priv->arl_mutex); 1891 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, true); 1892 mutex_unlock(&priv->arl_mutex); 1893 1894 return ret; 1895 } 1896 EXPORT_SYMBOL(b53_mdb_add); 1897 1898 int b53_mdb_del(struct dsa_switch *ds, int port, 1899 const struct switchdev_obj_port_mdb *mdb, 1900 struct dsa_db db) 1901 { 1902 struct b53_device *priv = ds->priv; 1903 int ret; 1904 1905 mutex_lock(&priv->arl_mutex); 1906 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, false); 1907 mutex_unlock(&priv->arl_mutex); 1908 if (ret) 1909 dev_err(ds->dev, "failed to delete MDB entry\n"); 1910 1911 return ret; 1912 } 1913 EXPORT_SYMBOL(b53_mdb_del); 1914 1915 int b53_br_join(struct dsa_switch *ds, int port, struct dsa_bridge bridge, 1916 bool *tx_fwd_offload, struct netlink_ext_ack *extack) 1917 { 1918 struct b53_device *dev = ds->priv; 1919 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 1920 u16 pvlan, reg; 1921 unsigned int i; 1922 1923 /* On 7278, port 7 which connects to the ASP should only receive 1924 * traffic from matching CFP rules. 1925 */ 1926 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7) 1927 return -EINVAL; 1928 1929 /* Make this port leave the all VLANs join since we will have proper 1930 * VLAN entries from now on 1931 */ 1932 if (is58xx(dev)) { 1933 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1934 reg &= ~BIT(port); 1935 if ((reg & BIT(cpu_port)) == BIT(cpu_port)) 1936 reg &= ~BIT(cpu_port); 1937 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1938 } 1939 1940 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1941 1942 b53_for_each_port(dev, i) { 1943 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge)) 1944 continue; 1945 1946 /* Add this local port to the remote port VLAN control 1947 * membership and update the remote port bitmask 1948 */ 1949 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1950 reg |= BIT(port); 1951 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1952 dev->ports[i].vlan_ctl_mask = reg; 1953 1954 pvlan |= BIT(i); 1955 } 1956 1957 /* Configure the local port VLAN control membership to include 1958 * remote ports and update the local port bitmask 1959 */ 1960 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1961 dev->ports[port].vlan_ctl_mask = pvlan; 1962 1963 return 0; 1964 } 1965 EXPORT_SYMBOL(b53_br_join); 1966 1967 void b53_br_leave(struct dsa_switch *ds, int port, struct dsa_bridge bridge) 1968 { 1969 struct b53_device *dev = ds->priv; 1970 struct b53_vlan *vl = &dev->vlans[0]; 1971 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 1972 unsigned int i; 1973 u16 pvlan, reg, pvid; 1974 1975 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1976 1977 b53_for_each_port(dev, i) { 1978 /* Don't touch the remaining ports */ 1979 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge)) 1980 continue; 1981 1982 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1983 reg &= ~BIT(port); 1984 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1985 dev->ports[port].vlan_ctl_mask = reg; 1986 1987 /* Prevent self removal to preserve isolation */ 1988 if (port != i) 1989 pvlan &= ~BIT(i); 1990 } 1991 1992 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1993 dev->ports[port].vlan_ctl_mask = pvlan; 1994 1995 pvid = b53_default_pvid(dev); 1996 1997 /* Make this port join all VLANs without VLAN entries */ 1998 if (is58xx(dev)) { 1999 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 2000 reg |= BIT(port); 2001 if (!(reg & BIT(cpu_port))) 2002 reg |= BIT(cpu_port); 2003 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 2004 } else { 2005 b53_get_vlan_entry(dev, pvid, vl); 2006 vl->members |= BIT(port) | BIT(cpu_port); 2007 vl->untag |= BIT(port) | BIT(cpu_port); 2008 b53_set_vlan_entry(dev, pvid, vl); 2009 } 2010 } 2011 EXPORT_SYMBOL(b53_br_leave); 2012 2013 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state) 2014 { 2015 struct b53_device *dev = ds->priv; 2016 u8 hw_state; 2017 u8 reg; 2018 2019 switch (state) { 2020 case BR_STATE_DISABLED: 2021 hw_state = PORT_CTRL_DIS_STATE; 2022 break; 2023 case BR_STATE_LISTENING: 2024 hw_state = PORT_CTRL_LISTEN_STATE; 2025 break; 2026 case BR_STATE_LEARNING: 2027 hw_state = PORT_CTRL_LEARN_STATE; 2028 break; 2029 case BR_STATE_FORWARDING: 2030 hw_state = PORT_CTRL_FWD_STATE; 2031 break; 2032 case BR_STATE_BLOCKING: 2033 hw_state = PORT_CTRL_BLOCK_STATE; 2034 break; 2035 default: 2036 dev_err(ds->dev, "invalid STP state: %d\n", state); 2037 return; 2038 } 2039 2040 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 2041 reg &= ~PORT_CTRL_STP_STATE_MASK; 2042 reg |= hw_state; 2043 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 2044 } 2045 EXPORT_SYMBOL(b53_br_set_stp_state); 2046 2047 void b53_br_fast_age(struct dsa_switch *ds, int port) 2048 { 2049 struct b53_device *dev = ds->priv; 2050 2051 if (b53_fast_age_port(dev, port)) 2052 dev_err(ds->dev, "fast ageing failed\n"); 2053 } 2054 EXPORT_SYMBOL(b53_br_fast_age); 2055 2056 int b53_br_flags_pre(struct dsa_switch *ds, int port, 2057 struct switchdev_brport_flags flags, 2058 struct netlink_ext_ack *extack) 2059 { 2060 if (flags.mask & ~(BR_FLOOD | BR_MCAST_FLOOD | BR_LEARNING)) 2061 return -EINVAL; 2062 2063 return 0; 2064 } 2065 EXPORT_SYMBOL(b53_br_flags_pre); 2066 2067 int b53_br_flags(struct dsa_switch *ds, int port, 2068 struct switchdev_brport_flags flags, 2069 struct netlink_ext_ack *extack) 2070 { 2071 if (flags.mask & BR_FLOOD) 2072 b53_port_set_ucast_flood(ds->priv, port, 2073 !!(flags.val & BR_FLOOD)); 2074 if (flags.mask & BR_MCAST_FLOOD) 2075 b53_port_set_mcast_flood(ds->priv, port, 2076 !!(flags.val & BR_MCAST_FLOOD)); 2077 if (flags.mask & BR_LEARNING) 2078 b53_port_set_learning(ds->priv, port, 2079 !!(flags.val & BR_LEARNING)); 2080 2081 return 0; 2082 } 2083 EXPORT_SYMBOL(b53_br_flags); 2084 2085 static bool b53_possible_cpu_port(struct dsa_switch *ds, int port) 2086 { 2087 /* Broadcom switches will accept enabling Broadcom tags on the 2088 * following ports: 5, 7 and 8, any other port is not supported 2089 */ 2090 switch (port) { 2091 case B53_CPU_PORT_25: 2092 case 7: 2093 case B53_CPU_PORT: 2094 return true; 2095 } 2096 2097 return false; 2098 } 2099 2100 static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port, 2101 enum dsa_tag_protocol tag_protocol) 2102 { 2103 bool ret = b53_possible_cpu_port(ds, port); 2104 2105 if (!ret) { 2106 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n", 2107 port); 2108 return ret; 2109 } 2110 2111 switch (tag_protocol) { 2112 case DSA_TAG_PROTO_BRCM: 2113 case DSA_TAG_PROTO_BRCM_PREPEND: 2114 dev_warn(ds->dev, 2115 "Port %d is stacked to Broadcom tag switch\n", port); 2116 ret = false; 2117 break; 2118 default: 2119 ret = true; 2120 break; 2121 } 2122 2123 return ret; 2124 } 2125 2126 enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port, 2127 enum dsa_tag_protocol mprot) 2128 { 2129 struct b53_device *dev = ds->priv; 2130 2131 if (!b53_can_enable_brcm_tags(ds, port, mprot)) { 2132 dev->tag_protocol = DSA_TAG_PROTO_NONE; 2133 goto out; 2134 } 2135 2136 /* Older models require a different 6 byte tag */ 2137 if (is5325(dev) || is5365(dev) || is63xx(dev)) { 2138 dev->tag_protocol = DSA_TAG_PROTO_BRCM_LEGACY; 2139 goto out; 2140 } 2141 2142 /* Broadcom BCM58xx chips have a flow accelerator on Port 8 2143 * which requires us to use the prepended Broadcom tag type 2144 */ 2145 if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT) { 2146 dev->tag_protocol = DSA_TAG_PROTO_BRCM_PREPEND; 2147 goto out; 2148 } 2149 2150 dev->tag_protocol = DSA_TAG_PROTO_BRCM; 2151 out: 2152 return dev->tag_protocol; 2153 } 2154 EXPORT_SYMBOL(b53_get_tag_protocol); 2155 2156 int b53_mirror_add(struct dsa_switch *ds, int port, 2157 struct dsa_mall_mirror_tc_entry *mirror, bool ingress, 2158 struct netlink_ext_ack *extack) 2159 { 2160 struct b53_device *dev = ds->priv; 2161 u16 reg, loc; 2162 2163 if (ingress) 2164 loc = B53_IG_MIR_CTL; 2165 else 2166 loc = B53_EG_MIR_CTL; 2167 2168 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 2169 reg |= BIT(port); 2170 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 2171 2172 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 2173 reg &= ~CAP_PORT_MASK; 2174 reg |= mirror->to_local_port; 2175 reg |= MIRROR_EN; 2176 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 2177 2178 return 0; 2179 } 2180 EXPORT_SYMBOL(b53_mirror_add); 2181 2182 void b53_mirror_del(struct dsa_switch *ds, int port, 2183 struct dsa_mall_mirror_tc_entry *mirror) 2184 { 2185 struct b53_device *dev = ds->priv; 2186 bool loc_disable = false, other_loc_disable = false; 2187 u16 reg, loc; 2188 2189 if (mirror->ingress) 2190 loc = B53_IG_MIR_CTL; 2191 else 2192 loc = B53_EG_MIR_CTL; 2193 2194 /* Update the desired ingress/egress register */ 2195 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 2196 reg &= ~BIT(port); 2197 if (!(reg & MIRROR_MASK)) 2198 loc_disable = true; 2199 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 2200 2201 /* Now look at the other one to know if we can disable mirroring 2202 * entirely 2203 */ 2204 if (mirror->ingress) 2205 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, ®); 2206 else 2207 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, ®); 2208 if (!(reg & MIRROR_MASK)) 2209 other_loc_disable = true; 2210 2211 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 2212 /* Both no longer have ports, let's disable mirroring */ 2213 if (loc_disable && other_loc_disable) { 2214 reg &= ~MIRROR_EN; 2215 reg &= ~mirror->to_local_port; 2216 } 2217 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 2218 } 2219 EXPORT_SYMBOL(b53_mirror_del); 2220 2221 /* Returns 0 if EEE was not enabled, or 1 otherwise 2222 */ 2223 int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy) 2224 { 2225 int ret; 2226 2227 ret = phy_init_eee(phy, false); 2228 if (ret) 2229 return 0; 2230 2231 b53_eee_enable_set(ds, port, true); 2232 2233 return 1; 2234 } 2235 EXPORT_SYMBOL(b53_eee_init); 2236 2237 bool b53_support_eee(struct dsa_switch *ds, int port) 2238 { 2239 struct b53_device *dev = ds->priv; 2240 2241 return !is5325(dev) && !is5365(dev); 2242 } 2243 EXPORT_SYMBOL(b53_support_eee); 2244 2245 int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_keee *e) 2246 { 2247 struct b53_device *dev = ds->priv; 2248 struct ethtool_keee *p = &dev->ports[port].eee; 2249 2250 p->eee_enabled = e->eee_enabled; 2251 b53_eee_enable_set(ds, port, e->eee_enabled); 2252 2253 return 0; 2254 } 2255 EXPORT_SYMBOL(b53_set_mac_eee); 2256 2257 static int b53_change_mtu(struct dsa_switch *ds, int port, int mtu) 2258 { 2259 struct b53_device *dev = ds->priv; 2260 bool enable_jumbo; 2261 bool allow_10_100; 2262 2263 if (is5325(dev) || is5365(dev)) 2264 return 0; 2265 2266 if (!dsa_is_cpu_port(ds, port)) 2267 return 0; 2268 2269 enable_jumbo = (mtu > ETH_DATA_LEN); 2270 allow_10_100 = !is63xx(dev); 2271 2272 return b53_set_jumbo(dev, enable_jumbo, allow_10_100); 2273 } 2274 2275 static int b53_get_max_mtu(struct dsa_switch *ds, int port) 2276 { 2277 struct b53_device *dev = ds->priv; 2278 2279 if (is5325(dev) || is5365(dev)) 2280 return B53_MAX_MTU_25; 2281 2282 return B53_MAX_MTU; 2283 } 2284 2285 static const struct phylink_mac_ops b53_phylink_mac_ops = { 2286 .mac_select_pcs = b53_phylink_mac_select_pcs, 2287 .mac_config = b53_phylink_mac_config, 2288 .mac_link_down = b53_phylink_mac_link_down, 2289 .mac_link_up = b53_phylink_mac_link_up, 2290 }; 2291 2292 static const struct dsa_switch_ops b53_switch_ops = { 2293 .get_tag_protocol = b53_get_tag_protocol, 2294 .setup = b53_setup, 2295 .teardown = b53_teardown, 2296 .get_strings = b53_get_strings, 2297 .get_ethtool_stats = b53_get_ethtool_stats, 2298 .get_sset_count = b53_get_sset_count, 2299 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 2300 .phy_read = b53_phy_read16, 2301 .phy_write = b53_phy_write16, 2302 .phylink_get_caps = b53_phylink_get_caps, 2303 .port_enable = b53_enable_port, 2304 .port_disable = b53_disable_port, 2305 .support_eee = b53_support_eee, 2306 .set_mac_eee = b53_set_mac_eee, 2307 .port_bridge_join = b53_br_join, 2308 .port_bridge_leave = b53_br_leave, 2309 .port_pre_bridge_flags = b53_br_flags_pre, 2310 .port_bridge_flags = b53_br_flags, 2311 .port_stp_state_set = b53_br_set_stp_state, 2312 .port_fast_age = b53_br_fast_age, 2313 .port_vlan_filtering = b53_vlan_filtering, 2314 .port_vlan_add = b53_vlan_add, 2315 .port_vlan_del = b53_vlan_del, 2316 .port_fdb_dump = b53_fdb_dump, 2317 .port_fdb_add = b53_fdb_add, 2318 .port_fdb_del = b53_fdb_del, 2319 .port_mirror_add = b53_mirror_add, 2320 .port_mirror_del = b53_mirror_del, 2321 .port_mdb_add = b53_mdb_add, 2322 .port_mdb_del = b53_mdb_del, 2323 .port_max_mtu = b53_get_max_mtu, 2324 .port_change_mtu = b53_change_mtu, 2325 }; 2326 2327 struct b53_chip_data { 2328 u32 chip_id; 2329 const char *dev_name; 2330 u16 vlans; 2331 u16 enabled_ports; 2332 u8 imp_port; 2333 u8 cpu_port; 2334 u8 vta_regs[3]; 2335 u8 arl_bins; 2336 u16 arl_buckets; 2337 u8 duplex_reg; 2338 u8 jumbo_pm_reg; 2339 u8 jumbo_size_reg; 2340 }; 2341 2342 #define B53_VTA_REGS \ 2343 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY } 2344 #define B53_VTA_REGS_9798 \ 2345 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 } 2346 #define B53_VTA_REGS_63XX \ 2347 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX } 2348 2349 static const struct b53_chip_data b53_switch_chips[] = { 2350 { 2351 .chip_id = BCM5325_DEVICE_ID, 2352 .dev_name = "BCM5325", 2353 .vlans = 16, 2354 .enabled_ports = 0x3f, 2355 .arl_bins = 2, 2356 .arl_buckets = 1024, 2357 .imp_port = 5, 2358 .duplex_reg = B53_DUPLEX_STAT_FE, 2359 }, 2360 { 2361 .chip_id = BCM5365_DEVICE_ID, 2362 .dev_name = "BCM5365", 2363 .vlans = 256, 2364 .enabled_ports = 0x3f, 2365 .arl_bins = 2, 2366 .arl_buckets = 1024, 2367 .imp_port = 5, 2368 .duplex_reg = B53_DUPLEX_STAT_FE, 2369 }, 2370 { 2371 .chip_id = BCM5389_DEVICE_ID, 2372 .dev_name = "BCM5389", 2373 .vlans = 4096, 2374 .enabled_ports = 0x11f, 2375 .arl_bins = 4, 2376 .arl_buckets = 1024, 2377 .imp_port = 8, 2378 .vta_regs = B53_VTA_REGS, 2379 .duplex_reg = B53_DUPLEX_STAT_GE, 2380 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2381 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2382 }, 2383 { 2384 .chip_id = BCM5395_DEVICE_ID, 2385 .dev_name = "BCM5395", 2386 .vlans = 4096, 2387 .enabled_ports = 0x11f, 2388 .arl_bins = 4, 2389 .arl_buckets = 1024, 2390 .imp_port = 8, 2391 .vta_regs = B53_VTA_REGS, 2392 .duplex_reg = B53_DUPLEX_STAT_GE, 2393 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2394 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2395 }, 2396 { 2397 .chip_id = BCM5397_DEVICE_ID, 2398 .dev_name = "BCM5397", 2399 .vlans = 4096, 2400 .enabled_ports = 0x11f, 2401 .arl_bins = 4, 2402 .arl_buckets = 1024, 2403 .imp_port = 8, 2404 .vta_regs = B53_VTA_REGS_9798, 2405 .duplex_reg = B53_DUPLEX_STAT_GE, 2406 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2407 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2408 }, 2409 { 2410 .chip_id = BCM5398_DEVICE_ID, 2411 .dev_name = "BCM5398", 2412 .vlans = 4096, 2413 .enabled_ports = 0x17f, 2414 .arl_bins = 4, 2415 .arl_buckets = 1024, 2416 .imp_port = 8, 2417 .vta_regs = B53_VTA_REGS_9798, 2418 .duplex_reg = B53_DUPLEX_STAT_GE, 2419 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2420 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2421 }, 2422 { 2423 .chip_id = BCM53101_DEVICE_ID, 2424 .dev_name = "BCM53101", 2425 .vlans = 4096, 2426 .enabled_ports = 0x11f, 2427 .arl_bins = 4, 2428 .arl_buckets = 512, 2429 .vta_regs = B53_VTA_REGS, 2430 .imp_port = 8, 2431 .duplex_reg = B53_DUPLEX_STAT_GE, 2432 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2433 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2434 }, 2435 { 2436 .chip_id = BCM53115_DEVICE_ID, 2437 .dev_name = "BCM53115", 2438 .vlans = 4096, 2439 .enabled_ports = 0x11f, 2440 .arl_bins = 4, 2441 .arl_buckets = 1024, 2442 .vta_regs = B53_VTA_REGS, 2443 .imp_port = 8, 2444 .duplex_reg = B53_DUPLEX_STAT_GE, 2445 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2446 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2447 }, 2448 { 2449 .chip_id = BCM53125_DEVICE_ID, 2450 .dev_name = "BCM53125", 2451 .vlans = 4096, 2452 .enabled_ports = 0x1ff, 2453 .arl_bins = 4, 2454 .arl_buckets = 1024, 2455 .imp_port = 8, 2456 .vta_regs = B53_VTA_REGS, 2457 .duplex_reg = B53_DUPLEX_STAT_GE, 2458 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2459 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2460 }, 2461 { 2462 .chip_id = BCM53128_DEVICE_ID, 2463 .dev_name = "BCM53128", 2464 .vlans = 4096, 2465 .enabled_ports = 0x1ff, 2466 .arl_bins = 4, 2467 .arl_buckets = 1024, 2468 .imp_port = 8, 2469 .vta_regs = B53_VTA_REGS, 2470 .duplex_reg = B53_DUPLEX_STAT_GE, 2471 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2472 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2473 }, 2474 { 2475 .chip_id = BCM63XX_DEVICE_ID, 2476 .dev_name = "BCM63xx", 2477 .vlans = 4096, 2478 .enabled_ports = 0, /* pdata must provide them */ 2479 .arl_bins = 4, 2480 .arl_buckets = 1024, 2481 .imp_port = 8, 2482 .vta_regs = B53_VTA_REGS_63XX, 2483 .duplex_reg = B53_DUPLEX_STAT_63XX, 2484 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, 2485 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, 2486 }, 2487 { 2488 .chip_id = BCM63268_DEVICE_ID, 2489 .dev_name = "BCM63268", 2490 .vlans = 4096, 2491 .enabled_ports = 0, /* pdata must provide them */ 2492 .arl_bins = 4, 2493 .arl_buckets = 1024, 2494 .imp_port = 8, 2495 .vta_regs = B53_VTA_REGS_63XX, 2496 .duplex_reg = B53_DUPLEX_STAT_63XX, 2497 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, 2498 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, 2499 }, 2500 { 2501 .chip_id = BCM53010_DEVICE_ID, 2502 .dev_name = "BCM53010", 2503 .vlans = 4096, 2504 .enabled_ports = 0x1bf, 2505 .arl_bins = 4, 2506 .arl_buckets = 1024, 2507 .imp_port = 8, 2508 .vta_regs = B53_VTA_REGS, 2509 .duplex_reg = B53_DUPLEX_STAT_GE, 2510 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2511 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2512 }, 2513 { 2514 .chip_id = BCM53011_DEVICE_ID, 2515 .dev_name = "BCM53011", 2516 .vlans = 4096, 2517 .enabled_ports = 0x1bf, 2518 .arl_bins = 4, 2519 .arl_buckets = 1024, 2520 .imp_port = 8, 2521 .vta_regs = B53_VTA_REGS, 2522 .duplex_reg = B53_DUPLEX_STAT_GE, 2523 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2524 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2525 }, 2526 { 2527 .chip_id = BCM53012_DEVICE_ID, 2528 .dev_name = "BCM53012", 2529 .vlans = 4096, 2530 .enabled_ports = 0x1bf, 2531 .arl_bins = 4, 2532 .arl_buckets = 1024, 2533 .imp_port = 8, 2534 .vta_regs = B53_VTA_REGS, 2535 .duplex_reg = B53_DUPLEX_STAT_GE, 2536 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2537 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2538 }, 2539 { 2540 .chip_id = BCM53018_DEVICE_ID, 2541 .dev_name = "BCM53018", 2542 .vlans = 4096, 2543 .enabled_ports = 0x1bf, 2544 .arl_bins = 4, 2545 .arl_buckets = 1024, 2546 .imp_port = 8, 2547 .vta_regs = B53_VTA_REGS, 2548 .duplex_reg = B53_DUPLEX_STAT_GE, 2549 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2550 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2551 }, 2552 { 2553 .chip_id = BCM53019_DEVICE_ID, 2554 .dev_name = "BCM53019", 2555 .vlans = 4096, 2556 .enabled_ports = 0x1bf, 2557 .arl_bins = 4, 2558 .arl_buckets = 1024, 2559 .imp_port = 8, 2560 .vta_regs = B53_VTA_REGS, 2561 .duplex_reg = B53_DUPLEX_STAT_GE, 2562 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2563 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2564 }, 2565 { 2566 .chip_id = BCM58XX_DEVICE_ID, 2567 .dev_name = "BCM585xx/586xx/88312", 2568 .vlans = 4096, 2569 .enabled_ports = 0x1ff, 2570 .arl_bins = 4, 2571 .arl_buckets = 1024, 2572 .imp_port = 8, 2573 .vta_regs = B53_VTA_REGS, 2574 .duplex_reg = B53_DUPLEX_STAT_GE, 2575 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2576 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2577 }, 2578 { 2579 .chip_id = BCM583XX_DEVICE_ID, 2580 .dev_name = "BCM583xx/11360", 2581 .vlans = 4096, 2582 .enabled_ports = 0x103, 2583 .arl_bins = 4, 2584 .arl_buckets = 1024, 2585 .imp_port = 8, 2586 .vta_regs = B53_VTA_REGS, 2587 .duplex_reg = B53_DUPLEX_STAT_GE, 2588 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2589 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2590 }, 2591 /* Starfighter 2 */ 2592 { 2593 .chip_id = BCM4908_DEVICE_ID, 2594 .dev_name = "BCM4908", 2595 .vlans = 4096, 2596 .enabled_ports = 0x1bf, 2597 .arl_bins = 4, 2598 .arl_buckets = 256, 2599 .imp_port = 8, 2600 .vta_regs = B53_VTA_REGS, 2601 .duplex_reg = B53_DUPLEX_STAT_GE, 2602 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2603 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2604 }, 2605 { 2606 .chip_id = BCM7445_DEVICE_ID, 2607 .dev_name = "BCM7445", 2608 .vlans = 4096, 2609 .enabled_ports = 0x1ff, 2610 .arl_bins = 4, 2611 .arl_buckets = 1024, 2612 .imp_port = 8, 2613 .vta_regs = B53_VTA_REGS, 2614 .duplex_reg = B53_DUPLEX_STAT_GE, 2615 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2616 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2617 }, 2618 { 2619 .chip_id = BCM7278_DEVICE_ID, 2620 .dev_name = "BCM7278", 2621 .vlans = 4096, 2622 .enabled_ports = 0x1ff, 2623 .arl_bins = 4, 2624 .arl_buckets = 256, 2625 .imp_port = 8, 2626 .vta_regs = B53_VTA_REGS, 2627 .duplex_reg = B53_DUPLEX_STAT_GE, 2628 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2629 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2630 }, 2631 { 2632 .chip_id = BCM53134_DEVICE_ID, 2633 .dev_name = "BCM53134", 2634 .vlans = 4096, 2635 .enabled_ports = 0x12f, 2636 .imp_port = 8, 2637 .cpu_port = B53_CPU_PORT, 2638 .vta_regs = B53_VTA_REGS, 2639 .arl_bins = 4, 2640 .arl_buckets = 1024, 2641 .duplex_reg = B53_DUPLEX_STAT_GE, 2642 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2643 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2644 }, 2645 }; 2646 2647 static int b53_switch_init(struct b53_device *dev) 2648 { 2649 unsigned int i; 2650 int ret; 2651 2652 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) { 2653 const struct b53_chip_data *chip = &b53_switch_chips[i]; 2654 2655 if (chip->chip_id == dev->chip_id) { 2656 if (!dev->enabled_ports) 2657 dev->enabled_ports = chip->enabled_ports; 2658 dev->name = chip->dev_name; 2659 dev->duplex_reg = chip->duplex_reg; 2660 dev->vta_regs[0] = chip->vta_regs[0]; 2661 dev->vta_regs[1] = chip->vta_regs[1]; 2662 dev->vta_regs[2] = chip->vta_regs[2]; 2663 dev->jumbo_pm_reg = chip->jumbo_pm_reg; 2664 dev->imp_port = chip->imp_port; 2665 dev->num_vlans = chip->vlans; 2666 dev->num_arl_bins = chip->arl_bins; 2667 dev->num_arl_buckets = chip->arl_buckets; 2668 break; 2669 } 2670 } 2671 2672 /* check which BCM5325x version we have */ 2673 if (is5325(dev)) { 2674 u8 vc4; 2675 2676 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 2677 2678 /* check reserved bits */ 2679 switch (vc4 & 3) { 2680 case 1: 2681 /* BCM5325E */ 2682 break; 2683 case 3: 2684 /* BCM5325F - do not use port 4 */ 2685 dev->enabled_ports &= ~BIT(4); 2686 break; 2687 default: 2688 /* On the BCM47XX SoCs this is the supported internal switch.*/ 2689 #ifndef CONFIG_BCM47XX 2690 /* BCM5325M */ 2691 return -EINVAL; 2692 #else 2693 break; 2694 #endif 2695 } 2696 } 2697 2698 dev->num_ports = fls(dev->enabled_ports); 2699 2700 dev->ds->num_ports = min_t(unsigned int, dev->num_ports, DSA_MAX_PORTS); 2701 2702 /* Include non standard CPU port built-in PHYs to be probed */ 2703 if (is539x(dev) || is531x5(dev)) { 2704 for (i = 0; i < dev->num_ports; i++) { 2705 if (!(dev->ds->phys_mii_mask & BIT(i)) && 2706 !b53_possible_cpu_port(dev->ds, i)) 2707 dev->ds->phys_mii_mask |= BIT(i); 2708 } 2709 } 2710 2711 dev->ports = devm_kcalloc(dev->dev, 2712 dev->num_ports, sizeof(struct b53_port), 2713 GFP_KERNEL); 2714 if (!dev->ports) 2715 return -ENOMEM; 2716 2717 dev->vlans = devm_kcalloc(dev->dev, 2718 dev->num_vlans, sizeof(struct b53_vlan), 2719 GFP_KERNEL); 2720 if (!dev->vlans) 2721 return -ENOMEM; 2722 2723 dev->reset_gpio = b53_switch_get_reset_gpio(dev); 2724 if (dev->reset_gpio >= 0) { 2725 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio, 2726 GPIOF_OUT_INIT_HIGH, "robo_reset"); 2727 if (ret) 2728 return ret; 2729 } 2730 2731 return 0; 2732 } 2733 2734 struct b53_device *b53_switch_alloc(struct device *base, 2735 const struct b53_io_ops *ops, 2736 void *priv) 2737 { 2738 struct dsa_switch *ds; 2739 struct b53_device *dev; 2740 2741 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 2742 if (!ds) 2743 return NULL; 2744 2745 ds->dev = base; 2746 2747 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL); 2748 if (!dev) 2749 return NULL; 2750 2751 ds->priv = dev; 2752 dev->dev = base; 2753 2754 dev->ds = ds; 2755 dev->priv = priv; 2756 dev->ops = ops; 2757 ds->ops = &b53_switch_ops; 2758 ds->phylink_mac_ops = &b53_phylink_mac_ops; 2759 dev->vlan_enabled = true; 2760 /* Let DSA handle the case were multiple bridges span the same switch 2761 * device and different VLAN awareness settings are requested, which 2762 * would be breaking filtering semantics for any of the other bridge 2763 * devices. (not hardware supported) 2764 */ 2765 ds->vlan_filtering_is_global = true; 2766 2767 mutex_init(&dev->reg_mutex); 2768 mutex_init(&dev->stats_mutex); 2769 mutex_init(&dev->arl_mutex); 2770 2771 return dev; 2772 } 2773 EXPORT_SYMBOL(b53_switch_alloc); 2774 2775 int b53_switch_detect(struct b53_device *dev) 2776 { 2777 u32 id32; 2778 u16 tmp; 2779 u8 id8; 2780 int ret; 2781 2782 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8); 2783 if (ret) 2784 return ret; 2785 2786 switch (id8) { 2787 case 0: 2788 /* BCM5325 and BCM5365 do not have this register so reads 2789 * return 0. But the read operation did succeed, so assume this 2790 * is one of them. 2791 * 2792 * Next check if we can write to the 5325's VTA register; for 2793 * 5365 it is read only. 2794 */ 2795 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf); 2796 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp); 2797 2798 if (tmp == 0xf) 2799 dev->chip_id = BCM5325_DEVICE_ID; 2800 else 2801 dev->chip_id = BCM5365_DEVICE_ID; 2802 break; 2803 case BCM5389_DEVICE_ID: 2804 case BCM5395_DEVICE_ID: 2805 case BCM5397_DEVICE_ID: 2806 case BCM5398_DEVICE_ID: 2807 dev->chip_id = id8; 2808 break; 2809 default: 2810 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32); 2811 if (ret) 2812 return ret; 2813 2814 switch (id32) { 2815 case BCM53101_DEVICE_ID: 2816 case BCM53115_DEVICE_ID: 2817 case BCM53125_DEVICE_ID: 2818 case BCM53128_DEVICE_ID: 2819 case BCM53010_DEVICE_ID: 2820 case BCM53011_DEVICE_ID: 2821 case BCM53012_DEVICE_ID: 2822 case BCM53018_DEVICE_ID: 2823 case BCM53019_DEVICE_ID: 2824 case BCM53134_DEVICE_ID: 2825 dev->chip_id = id32; 2826 break; 2827 default: 2828 dev_err(dev->dev, 2829 "unsupported switch detected (BCM53%02x/BCM%x)\n", 2830 id8, id32); 2831 return -ENODEV; 2832 } 2833 } 2834 2835 if (dev->chip_id == BCM5325_DEVICE_ID) 2836 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25, 2837 &dev->core_rev); 2838 else 2839 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID, 2840 &dev->core_rev); 2841 } 2842 EXPORT_SYMBOL(b53_switch_detect); 2843 2844 int b53_switch_register(struct b53_device *dev) 2845 { 2846 int ret; 2847 2848 if (dev->pdata) { 2849 dev->chip_id = dev->pdata->chip_id; 2850 dev->enabled_ports = dev->pdata->enabled_ports; 2851 } 2852 2853 if (!dev->chip_id && b53_switch_detect(dev)) 2854 return -EINVAL; 2855 2856 ret = b53_switch_init(dev); 2857 if (ret) 2858 return ret; 2859 2860 dev_info(dev->dev, "found switch: %s, rev %i\n", 2861 dev->name, dev->core_rev); 2862 2863 return dsa_register_switch(dev->ds); 2864 } 2865 EXPORT_SYMBOL(b53_switch_register); 2866 2867 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>"); 2868 MODULE_DESCRIPTION("B53 switch library"); 2869 MODULE_LICENSE("Dual BSD/GPL"); 2870