1 /* 2 * B53 switch driver main logic 3 * 4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org> 5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com> 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <linux/delay.h> 21 #include <linux/export.h> 22 #include <linux/gpio.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/platform_data/b53.h> 26 #include <linux/phy.h> 27 #include <linux/phylink.h> 28 #include <linux/etherdevice.h> 29 #include <linux/if_bridge.h> 30 #include <linux/if_vlan.h> 31 #include <net/dsa.h> 32 33 #include "b53_regs.h" 34 #include "b53_priv.h" 35 36 struct b53_mib_desc { 37 u8 size; 38 u8 offset; 39 const char *name; 40 }; 41 42 /* BCM5365 MIB counters */ 43 static const struct b53_mib_desc b53_mibs_65[] = { 44 { 8, 0x00, "TxOctets" }, 45 { 4, 0x08, "TxDropPkts" }, 46 { 4, 0x10, "TxBroadcastPkts" }, 47 { 4, 0x14, "TxMulticastPkts" }, 48 { 4, 0x18, "TxUnicastPkts" }, 49 { 4, 0x1c, "TxCollisions" }, 50 { 4, 0x20, "TxSingleCollision" }, 51 { 4, 0x24, "TxMultipleCollision" }, 52 { 4, 0x28, "TxDeferredTransmit" }, 53 { 4, 0x2c, "TxLateCollision" }, 54 { 4, 0x30, "TxExcessiveCollision" }, 55 { 4, 0x38, "TxPausePkts" }, 56 { 8, 0x44, "RxOctets" }, 57 { 4, 0x4c, "RxUndersizePkts" }, 58 { 4, 0x50, "RxPausePkts" }, 59 { 4, 0x54, "Pkts64Octets" }, 60 { 4, 0x58, "Pkts65to127Octets" }, 61 { 4, 0x5c, "Pkts128to255Octets" }, 62 { 4, 0x60, "Pkts256to511Octets" }, 63 { 4, 0x64, "Pkts512to1023Octets" }, 64 { 4, 0x68, "Pkts1024to1522Octets" }, 65 { 4, 0x6c, "RxOversizePkts" }, 66 { 4, 0x70, "RxJabbers" }, 67 { 4, 0x74, "RxAlignmentErrors" }, 68 { 4, 0x78, "RxFCSErrors" }, 69 { 8, 0x7c, "RxGoodOctets" }, 70 { 4, 0x84, "RxDropPkts" }, 71 { 4, 0x88, "RxUnicastPkts" }, 72 { 4, 0x8c, "RxMulticastPkts" }, 73 { 4, 0x90, "RxBroadcastPkts" }, 74 { 4, 0x94, "RxSAChanges" }, 75 { 4, 0x98, "RxFragments" }, 76 }; 77 78 #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65) 79 80 /* BCM63xx MIB counters */ 81 static const struct b53_mib_desc b53_mibs_63xx[] = { 82 { 8, 0x00, "TxOctets" }, 83 { 4, 0x08, "TxDropPkts" }, 84 { 4, 0x0c, "TxQoSPkts" }, 85 { 4, 0x10, "TxBroadcastPkts" }, 86 { 4, 0x14, "TxMulticastPkts" }, 87 { 4, 0x18, "TxUnicastPkts" }, 88 { 4, 0x1c, "TxCollisions" }, 89 { 4, 0x20, "TxSingleCollision" }, 90 { 4, 0x24, "TxMultipleCollision" }, 91 { 4, 0x28, "TxDeferredTransmit" }, 92 { 4, 0x2c, "TxLateCollision" }, 93 { 4, 0x30, "TxExcessiveCollision" }, 94 { 4, 0x38, "TxPausePkts" }, 95 { 8, 0x3c, "TxQoSOctets" }, 96 { 8, 0x44, "RxOctets" }, 97 { 4, 0x4c, "RxUndersizePkts" }, 98 { 4, 0x50, "RxPausePkts" }, 99 { 4, 0x54, "Pkts64Octets" }, 100 { 4, 0x58, "Pkts65to127Octets" }, 101 { 4, 0x5c, "Pkts128to255Octets" }, 102 { 4, 0x60, "Pkts256to511Octets" }, 103 { 4, 0x64, "Pkts512to1023Octets" }, 104 { 4, 0x68, "Pkts1024to1522Octets" }, 105 { 4, 0x6c, "RxOversizePkts" }, 106 { 4, 0x70, "RxJabbers" }, 107 { 4, 0x74, "RxAlignmentErrors" }, 108 { 4, 0x78, "RxFCSErrors" }, 109 { 8, 0x7c, "RxGoodOctets" }, 110 { 4, 0x84, "RxDropPkts" }, 111 { 4, 0x88, "RxUnicastPkts" }, 112 { 4, 0x8c, "RxMulticastPkts" }, 113 { 4, 0x90, "RxBroadcastPkts" }, 114 { 4, 0x94, "RxSAChanges" }, 115 { 4, 0x98, "RxFragments" }, 116 { 4, 0xa0, "RxSymbolErrors" }, 117 { 4, 0xa4, "RxQoSPkts" }, 118 { 8, 0xa8, "RxQoSOctets" }, 119 { 4, 0xb0, "Pkts1523to2047Octets" }, 120 { 4, 0xb4, "Pkts2048to4095Octets" }, 121 { 4, 0xb8, "Pkts4096to8191Octets" }, 122 { 4, 0xbc, "Pkts8192to9728Octets" }, 123 { 4, 0xc0, "RxDiscarded" }, 124 }; 125 126 #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx) 127 128 /* MIB counters */ 129 static const struct b53_mib_desc b53_mibs[] = { 130 { 8, 0x00, "TxOctets" }, 131 { 4, 0x08, "TxDropPkts" }, 132 { 4, 0x10, "TxBroadcastPkts" }, 133 { 4, 0x14, "TxMulticastPkts" }, 134 { 4, 0x18, "TxUnicastPkts" }, 135 { 4, 0x1c, "TxCollisions" }, 136 { 4, 0x20, "TxSingleCollision" }, 137 { 4, 0x24, "TxMultipleCollision" }, 138 { 4, 0x28, "TxDeferredTransmit" }, 139 { 4, 0x2c, "TxLateCollision" }, 140 { 4, 0x30, "TxExcessiveCollision" }, 141 { 4, 0x38, "TxPausePkts" }, 142 { 8, 0x50, "RxOctets" }, 143 { 4, 0x58, "RxUndersizePkts" }, 144 { 4, 0x5c, "RxPausePkts" }, 145 { 4, 0x60, "Pkts64Octets" }, 146 { 4, 0x64, "Pkts65to127Octets" }, 147 { 4, 0x68, "Pkts128to255Octets" }, 148 { 4, 0x6c, "Pkts256to511Octets" }, 149 { 4, 0x70, "Pkts512to1023Octets" }, 150 { 4, 0x74, "Pkts1024to1522Octets" }, 151 { 4, 0x78, "RxOversizePkts" }, 152 { 4, 0x7c, "RxJabbers" }, 153 { 4, 0x80, "RxAlignmentErrors" }, 154 { 4, 0x84, "RxFCSErrors" }, 155 { 8, 0x88, "RxGoodOctets" }, 156 { 4, 0x90, "RxDropPkts" }, 157 { 4, 0x94, "RxUnicastPkts" }, 158 { 4, 0x98, "RxMulticastPkts" }, 159 { 4, 0x9c, "RxBroadcastPkts" }, 160 { 4, 0xa0, "RxSAChanges" }, 161 { 4, 0xa4, "RxFragments" }, 162 { 4, 0xa8, "RxJumboPkts" }, 163 { 4, 0xac, "RxSymbolErrors" }, 164 { 4, 0xc0, "RxDiscarded" }, 165 }; 166 167 #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs) 168 169 static const struct b53_mib_desc b53_mibs_58xx[] = { 170 { 8, 0x00, "TxOctets" }, 171 { 4, 0x08, "TxDropPkts" }, 172 { 4, 0x0c, "TxQPKTQ0" }, 173 { 4, 0x10, "TxBroadcastPkts" }, 174 { 4, 0x14, "TxMulticastPkts" }, 175 { 4, 0x18, "TxUnicastPKts" }, 176 { 4, 0x1c, "TxCollisions" }, 177 { 4, 0x20, "TxSingleCollision" }, 178 { 4, 0x24, "TxMultipleCollision" }, 179 { 4, 0x28, "TxDeferredCollision" }, 180 { 4, 0x2c, "TxLateCollision" }, 181 { 4, 0x30, "TxExcessiveCollision" }, 182 { 4, 0x34, "TxFrameInDisc" }, 183 { 4, 0x38, "TxPausePkts" }, 184 { 4, 0x3c, "TxQPKTQ1" }, 185 { 4, 0x40, "TxQPKTQ2" }, 186 { 4, 0x44, "TxQPKTQ3" }, 187 { 4, 0x48, "TxQPKTQ4" }, 188 { 4, 0x4c, "TxQPKTQ5" }, 189 { 8, 0x50, "RxOctets" }, 190 { 4, 0x58, "RxUndersizePkts" }, 191 { 4, 0x5c, "RxPausePkts" }, 192 { 4, 0x60, "RxPkts64Octets" }, 193 { 4, 0x64, "RxPkts65to127Octets" }, 194 { 4, 0x68, "RxPkts128to255Octets" }, 195 { 4, 0x6c, "RxPkts256to511Octets" }, 196 { 4, 0x70, "RxPkts512to1023Octets" }, 197 { 4, 0x74, "RxPkts1024toMaxPktsOctets" }, 198 { 4, 0x78, "RxOversizePkts" }, 199 { 4, 0x7c, "RxJabbers" }, 200 { 4, 0x80, "RxAlignmentErrors" }, 201 { 4, 0x84, "RxFCSErrors" }, 202 { 8, 0x88, "RxGoodOctets" }, 203 { 4, 0x90, "RxDropPkts" }, 204 { 4, 0x94, "RxUnicastPkts" }, 205 { 4, 0x98, "RxMulticastPkts" }, 206 { 4, 0x9c, "RxBroadcastPkts" }, 207 { 4, 0xa0, "RxSAChanges" }, 208 { 4, 0xa4, "RxFragments" }, 209 { 4, 0xa8, "RxJumboPkt" }, 210 { 4, 0xac, "RxSymblErr" }, 211 { 4, 0xb0, "InRangeErrCount" }, 212 { 4, 0xb4, "OutRangeErrCount" }, 213 { 4, 0xb8, "EEELpiEvent" }, 214 { 4, 0xbc, "EEELpiDuration" }, 215 { 4, 0xc0, "RxDiscard" }, 216 { 4, 0xc8, "TxQPKTQ6" }, 217 { 4, 0xcc, "TxQPKTQ7" }, 218 { 4, 0xd0, "TxPkts64Octets" }, 219 { 4, 0xd4, "TxPkts65to127Octets" }, 220 { 4, 0xd8, "TxPkts128to255Octets" }, 221 { 4, 0xdc, "TxPkts256to511Ocets" }, 222 { 4, 0xe0, "TxPkts512to1023Ocets" }, 223 { 4, 0xe4, "TxPkts1024toMaxPktOcets" }, 224 }; 225 226 #define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx) 227 228 #define B53_MAX_MTU_25 (1536 - ETH_HLEN - VLAN_HLEN - ETH_FCS_LEN) 229 #define B53_MAX_MTU (9720 - ETH_HLEN - VLAN_HLEN - ETH_FCS_LEN) 230 231 static int b53_do_vlan_op(struct b53_device *dev, u8 op) 232 { 233 unsigned int i; 234 235 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op); 236 237 for (i = 0; i < 10; i++) { 238 u8 vta; 239 240 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta); 241 if (!(vta & VTA_START_CMD)) 242 return 0; 243 244 usleep_range(100, 200); 245 } 246 247 return -EIO; 248 } 249 250 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, 251 struct b53_vlan *vlan) 252 { 253 if (is5325(dev)) { 254 u32 entry = 0; 255 256 if (vlan->members) { 257 entry = ((vlan->untag & VA_UNTAG_MASK_25) << 258 VA_UNTAG_S_25) | vlan->members; 259 if (dev->core_rev >= 3) 260 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S; 261 else 262 entry |= VA_VALID_25; 263 } 264 265 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry); 266 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 267 VTA_RW_STATE_WR | VTA_RW_OP_EN); 268 } else if (is5365(dev)) { 269 u16 entry = 0; 270 271 if (vlan->members) 272 entry = ((vlan->untag & VA_UNTAG_MASK_65) << 273 VA_UNTAG_S_65) | vlan->members | VA_VALID_65; 274 275 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry); 276 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 277 VTA_RW_STATE_WR | VTA_RW_OP_EN); 278 } else { 279 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 280 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], 281 (vlan->untag << VTE_UNTAG_S) | vlan->members); 282 283 b53_do_vlan_op(dev, VTA_CMD_WRITE); 284 } 285 286 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n", 287 vid, vlan->members, vlan->untag); 288 } 289 290 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid, 291 struct b53_vlan *vlan) 292 { 293 if (is5325(dev)) { 294 u32 entry = 0; 295 296 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 297 VTA_RW_STATE_RD | VTA_RW_OP_EN); 298 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry); 299 300 if (dev->core_rev >= 3) 301 vlan->valid = !!(entry & VA_VALID_25_R4); 302 else 303 vlan->valid = !!(entry & VA_VALID_25); 304 vlan->members = entry & VA_MEMBER_MASK; 305 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25; 306 307 } else if (is5365(dev)) { 308 u16 entry = 0; 309 310 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 311 VTA_RW_STATE_WR | VTA_RW_OP_EN); 312 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry); 313 314 vlan->valid = !!(entry & VA_VALID_65); 315 vlan->members = entry & VA_MEMBER_MASK; 316 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65; 317 } else { 318 u32 entry = 0; 319 320 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 321 b53_do_vlan_op(dev, VTA_CMD_READ); 322 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry); 323 vlan->members = entry & VTE_MEMBERS; 324 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS; 325 vlan->valid = true; 326 } 327 } 328 329 static void b53_set_forwarding(struct b53_device *dev, int enable) 330 { 331 u8 mgmt; 332 333 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 334 335 if (enable) 336 mgmt |= SM_SW_FWD_EN; 337 else 338 mgmt &= ~SM_SW_FWD_EN; 339 340 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 341 342 /* Include IMP port in dumb forwarding mode 343 */ 344 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt); 345 mgmt |= B53_MII_DUMB_FWDG_EN; 346 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt); 347 348 /* Look at B53_UC_FWD_EN and B53_MC_FWD_EN to decide whether 349 * frames should be flooded or not. 350 */ 351 b53_read8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, &mgmt); 352 mgmt |= B53_UC_FWD_EN | B53_MC_FWD_EN | B53_IPMC_FWD_EN; 353 b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt); 354 } 355 356 static void b53_enable_vlan(struct b53_device *dev, int port, bool enable, 357 bool enable_filtering) 358 { 359 u8 mgmt, vc0, vc1, vc4 = 0, vc5; 360 361 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 362 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0); 363 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1); 364 365 if (is5325(dev) || is5365(dev)) { 366 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 367 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5); 368 } else if (is63xx(dev)) { 369 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4); 370 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5); 371 } else { 372 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4); 373 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5); 374 } 375 376 if (enable) { 377 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID; 378 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN; 379 vc4 &= ~VC4_ING_VID_CHECK_MASK; 380 if (enable_filtering) { 381 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S; 382 vc5 |= VC5_DROP_VTABLE_MISS; 383 } else { 384 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 385 vc5 &= ~VC5_DROP_VTABLE_MISS; 386 } 387 388 if (is5325(dev)) 389 vc0 &= ~VC0_RESERVED_1; 390 391 if (is5325(dev) || is5365(dev)) 392 vc1 |= VC1_RX_MCST_TAG_EN; 393 394 } else { 395 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID); 396 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN); 397 vc4 &= ~VC4_ING_VID_CHECK_MASK; 398 vc5 &= ~VC5_DROP_VTABLE_MISS; 399 400 if (is5325(dev) || is5365(dev)) 401 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 402 else 403 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S; 404 405 if (is5325(dev) || is5365(dev)) 406 vc1 &= ~VC1_RX_MCST_TAG_EN; 407 } 408 409 if (!is5325(dev) && !is5365(dev)) 410 vc5 &= ~VC5_VID_FFF_EN; 411 412 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0); 413 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1); 414 415 if (is5325(dev) || is5365(dev)) { 416 /* enable the high 8 bit vid check on 5325 */ 417 if (is5325(dev) && enable) 418 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 419 VC3_HIGH_8BIT_EN); 420 else 421 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 422 423 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4); 424 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5); 425 } else if (is63xx(dev)) { 426 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0); 427 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4); 428 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5); 429 } else { 430 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 431 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4); 432 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5); 433 } 434 435 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 436 437 dev->vlan_enabled = enable; 438 439 dev_dbg(dev->dev, "Port %d VLAN enabled: %d, filtering: %d\n", 440 port, enable, enable_filtering); 441 } 442 443 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100) 444 { 445 u32 port_mask = 0; 446 u16 max_size = JMS_MIN_SIZE; 447 448 if (is5325(dev) || is5365(dev)) 449 return -EINVAL; 450 451 if (enable) { 452 port_mask = dev->enabled_ports; 453 max_size = JMS_MAX_SIZE; 454 if (allow_10_100) 455 port_mask |= JPM_10_100_JUMBO_EN; 456 } 457 458 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask); 459 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size); 460 } 461 462 static int b53_flush_arl(struct b53_device *dev, u8 mask) 463 { 464 unsigned int i; 465 466 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 467 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask); 468 469 for (i = 0; i < 10; i++) { 470 u8 fast_age_ctrl; 471 472 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 473 &fast_age_ctrl); 474 475 if (!(fast_age_ctrl & FAST_AGE_DONE)) 476 goto out; 477 478 msleep(1); 479 } 480 481 return -ETIMEDOUT; 482 out: 483 /* Only age dynamic entries (default behavior) */ 484 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC); 485 return 0; 486 } 487 488 static int b53_fast_age_port(struct b53_device *dev, int port) 489 { 490 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port); 491 492 return b53_flush_arl(dev, FAST_AGE_PORT); 493 } 494 495 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid) 496 { 497 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid); 498 499 return b53_flush_arl(dev, FAST_AGE_VLAN); 500 } 501 502 void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port) 503 { 504 struct b53_device *dev = ds->priv; 505 unsigned int i; 506 u16 pvlan; 507 508 /* Enable the IMP port to be in the same VLAN as the other ports 509 * on a per-port basis such that we only have Port i and IMP in 510 * the same VLAN. 511 */ 512 b53_for_each_port(dev, i) { 513 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan); 514 pvlan |= BIT(cpu_port); 515 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan); 516 } 517 } 518 EXPORT_SYMBOL(b53_imp_vlan_setup); 519 520 static void b53_port_set_ucast_flood(struct b53_device *dev, int port, 521 bool unicast) 522 { 523 u16 uc; 524 525 b53_read16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, &uc); 526 if (unicast) 527 uc |= BIT(port); 528 else 529 uc &= ~BIT(port); 530 b53_write16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, uc); 531 } 532 533 static void b53_port_set_mcast_flood(struct b53_device *dev, int port, 534 bool multicast) 535 { 536 u16 mc; 537 538 b53_read16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, &mc); 539 if (multicast) 540 mc |= BIT(port); 541 else 542 mc &= ~BIT(port); 543 b53_write16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, mc); 544 545 b53_read16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, &mc); 546 if (multicast) 547 mc |= BIT(port); 548 else 549 mc &= ~BIT(port); 550 b53_write16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, mc); 551 } 552 553 static void b53_port_set_learning(struct b53_device *dev, int port, 554 bool learning) 555 { 556 u16 reg; 557 558 b53_read16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, ®); 559 if (learning) 560 reg &= ~BIT(port); 561 else 562 reg |= BIT(port); 563 b53_write16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, reg); 564 } 565 566 static void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable) 567 { 568 struct b53_device *dev = ds->priv; 569 u16 reg; 570 571 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, ®); 572 if (enable) 573 reg |= BIT(port); 574 else 575 reg &= ~BIT(port); 576 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg); 577 } 578 579 int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy) 580 { 581 struct b53_device *dev = ds->priv; 582 unsigned int cpu_port; 583 int ret = 0; 584 u16 pvlan; 585 586 if (!dsa_is_user_port(ds, port)) 587 return 0; 588 589 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 590 591 b53_port_set_ucast_flood(dev, port, true); 592 b53_port_set_mcast_flood(dev, port, true); 593 b53_port_set_learning(dev, port, false); 594 595 if (dev->ops->irq_enable) 596 ret = dev->ops->irq_enable(dev, port); 597 if (ret) 598 return ret; 599 600 /* Clear the Rx and Tx disable bits and set to no spanning tree */ 601 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0); 602 603 /* Set this port, and only this one to be in the default VLAN, 604 * if member of a bridge, restore its membership prior to 605 * bringing down this port. 606 */ 607 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 608 pvlan &= ~0x1ff; 609 pvlan |= BIT(port); 610 pvlan |= dev->ports[port].vlan_ctl_mask; 611 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 612 613 b53_imp_vlan_setup(ds, cpu_port); 614 615 /* If EEE was enabled, restore it */ 616 if (dev->ports[port].eee.eee_enabled) 617 b53_eee_enable_set(ds, port, true); 618 619 return 0; 620 } 621 EXPORT_SYMBOL(b53_enable_port); 622 623 void b53_disable_port(struct dsa_switch *ds, int port) 624 { 625 struct b53_device *dev = ds->priv; 626 u8 reg; 627 628 /* Disable Tx/Rx for the port */ 629 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 630 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE; 631 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 632 633 if (dev->ops->irq_disable) 634 dev->ops->irq_disable(dev, port); 635 } 636 EXPORT_SYMBOL(b53_disable_port); 637 638 void b53_brcm_hdr_setup(struct dsa_switch *ds, int port) 639 { 640 struct b53_device *dev = ds->priv; 641 bool tag_en = !(dev->tag_protocol == DSA_TAG_PROTO_NONE); 642 u8 hdr_ctl, val; 643 u16 reg; 644 645 /* Resolve which bit controls the Broadcom tag */ 646 switch (port) { 647 case 8: 648 val = BRCM_HDR_P8_EN; 649 break; 650 case 7: 651 val = BRCM_HDR_P7_EN; 652 break; 653 case 5: 654 val = BRCM_HDR_P5_EN; 655 break; 656 default: 657 val = 0; 658 break; 659 } 660 661 /* Enable management mode if tagging is requested */ 662 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &hdr_ctl); 663 if (tag_en) 664 hdr_ctl |= SM_SW_FWD_MODE; 665 else 666 hdr_ctl &= ~SM_SW_FWD_MODE; 667 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, hdr_ctl); 668 669 /* Configure the appropriate IMP port */ 670 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &hdr_ctl); 671 if (port == 8) 672 hdr_ctl |= GC_FRM_MGMT_PORT_MII; 673 else if (port == 5) 674 hdr_ctl |= GC_FRM_MGMT_PORT_M; 675 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, hdr_ctl); 676 677 /* Enable Broadcom tags for IMP port */ 678 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl); 679 if (tag_en) 680 hdr_ctl |= val; 681 else 682 hdr_ctl &= ~val; 683 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl); 684 685 /* Registers below are only accessible on newer devices */ 686 if (!is58xx(dev)) 687 return; 688 689 /* Enable reception Broadcom tag for CPU TX (switch RX) to 690 * allow us to tag outgoing frames 691 */ 692 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, ®); 693 if (tag_en) 694 reg &= ~BIT(port); 695 else 696 reg |= BIT(port); 697 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg); 698 699 /* Enable transmission of Broadcom tags from the switch (CPU RX) to 700 * allow delivering frames to the per-port net_devices 701 */ 702 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, ®); 703 if (tag_en) 704 reg &= ~BIT(port); 705 else 706 reg |= BIT(port); 707 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg); 708 } 709 EXPORT_SYMBOL(b53_brcm_hdr_setup); 710 711 static void b53_enable_cpu_port(struct b53_device *dev, int port) 712 { 713 u8 port_ctrl; 714 715 /* BCM5325 CPU port is at 8 */ 716 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25) 717 port = B53_CPU_PORT; 718 719 port_ctrl = PORT_CTRL_RX_BCST_EN | 720 PORT_CTRL_RX_MCST_EN | 721 PORT_CTRL_RX_UCST_EN; 722 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl); 723 724 b53_brcm_hdr_setup(dev->ds, port); 725 726 b53_port_set_ucast_flood(dev, port, true); 727 b53_port_set_mcast_flood(dev, port, true); 728 b53_port_set_learning(dev, port, false); 729 } 730 731 static void b53_enable_mib(struct b53_device *dev) 732 { 733 u8 gc; 734 735 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 736 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN); 737 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc); 738 } 739 740 static u16 b53_default_pvid(struct b53_device *dev) 741 { 742 if (is5325(dev) || is5365(dev)) 743 return 1; 744 else 745 return 0; 746 } 747 748 static bool b53_vlan_port_needs_forced_tagged(struct dsa_switch *ds, int port) 749 { 750 struct b53_device *dev = ds->priv; 751 752 return dev->tag_protocol == DSA_TAG_PROTO_NONE && dsa_is_cpu_port(ds, port); 753 } 754 755 int b53_configure_vlan(struct dsa_switch *ds) 756 { 757 struct b53_device *dev = ds->priv; 758 struct b53_vlan vl = { 0 }; 759 struct b53_vlan *v; 760 int i, def_vid; 761 u16 vid; 762 763 def_vid = b53_default_pvid(dev); 764 765 /* clear all vlan entries */ 766 if (is5325(dev) || is5365(dev)) { 767 for (i = def_vid; i < dev->num_vlans; i++) 768 b53_set_vlan_entry(dev, i, &vl); 769 } else { 770 b53_do_vlan_op(dev, VTA_CMD_CLEAR); 771 } 772 773 b53_enable_vlan(dev, -1, dev->vlan_enabled, ds->vlan_filtering); 774 775 /* Create an untagged VLAN entry for the default PVID in case 776 * CONFIG_VLAN_8021Q is disabled and there are no calls to 777 * dsa_user_vlan_rx_add_vid() to create the default VLAN 778 * entry. Do this only when the tagging protocol is not 779 * DSA_TAG_PROTO_NONE 780 */ 781 b53_for_each_port(dev, i) { 782 v = &dev->vlans[def_vid]; 783 v->members |= BIT(i); 784 if (!b53_vlan_port_needs_forced_tagged(ds, i)) 785 v->untag = v->members; 786 b53_write16(dev, B53_VLAN_PAGE, 787 B53_VLAN_PORT_DEF_TAG(i), def_vid); 788 } 789 790 /* Upon initial call we have not set-up any VLANs, but upon 791 * system resume, we need to restore all VLAN entries. 792 */ 793 for (vid = def_vid; vid < dev->num_vlans; vid++) { 794 v = &dev->vlans[vid]; 795 796 if (!v->members) 797 continue; 798 799 b53_set_vlan_entry(dev, vid, v); 800 b53_fast_age_vlan(dev, vid); 801 } 802 803 return 0; 804 } 805 EXPORT_SYMBOL(b53_configure_vlan); 806 807 static void b53_switch_reset_gpio(struct b53_device *dev) 808 { 809 int gpio = dev->reset_gpio; 810 811 if (gpio < 0) 812 return; 813 814 /* Reset sequence: RESET low(50ms)->high(20ms) 815 */ 816 gpio_set_value(gpio, 0); 817 mdelay(50); 818 819 gpio_set_value(gpio, 1); 820 mdelay(20); 821 822 dev->current_page = 0xff; 823 } 824 825 static int b53_switch_reset(struct b53_device *dev) 826 { 827 unsigned int timeout = 1000; 828 u8 mgmt, reg; 829 830 b53_switch_reset_gpio(dev); 831 832 if (is539x(dev)) { 833 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83); 834 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00); 835 } 836 837 /* This is specific to 58xx devices here, do not use is58xx() which 838 * covers the larger Starfigther 2 family, including 7445/7278 which 839 * still use this driver as a library and need to perform the reset 840 * earlier. 841 */ 842 if (dev->chip_id == BCM58XX_DEVICE_ID || 843 dev->chip_id == BCM583XX_DEVICE_ID) { 844 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 845 reg |= SW_RST | EN_SW_RST | EN_CH_RST; 846 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg); 847 848 do { 849 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 850 if (!(reg & SW_RST)) 851 break; 852 853 usleep_range(1000, 2000); 854 } while (timeout-- > 0); 855 856 if (timeout == 0) { 857 dev_err(dev->dev, 858 "Timeout waiting for SW_RST to clear!\n"); 859 return -ETIMEDOUT; 860 } 861 } 862 863 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 864 865 if (!(mgmt & SM_SW_FWD_EN)) { 866 mgmt &= ~SM_SW_FWD_MODE; 867 mgmt |= SM_SW_FWD_EN; 868 869 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 870 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 871 872 if (!(mgmt & SM_SW_FWD_EN)) { 873 dev_err(dev->dev, "Failed to enable switch!\n"); 874 return -EINVAL; 875 } 876 } 877 878 b53_enable_mib(dev); 879 880 return b53_flush_arl(dev, FAST_AGE_STATIC); 881 } 882 883 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg) 884 { 885 struct b53_device *priv = ds->priv; 886 u16 value = 0; 887 int ret; 888 889 if (priv->ops->phy_read16) 890 ret = priv->ops->phy_read16(priv, addr, reg, &value); 891 else 892 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr), 893 reg * 2, &value); 894 895 return ret ? ret : value; 896 } 897 898 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 899 { 900 struct b53_device *priv = ds->priv; 901 902 if (priv->ops->phy_write16) 903 return priv->ops->phy_write16(priv, addr, reg, val); 904 905 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val); 906 } 907 908 static int b53_reset_switch(struct b53_device *priv) 909 { 910 /* reset vlans */ 911 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans); 912 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports); 913 914 priv->serdes_lane = B53_INVALID_LANE; 915 916 return b53_switch_reset(priv); 917 } 918 919 static int b53_apply_config(struct b53_device *priv) 920 { 921 /* disable switching */ 922 b53_set_forwarding(priv, 0); 923 924 b53_configure_vlan(priv->ds); 925 926 /* enable switching */ 927 b53_set_forwarding(priv, 1); 928 929 return 0; 930 } 931 932 static void b53_reset_mib(struct b53_device *priv) 933 { 934 u8 gc; 935 936 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 937 938 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB); 939 msleep(1); 940 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB); 941 msleep(1); 942 } 943 944 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev) 945 { 946 if (is5365(dev)) 947 return b53_mibs_65; 948 else if (is63xx(dev)) 949 return b53_mibs_63xx; 950 else if (is58xx(dev)) 951 return b53_mibs_58xx; 952 else 953 return b53_mibs; 954 } 955 956 static unsigned int b53_get_mib_size(struct b53_device *dev) 957 { 958 if (is5365(dev)) 959 return B53_MIBS_65_SIZE; 960 else if (is63xx(dev)) 961 return B53_MIBS_63XX_SIZE; 962 else if (is58xx(dev)) 963 return B53_MIBS_58XX_SIZE; 964 else 965 return B53_MIBS_SIZE; 966 } 967 968 static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port) 969 { 970 /* These ports typically do not have built-in PHYs */ 971 switch (port) { 972 case B53_CPU_PORT_25: 973 case 7: 974 case B53_CPU_PORT: 975 return NULL; 976 } 977 978 return mdiobus_get_phy(ds->user_mii_bus, port); 979 } 980 981 void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset, 982 uint8_t *data) 983 { 984 struct b53_device *dev = ds->priv; 985 const struct b53_mib_desc *mibs = b53_get_mib(dev); 986 unsigned int mib_size = b53_get_mib_size(dev); 987 struct phy_device *phydev; 988 unsigned int i; 989 990 if (stringset == ETH_SS_STATS) { 991 for (i = 0; i < mib_size; i++) 992 ethtool_puts(&data, mibs[i].name); 993 } else if (stringset == ETH_SS_PHY_STATS) { 994 phydev = b53_get_phy_device(ds, port); 995 if (!phydev) 996 return; 997 998 phy_ethtool_get_strings(phydev, data); 999 } 1000 } 1001 EXPORT_SYMBOL(b53_get_strings); 1002 1003 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) 1004 { 1005 struct b53_device *dev = ds->priv; 1006 const struct b53_mib_desc *mibs = b53_get_mib(dev); 1007 unsigned int mib_size = b53_get_mib_size(dev); 1008 const struct b53_mib_desc *s; 1009 unsigned int i; 1010 u64 val = 0; 1011 1012 if (is5365(dev) && port == 5) 1013 port = 8; 1014 1015 mutex_lock(&dev->stats_mutex); 1016 1017 for (i = 0; i < mib_size; i++) { 1018 s = &mibs[i]; 1019 1020 if (s->size == 8) { 1021 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val); 1022 } else { 1023 u32 val32; 1024 1025 b53_read32(dev, B53_MIB_PAGE(port), s->offset, 1026 &val32); 1027 val = val32; 1028 } 1029 data[i] = (u64)val; 1030 } 1031 1032 mutex_unlock(&dev->stats_mutex); 1033 } 1034 EXPORT_SYMBOL(b53_get_ethtool_stats); 1035 1036 void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data) 1037 { 1038 struct phy_device *phydev; 1039 1040 phydev = b53_get_phy_device(ds, port); 1041 if (!phydev) 1042 return; 1043 1044 phy_ethtool_get_stats(phydev, NULL, data); 1045 } 1046 EXPORT_SYMBOL(b53_get_ethtool_phy_stats); 1047 1048 int b53_get_sset_count(struct dsa_switch *ds, int port, int sset) 1049 { 1050 struct b53_device *dev = ds->priv; 1051 struct phy_device *phydev; 1052 1053 if (sset == ETH_SS_STATS) { 1054 return b53_get_mib_size(dev); 1055 } else if (sset == ETH_SS_PHY_STATS) { 1056 phydev = b53_get_phy_device(ds, port); 1057 if (!phydev) 1058 return 0; 1059 1060 return phy_ethtool_get_sset_count(phydev); 1061 } 1062 1063 return 0; 1064 } 1065 EXPORT_SYMBOL(b53_get_sset_count); 1066 1067 enum b53_devlink_resource_id { 1068 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1069 }; 1070 1071 static u64 b53_devlink_vlan_table_get(void *priv) 1072 { 1073 struct b53_device *dev = priv; 1074 struct b53_vlan *vl; 1075 unsigned int i; 1076 u64 count = 0; 1077 1078 for (i = 0; i < dev->num_vlans; i++) { 1079 vl = &dev->vlans[i]; 1080 if (vl->members) 1081 count++; 1082 } 1083 1084 return count; 1085 } 1086 1087 int b53_setup_devlink_resources(struct dsa_switch *ds) 1088 { 1089 struct devlink_resource_size_params size_params; 1090 struct b53_device *dev = ds->priv; 1091 int err; 1092 1093 devlink_resource_size_params_init(&size_params, dev->num_vlans, 1094 dev->num_vlans, 1095 1, DEVLINK_RESOURCE_UNIT_ENTRY); 1096 1097 err = dsa_devlink_resource_register(ds, "VLAN", dev->num_vlans, 1098 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1099 DEVLINK_RESOURCE_ID_PARENT_TOP, 1100 &size_params); 1101 if (err) 1102 goto out; 1103 1104 dsa_devlink_resource_occ_get_register(ds, 1105 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1106 b53_devlink_vlan_table_get, dev); 1107 1108 return 0; 1109 out: 1110 dsa_devlink_resources_unregister(ds); 1111 return err; 1112 } 1113 EXPORT_SYMBOL(b53_setup_devlink_resources); 1114 1115 static int b53_setup(struct dsa_switch *ds) 1116 { 1117 struct b53_device *dev = ds->priv; 1118 unsigned int port; 1119 int ret; 1120 1121 /* Request bridge PVID untagged when DSA_TAG_PROTO_NONE is set 1122 * which forces the CPU port to be tagged in all VLANs. 1123 */ 1124 ds->untag_bridge_pvid = dev->tag_protocol == DSA_TAG_PROTO_NONE; 1125 1126 ret = b53_reset_switch(dev); 1127 if (ret) { 1128 dev_err(ds->dev, "failed to reset switch\n"); 1129 return ret; 1130 } 1131 1132 b53_reset_mib(dev); 1133 1134 ret = b53_apply_config(dev); 1135 if (ret) { 1136 dev_err(ds->dev, "failed to apply configuration\n"); 1137 return ret; 1138 } 1139 1140 /* Configure IMP/CPU port, disable all other ports. Enabled 1141 * ports will be configured with .port_enable 1142 */ 1143 for (port = 0; port < dev->num_ports; port++) { 1144 if (dsa_is_cpu_port(ds, port)) 1145 b53_enable_cpu_port(dev, port); 1146 else 1147 b53_disable_port(ds, port); 1148 } 1149 1150 return b53_setup_devlink_resources(ds); 1151 } 1152 1153 static void b53_teardown(struct dsa_switch *ds) 1154 { 1155 dsa_devlink_resources_unregister(ds); 1156 } 1157 1158 static void b53_force_link(struct b53_device *dev, int port, int link) 1159 { 1160 u8 reg, val, off; 1161 1162 /* Override the port settings */ 1163 if (port == dev->imp_port) { 1164 off = B53_PORT_OVERRIDE_CTRL; 1165 val = PORT_OVERRIDE_EN; 1166 } else { 1167 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 1168 val = GMII_PO_EN; 1169 } 1170 1171 b53_read8(dev, B53_CTRL_PAGE, off, ®); 1172 reg |= val; 1173 if (link) 1174 reg |= PORT_OVERRIDE_LINK; 1175 else 1176 reg &= ~PORT_OVERRIDE_LINK; 1177 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1178 } 1179 1180 static void b53_force_port_config(struct b53_device *dev, int port, 1181 int speed, int duplex, 1182 bool tx_pause, bool rx_pause) 1183 { 1184 u8 reg, val, off; 1185 1186 /* Override the port settings */ 1187 if (port == dev->imp_port) { 1188 off = B53_PORT_OVERRIDE_CTRL; 1189 val = PORT_OVERRIDE_EN; 1190 } else { 1191 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 1192 val = GMII_PO_EN; 1193 } 1194 1195 b53_read8(dev, B53_CTRL_PAGE, off, ®); 1196 reg |= val; 1197 if (duplex == DUPLEX_FULL) 1198 reg |= PORT_OVERRIDE_FULL_DUPLEX; 1199 else 1200 reg &= ~PORT_OVERRIDE_FULL_DUPLEX; 1201 1202 switch (speed) { 1203 case 2000: 1204 reg |= PORT_OVERRIDE_SPEED_2000M; 1205 fallthrough; 1206 case SPEED_1000: 1207 reg |= PORT_OVERRIDE_SPEED_1000M; 1208 break; 1209 case SPEED_100: 1210 reg |= PORT_OVERRIDE_SPEED_100M; 1211 break; 1212 case SPEED_10: 1213 reg |= PORT_OVERRIDE_SPEED_10M; 1214 break; 1215 default: 1216 dev_err(dev->dev, "unknown speed: %d\n", speed); 1217 return; 1218 } 1219 1220 if (rx_pause) 1221 reg |= PORT_OVERRIDE_RX_FLOW; 1222 if (tx_pause) 1223 reg |= PORT_OVERRIDE_TX_FLOW; 1224 1225 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1226 } 1227 1228 static void b53_adjust_63xx_rgmii(struct dsa_switch *ds, int port, 1229 phy_interface_t interface) 1230 { 1231 struct b53_device *dev = ds->priv; 1232 u8 rgmii_ctrl = 0, off; 1233 1234 if (port == dev->imp_port) 1235 off = B53_RGMII_CTRL_IMP; 1236 else 1237 off = B53_RGMII_CTRL_P(port); 1238 1239 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl); 1240 1241 switch (interface) { 1242 case PHY_INTERFACE_MODE_RGMII_ID: 1243 rgmii_ctrl |= (RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC); 1244 break; 1245 case PHY_INTERFACE_MODE_RGMII_RXID: 1246 rgmii_ctrl &= ~(RGMII_CTRL_DLL_TXC); 1247 rgmii_ctrl |= RGMII_CTRL_DLL_RXC; 1248 break; 1249 case PHY_INTERFACE_MODE_RGMII_TXID: 1250 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC); 1251 rgmii_ctrl |= RGMII_CTRL_DLL_TXC; 1252 break; 1253 case PHY_INTERFACE_MODE_RGMII: 1254 default: 1255 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC); 1256 break; 1257 } 1258 1259 if (port != dev->imp_port) { 1260 if (is63268(dev)) 1261 rgmii_ctrl |= RGMII_CTRL_MII_OVERRIDE; 1262 1263 rgmii_ctrl |= RGMII_CTRL_ENABLE_GMII; 1264 } 1265 1266 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl); 1267 1268 dev_dbg(ds->dev, "Configured port %d for %s\n", port, 1269 phy_modes(interface)); 1270 } 1271 1272 static void b53_adjust_531x5_rgmii(struct dsa_switch *ds, int port, 1273 phy_interface_t interface) 1274 { 1275 struct b53_device *dev = ds->priv; 1276 u8 rgmii_ctrl = 0, off; 1277 1278 if (port == dev->imp_port) 1279 off = B53_RGMII_CTRL_IMP; 1280 else 1281 off = B53_RGMII_CTRL_P(port); 1282 1283 /* Configure the port RGMII clock delay by DLL disabled and 1284 * tx_clk aligned timing (restoring to reset defaults) 1285 */ 1286 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl); 1287 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC | 1288 RGMII_CTRL_TIMING_SEL); 1289 1290 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make 1291 * sure that we enable the port TX clock internal delay to 1292 * account for this internal delay that is inserted, otherwise 1293 * the switch won't be able to receive correctly. 1294 * 1295 * PHY_INTERFACE_MODE_RGMII means that we are not introducing 1296 * any delay neither on transmission nor reception, so the 1297 * BCM53125 must also be configured accordingly to account for 1298 * the lack of delay and introduce 1299 * 1300 * The BCM53125 switch has its RX clock and TX clock control 1301 * swapped, hence the reason why we modify the TX clock path in 1302 * the "RGMII" case 1303 */ 1304 if (interface == PHY_INTERFACE_MODE_RGMII_TXID) 1305 rgmii_ctrl |= RGMII_CTRL_DLL_TXC; 1306 if (interface == PHY_INTERFACE_MODE_RGMII) 1307 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC; 1308 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL; 1309 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl); 1310 1311 dev_info(ds->dev, "Configured port %d for %s\n", port, 1312 phy_modes(interface)); 1313 } 1314 1315 static void b53_adjust_5325_mii(struct dsa_switch *ds, int port) 1316 { 1317 struct b53_device *dev = ds->priv; 1318 u8 reg = 0; 1319 1320 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1321 ®); 1322 1323 /* reverse mii needs to be enabled */ 1324 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1325 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1326 reg | PORT_OVERRIDE_RV_MII_25); 1327 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1328 ®); 1329 1330 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1331 dev_err(ds->dev, 1332 "Failed to enable reverse MII mode\n"); 1333 return; 1334 } 1335 } 1336 } 1337 1338 void b53_port_event(struct dsa_switch *ds, int port) 1339 { 1340 struct b53_device *dev = ds->priv; 1341 bool link; 1342 u16 sts; 1343 1344 b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts); 1345 link = !!(sts & BIT(port)); 1346 dsa_port_phylink_mac_change(ds, port, link); 1347 } 1348 EXPORT_SYMBOL(b53_port_event); 1349 1350 static void b53_phylink_get_caps(struct dsa_switch *ds, int port, 1351 struct phylink_config *config) 1352 { 1353 struct b53_device *dev = ds->priv; 1354 1355 /* Internal ports need GMII for PHYLIB */ 1356 __set_bit(PHY_INTERFACE_MODE_GMII, config->supported_interfaces); 1357 1358 /* These switches appear to support MII and RevMII too, but beyond 1359 * this, the code gives very few clues. FIXME: We probably need more 1360 * interface modes here. 1361 * 1362 * According to b53_srab_mux_init(), ports 3..5 can support: 1363 * SGMII, MII, GMII, RGMII or INTERNAL depending on the MUX setting. 1364 * However, the interface mode read from the MUX configuration is 1365 * not passed back to DSA, so phylink uses NA. 1366 * DT can specify RGMII for ports 0, 1. 1367 * For MDIO, port 8 can be RGMII_TXID. 1368 */ 1369 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 1370 __set_bit(PHY_INTERFACE_MODE_REVMII, config->supported_interfaces); 1371 1372 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 1373 MAC_10 | MAC_100; 1374 1375 /* 5325/5365 are not capable of gigabit speeds, everything else is. 1376 * Note: the original code also exclulded Gigagbit for MII, RevMII 1377 * and 802.3z modes. MII and RevMII are not able to work above 100M, 1378 * so will be excluded by the generic validator implementation. 1379 * However, the exclusion of Gigabit for 802.3z just seems wrong. 1380 */ 1381 if (!(is5325(dev) || is5365(dev))) 1382 config->mac_capabilities |= MAC_1000; 1383 1384 /* Get the implementation specific capabilities */ 1385 if (dev->ops->phylink_get_caps) 1386 dev->ops->phylink_get_caps(dev, port, config); 1387 } 1388 1389 static struct phylink_pcs *b53_phylink_mac_select_pcs(struct phylink_config *config, 1390 phy_interface_t interface) 1391 { 1392 struct dsa_port *dp = dsa_phylink_to_port(config); 1393 struct b53_device *dev = dp->ds->priv; 1394 1395 if (!dev->ops->phylink_mac_select_pcs) 1396 return NULL; 1397 1398 return dev->ops->phylink_mac_select_pcs(dev, dp->index, interface); 1399 } 1400 1401 static void b53_phylink_mac_config(struct phylink_config *config, 1402 unsigned int mode, 1403 const struct phylink_link_state *state) 1404 { 1405 struct dsa_port *dp = dsa_phylink_to_port(config); 1406 phy_interface_t interface = state->interface; 1407 struct dsa_switch *ds = dp->ds; 1408 struct b53_device *dev = ds->priv; 1409 int port = dp->index; 1410 1411 if (is63xx(dev) && port >= B53_63XX_RGMII0) 1412 b53_adjust_63xx_rgmii(ds, port, interface); 1413 1414 if (mode == MLO_AN_FIXED) { 1415 if (is531x5(dev) && phy_interface_mode_is_rgmii(interface)) 1416 b53_adjust_531x5_rgmii(ds, port, interface); 1417 1418 /* configure MII port if necessary */ 1419 if (is5325(dev)) 1420 b53_adjust_5325_mii(ds, port); 1421 } 1422 } 1423 1424 static void b53_phylink_mac_link_down(struct phylink_config *config, 1425 unsigned int mode, 1426 phy_interface_t interface) 1427 { 1428 struct dsa_port *dp = dsa_phylink_to_port(config); 1429 struct b53_device *dev = dp->ds->priv; 1430 int port = dp->index; 1431 1432 if (mode == MLO_AN_PHY) 1433 return; 1434 1435 if (mode == MLO_AN_FIXED) { 1436 b53_force_link(dev, port, false); 1437 return; 1438 } 1439 1440 if (phy_interface_mode_is_8023z(interface) && 1441 dev->ops->serdes_link_set) 1442 dev->ops->serdes_link_set(dev, port, mode, interface, false); 1443 } 1444 1445 static void b53_phylink_mac_link_up(struct phylink_config *config, 1446 struct phy_device *phydev, 1447 unsigned int mode, 1448 phy_interface_t interface, 1449 int speed, int duplex, 1450 bool tx_pause, bool rx_pause) 1451 { 1452 struct dsa_port *dp = dsa_phylink_to_port(config); 1453 struct dsa_switch *ds = dp->ds; 1454 struct b53_device *dev = ds->priv; 1455 struct ethtool_keee *p = &dev->ports[dp->index].eee; 1456 int port = dp->index; 1457 1458 if (mode == MLO_AN_PHY) { 1459 /* Re-negotiate EEE if it was enabled already */ 1460 p->eee_enabled = b53_eee_init(ds, port, phydev); 1461 return; 1462 } 1463 1464 if (mode == MLO_AN_FIXED) { 1465 /* Force flow control on BCM5301x's CPU port */ 1466 if (is5301x(dev) && dsa_is_cpu_port(ds, port)) 1467 tx_pause = rx_pause = true; 1468 1469 b53_force_port_config(dev, port, speed, duplex, 1470 tx_pause, rx_pause); 1471 b53_force_link(dev, port, true); 1472 return; 1473 } 1474 1475 if (phy_interface_mode_is_8023z(interface) && 1476 dev->ops->serdes_link_set) 1477 dev->ops->serdes_link_set(dev, port, mode, interface, true); 1478 } 1479 1480 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1481 struct netlink_ext_ack *extack) 1482 { 1483 struct b53_device *dev = ds->priv; 1484 1485 b53_enable_vlan(dev, port, dev->vlan_enabled, vlan_filtering); 1486 1487 return 0; 1488 } 1489 EXPORT_SYMBOL(b53_vlan_filtering); 1490 1491 static int b53_vlan_prepare(struct dsa_switch *ds, int port, 1492 const struct switchdev_obj_port_vlan *vlan) 1493 { 1494 struct b53_device *dev = ds->priv; 1495 1496 if ((is5325(dev) || is5365(dev)) && vlan->vid == 0) 1497 return -EOPNOTSUPP; 1498 1499 /* Port 7 on 7278 connects to the ASP's UniMAC which is not capable of 1500 * receiving VLAN tagged frames at all, we can still allow the port to 1501 * be configured for egress untagged. 1502 */ 1503 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7 && 1504 !(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)) 1505 return -EINVAL; 1506 1507 if (vlan->vid >= dev->num_vlans) 1508 return -ERANGE; 1509 1510 b53_enable_vlan(dev, port, true, ds->vlan_filtering); 1511 1512 return 0; 1513 } 1514 1515 int b53_vlan_add(struct dsa_switch *ds, int port, 1516 const struct switchdev_obj_port_vlan *vlan, 1517 struct netlink_ext_ack *extack) 1518 { 1519 struct b53_device *dev = ds->priv; 1520 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1521 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1522 struct b53_vlan *vl; 1523 int err; 1524 1525 err = b53_vlan_prepare(ds, port, vlan); 1526 if (err) 1527 return err; 1528 1529 vl = &dev->vlans[vlan->vid]; 1530 1531 b53_get_vlan_entry(dev, vlan->vid, vl); 1532 1533 if (vlan->vid == 0 && vlan->vid == b53_default_pvid(dev)) 1534 untagged = true; 1535 1536 vl->members |= BIT(port); 1537 if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port)) 1538 vl->untag |= BIT(port); 1539 else 1540 vl->untag &= ~BIT(port); 1541 1542 b53_set_vlan_entry(dev, vlan->vid, vl); 1543 b53_fast_age_vlan(dev, vlan->vid); 1544 1545 if (pvid && !dsa_is_cpu_port(ds, port)) { 1546 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), 1547 vlan->vid); 1548 b53_fast_age_vlan(dev, vlan->vid); 1549 } 1550 1551 return 0; 1552 } 1553 EXPORT_SYMBOL(b53_vlan_add); 1554 1555 int b53_vlan_del(struct dsa_switch *ds, int port, 1556 const struct switchdev_obj_port_vlan *vlan) 1557 { 1558 struct b53_device *dev = ds->priv; 1559 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1560 struct b53_vlan *vl; 1561 u16 pvid; 1562 1563 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid); 1564 1565 vl = &dev->vlans[vlan->vid]; 1566 1567 b53_get_vlan_entry(dev, vlan->vid, vl); 1568 1569 vl->members &= ~BIT(port); 1570 1571 if (pvid == vlan->vid) 1572 pvid = b53_default_pvid(dev); 1573 1574 if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port)) 1575 vl->untag &= ~(BIT(port)); 1576 1577 b53_set_vlan_entry(dev, vlan->vid, vl); 1578 b53_fast_age_vlan(dev, vlan->vid); 1579 1580 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid); 1581 b53_fast_age_vlan(dev, pvid); 1582 1583 return 0; 1584 } 1585 EXPORT_SYMBOL(b53_vlan_del); 1586 1587 /* Address Resolution Logic routines. Caller must hold &dev->arl_mutex. */ 1588 static int b53_arl_op_wait(struct b53_device *dev) 1589 { 1590 unsigned int timeout = 10; 1591 u8 reg; 1592 1593 do { 1594 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1595 if (!(reg & ARLTBL_START_DONE)) 1596 return 0; 1597 1598 usleep_range(1000, 2000); 1599 } while (timeout--); 1600 1601 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg); 1602 1603 return -ETIMEDOUT; 1604 } 1605 1606 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op) 1607 { 1608 u8 reg; 1609 1610 if (op > ARLTBL_RW) 1611 return -EINVAL; 1612 1613 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1614 reg |= ARLTBL_START_DONE; 1615 if (op) 1616 reg |= ARLTBL_RW; 1617 else 1618 reg &= ~ARLTBL_RW; 1619 if (dev->vlan_enabled) 1620 reg &= ~ARLTBL_IVL_SVL_SELECT; 1621 else 1622 reg |= ARLTBL_IVL_SVL_SELECT; 1623 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg); 1624 1625 return b53_arl_op_wait(dev); 1626 } 1627 1628 static int b53_arl_read(struct b53_device *dev, u64 mac, 1629 u16 vid, struct b53_arl_entry *ent, u8 *idx) 1630 { 1631 DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES); 1632 unsigned int i; 1633 int ret; 1634 1635 ret = b53_arl_op_wait(dev); 1636 if (ret) 1637 return ret; 1638 1639 bitmap_zero(free_bins, dev->num_arl_bins); 1640 1641 /* Read the bins */ 1642 for (i = 0; i < dev->num_arl_bins; i++) { 1643 u64 mac_vid; 1644 u32 fwd_entry; 1645 1646 b53_read64(dev, B53_ARLIO_PAGE, 1647 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid); 1648 b53_read32(dev, B53_ARLIO_PAGE, 1649 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry); 1650 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1651 1652 if (!(fwd_entry & ARLTBL_VALID)) { 1653 set_bit(i, free_bins); 1654 continue; 1655 } 1656 if ((mac_vid & ARLTBL_MAC_MASK) != mac) 1657 continue; 1658 if (dev->vlan_enabled && 1659 ((mac_vid >> ARLTBL_VID_S) & ARLTBL_VID_MASK) != vid) 1660 continue; 1661 *idx = i; 1662 return 0; 1663 } 1664 1665 *idx = find_first_bit(free_bins, dev->num_arl_bins); 1666 return *idx >= dev->num_arl_bins ? -ENOSPC : -ENOENT; 1667 } 1668 1669 static int b53_arl_op(struct b53_device *dev, int op, int port, 1670 const unsigned char *addr, u16 vid, bool is_valid) 1671 { 1672 struct b53_arl_entry ent; 1673 u32 fwd_entry; 1674 u64 mac, mac_vid = 0; 1675 u8 idx = 0; 1676 int ret; 1677 1678 /* Convert the array into a 64-bit MAC */ 1679 mac = ether_addr_to_u64(addr); 1680 1681 /* Perform a read for the given MAC and VID */ 1682 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac); 1683 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid); 1684 1685 /* Issue a read operation for this MAC */ 1686 ret = b53_arl_rw_op(dev, 1); 1687 if (ret) 1688 return ret; 1689 1690 ret = b53_arl_read(dev, mac, vid, &ent, &idx); 1691 1692 /* If this is a read, just finish now */ 1693 if (op) 1694 return ret; 1695 1696 switch (ret) { 1697 case -ETIMEDOUT: 1698 return ret; 1699 case -ENOSPC: 1700 dev_dbg(dev->dev, "{%pM,%.4d} no space left in ARL\n", 1701 addr, vid); 1702 return is_valid ? ret : 0; 1703 case -ENOENT: 1704 /* We could not find a matching MAC, so reset to a new entry */ 1705 dev_dbg(dev->dev, "{%pM,%.4d} not found, using idx: %d\n", 1706 addr, vid, idx); 1707 fwd_entry = 0; 1708 break; 1709 default: 1710 dev_dbg(dev->dev, "{%pM,%.4d} found, using idx: %d\n", 1711 addr, vid, idx); 1712 break; 1713 } 1714 1715 /* For multicast address, the port is a bitmask and the validity 1716 * is determined by having at least one port being still active 1717 */ 1718 if (!is_multicast_ether_addr(addr)) { 1719 ent.port = port; 1720 ent.is_valid = is_valid; 1721 } else { 1722 if (is_valid) 1723 ent.port |= BIT(port); 1724 else 1725 ent.port &= ~BIT(port); 1726 1727 ent.is_valid = !!(ent.port); 1728 } 1729 1730 ent.vid = vid; 1731 ent.is_static = true; 1732 ent.is_age = false; 1733 memcpy(ent.mac, addr, ETH_ALEN); 1734 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent); 1735 1736 b53_write64(dev, B53_ARLIO_PAGE, 1737 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid); 1738 b53_write32(dev, B53_ARLIO_PAGE, 1739 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry); 1740 1741 return b53_arl_rw_op(dev, 0); 1742 } 1743 1744 int b53_fdb_add(struct dsa_switch *ds, int port, 1745 const unsigned char *addr, u16 vid, 1746 struct dsa_db db) 1747 { 1748 struct b53_device *priv = ds->priv; 1749 int ret; 1750 1751 /* 5325 and 5365 require some more massaging, but could 1752 * be supported eventually 1753 */ 1754 if (is5325(priv) || is5365(priv)) 1755 return -EOPNOTSUPP; 1756 1757 mutex_lock(&priv->arl_mutex); 1758 ret = b53_arl_op(priv, 0, port, addr, vid, true); 1759 mutex_unlock(&priv->arl_mutex); 1760 1761 return ret; 1762 } 1763 EXPORT_SYMBOL(b53_fdb_add); 1764 1765 int b53_fdb_del(struct dsa_switch *ds, int port, 1766 const unsigned char *addr, u16 vid, 1767 struct dsa_db db) 1768 { 1769 struct b53_device *priv = ds->priv; 1770 int ret; 1771 1772 mutex_lock(&priv->arl_mutex); 1773 ret = b53_arl_op(priv, 0, port, addr, vid, false); 1774 mutex_unlock(&priv->arl_mutex); 1775 1776 return ret; 1777 } 1778 EXPORT_SYMBOL(b53_fdb_del); 1779 1780 static int b53_arl_search_wait(struct b53_device *dev) 1781 { 1782 unsigned int timeout = 1000; 1783 u8 reg; 1784 1785 do { 1786 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®); 1787 if (!(reg & ARL_SRCH_STDN)) 1788 return 0; 1789 1790 if (reg & ARL_SRCH_VLID) 1791 return 0; 1792 1793 usleep_range(1000, 2000); 1794 } while (timeout--); 1795 1796 return -ETIMEDOUT; 1797 } 1798 1799 static void b53_arl_search_rd(struct b53_device *dev, u8 idx, 1800 struct b53_arl_entry *ent) 1801 { 1802 u64 mac_vid; 1803 u32 fwd_entry; 1804 1805 b53_read64(dev, B53_ARLIO_PAGE, 1806 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid); 1807 b53_read32(dev, B53_ARLIO_PAGE, 1808 B53_ARL_SRCH_RSTL(idx), &fwd_entry); 1809 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1810 } 1811 1812 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent, 1813 dsa_fdb_dump_cb_t *cb, void *data) 1814 { 1815 if (!ent->is_valid) 1816 return 0; 1817 1818 if (port != ent->port) 1819 return 0; 1820 1821 return cb(ent->mac, ent->vid, ent->is_static, data); 1822 } 1823 1824 int b53_fdb_dump(struct dsa_switch *ds, int port, 1825 dsa_fdb_dump_cb_t *cb, void *data) 1826 { 1827 struct b53_device *priv = ds->priv; 1828 struct b53_arl_entry results[2]; 1829 unsigned int count = 0; 1830 int ret; 1831 u8 reg; 1832 1833 mutex_lock(&priv->arl_mutex); 1834 1835 /* Start search operation */ 1836 reg = ARL_SRCH_STDN; 1837 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg); 1838 1839 do { 1840 ret = b53_arl_search_wait(priv); 1841 if (ret) 1842 break; 1843 1844 b53_arl_search_rd(priv, 0, &results[0]); 1845 ret = b53_fdb_copy(port, &results[0], cb, data); 1846 if (ret) 1847 break; 1848 1849 if (priv->num_arl_bins > 2) { 1850 b53_arl_search_rd(priv, 1, &results[1]); 1851 ret = b53_fdb_copy(port, &results[1], cb, data); 1852 if (ret) 1853 break; 1854 1855 if (!results[0].is_valid && !results[1].is_valid) 1856 break; 1857 } 1858 1859 } while (count++ < b53_max_arl_entries(priv) / 2); 1860 1861 mutex_unlock(&priv->arl_mutex); 1862 1863 return 0; 1864 } 1865 EXPORT_SYMBOL(b53_fdb_dump); 1866 1867 int b53_mdb_add(struct dsa_switch *ds, int port, 1868 const struct switchdev_obj_port_mdb *mdb, 1869 struct dsa_db db) 1870 { 1871 struct b53_device *priv = ds->priv; 1872 int ret; 1873 1874 /* 5325 and 5365 require some more massaging, but could 1875 * be supported eventually 1876 */ 1877 if (is5325(priv) || is5365(priv)) 1878 return -EOPNOTSUPP; 1879 1880 mutex_lock(&priv->arl_mutex); 1881 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, true); 1882 mutex_unlock(&priv->arl_mutex); 1883 1884 return ret; 1885 } 1886 EXPORT_SYMBOL(b53_mdb_add); 1887 1888 int b53_mdb_del(struct dsa_switch *ds, int port, 1889 const struct switchdev_obj_port_mdb *mdb, 1890 struct dsa_db db) 1891 { 1892 struct b53_device *priv = ds->priv; 1893 int ret; 1894 1895 mutex_lock(&priv->arl_mutex); 1896 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, false); 1897 mutex_unlock(&priv->arl_mutex); 1898 if (ret) 1899 dev_err(ds->dev, "failed to delete MDB entry\n"); 1900 1901 return ret; 1902 } 1903 EXPORT_SYMBOL(b53_mdb_del); 1904 1905 int b53_br_join(struct dsa_switch *ds, int port, struct dsa_bridge bridge, 1906 bool *tx_fwd_offload, struct netlink_ext_ack *extack) 1907 { 1908 struct b53_device *dev = ds->priv; 1909 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 1910 u16 pvlan, reg; 1911 unsigned int i; 1912 1913 /* On 7278, port 7 which connects to the ASP should only receive 1914 * traffic from matching CFP rules. 1915 */ 1916 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7) 1917 return -EINVAL; 1918 1919 /* Make this port leave the all VLANs join since we will have proper 1920 * VLAN entries from now on 1921 */ 1922 if (is58xx(dev)) { 1923 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1924 reg &= ~BIT(port); 1925 if ((reg & BIT(cpu_port)) == BIT(cpu_port)) 1926 reg &= ~BIT(cpu_port); 1927 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1928 } 1929 1930 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1931 1932 b53_for_each_port(dev, i) { 1933 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge)) 1934 continue; 1935 1936 /* Add this local port to the remote port VLAN control 1937 * membership and update the remote port bitmask 1938 */ 1939 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1940 reg |= BIT(port); 1941 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1942 dev->ports[i].vlan_ctl_mask = reg; 1943 1944 pvlan |= BIT(i); 1945 } 1946 1947 /* Configure the local port VLAN control membership to include 1948 * remote ports and update the local port bitmask 1949 */ 1950 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1951 dev->ports[port].vlan_ctl_mask = pvlan; 1952 1953 return 0; 1954 } 1955 EXPORT_SYMBOL(b53_br_join); 1956 1957 void b53_br_leave(struct dsa_switch *ds, int port, struct dsa_bridge bridge) 1958 { 1959 struct b53_device *dev = ds->priv; 1960 struct b53_vlan *vl = &dev->vlans[0]; 1961 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 1962 unsigned int i; 1963 u16 pvlan, reg, pvid; 1964 1965 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1966 1967 b53_for_each_port(dev, i) { 1968 /* Don't touch the remaining ports */ 1969 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge)) 1970 continue; 1971 1972 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1973 reg &= ~BIT(port); 1974 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1975 dev->ports[port].vlan_ctl_mask = reg; 1976 1977 /* Prevent self removal to preserve isolation */ 1978 if (port != i) 1979 pvlan &= ~BIT(i); 1980 } 1981 1982 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1983 dev->ports[port].vlan_ctl_mask = pvlan; 1984 1985 pvid = b53_default_pvid(dev); 1986 1987 /* Make this port join all VLANs without VLAN entries */ 1988 if (is58xx(dev)) { 1989 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1990 reg |= BIT(port); 1991 if (!(reg & BIT(cpu_port))) 1992 reg |= BIT(cpu_port); 1993 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1994 } else { 1995 b53_get_vlan_entry(dev, pvid, vl); 1996 vl->members |= BIT(port) | BIT(cpu_port); 1997 vl->untag |= BIT(port) | BIT(cpu_port); 1998 b53_set_vlan_entry(dev, pvid, vl); 1999 } 2000 } 2001 EXPORT_SYMBOL(b53_br_leave); 2002 2003 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state) 2004 { 2005 struct b53_device *dev = ds->priv; 2006 u8 hw_state; 2007 u8 reg; 2008 2009 switch (state) { 2010 case BR_STATE_DISABLED: 2011 hw_state = PORT_CTRL_DIS_STATE; 2012 break; 2013 case BR_STATE_LISTENING: 2014 hw_state = PORT_CTRL_LISTEN_STATE; 2015 break; 2016 case BR_STATE_LEARNING: 2017 hw_state = PORT_CTRL_LEARN_STATE; 2018 break; 2019 case BR_STATE_FORWARDING: 2020 hw_state = PORT_CTRL_FWD_STATE; 2021 break; 2022 case BR_STATE_BLOCKING: 2023 hw_state = PORT_CTRL_BLOCK_STATE; 2024 break; 2025 default: 2026 dev_err(ds->dev, "invalid STP state: %d\n", state); 2027 return; 2028 } 2029 2030 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 2031 reg &= ~PORT_CTRL_STP_STATE_MASK; 2032 reg |= hw_state; 2033 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 2034 } 2035 EXPORT_SYMBOL(b53_br_set_stp_state); 2036 2037 void b53_br_fast_age(struct dsa_switch *ds, int port) 2038 { 2039 struct b53_device *dev = ds->priv; 2040 2041 if (b53_fast_age_port(dev, port)) 2042 dev_err(ds->dev, "fast ageing failed\n"); 2043 } 2044 EXPORT_SYMBOL(b53_br_fast_age); 2045 2046 int b53_br_flags_pre(struct dsa_switch *ds, int port, 2047 struct switchdev_brport_flags flags, 2048 struct netlink_ext_ack *extack) 2049 { 2050 if (flags.mask & ~(BR_FLOOD | BR_MCAST_FLOOD | BR_LEARNING)) 2051 return -EINVAL; 2052 2053 return 0; 2054 } 2055 EXPORT_SYMBOL(b53_br_flags_pre); 2056 2057 int b53_br_flags(struct dsa_switch *ds, int port, 2058 struct switchdev_brport_flags flags, 2059 struct netlink_ext_ack *extack) 2060 { 2061 if (flags.mask & BR_FLOOD) 2062 b53_port_set_ucast_flood(ds->priv, port, 2063 !!(flags.val & BR_FLOOD)); 2064 if (flags.mask & BR_MCAST_FLOOD) 2065 b53_port_set_mcast_flood(ds->priv, port, 2066 !!(flags.val & BR_MCAST_FLOOD)); 2067 if (flags.mask & BR_LEARNING) 2068 b53_port_set_learning(ds->priv, port, 2069 !!(flags.val & BR_LEARNING)); 2070 2071 return 0; 2072 } 2073 EXPORT_SYMBOL(b53_br_flags); 2074 2075 static bool b53_possible_cpu_port(struct dsa_switch *ds, int port) 2076 { 2077 /* Broadcom switches will accept enabling Broadcom tags on the 2078 * following ports: 5, 7 and 8, any other port is not supported 2079 */ 2080 switch (port) { 2081 case B53_CPU_PORT_25: 2082 case 7: 2083 case B53_CPU_PORT: 2084 return true; 2085 } 2086 2087 return false; 2088 } 2089 2090 static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port, 2091 enum dsa_tag_protocol tag_protocol) 2092 { 2093 bool ret = b53_possible_cpu_port(ds, port); 2094 2095 if (!ret) { 2096 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n", 2097 port); 2098 return ret; 2099 } 2100 2101 switch (tag_protocol) { 2102 case DSA_TAG_PROTO_BRCM: 2103 case DSA_TAG_PROTO_BRCM_PREPEND: 2104 dev_warn(ds->dev, 2105 "Port %d is stacked to Broadcom tag switch\n", port); 2106 ret = false; 2107 break; 2108 default: 2109 ret = true; 2110 break; 2111 } 2112 2113 return ret; 2114 } 2115 2116 enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port, 2117 enum dsa_tag_protocol mprot) 2118 { 2119 struct b53_device *dev = ds->priv; 2120 2121 if (!b53_can_enable_brcm_tags(ds, port, mprot)) { 2122 dev->tag_protocol = DSA_TAG_PROTO_NONE; 2123 goto out; 2124 } 2125 2126 /* Older models require a different 6 byte tag */ 2127 if (is5325(dev) || is5365(dev) || is63xx(dev)) { 2128 dev->tag_protocol = DSA_TAG_PROTO_BRCM_LEGACY; 2129 goto out; 2130 } 2131 2132 /* Broadcom BCM58xx chips have a flow accelerator on Port 8 2133 * which requires us to use the prepended Broadcom tag type 2134 */ 2135 if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT) { 2136 dev->tag_protocol = DSA_TAG_PROTO_BRCM_PREPEND; 2137 goto out; 2138 } 2139 2140 dev->tag_protocol = DSA_TAG_PROTO_BRCM; 2141 out: 2142 return dev->tag_protocol; 2143 } 2144 EXPORT_SYMBOL(b53_get_tag_protocol); 2145 2146 int b53_mirror_add(struct dsa_switch *ds, int port, 2147 struct dsa_mall_mirror_tc_entry *mirror, bool ingress, 2148 struct netlink_ext_ack *extack) 2149 { 2150 struct b53_device *dev = ds->priv; 2151 u16 reg, loc; 2152 2153 if (ingress) 2154 loc = B53_IG_MIR_CTL; 2155 else 2156 loc = B53_EG_MIR_CTL; 2157 2158 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 2159 reg |= BIT(port); 2160 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 2161 2162 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 2163 reg &= ~CAP_PORT_MASK; 2164 reg |= mirror->to_local_port; 2165 reg |= MIRROR_EN; 2166 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 2167 2168 return 0; 2169 } 2170 EXPORT_SYMBOL(b53_mirror_add); 2171 2172 void b53_mirror_del(struct dsa_switch *ds, int port, 2173 struct dsa_mall_mirror_tc_entry *mirror) 2174 { 2175 struct b53_device *dev = ds->priv; 2176 bool loc_disable = false, other_loc_disable = false; 2177 u16 reg, loc; 2178 2179 if (mirror->ingress) 2180 loc = B53_IG_MIR_CTL; 2181 else 2182 loc = B53_EG_MIR_CTL; 2183 2184 /* Update the desired ingress/egress register */ 2185 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 2186 reg &= ~BIT(port); 2187 if (!(reg & MIRROR_MASK)) 2188 loc_disable = true; 2189 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 2190 2191 /* Now look at the other one to know if we can disable mirroring 2192 * entirely 2193 */ 2194 if (mirror->ingress) 2195 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, ®); 2196 else 2197 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, ®); 2198 if (!(reg & MIRROR_MASK)) 2199 other_loc_disable = true; 2200 2201 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 2202 /* Both no longer have ports, let's disable mirroring */ 2203 if (loc_disable && other_loc_disable) { 2204 reg &= ~MIRROR_EN; 2205 reg &= ~mirror->to_local_port; 2206 } 2207 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 2208 } 2209 EXPORT_SYMBOL(b53_mirror_del); 2210 2211 /* Returns 0 if EEE was not enabled, or 1 otherwise 2212 */ 2213 int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy) 2214 { 2215 int ret; 2216 2217 ret = phy_init_eee(phy, false); 2218 if (ret) 2219 return 0; 2220 2221 b53_eee_enable_set(ds, port, true); 2222 2223 return 1; 2224 } 2225 EXPORT_SYMBOL(b53_eee_init); 2226 2227 int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_keee *e) 2228 { 2229 struct b53_device *dev = ds->priv; 2230 2231 if (is5325(dev) || is5365(dev)) 2232 return -EOPNOTSUPP; 2233 2234 return 0; 2235 } 2236 EXPORT_SYMBOL(b53_get_mac_eee); 2237 2238 int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_keee *e) 2239 { 2240 struct b53_device *dev = ds->priv; 2241 struct ethtool_keee *p = &dev->ports[port].eee; 2242 2243 if (is5325(dev) || is5365(dev)) 2244 return -EOPNOTSUPP; 2245 2246 p->eee_enabled = e->eee_enabled; 2247 b53_eee_enable_set(ds, port, e->eee_enabled); 2248 2249 return 0; 2250 } 2251 EXPORT_SYMBOL(b53_set_mac_eee); 2252 2253 static int b53_change_mtu(struct dsa_switch *ds, int port, int mtu) 2254 { 2255 struct b53_device *dev = ds->priv; 2256 bool enable_jumbo; 2257 bool allow_10_100; 2258 2259 if (is5325(dev) || is5365(dev)) 2260 return 0; 2261 2262 if (!dsa_is_cpu_port(ds, port)) 2263 return 0; 2264 2265 enable_jumbo = (mtu > ETH_DATA_LEN); 2266 allow_10_100 = !is63xx(dev); 2267 2268 return b53_set_jumbo(dev, enable_jumbo, allow_10_100); 2269 } 2270 2271 static int b53_get_max_mtu(struct dsa_switch *ds, int port) 2272 { 2273 struct b53_device *dev = ds->priv; 2274 2275 if (is5325(dev) || is5365(dev)) 2276 return B53_MAX_MTU_25; 2277 2278 return B53_MAX_MTU; 2279 } 2280 2281 static const struct phylink_mac_ops b53_phylink_mac_ops = { 2282 .mac_select_pcs = b53_phylink_mac_select_pcs, 2283 .mac_config = b53_phylink_mac_config, 2284 .mac_link_down = b53_phylink_mac_link_down, 2285 .mac_link_up = b53_phylink_mac_link_up, 2286 }; 2287 2288 static const struct dsa_switch_ops b53_switch_ops = { 2289 .get_tag_protocol = b53_get_tag_protocol, 2290 .setup = b53_setup, 2291 .teardown = b53_teardown, 2292 .get_strings = b53_get_strings, 2293 .get_ethtool_stats = b53_get_ethtool_stats, 2294 .get_sset_count = b53_get_sset_count, 2295 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 2296 .phy_read = b53_phy_read16, 2297 .phy_write = b53_phy_write16, 2298 .phylink_get_caps = b53_phylink_get_caps, 2299 .port_enable = b53_enable_port, 2300 .port_disable = b53_disable_port, 2301 .get_mac_eee = b53_get_mac_eee, 2302 .set_mac_eee = b53_set_mac_eee, 2303 .port_bridge_join = b53_br_join, 2304 .port_bridge_leave = b53_br_leave, 2305 .port_pre_bridge_flags = b53_br_flags_pre, 2306 .port_bridge_flags = b53_br_flags, 2307 .port_stp_state_set = b53_br_set_stp_state, 2308 .port_fast_age = b53_br_fast_age, 2309 .port_vlan_filtering = b53_vlan_filtering, 2310 .port_vlan_add = b53_vlan_add, 2311 .port_vlan_del = b53_vlan_del, 2312 .port_fdb_dump = b53_fdb_dump, 2313 .port_fdb_add = b53_fdb_add, 2314 .port_fdb_del = b53_fdb_del, 2315 .port_mirror_add = b53_mirror_add, 2316 .port_mirror_del = b53_mirror_del, 2317 .port_mdb_add = b53_mdb_add, 2318 .port_mdb_del = b53_mdb_del, 2319 .port_max_mtu = b53_get_max_mtu, 2320 .port_change_mtu = b53_change_mtu, 2321 }; 2322 2323 struct b53_chip_data { 2324 u32 chip_id; 2325 const char *dev_name; 2326 u16 vlans; 2327 u16 enabled_ports; 2328 u8 imp_port; 2329 u8 cpu_port; 2330 u8 vta_regs[3]; 2331 u8 arl_bins; 2332 u16 arl_buckets; 2333 u8 duplex_reg; 2334 u8 jumbo_pm_reg; 2335 u8 jumbo_size_reg; 2336 }; 2337 2338 #define B53_VTA_REGS \ 2339 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY } 2340 #define B53_VTA_REGS_9798 \ 2341 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 } 2342 #define B53_VTA_REGS_63XX \ 2343 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX } 2344 2345 static const struct b53_chip_data b53_switch_chips[] = { 2346 { 2347 .chip_id = BCM5325_DEVICE_ID, 2348 .dev_name = "BCM5325", 2349 .vlans = 16, 2350 .enabled_ports = 0x3f, 2351 .arl_bins = 2, 2352 .arl_buckets = 1024, 2353 .imp_port = 5, 2354 .duplex_reg = B53_DUPLEX_STAT_FE, 2355 }, 2356 { 2357 .chip_id = BCM5365_DEVICE_ID, 2358 .dev_name = "BCM5365", 2359 .vlans = 256, 2360 .enabled_ports = 0x3f, 2361 .arl_bins = 2, 2362 .arl_buckets = 1024, 2363 .imp_port = 5, 2364 .duplex_reg = B53_DUPLEX_STAT_FE, 2365 }, 2366 { 2367 .chip_id = BCM5389_DEVICE_ID, 2368 .dev_name = "BCM5389", 2369 .vlans = 4096, 2370 .enabled_ports = 0x11f, 2371 .arl_bins = 4, 2372 .arl_buckets = 1024, 2373 .imp_port = 8, 2374 .vta_regs = B53_VTA_REGS, 2375 .duplex_reg = B53_DUPLEX_STAT_GE, 2376 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2377 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2378 }, 2379 { 2380 .chip_id = BCM5395_DEVICE_ID, 2381 .dev_name = "BCM5395", 2382 .vlans = 4096, 2383 .enabled_ports = 0x11f, 2384 .arl_bins = 4, 2385 .arl_buckets = 1024, 2386 .imp_port = 8, 2387 .vta_regs = B53_VTA_REGS, 2388 .duplex_reg = B53_DUPLEX_STAT_GE, 2389 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2390 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2391 }, 2392 { 2393 .chip_id = BCM5397_DEVICE_ID, 2394 .dev_name = "BCM5397", 2395 .vlans = 4096, 2396 .enabled_ports = 0x11f, 2397 .arl_bins = 4, 2398 .arl_buckets = 1024, 2399 .imp_port = 8, 2400 .vta_regs = B53_VTA_REGS_9798, 2401 .duplex_reg = B53_DUPLEX_STAT_GE, 2402 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2403 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2404 }, 2405 { 2406 .chip_id = BCM5398_DEVICE_ID, 2407 .dev_name = "BCM5398", 2408 .vlans = 4096, 2409 .enabled_ports = 0x17f, 2410 .arl_bins = 4, 2411 .arl_buckets = 1024, 2412 .imp_port = 8, 2413 .vta_regs = B53_VTA_REGS_9798, 2414 .duplex_reg = B53_DUPLEX_STAT_GE, 2415 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2416 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2417 }, 2418 { 2419 .chip_id = BCM53115_DEVICE_ID, 2420 .dev_name = "BCM53115", 2421 .vlans = 4096, 2422 .enabled_ports = 0x11f, 2423 .arl_bins = 4, 2424 .arl_buckets = 1024, 2425 .vta_regs = B53_VTA_REGS, 2426 .imp_port = 8, 2427 .duplex_reg = B53_DUPLEX_STAT_GE, 2428 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2429 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2430 }, 2431 { 2432 .chip_id = BCM53125_DEVICE_ID, 2433 .dev_name = "BCM53125", 2434 .vlans = 4096, 2435 .enabled_ports = 0x1ff, 2436 .arl_bins = 4, 2437 .arl_buckets = 1024, 2438 .imp_port = 8, 2439 .vta_regs = B53_VTA_REGS, 2440 .duplex_reg = B53_DUPLEX_STAT_GE, 2441 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2442 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2443 }, 2444 { 2445 .chip_id = BCM53128_DEVICE_ID, 2446 .dev_name = "BCM53128", 2447 .vlans = 4096, 2448 .enabled_ports = 0x1ff, 2449 .arl_bins = 4, 2450 .arl_buckets = 1024, 2451 .imp_port = 8, 2452 .vta_regs = B53_VTA_REGS, 2453 .duplex_reg = B53_DUPLEX_STAT_GE, 2454 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2455 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2456 }, 2457 { 2458 .chip_id = BCM63XX_DEVICE_ID, 2459 .dev_name = "BCM63xx", 2460 .vlans = 4096, 2461 .enabled_ports = 0, /* pdata must provide them */ 2462 .arl_bins = 4, 2463 .arl_buckets = 1024, 2464 .imp_port = 8, 2465 .vta_regs = B53_VTA_REGS_63XX, 2466 .duplex_reg = B53_DUPLEX_STAT_63XX, 2467 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, 2468 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, 2469 }, 2470 { 2471 .chip_id = BCM63268_DEVICE_ID, 2472 .dev_name = "BCM63268", 2473 .vlans = 4096, 2474 .enabled_ports = 0, /* pdata must provide them */ 2475 .arl_bins = 4, 2476 .arl_buckets = 1024, 2477 .imp_port = 8, 2478 .vta_regs = B53_VTA_REGS_63XX, 2479 .duplex_reg = B53_DUPLEX_STAT_63XX, 2480 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, 2481 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, 2482 }, 2483 { 2484 .chip_id = BCM53010_DEVICE_ID, 2485 .dev_name = "BCM53010", 2486 .vlans = 4096, 2487 .enabled_ports = 0x1bf, 2488 .arl_bins = 4, 2489 .arl_buckets = 1024, 2490 .imp_port = 8, 2491 .vta_regs = B53_VTA_REGS, 2492 .duplex_reg = B53_DUPLEX_STAT_GE, 2493 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2494 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2495 }, 2496 { 2497 .chip_id = BCM53011_DEVICE_ID, 2498 .dev_name = "BCM53011", 2499 .vlans = 4096, 2500 .enabled_ports = 0x1bf, 2501 .arl_bins = 4, 2502 .arl_buckets = 1024, 2503 .imp_port = 8, 2504 .vta_regs = B53_VTA_REGS, 2505 .duplex_reg = B53_DUPLEX_STAT_GE, 2506 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2507 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2508 }, 2509 { 2510 .chip_id = BCM53012_DEVICE_ID, 2511 .dev_name = "BCM53012", 2512 .vlans = 4096, 2513 .enabled_ports = 0x1bf, 2514 .arl_bins = 4, 2515 .arl_buckets = 1024, 2516 .imp_port = 8, 2517 .vta_regs = B53_VTA_REGS, 2518 .duplex_reg = B53_DUPLEX_STAT_GE, 2519 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2520 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2521 }, 2522 { 2523 .chip_id = BCM53018_DEVICE_ID, 2524 .dev_name = "BCM53018", 2525 .vlans = 4096, 2526 .enabled_ports = 0x1bf, 2527 .arl_bins = 4, 2528 .arl_buckets = 1024, 2529 .imp_port = 8, 2530 .vta_regs = B53_VTA_REGS, 2531 .duplex_reg = B53_DUPLEX_STAT_GE, 2532 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2533 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2534 }, 2535 { 2536 .chip_id = BCM53019_DEVICE_ID, 2537 .dev_name = "BCM53019", 2538 .vlans = 4096, 2539 .enabled_ports = 0x1bf, 2540 .arl_bins = 4, 2541 .arl_buckets = 1024, 2542 .imp_port = 8, 2543 .vta_regs = B53_VTA_REGS, 2544 .duplex_reg = B53_DUPLEX_STAT_GE, 2545 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2546 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2547 }, 2548 { 2549 .chip_id = BCM58XX_DEVICE_ID, 2550 .dev_name = "BCM585xx/586xx/88312", 2551 .vlans = 4096, 2552 .enabled_ports = 0x1ff, 2553 .arl_bins = 4, 2554 .arl_buckets = 1024, 2555 .imp_port = 8, 2556 .vta_regs = B53_VTA_REGS, 2557 .duplex_reg = B53_DUPLEX_STAT_GE, 2558 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2559 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2560 }, 2561 { 2562 .chip_id = BCM583XX_DEVICE_ID, 2563 .dev_name = "BCM583xx/11360", 2564 .vlans = 4096, 2565 .enabled_ports = 0x103, 2566 .arl_bins = 4, 2567 .arl_buckets = 1024, 2568 .imp_port = 8, 2569 .vta_regs = B53_VTA_REGS, 2570 .duplex_reg = B53_DUPLEX_STAT_GE, 2571 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2572 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2573 }, 2574 /* Starfighter 2 */ 2575 { 2576 .chip_id = BCM4908_DEVICE_ID, 2577 .dev_name = "BCM4908", 2578 .vlans = 4096, 2579 .enabled_ports = 0x1bf, 2580 .arl_bins = 4, 2581 .arl_buckets = 256, 2582 .imp_port = 8, 2583 .vta_regs = B53_VTA_REGS, 2584 .duplex_reg = B53_DUPLEX_STAT_GE, 2585 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2586 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2587 }, 2588 { 2589 .chip_id = BCM7445_DEVICE_ID, 2590 .dev_name = "BCM7445", 2591 .vlans = 4096, 2592 .enabled_ports = 0x1ff, 2593 .arl_bins = 4, 2594 .arl_buckets = 1024, 2595 .imp_port = 8, 2596 .vta_regs = B53_VTA_REGS, 2597 .duplex_reg = B53_DUPLEX_STAT_GE, 2598 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2599 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2600 }, 2601 { 2602 .chip_id = BCM7278_DEVICE_ID, 2603 .dev_name = "BCM7278", 2604 .vlans = 4096, 2605 .enabled_ports = 0x1ff, 2606 .arl_bins = 4, 2607 .arl_buckets = 256, 2608 .imp_port = 8, 2609 .vta_regs = B53_VTA_REGS, 2610 .duplex_reg = B53_DUPLEX_STAT_GE, 2611 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2612 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2613 }, 2614 { 2615 .chip_id = BCM53134_DEVICE_ID, 2616 .dev_name = "BCM53134", 2617 .vlans = 4096, 2618 .enabled_ports = 0x12f, 2619 .imp_port = 8, 2620 .cpu_port = B53_CPU_PORT, 2621 .vta_regs = B53_VTA_REGS, 2622 .arl_bins = 4, 2623 .arl_buckets = 1024, 2624 .duplex_reg = B53_DUPLEX_STAT_GE, 2625 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2626 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2627 }, 2628 }; 2629 2630 static int b53_switch_init(struct b53_device *dev) 2631 { 2632 unsigned int i; 2633 int ret; 2634 2635 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) { 2636 const struct b53_chip_data *chip = &b53_switch_chips[i]; 2637 2638 if (chip->chip_id == dev->chip_id) { 2639 if (!dev->enabled_ports) 2640 dev->enabled_ports = chip->enabled_ports; 2641 dev->name = chip->dev_name; 2642 dev->duplex_reg = chip->duplex_reg; 2643 dev->vta_regs[0] = chip->vta_regs[0]; 2644 dev->vta_regs[1] = chip->vta_regs[1]; 2645 dev->vta_regs[2] = chip->vta_regs[2]; 2646 dev->jumbo_pm_reg = chip->jumbo_pm_reg; 2647 dev->imp_port = chip->imp_port; 2648 dev->num_vlans = chip->vlans; 2649 dev->num_arl_bins = chip->arl_bins; 2650 dev->num_arl_buckets = chip->arl_buckets; 2651 break; 2652 } 2653 } 2654 2655 /* check which BCM5325x version we have */ 2656 if (is5325(dev)) { 2657 u8 vc4; 2658 2659 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 2660 2661 /* check reserved bits */ 2662 switch (vc4 & 3) { 2663 case 1: 2664 /* BCM5325E */ 2665 break; 2666 case 3: 2667 /* BCM5325F - do not use port 4 */ 2668 dev->enabled_ports &= ~BIT(4); 2669 break; 2670 default: 2671 /* On the BCM47XX SoCs this is the supported internal switch.*/ 2672 #ifndef CONFIG_BCM47XX 2673 /* BCM5325M */ 2674 return -EINVAL; 2675 #else 2676 break; 2677 #endif 2678 } 2679 } 2680 2681 dev->num_ports = fls(dev->enabled_ports); 2682 2683 dev->ds->num_ports = min_t(unsigned int, dev->num_ports, DSA_MAX_PORTS); 2684 2685 /* Include non standard CPU port built-in PHYs to be probed */ 2686 if (is539x(dev) || is531x5(dev)) { 2687 for (i = 0; i < dev->num_ports; i++) { 2688 if (!(dev->ds->phys_mii_mask & BIT(i)) && 2689 !b53_possible_cpu_port(dev->ds, i)) 2690 dev->ds->phys_mii_mask |= BIT(i); 2691 } 2692 } 2693 2694 dev->ports = devm_kcalloc(dev->dev, 2695 dev->num_ports, sizeof(struct b53_port), 2696 GFP_KERNEL); 2697 if (!dev->ports) 2698 return -ENOMEM; 2699 2700 dev->vlans = devm_kcalloc(dev->dev, 2701 dev->num_vlans, sizeof(struct b53_vlan), 2702 GFP_KERNEL); 2703 if (!dev->vlans) 2704 return -ENOMEM; 2705 2706 dev->reset_gpio = b53_switch_get_reset_gpio(dev); 2707 if (dev->reset_gpio >= 0) { 2708 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio, 2709 GPIOF_OUT_INIT_HIGH, "robo_reset"); 2710 if (ret) 2711 return ret; 2712 } 2713 2714 return 0; 2715 } 2716 2717 struct b53_device *b53_switch_alloc(struct device *base, 2718 const struct b53_io_ops *ops, 2719 void *priv) 2720 { 2721 struct dsa_switch *ds; 2722 struct b53_device *dev; 2723 2724 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 2725 if (!ds) 2726 return NULL; 2727 2728 ds->dev = base; 2729 2730 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL); 2731 if (!dev) 2732 return NULL; 2733 2734 ds->priv = dev; 2735 dev->dev = base; 2736 2737 dev->ds = ds; 2738 dev->priv = priv; 2739 dev->ops = ops; 2740 ds->ops = &b53_switch_ops; 2741 ds->phylink_mac_ops = &b53_phylink_mac_ops; 2742 dev->vlan_enabled = true; 2743 /* Let DSA handle the case were multiple bridges span the same switch 2744 * device and different VLAN awareness settings are requested, which 2745 * would be breaking filtering semantics for any of the other bridge 2746 * devices. (not hardware supported) 2747 */ 2748 ds->vlan_filtering_is_global = true; 2749 2750 mutex_init(&dev->reg_mutex); 2751 mutex_init(&dev->stats_mutex); 2752 mutex_init(&dev->arl_mutex); 2753 2754 return dev; 2755 } 2756 EXPORT_SYMBOL(b53_switch_alloc); 2757 2758 int b53_switch_detect(struct b53_device *dev) 2759 { 2760 u32 id32; 2761 u16 tmp; 2762 u8 id8; 2763 int ret; 2764 2765 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8); 2766 if (ret) 2767 return ret; 2768 2769 switch (id8) { 2770 case 0: 2771 /* BCM5325 and BCM5365 do not have this register so reads 2772 * return 0. But the read operation did succeed, so assume this 2773 * is one of them. 2774 * 2775 * Next check if we can write to the 5325's VTA register; for 2776 * 5365 it is read only. 2777 */ 2778 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf); 2779 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp); 2780 2781 if (tmp == 0xf) 2782 dev->chip_id = BCM5325_DEVICE_ID; 2783 else 2784 dev->chip_id = BCM5365_DEVICE_ID; 2785 break; 2786 case BCM5389_DEVICE_ID: 2787 case BCM5395_DEVICE_ID: 2788 case BCM5397_DEVICE_ID: 2789 case BCM5398_DEVICE_ID: 2790 dev->chip_id = id8; 2791 break; 2792 default: 2793 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32); 2794 if (ret) 2795 return ret; 2796 2797 switch (id32) { 2798 case BCM53115_DEVICE_ID: 2799 case BCM53125_DEVICE_ID: 2800 case BCM53128_DEVICE_ID: 2801 case BCM53010_DEVICE_ID: 2802 case BCM53011_DEVICE_ID: 2803 case BCM53012_DEVICE_ID: 2804 case BCM53018_DEVICE_ID: 2805 case BCM53019_DEVICE_ID: 2806 case BCM53134_DEVICE_ID: 2807 dev->chip_id = id32; 2808 break; 2809 default: 2810 dev_err(dev->dev, 2811 "unsupported switch detected (BCM53%02x/BCM%x)\n", 2812 id8, id32); 2813 return -ENODEV; 2814 } 2815 } 2816 2817 if (dev->chip_id == BCM5325_DEVICE_ID) 2818 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25, 2819 &dev->core_rev); 2820 else 2821 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID, 2822 &dev->core_rev); 2823 } 2824 EXPORT_SYMBOL(b53_switch_detect); 2825 2826 int b53_switch_register(struct b53_device *dev) 2827 { 2828 int ret; 2829 2830 if (dev->pdata) { 2831 dev->chip_id = dev->pdata->chip_id; 2832 dev->enabled_ports = dev->pdata->enabled_ports; 2833 } 2834 2835 if (!dev->chip_id && b53_switch_detect(dev)) 2836 return -EINVAL; 2837 2838 ret = b53_switch_init(dev); 2839 if (ret) 2840 return ret; 2841 2842 dev_info(dev->dev, "found switch: %s, rev %i\n", 2843 dev->name, dev->core_rev); 2844 2845 return dsa_register_switch(dev->ds); 2846 } 2847 EXPORT_SYMBOL(b53_switch_register); 2848 2849 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>"); 2850 MODULE_DESCRIPTION("B53 switch library"); 2851 MODULE_LICENSE("Dual BSD/GPL"); 2852