1 /* 2 * B53 switch driver main logic 3 * 4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org> 5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com> 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <linux/delay.h> 21 #include <linux/export.h> 22 #include <linux/gpio.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/platform_data/b53.h> 26 #include <linux/phy.h> 27 #include <linux/phylink.h> 28 #include <linux/etherdevice.h> 29 #include <linux/if_bridge.h> 30 #include <net/dsa.h> 31 32 #include "b53_regs.h" 33 #include "b53_priv.h" 34 35 struct b53_mib_desc { 36 u8 size; 37 u8 offset; 38 const char *name; 39 }; 40 41 /* BCM5365 MIB counters */ 42 static const struct b53_mib_desc b53_mibs_65[] = { 43 { 8, 0x00, "TxOctets" }, 44 { 4, 0x08, "TxDropPkts" }, 45 { 4, 0x10, "TxBroadcastPkts" }, 46 { 4, 0x14, "TxMulticastPkts" }, 47 { 4, 0x18, "TxUnicastPkts" }, 48 { 4, 0x1c, "TxCollisions" }, 49 { 4, 0x20, "TxSingleCollision" }, 50 { 4, 0x24, "TxMultipleCollision" }, 51 { 4, 0x28, "TxDeferredTransmit" }, 52 { 4, 0x2c, "TxLateCollision" }, 53 { 4, 0x30, "TxExcessiveCollision" }, 54 { 4, 0x38, "TxPausePkts" }, 55 { 8, 0x44, "RxOctets" }, 56 { 4, 0x4c, "RxUndersizePkts" }, 57 { 4, 0x50, "RxPausePkts" }, 58 { 4, 0x54, "Pkts64Octets" }, 59 { 4, 0x58, "Pkts65to127Octets" }, 60 { 4, 0x5c, "Pkts128to255Octets" }, 61 { 4, 0x60, "Pkts256to511Octets" }, 62 { 4, 0x64, "Pkts512to1023Octets" }, 63 { 4, 0x68, "Pkts1024to1522Octets" }, 64 { 4, 0x6c, "RxOversizePkts" }, 65 { 4, 0x70, "RxJabbers" }, 66 { 4, 0x74, "RxAlignmentErrors" }, 67 { 4, 0x78, "RxFCSErrors" }, 68 { 8, 0x7c, "RxGoodOctets" }, 69 { 4, 0x84, "RxDropPkts" }, 70 { 4, 0x88, "RxUnicastPkts" }, 71 { 4, 0x8c, "RxMulticastPkts" }, 72 { 4, 0x90, "RxBroadcastPkts" }, 73 { 4, 0x94, "RxSAChanges" }, 74 { 4, 0x98, "RxFragments" }, 75 }; 76 77 #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65) 78 79 /* BCM63xx MIB counters */ 80 static const struct b53_mib_desc b53_mibs_63xx[] = { 81 { 8, 0x00, "TxOctets" }, 82 { 4, 0x08, "TxDropPkts" }, 83 { 4, 0x0c, "TxQoSPkts" }, 84 { 4, 0x10, "TxBroadcastPkts" }, 85 { 4, 0x14, "TxMulticastPkts" }, 86 { 4, 0x18, "TxUnicastPkts" }, 87 { 4, 0x1c, "TxCollisions" }, 88 { 4, 0x20, "TxSingleCollision" }, 89 { 4, 0x24, "TxMultipleCollision" }, 90 { 4, 0x28, "TxDeferredTransmit" }, 91 { 4, 0x2c, "TxLateCollision" }, 92 { 4, 0x30, "TxExcessiveCollision" }, 93 { 4, 0x38, "TxPausePkts" }, 94 { 8, 0x3c, "TxQoSOctets" }, 95 { 8, 0x44, "RxOctets" }, 96 { 4, 0x4c, "RxUndersizePkts" }, 97 { 4, 0x50, "RxPausePkts" }, 98 { 4, 0x54, "Pkts64Octets" }, 99 { 4, 0x58, "Pkts65to127Octets" }, 100 { 4, 0x5c, "Pkts128to255Octets" }, 101 { 4, 0x60, "Pkts256to511Octets" }, 102 { 4, 0x64, "Pkts512to1023Octets" }, 103 { 4, 0x68, "Pkts1024to1522Octets" }, 104 { 4, 0x6c, "RxOversizePkts" }, 105 { 4, 0x70, "RxJabbers" }, 106 { 4, 0x74, "RxAlignmentErrors" }, 107 { 4, 0x78, "RxFCSErrors" }, 108 { 8, 0x7c, "RxGoodOctets" }, 109 { 4, 0x84, "RxDropPkts" }, 110 { 4, 0x88, "RxUnicastPkts" }, 111 { 4, 0x8c, "RxMulticastPkts" }, 112 { 4, 0x90, "RxBroadcastPkts" }, 113 { 4, 0x94, "RxSAChanges" }, 114 { 4, 0x98, "RxFragments" }, 115 { 4, 0xa0, "RxSymbolErrors" }, 116 { 4, 0xa4, "RxQoSPkts" }, 117 { 8, 0xa8, "RxQoSOctets" }, 118 { 4, 0xb0, "Pkts1523to2047Octets" }, 119 { 4, 0xb4, "Pkts2048to4095Octets" }, 120 { 4, 0xb8, "Pkts4096to8191Octets" }, 121 { 4, 0xbc, "Pkts8192to9728Octets" }, 122 { 4, 0xc0, "RxDiscarded" }, 123 }; 124 125 #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx) 126 127 /* MIB counters */ 128 static const struct b53_mib_desc b53_mibs[] = { 129 { 8, 0x00, "TxOctets" }, 130 { 4, 0x08, "TxDropPkts" }, 131 { 4, 0x10, "TxBroadcastPkts" }, 132 { 4, 0x14, "TxMulticastPkts" }, 133 { 4, 0x18, "TxUnicastPkts" }, 134 { 4, 0x1c, "TxCollisions" }, 135 { 4, 0x20, "TxSingleCollision" }, 136 { 4, 0x24, "TxMultipleCollision" }, 137 { 4, 0x28, "TxDeferredTransmit" }, 138 { 4, 0x2c, "TxLateCollision" }, 139 { 4, 0x30, "TxExcessiveCollision" }, 140 { 4, 0x38, "TxPausePkts" }, 141 { 8, 0x50, "RxOctets" }, 142 { 4, 0x58, "RxUndersizePkts" }, 143 { 4, 0x5c, "RxPausePkts" }, 144 { 4, 0x60, "Pkts64Octets" }, 145 { 4, 0x64, "Pkts65to127Octets" }, 146 { 4, 0x68, "Pkts128to255Octets" }, 147 { 4, 0x6c, "Pkts256to511Octets" }, 148 { 4, 0x70, "Pkts512to1023Octets" }, 149 { 4, 0x74, "Pkts1024to1522Octets" }, 150 { 4, 0x78, "RxOversizePkts" }, 151 { 4, 0x7c, "RxJabbers" }, 152 { 4, 0x80, "RxAlignmentErrors" }, 153 { 4, 0x84, "RxFCSErrors" }, 154 { 8, 0x88, "RxGoodOctets" }, 155 { 4, 0x90, "RxDropPkts" }, 156 { 4, 0x94, "RxUnicastPkts" }, 157 { 4, 0x98, "RxMulticastPkts" }, 158 { 4, 0x9c, "RxBroadcastPkts" }, 159 { 4, 0xa0, "RxSAChanges" }, 160 { 4, 0xa4, "RxFragments" }, 161 { 4, 0xa8, "RxJumboPkts" }, 162 { 4, 0xac, "RxSymbolErrors" }, 163 { 4, 0xc0, "RxDiscarded" }, 164 }; 165 166 #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs) 167 168 static const struct b53_mib_desc b53_mibs_58xx[] = { 169 { 8, 0x00, "TxOctets" }, 170 { 4, 0x08, "TxDropPkts" }, 171 { 4, 0x0c, "TxQPKTQ0" }, 172 { 4, 0x10, "TxBroadcastPkts" }, 173 { 4, 0x14, "TxMulticastPkts" }, 174 { 4, 0x18, "TxUnicastPKts" }, 175 { 4, 0x1c, "TxCollisions" }, 176 { 4, 0x20, "TxSingleCollision" }, 177 { 4, 0x24, "TxMultipleCollision" }, 178 { 4, 0x28, "TxDeferredCollision" }, 179 { 4, 0x2c, "TxLateCollision" }, 180 { 4, 0x30, "TxExcessiveCollision" }, 181 { 4, 0x34, "TxFrameInDisc" }, 182 { 4, 0x38, "TxPausePkts" }, 183 { 4, 0x3c, "TxQPKTQ1" }, 184 { 4, 0x40, "TxQPKTQ2" }, 185 { 4, 0x44, "TxQPKTQ3" }, 186 { 4, 0x48, "TxQPKTQ4" }, 187 { 4, 0x4c, "TxQPKTQ5" }, 188 { 8, 0x50, "RxOctets" }, 189 { 4, 0x58, "RxUndersizePkts" }, 190 { 4, 0x5c, "RxPausePkts" }, 191 { 4, 0x60, "RxPkts64Octets" }, 192 { 4, 0x64, "RxPkts65to127Octets" }, 193 { 4, 0x68, "RxPkts128to255Octets" }, 194 { 4, 0x6c, "RxPkts256to511Octets" }, 195 { 4, 0x70, "RxPkts512to1023Octets" }, 196 { 4, 0x74, "RxPkts1024toMaxPktsOctets" }, 197 { 4, 0x78, "RxOversizePkts" }, 198 { 4, 0x7c, "RxJabbers" }, 199 { 4, 0x80, "RxAlignmentErrors" }, 200 { 4, 0x84, "RxFCSErrors" }, 201 { 8, 0x88, "RxGoodOctets" }, 202 { 4, 0x90, "RxDropPkts" }, 203 { 4, 0x94, "RxUnicastPkts" }, 204 { 4, 0x98, "RxMulticastPkts" }, 205 { 4, 0x9c, "RxBroadcastPkts" }, 206 { 4, 0xa0, "RxSAChanges" }, 207 { 4, 0xa4, "RxFragments" }, 208 { 4, 0xa8, "RxJumboPkt" }, 209 { 4, 0xac, "RxSymblErr" }, 210 { 4, 0xb0, "InRangeErrCount" }, 211 { 4, 0xb4, "OutRangeErrCount" }, 212 { 4, 0xb8, "EEELpiEvent" }, 213 { 4, 0xbc, "EEELpiDuration" }, 214 { 4, 0xc0, "RxDiscard" }, 215 { 4, 0xc8, "TxQPKTQ6" }, 216 { 4, 0xcc, "TxQPKTQ7" }, 217 { 4, 0xd0, "TxPkts64Octets" }, 218 { 4, 0xd4, "TxPkts65to127Octets" }, 219 { 4, 0xd8, "TxPkts128to255Octets" }, 220 { 4, 0xdc, "TxPkts256to511Ocets" }, 221 { 4, 0xe0, "TxPkts512to1023Ocets" }, 222 { 4, 0xe4, "TxPkts1024toMaxPktOcets" }, 223 }; 224 225 #define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx) 226 227 static int b53_do_vlan_op(struct b53_device *dev, u8 op) 228 { 229 unsigned int i; 230 231 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op); 232 233 for (i = 0; i < 10; i++) { 234 u8 vta; 235 236 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta); 237 if (!(vta & VTA_START_CMD)) 238 return 0; 239 240 usleep_range(100, 200); 241 } 242 243 return -EIO; 244 } 245 246 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, 247 struct b53_vlan *vlan) 248 { 249 if (is5325(dev)) { 250 u32 entry = 0; 251 252 if (vlan->members) { 253 entry = ((vlan->untag & VA_UNTAG_MASK_25) << 254 VA_UNTAG_S_25) | vlan->members; 255 if (dev->core_rev >= 3) 256 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S; 257 else 258 entry |= VA_VALID_25; 259 } 260 261 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry); 262 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 263 VTA_RW_STATE_WR | VTA_RW_OP_EN); 264 } else if (is5365(dev)) { 265 u16 entry = 0; 266 267 if (vlan->members) 268 entry = ((vlan->untag & VA_UNTAG_MASK_65) << 269 VA_UNTAG_S_65) | vlan->members | VA_VALID_65; 270 271 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry); 272 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 273 VTA_RW_STATE_WR | VTA_RW_OP_EN); 274 } else { 275 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 276 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], 277 (vlan->untag << VTE_UNTAG_S) | vlan->members); 278 279 b53_do_vlan_op(dev, VTA_CMD_WRITE); 280 } 281 282 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n", 283 vid, vlan->members, vlan->untag); 284 } 285 286 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid, 287 struct b53_vlan *vlan) 288 { 289 if (is5325(dev)) { 290 u32 entry = 0; 291 292 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 293 VTA_RW_STATE_RD | VTA_RW_OP_EN); 294 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry); 295 296 if (dev->core_rev >= 3) 297 vlan->valid = !!(entry & VA_VALID_25_R4); 298 else 299 vlan->valid = !!(entry & VA_VALID_25); 300 vlan->members = entry & VA_MEMBER_MASK; 301 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25; 302 303 } else if (is5365(dev)) { 304 u16 entry = 0; 305 306 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 307 VTA_RW_STATE_WR | VTA_RW_OP_EN); 308 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry); 309 310 vlan->valid = !!(entry & VA_VALID_65); 311 vlan->members = entry & VA_MEMBER_MASK; 312 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65; 313 } else { 314 u32 entry = 0; 315 316 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 317 b53_do_vlan_op(dev, VTA_CMD_READ); 318 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry); 319 vlan->members = entry & VTE_MEMBERS; 320 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS; 321 vlan->valid = true; 322 } 323 } 324 325 static void b53_set_forwarding(struct b53_device *dev, int enable) 326 { 327 u8 mgmt; 328 329 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 330 331 if (enable) 332 mgmt |= SM_SW_FWD_EN; 333 else 334 mgmt &= ~SM_SW_FWD_EN; 335 336 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 337 338 /* Include IMP port in dumb forwarding mode 339 */ 340 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt); 341 mgmt |= B53_MII_DUMB_FWDG_EN; 342 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt); 343 344 /* Look at B53_UC_FWD_EN and B53_MC_FWD_EN to decide whether 345 * frames should be flooded or not. 346 */ 347 b53_read8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, &mgmt); 348 mgmt |= B53_UC_FWD_EN | B53_MC_FWD_EN | B53_IPMC_FWD_EN; 349 b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt); 350 } 351 352 static void b53_enable_vlan(struct b53_device *dev, int port, bool enable, 353 bool enable_filtering) 354 { 355 u8 mgmt, vc0, vc1, vc4 = 0, vc5; 356 357 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 358 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0); 359 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1); 360 361 if (is5325(dev) || is5365(dev)) { 362 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 363 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5); 364 } else if (is63xx(dev)) { 365 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4); 366 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5); 367 } else { 368 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4); 369 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5); 370 } 371 372 if (enable) { 373 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID; 374 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN; 375 vc4 &= ~VC4_ING_VID_CHECK_MASK; 376 if (enable_filtering) { 377 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S; 378 vc5 |= VC5_DROP_VTABLE_MISS; 379 } else { 380 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 381 vc5 &= ~VC5_DROP_VTABLE_MISS; 382 } 383 384 if (is5325(dev)) 385 vc0 &= ~VC0_RESERVED_1; 386 387 if (is5325(dev) || is5365(dev)) 388 vc1 |= VC1_RX_MCST_TAG_EN; 389 390 } else { 391 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID); 392 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN); 393 vc4 &= ~VC4_ING_VID_CHECK_MASK; 394 vc5 &= ~VC5_DROP_VTABLE_MISS; 395 396 if (is5325(dev) || is5365(dev)) 397 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 398 else 399 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S; 400 401 if (is5325(dev) || is5365(dev)) 402 vc1 &= ~VC1_RX_MCST_TAG_EN; 403 } 404 405 if (!is5325(dev) && !is5365(dev)) 406 vc5 &= ~VC5_VID_FFF_EN; 407 408 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0); 409 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1); 410 411 if (is5325(dev) || is5365(dev)) { 412 /* enable the high 8 bit vid check on 5325 */ 413 if (is5325(dev) && enable) 414 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 415 VC3_HIGH_8BIT_EN); 416 else 417 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 418 419 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4); 420 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5); 421 } else if (is63xx(dev)) { 422 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0); 423 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4); 424 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5); 425 } else { 426 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 427 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4); 428 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5); 429 } 430 431 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 432 433 dev->vlan_enabled = enable; 434 435 dev_dbg(dev->dev, "Port %d VLAN enabled: %d, filtering: %d\n", 436 port, enable, enable_filtering); 437 } 438 439 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100) 440 { 441 u32 port_mask = 0; 442 u16 max_size = JMS_MIN_SIZE; 443 444 if (is5325(dev) || is5365(dev)) 445 return -EINVAL; 446 447 if (enable) { 448 port_mask = dev->enabled_ports; 449 max_size = JMS_MAX_SIZE; 450 if (allow_10_100) 451 port_mask |= JPM_10_100_JUMBO_EN; 452 } 453 454 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask); 455 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size); 456 } 457 458 static int b53_flush_arl(struct b53_device *dev, u8 mask) 459 { 460 unsigned int i; 461 462 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 463 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask); 464 465 for (i = 0; i < 10; i++) { 466 u8 fast_age_ctrl; 467 468 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 469 &fast_age_ctrl); 470 471 if (!(fast_age_ctrl & FAST_AGE_DONE)) 472 goto out; 473 474 msleep(1); 475 } 476 477 return -ETIMEDOUT; 478 out: 479 /* Only age dynamic entries (default behavior) */ 480 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC); 481 return 0; 482 } 483 484 static int b53_fast_age_port(struct b53_device *dev, int port) 485 { 486 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port); 487 488 return b53_flush_arl(dev, FAST_AGE_PORT); 489 } 490 491 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid) 492 { 493 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid); 494 495 return b53_flush_arl(dev, FAST_AGE_VLAN); 496 } 497 498 void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port) 499 { 500 struct b53_device *dev = ds->priv; 501 unsigned int i; 502 u16 pvlan; 503 504 /* Enable the IMP port to be in the same VLAN as the other ports 505 * on a per-port basis such that we only have Port i and IMP in 506 * the same VLAN. 507 */ 508 b53_for_each_port(dev, i) { 509 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan); 510 pvlan |= BIT(cpu_port); 511 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan); 512 } 513 } 514 EXPORT_SYMBOL(b53_imp_vlan_setup); 515 516 static void b53_port_set_ucast_flood(struct b53_device *dev, int port, 517 bool unicast) 518 { 519 u16 uc; 520 521 b53_read16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, &uc); 522 if (unicast) 523 uc |= BIT(port); 524 else 525 uc &= ~BIT(port); 526 b53_write16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, uc); 527 } 528 529 static void b53_port_set_mcast_flood(struct b53_device *dev, int port, 530 bool multicast) 531 { 532 u16 mc; 533 534 b53_read16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, &mc); 535 if (multicast) 536 mc |= BIT(port); 537 else 538 mc &= ~BIT(port); 539 b53_write16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, mc); 540 541 b53_read16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, &mc); 542 if (multicast) 543 mc |= BIT(port); 544 else 545 mc &= ~BIT(port); 546 b53_write16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, mc); 547 } 548 549 static void b53_port_set_learning(struct b53_device *dev, int port, 550 bool learning) 551 { 552 u16 reg; 553 554 b53_read16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, ®); 555 if (learning) 556 reg &= ~BIT(port); 557 else 558 reg |= BIT(port); 559 b53_write16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, reg); 560 } 561 562 static void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable) 563 { 564 struct b53_device *dev = ds->priv; 565 u16 reg; 566 567 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, ®); 568 if (enable) 569 reg |= BIT(port); 570 else 571 reg &= ~BIT(port); 572 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg); 573 } 574 575 int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy) 576 { 577 struct b53_device *dev = ds->priv; 578 unsigned int cpu_port; 579 int ret = 0; 580 u16 pvlan; 581 582 if (!dsa_is_user_port(ds, port)) 583 return 0; 584 585 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 586 587 b53_port_set_ucast_flood(dev, port, true); 588 b53_port_set_mcast_flood(dev, port, true); 589 b53_port_set_learning(dev, port, false); 590 591 if (dev->ops->irq_enable) 592 ret = dev->ops->irq_enable(dev, port); 593 if (ret) 594 return ret; 595 596 /* Clear the Rx and Tx disable bits and set to no spanning tree */ 597 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0); 598 599 /* Set this port, and only this one to be in the default VLAN, 600 * if member of a bridge, restore its membership prior to 601 * bringing down this port. 602 */ 603 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 604 pvlan &= ~0x1ff; 605 pvlan |= BIT(port); 606 pvlan |= dev->ports[port].vlan_ctl_mask; 607 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 608 609 b53_imp_vlan_setup(ds, cpu_port); 610 611 /* If EEE was enabled, restore it */ 612 if (dev->ports[port].eee.eee_enabled) 613 b53_eee_enable_set(ds, port, true); 614 615 return 0; 616 } 617 EXPORT_SYMBOL(b53_enable_port); 618 619 void b53_disable_port(struct dsa_switch *ds, int port) 620 { 621 struct b53_device *dev = ds->priv; 622 u8 reg; 623 624 /* Disable Tx/Rx for the port */ 625 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 626 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE; 627 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 628 629 if (dev->ops->irq_disable) 630 dev->ops->irq_disable(dev, port); 631 } 632 EXPORT_SYMBOL(b53_disable_port); 633 634 void b53_brcm_hdr_setup(struct dsa_switch *ds, int port) 635 { 636 struct b53_device *dev = ds->priv; 637 bool tag_en = !(dev->tag_protocol == DSA_TAG_PROTO_NONE); 638 u8 hdr_ctl, val; 639 u16 reg; 640 641 /* Resolve which bit controls the Broadcom tag */ 642 switch (port) { 643 case 8: 644 val = BRCM_HDR_P8_EN; 645 break; 646 case 7: 647 val = BRCM_HDR_P7_EN; 648 break; 649 case 5: 650 val = BRCM_HDR_P5_EN; 651 break; 652 default: 653 val = 0; 654 break; 655 } 656 657 /* Enable management mode if tagging is requested */ 658 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &hdr_ctl); 659 if (tag_en) 660 hdr_ctl |= SM_SW_FWD_MODE; 661 else 662 hdr_ctl &= ~SM_SW_FWD_MODE; 663 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, hdr_ctl); 664 665 /* Configure the appropriate IMP port */ 666 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &hdr_ctl); 667 if (port == 8) 668 hdr_ctl |= GC_FRM_MGMT_PORT_MII; 669 else if (port == 5) 670 hdr_ctl |= GC_FRM_MGMT_PORT_M; 671 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, hdr_ctl); 672 673 /* Enable Broadcom tags for IMP port */ 674 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl); 675 if (tag_en) 676 hdr_ctl |= val; 677 else 678 hdr_ctl &= ~val; 679 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl); 680 681 /* Registers below are only accessible on newer devices */ 682 if (!is58xx(dev)) 683 return; 684 685 /* Enable reception Broadcom tag for CPU TX (switch RX) to 686 * allow us to tag outgoing frames 687 */ 688 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, ®); 689 if (tag_en) 690 reg &= ~BIT(port); 691 else 692 reg |= BIT(port); 693 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg); 694 695 /* Enable transmission of Broadcom tags from the switch (CPU RX) to 696 * allow delivering frames to the per-port net_devices 697 */ 698 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, ®); 699 if (tag_en) 700 reg &= ~BIT(port); 701 else 702 reg |= BIT(port); 703 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg); 704 } 705 EXPORT_SYMBOL(b53_brcm_hdr_setup); 706 707 static void b53_enable_cpu_port(struct b53_device *dev, int port) 708 { 709 u8 port_ctrl; 710 711 /* BCM5325 CPU port is at 8 */ 712 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25) 713 port = B53_CPU_PORT; 714 715 port_ctrl = PORT_CTRL_RX_BCST_EN | 716 PORT_CTRL_RX_MCST_EN | 717 PORT_CTRL_RX_UCST_EN; 718 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl); 719 720 b53_brcm_hdr_setup(dev->ds, port); 721 722 b53_port_set_ucast_flood(dev, port, true); 723 b53_port_set_mcast_flood(dev, port, true); 724 b53_port_set_learning(dev, port, false); 725 } 726 727 static void b53_enable_mib(struct b53_device *dev) 728 { 729 u8 gc; 730 731 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 732 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN); 733 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc); 734 } 735 736 static u16 b53_default_pvid(struct b53_device *dev) 737 { 738 if (is5325(dev) || is5365(dev)) 739 return 1; 740 else 741 return 0; 742 } 743 744 static bool b53_vlan_port_needs_forced_tagged(struct dsa_switch *ds, int port) 745 { 746 struct b53_device *dev = ds->priv; 747 748 return dev->tag_protocol == DSA_TAG_PROTO_NONE && dsa_is_cpu_port(ds, port); 749 } 750 751 int b53_configure_vlan(struct dsa_switch *ds) 752 { 753 struct b53_device *dev = ds->priv; 754 struct b53_vlan vl = { 0 }; 755 struct b53_vlan *v; 756 int i, def_vid; 757 u16 vid; 758 759 def_vid = b53_default_pvid(dev); 760 761 /* clear all vlan entries */ 762 if (is5325(dev) || is5365(dev)) { 763 for (i = def_vid; i < dev->num_vlans; i++) 764 b53_set_vlan_entry(dev, i, &vl); 765 } else { 766 b53_do_vlan_op(dev, VTA_CMD_CLEAR); 767 } 768 769 b53_enable_vlan(dev, -1, dev->vlan_enabled, ds->vlan_filtering); 770 771 /* Create an untagged VLAN entry for the default PVID in case 772 * CONFIG_VLAN_8021Q is disabled and there are no calls to 773 * dsa_user_vlan_rx_add_vid() to create the default VLAN 774 * entry. Do this only when the tagging protocol is not 775 * DSA_TAG_PROTO_NONE 776 */ 777 b53_for_each_port(dev, i) { 778 v = &dev->vlans[def_vid]; 779 v->members |= BIT(i); 780 if (!b53_vlan_port_needs_forced_tagged(ds, i)) 781 v->untag = v->members; 782 b53_write16(dev, B53_VLAN_PAGE, 783 B53_VLAN_PORT_DEF_TAG(i), def_vid); 784 } 785 786 /* Upon initial call we have not set-up any VLANs, but upon 787 * system resume, we need to restore all VLAN entries. 788 */ 789 for (vid = def_vid; vid < dev->num_vlans; vid++) { 790 v = &dev->vlans[vid]; 791 792 if (!v->members) 793 continue; 794 795 b53_set_vlan_entry(dev, vid, v); 796 b53_fast_age_vlan(dev, vid); 797 } 798 799 return 0; 800 } 801 EXPORT_SYMBOL(b53_configure_vlan); 802 803 static void b53_switch_reset_gpio(struct b53_device *dev) 804 { 805 int gpio = dev->reset_gpio; 806 807 if (gpio < 0) 808 return; 809 810 /* Reset sequence: RESET low(50ms)->high(20ms) 811 */ 812 gpio_set_value(gpio, 0); 813 mdelay(50); 814 815 gpio_set_value(gpio, 1); 816 mdelay(20); 817 818 dev->current_page = 0xff; 819 } 820 821 static int b53_switch_reset(struct b53_device *dev) 822 { 823 unsigned int timeout = 1000; 824 u8 mgmt, reg; 825 826 b53_switch_reset_gpio(dev); 827 828 if (is539x(dev)) { 829 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83); 830 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00); 831 } 832 833 /* This is specific to 58xx devices here, do not use is58xx() which 834 * covers the larger Starfigther 2 family, including 7445/7278 which 835 * still use this driver as a library and need to perform the reset 836 * earlier. 837 */ 838 if (dev->chip_id == BCM58XX_DEVICE_ID || 839 dev->chip_id == BCM583XX_DEVICE_ID) { 840 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 841 reg |= SW_RST | EN_SW_RST | EN_CH_RST; 842 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg); 843 844 do { 845 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 846 if (!(reg & SW_RST)) 847 break; 848 849 usleep_range(1000, 2000); 850 } while (timeout-- > 0); 851 852 if (timeout == 0) { 853 dev_err(dev->dev, 854 "Timeout waiting for SW_RST to clear!\n"); 855 return -ETIMEDOUT; 856 } 857 } 858 859 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 860 861 if (!(mgmt & SM_SW_FWD_EN)) { 862 mgmt &= ~SM_SW_FWD_MODE; 863 mgmt |= SM_SW_FWD_EN; 864 865 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 866 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 867 868 if (!(mgmt & SM_SW_FWD_EN)) { 869 dev_err(dev->dev, "Failed to enable switch!\n"); 870 return -EINVAL; 871 } 872 } 873 874 b53_enable_mib(dev); 875 876 return b53_flush_arl(dev, FAST_AGE_STATIC); 877 } 878 879 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg) 880 { 881 struct b53_device *priv = ds->priv; 882 u16 value = 0; 883 int ret; 884 885 if (priv->ops->phy_read16) 886 ret = priv->ops->phy_read16(priv, addr, reg, &value); 887 else 888 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr), 889 reg * 2, &value); 890 891 return ret ? ret : value; 892 } 893 894 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 895 { 896 struct b53_device *priv = ds->priv; 897 898 if (priv->ops->phy_write16) 899 return priv->ops->phy_write16(priv, addr, reg, val); 900 901 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val); 902 } 903 904 static int b53_reset_switch(struct b53_device *priv) 905 { 906 /* reset vlans */ 907 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans); 908 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports); 909 910 priv->serdes_lane = B53_INVALID_LANE; 911 912 return b53_switch_reset(priv); 913 } 914 915 static int b53_apply_config(struct b53_device *priv) 916 { 917 /* disable switching */ 918 b53_set_forwarding(priv, 0); 919 920 b53_configure_vlan(priv->ds); 921 922 /* enable switching */ 923 b53_set_forwarding(priv, 1); 924 925 return 0; 926 } 927 928 static void b53_reset_mib(struct b53_device *priv) 929 { 930 u8 gc; 931 932 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 933 934 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB); 935 msleep(1); 936 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB); 937 msleep(1); 938 } 939 940 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev) 941 { 942 if (is5365(dev)) 943 return b53_mibs_65; 944 else if (is63xx(dev)) 945 return b53_mibs_63xx; 946 else if (is58xx(dev)) 947 return b53_mibs_58xx; 948 else 949 return b53_mibs; 950 } 951 952 static unsigned int b53_get_mib_size(struct b53_device *dev) 953 { 954 if (is5365(dev)) 955 return B53_MIBS_65_SIZE; 956 else if (is63xx(dev)) 957 return B53_MIBS_63XX_SIZE; 958 else if (is58xx(dev)) 959 return B53_MIBS_58XX_SIZE; 960 else 961 return B53_MIBS_SIZE; 962 } 963 964 static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port) 965 { 966 /* These ports typically do not have built-in PHYs */ 967 switch (port) { 968 case B53_CPU_PORT_25: 969 case 7: 970 case B53_CPU_PORT: 971 return NULL; 972 } 973 974 return mdiobus_get_phy(ds->user_mii_bus, port); 975 } 976 977 void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset, 978 uint8_t *data) 979 { 980 struct b53_device *dev = ds->priv; 981 const struct b53_mib_desc *mibs = b53_get_mib(dev); 982 unsigned int mib_size = b53_get_mib_size(dev); 983 struct phy_device *phydev; 984 unsigned int i; 985 986 if (stringset == ETH_SS_STATS) { 987 for (i = 0; i < mib_size; i++) 988 strscpy(data + i * ETH_GSTRING_LEN, 989 mibs[i].name, ETH_GSTRING_LEN); 990 } else if (stringset == ETH_SS_PHY_STATS) { 991 phydev = b53_get_phy_device(ds, port); 992 if (!phydev) 993 return; 994 995 phy_ethtool_get_strings(phydev, data); 996 } 997 } 998 EXPORT_SYMBOL(b53_get_strings); 999 1000 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) 1001 { 1002 struct b53_device *dev = ds->priv; 1003 const struct b53_mib_desc *mibs = b53_get_mib(dev); 1004 unsigned int mib_size = b53_get_mib_size(dev); 1005 const struct b53_mib_desc *s; 1006 unsigned int i; 1007 u64 val = 0; 1008 1009 if (is5365(dev) && port == 5) 1010 port = 8; 1011 1012 mutex_lock(&dev->stats_mutex); 1013 1014 for (i = 0; i < mib_size; i++) { 1015 s = &mibs[i]; 1016 1017 if (s->size == 8) { 1018 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val); 1019 } else { 1020 u32 val32; 1021 1022 b53_read32(dev, B53_MIB_PAGE(port), s->offset, 1023 &val32); 1024 val = val32; 1025 } 1026 data[i] = (u64)val; 1027 } 1028 1029 mutex_unlock(&dev->stats_mutex); 1030 } 1031 EXPORT_SYMBOL(b53_get_ethtool_stats); 1032 1033 void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data) 1034 { 1035 struct phy_device *phydev; 1036 1037 phydev = b53_get_phy_device(ds, port); 1038 if (!phydev) 1039 return; 1040 1041 phy_ethtool_get_stats(phydev, NULL, data); 1042 } 1043 EXPORT_SYMBOL(b53_get_ethtool_phy_stats); 1044 1045 int b53_get_sset_count(struct dsa_switch *ds, int port, int sset) 1046 { 1047 struct b53_device *dev = ds->priv; 1048 struct phy_device *phydev; 1049 1050 if (sset == ETH_SS_STATS) { 1051 return b53_get_mib_size(dev); 1052 } else if (sset == ETH_SS_PHY_STATS) { 1053 phydev = b53_get_phy_device(ds, port); 1054 if (!phydev) 1055 return 0; 1056 1057 return phy_ethtool_get_sset_count(phydev); 1058 } 1059 1060 return 0; 1061 } 1062 EXPORT_SYMBOL(b53_get_sset_count); 1063 1064 enum b53_devlink_resource_id { 1065 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1066 }; 1067 1068 static u64 b53_devlink_vlan_table_get(void *priv) 1069 { 1070 struct b53_device *dev = priv; 1071 struct b53_vlan *vl; 1072 unsigned int i; 1073 u64 count = 0; 1074 1075 for (i = 0; i < dev->num_vlans; i++) { 1076 vl = &dev->vlans[i]; 1077 if (vl->members) 1078 count++; 1079 } 1080 1081 return count; 1082 } 1083 1084 int b53_setup_devlink_resources(struct dsa_switch *ds) 1085 { 1086 struct devlink_resource_size_params size_params; 1087 struct b53_device *dev = ds->priv; 1088 int err; 1089 1090 devlink_resource_size_params_init(&size_params, dev->num_vlans, 1091 dev->num_vlans, 1092 1, DEVLINK_RESOURCE_UNIT_ENTRY); 1093 1094 err = dsa_devlink_resource_register(ds, "VLAN", dev->num_vlans, 1095 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1096 DEVLINK_RESOURCE_ID_PARENT_TOP, 1097 &size_params); 1098 if (err) 1099 goto out; 1100 1101 dsa_devlink_resource_occ_get_register(ds, 1102 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1103 b53_devlink_vlan_table_get, dev); 1104 1105 return 0; 1106 out: 1107 dsa_devlink_resources_unregister(ds); 1108 return err; 1109 } 1110 EXPORT_SYMBOL(b53_setup_devlink_resources); 1111 1112 static int b53_setup(struct dsa_switch *ds) 1113 { 1114 struct b53_device *dev = ds->priv; 1115 unsigned int port; 1116 int ret; 1117 1118 /* Request bridge PVID untagged when DSA_TAG_PROTO_NONE is set 1119 * which forces the CPU port to be tagged in all VLANs. 1120 */ 1121 ds->untag_bridge_pvid = dev->tag_protocol == DSA_TAG_PROTO_NONE; 1122 1123 ret = b53_reset_switch(dev); 1124 if (ret) { 1125 dev_err(ds->dev, "failed to reset switch\n"); 1126 return ret; 1127 } 1128 1129 b53_reset_mib(dev); 1130 1131 ret = b53_apply_config(dev); 1132 if (ret) { 1133 dev_err(ds->dev, "failed to apply configuration\n"); 1134 return ret; 1135 } 1136 1137 /* Configure IMP/CPU port, disable all other ports. Enabled 1138 * ports will be configured with .port_enable 1139 */ 1140 for (port = 0; port < dev->num_ports; port++) { 1141 if (dsa_is_cpu_port(ds, port)) 1142 b53_enable_cpu_port(dev, port); 1143 else 1144 b53_disable_port(ds, port); 1145 } 1146 1147 return b53_setup_devlink_resources(ds); 1148 } 1149 1150 static void b53_teardown(struct dsa_switch *ds) 1151 { 1152 dsa_devlink_resources_unregister(ds); 1153 } 1154 1155 static void b53_force_link(struct b53_device *dev, int port, int link) 1156 { 1157 u8 reg, val, off; 1158 1159 /* Override the port settings */ 1160 if (port == dev->imp_port) { 1161 off = B53_PORT_OVERRIDE_CTRL; 1162 val = PORT_OVERRIDE_EN; 1163 } else { 1164 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 1165 val = GMII_PO_EN; 1166 } 1167 1168 b53_read8(dev, B53_CTRL_PAGE, off, ®); 1169 reg |= val; 1170 if (link) 1171 reg |= PORT_OVERRIDE_LINK; 1172 else 1173 reg &= ~PORT_OVERRIDE_LINK; 1174 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1175 } 1176 1177 static void b53_force_port_config(struct b53_device *dev, int port, 1178 int speed, int duplex, 1179 bool tx_pause, bool rx_pause) 1180 { 1181 u8 reg, val, off; 1182 1183 /* Override the port settings */ 1184 if (port == dev->imp_port) { 1185 off = B53_PORT_OVERRIDE_CTRL; 1186 val = PORT_OVERRIDE_EN; 1187 } else { 1188 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 1189 val = GMII_PO_EN; 1190 } 1191 1192 b53_read8(dev, B53_CTRL_PAGE, off, ®); 1193 reg |= val; 1194 if (duplex == DUPLEX_FULL) 1195 reg |= PORT_OVERRIDE_FULL_DUPLEX; 1196 else 1197 reg &= ~PORT_OVERRIDE_FULL_DUPLEX; 1198 1199 switch (speed) { 1200 case 2000: 1201 reg |= PORT_OVERRIDE_SPEED_2000M; 1202 fallthrough; 1203 case SPEED_1000: 1204 reg |= PORT_OVERRIDE_SPEED_1000M; 1205 break; 1206 case SPEED_100: 1207 reg |= PORT_OVERRIDE_SPEED_100M; 1208 break; 1209 case SPEED_10: 1210 reg |= PORT_OVERRIDE_SPEED_10M; 1211 break; 1212 default: 1213 dev_err(dev->dev, "unknown speed: %d\n", speed); 1214 return; 1215 } 1216 1217 if (rx_pause) 1218 reg |= PORT_OVERRIDE_RX_FLOW; 1219 if (tx_pause) 1220 reg |= PORT_OVERRIDE_TX_FLOW; 1221 1222 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1223 } 1224 1225 static void b53_adjust_63xx_rgmii(struct dsa_switch *ds, int port, 1226 phy_interface_t interface) 1227 { 1228 struct b53_device *dev = ds->priv; 1229 u8 rgmii_ctrl = 0, off; 1230 1231 if (port == dev->imp_port) 1232 off = B53_RGMII_CTRL_IMP; 1233 else 1234 off = B53_RGMII_CTRL_P(port); 1235 1236 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl); 1237 1238 switch (interface) { 1239 case PHY_INTERFACE_MODE_RGMII_ID: 1240 rgmii_ctrl |= (RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC); 1241 break; 1242 case PHY_INTERFACE_MODE_RGMII_RXID: 1243 rgmii_ctrl &= ~(RGMII_CTRL_DLL_TXC); 1244 rgmii_ctrl |= RGMII_CTRL_DLL_RXC; 1245 break; 1246 case PHY_INTERFACE_MODE_RGMII_TXID: 1247 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC); 1248 rgmii_ctrl |= RGMII_CTRL_DLL_TXC; 1249 break; 1250 case PHY_INTERFACE_MODE_RGMII: 1251 default: 1252 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC); 1253 break; 1254 } 1255 1256 if (port != dev->imp_port) { 1257 if (is63268(dev)) 1258 rgmii_ctrl |= RGMII_CTRL_MII_OVERRIDE; 1259 1260 rgmii_ctrl |= RGMII_CTRL_ENABLE_GMII; 1261 } 1262 1263 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl); 1264 1265 dev_dbg(ds->dev, "Configured port %d for %s\n", port, 1266 phy_modes(interface)); 1267 } 1268 1269 static void b53_adjust_531x5_rgmii(struct dsa_switch *ds, int port, 1270 phy_interface_t interface) 1271 { 1272 struct b53_device *dev = ds->priv; 1273 u8 rgmii_ctrl = 0, off; 1274 1275 if (port == dev->imp_port) 1276 off = B53_RGMII_CTRL_IMP; 1277 else 1278 off = B53_RGMII_CTRL_P(port); 1279 1280 /* Configure the port RGMII clock delay by DLL disabled and 1281 * tx_clk aligned timing (restoring to reset defaults) 1282 */ 1283 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl); 1284 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC | 1285 RGMII_CTRL_TIMING_SEL); 1286 1287 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make 1288 * sure that we enable the port TX clock internal delay to 1289 * account for this internal delay that is inserted, otherwise 1290 * the switch won't be able to receive correctly. 1291 * 1292 * PHY_INTERFACE_MODE_RGMII means that we are not introducing 1293 * any delay neither on transmission nor reception, so the 1294 * BCM53125 must also be configured accordingly to account for 1295 * the lack of delay and introduce 1296 * 1297 * The BCM53125 switch has its RX clock and TX clock control 1298 * swapped, hence the reason why we modify the TX clock path in 1299 * the "RGMII" case 1300 */ 1301 if (interface == PHY_INTERFACE_MODE_RGMII_TXID) 1302 rgmii_ctrl |= RGMII_CTRL_DLL_TXC; 1303 if (interface == PHY_INTERFACE_MODE_RGMII) 1304 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC; 1305 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL; 1306 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl); 1307 1308 dev_info(ds->dev, "Configured port %d for %s\n", port, 1309 phy_modes(interface)); 1310 } 1311 1312 static void b53_adjust_5325_mii(struct dsa_switch *ds, int port) 1313 { 1314 struct b53_device *dev = ds->priv; 1315 u8 reg = 0; 1316 1317 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1318 ®); 1319 1320 /* reverse mii needs to be enabled */ 1321 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1322 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1323 reg | PORT_OVERRIDE_RV_MII_25); 1324 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1325 ®); 1326 1327 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1328 dev_err(ds->dev, 1329 "Failed to enable reverse MII mode\n"); 1330 return; 1331 } 1332 } 1333 } 1334 1335 void b53_port_event(struct dsa_switch *ds, int port) 1336 { 1337 struct b53_device *dev = ds->priv; 1338 bool link; 1339 u16 sts; 1340 1341 b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts); 1342 link = !!(sts & BIT(port)); 1343 dsa_port_phylink_mac_change(ds, port, link); 1344 } 1345 EXPORT_SYMBOL(b53_port_event); 1346 1347 static void b53_phylink_get_caps(struct dsa_switch *ds, int port, 1348 struct phylink_config *config) 1349 { 1350 struct b53_device *dev = ds->priv; 1351 1352 /* Internal ports need GMII for PHYLIB */ 1353 __set_bit(PHY_INTERFACE_MODE_GMII, config->supported_interfaces); 1354 1355 /* These switches appear to support MII and RevMII too, but beyond 1356 * this, the code gives very few clues. FIXME: We probably need more 1357 * interface modes here. 1358 * 1359 * According to b53_srab_mux_init(), ports 3..5 can support: 1360 * SGMII, MII, GMII, RGMII or INTERNAL depending on the MUX setting. 1361 * However, the interface mode read from the MUX configuration is 1362 * not passed back to DSA, so phylink uses NA. 1363 * DT can specify RGMII for ports 0, 1. 1364 * For MDIO, port 8 can be RGMII_TXID. 1365 */ 1366 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 1367 __set_bit(PHY_INTERFACE_MODE_REVMII, config->supported_interfaces); 1368 1369 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 1370 MAC_10 | MAC_100; 1371 1372 /* 5325/5365 are not capable of gigabit speeds, everything else is. 1373 * Note: the original code also exclulded Gigagbit for MII, RevMII 1374 * and 802.3z modes. MII and RevMII are not able to work above 100M, 1375 * so will be excluded by the generic validator implementation. 1376 * However, the exclusion of Gigabit for 802.3z just seems wrong. 1377 */ 1378 if (!(is5325(dev) || is5365(dev))) 1379 config->mac_capabilities |= MAC_1000; 1380 1381 /* Get the implementation specific capabilities */ 1382 if (dev->ops->phylink_get_caps) 1383 dev->ops->phylink_get_caps(dev, port, config); 1384 } 1385 1386 static struct phylink_pcs *b53_phylink_mac_select_pcs(struct phylink_config *config, 1387 phy_interface_t interface) 1388 { 1389 struct dsa_port *dp = dsa_phylink_to_port(config); 1390 struct b53_device *dev = dp->ds->priv; 1391 1392 if (!dev->ops->phylink_mac_select_pcs) 1393 return NULL; 1394 1395 return dev->ops->phylink_mac_select_pcs(dev, dp->index, interface); 1396 } 1397 1398 static void b53_phylink_mac_config(struct phylink_config *config, 1399 unsigned int mode, 1400 const struct phylink_link_state *state) 1401 { 1402 struct dsa_port *dp = dsa_phylink_to_port(config); 1403 phy_interface_t interface = state->interface; 1404 struct dsa_switch *ds = dp->ds; 1405 struct b53_device *dev = ds->priv; 1406 int port = dp->index; 1407 1408 if (is63xx(dev) && port >= B53_63XX_RGMII0) 1409 b53_adjust_63xx_rgmii(ds, port, interface); 1410 1411 if (mode == MLO_AN_FIXED) { 1412 if (is531x5(dev) && phy_interface_mode_is_rgmii(interface)) 1413 b53_adjust_531x5_rgmii(ds, port, interface); 1414 1415 /* configure MII port if necessary */ 1416 if (is5325(dev)) 1417 b53_adjust_5325_mii(ds, port); 1418 } 1419 } 1420 1421 static void b53_phylink_mac_link_down(struct phylink_config *config, 1422 unsigned int mode, 1423 phy_interface_t interface) 1424 { 1425 struct dsa_port *dp = dsa_phylink_to_port(config); 1426 struct b53_device *dev = dp->ds->priv; 1427 int port = dp->index; 1428 1429 if (mode == MLO_AN_PHY) 1430 return; 1431 1432 if (mode == MLO_AN_FIXED) { 1433 b53_force_link(dev, port, false); 1434 return; 1435 } 1436 1437 if (phy_interface_mode_is_8023z(interface) && 1438 dev->ops->serdes_link_set) 1439 dev->ops->serdes_link_set(dev, port, mode, interface, false); 1440 } 1441 1442 static void b53_phylink_mac_link_up(struct phylink_config *config, 1443 struct phy_device *phydev, 1444 unsigned int mode, 1445 phy_interface_t interface, 1446 int speed, int duplex, 1447 bool tx_pause, bool rx_pause) 1448 { 1449 struct dsa_port *dp = dsa_phylink_to_port(config); 1450 struct dsa_switch *ds = dp->ds; 1451 struct b53_device *dev = ds->priv; 1452 struct ethtool_keee *p = &dev->ports[dp->index].eee; 1453 int port = dp->index; 1454 1455 if (mode == MLO_AN_PHY) { 1456 /* Re-negotiate EEE if it was enabled already */ 1457 p->eee_enabled = b53_eee_init(ds, port, phydev); 1458 return; 1459 } 1460 1461 if (mode == MLO_AN_FIXED) { 1462 /* Force flow control on BCM5301x's CPU port */ 1463 if (is5301x(dev) && dsa_is_cpu_port(ds, port)) 1464 tx_pause = rx_pause = true; 1465 1466 b53_force_port_config(dev, port, speed, duplex, 1467 tx_pause, rx_pause); 1468 b53_force_link(dev, port, true); 1469 return; 1470 } 1471 1472 if (phy_interface_mode_is_8023z(interface) && 1473 dev->ops->serdes_link_set) 1474 dev->ops->serdes_link_set(dev, port, mode, interface, true); 1475 } 1476 1477 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1478 struct netlink_ext_ack *extack) 1479 { 1480 struct b53_device *dev = ds->priv; 1481 1482 b53_enable_vlan(dev, port, dev->vlan_enabled, vlan_filtering); 1483 1484 return 0; 1485 } 1486 EXPORT_SYMBOL(b53_vlan_filtering); 1487 1488 static int b53_vlan_prepare(struct dsa_switch *ds, int port, 1489 const struct switchdev_obj_port_vlan *vlan) 1490 { 1491 struct b53_device *dev = ds->priv; 1492 1493 if ((is5325(dev) || is5365(dev)) && vlan->vid == 0) 1494 return -EOPNOTSUPP; 1495 1496 /* Port 7 on 7278 connects to the ASP's UniMAC which is not capable of 1497 * receiving VLAN tagged frames at all, we can still allow the port to 1498 * be configured for egress untagged. 1499 */ 1500 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7 && 1501 !(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)) 1502 return -EINVAL; 1503 1504 if (vlan->vid >= dev->num_vlans) 1505 return -ERANGE; 1506 1507 b53_enable_vlan(dev, port, true, ds->vlan_filtering); 1508 1509 return 0; 1510 } 1511 1512 int b53_vlan_add(struct dsa_switch *ds, int port, 1513 const struct switchdev_obj_port_vlan *vlan, 1514 struct netlink_ext_ack *extack) 1515 { 1516 struct b53_device *dev = ds->priv; 1517 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1518 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1519 struct b53_vlan *vl; 1520 int err; 1521 1522 err = b53_vlan_prepare(ds, port, vlan); 1523 if (err) 1524 return err; 1525 1526 vl = &dev->vlans[vlan->vid]; 1527 1528 b53_get_vlan_entry(dev, vlan->vid, vl); 1529 1530 if (vlan->vid == 0 && vlan->vid == b53_default_pvid(dev)) 1531 untagged = true; 1532 1533 vl->members |= BIT(port); 1534 if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port)) 1535 vl->untag |= BIT(port); 1536 else 1537 vl->untag &= ~BIT(port); 1538 1539 b53_set_vlan_entry(dev, vlan->vid, vl); 1540 b53_fast_age_vlan(dev, vlan->vid); 1541 1542 if (pvid && !dsa_is_cpu_port(ds, port)) { 1543 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), 1544 vlan->vid); 1545 b53_fast_age_vlan(dev, vlan->vid); 1546 } 1547 1548 return 0; 1549 } 1550 EXPORT_SYMBOL(b53_vlan_add); 1551 1552 int b53_vlan_del(struct dsa_switch *ds, int port, 1553 const struct switchdev_obj_port_vlan *vlan) 1554 { 1555 struct b53_device *dev = ds->priv; 1556 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1557 struct b53_vlan *vl; 1558 u16 pvid; 1559 1560 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid); 1561 1562 vl = &dev->vlans[vlan->vid]; 1563 1564 b53_get_vlan_entry(dev, vlan->vid, vl); 1565 1566 vl->members &= ~BIT(port); 1567 1568 if (pvid == vlan->vid) 1569 pvid = b53_default_pvid(dev); 1570 1571 if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port)) 1572 vl->untag &= ~(BIT(port)); 1573 1574 b53_set_vlan_entry(dev, vlan->vid, vl); 1575 b53_fast_age_vlan(dev, vlan->vid); 1576 1577 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid); 1578 b53_fast_age_vlan(dev, pvid); 1579 1580 return 0; 1581 } 1582 EXPORT_SYMBOL(b53_vlan_del); 1583 1584 /* Address Resolution Logic routines. Caller must hold &dev->arl_mutex. */ 1585 static int b53_arl_op_wait(struct b53_device *dev) 1586 { 1587 unsigned int timeout = 10; 1588 u8 reg; 1589 1590 do { 1591 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1592 if (!(reg & ARLTBL_START_DONE)) 1593 return 0; 1594 1595 usleep_range(1000, 2000); 1596 } while (timeout--); 1597 1598 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg); 1599 1600 return -ETIMEDOUT; 1601 } 1602 1603 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op) 1604 { 1605 u8 reg; 1606 1607 if (op > ARLTBL_RW) 1608 return -EINVAL; 1609 1610 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1611 reg |= ARLTBL_START_DONE; 1612 if (op) 1613 reg |= ARLTBL_RW; 1614 else 1615 reg &= ~ARLTBL_RW; 1616 if (dev->vlan_enabled) 1617 reg &= ~ARLTBL_IVL_SVL_SELECT; 1618 else 1619 reg |= ARLTBL_IVL_SVL_SELECT; 1620 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg); 1621 1622 return b53_arl_op_wait(dev); 1623 } 1624 1625 static int b53_arl_read(struct b53_device *dev, u64 mac, 1626 u16 vid, struct b53_arl_entry *ent, u8 *idx) 1627 { 1628 DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES); 1629 unsigned int i; 1630 int ret; 1631 1632 ret = b53_arl_op_wait(dev); 1633 if (ret) 1634 return ret; 1635 1636 bitmap_zero(free_bins, dev->num_arl_bins); 1637 1638 /* Read the bins */ 1639 for (i = 0; i < dev->num_arl_bins; i++) { 1640 u64 mac_vid; 1641 u32 fwd_entry; 1642 1643 b53_read64(dev, B53_ARLIO_PAGE, 1644 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid); 1645 b53_read32(dev, B53_ARLIO_PAGE, 1646 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry); 1647 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1648 1649 if (!(fwd_entry & ARLTBL_VALID)) { 1650 set_bit(i, free_bins); 1651 continue; 1652 } 1653 if ((mac_vid & ARLTBL_MAC_MASK) != mac) 1654 continue; 1655 if (dev->vlan_enabled && 1656 ((mac_vid >> ARLTBL_VID_S) & ARLTBL_VID_MASK) != vid) 1657 continue; 1658 *idx = i; 1659 return 0; 1660 } 1661 1662 *idx = find_first_bit(free_bins, dev->num_arl_bins); 1663 return *idx >= dev->num_arl_bins ? -ENOSPC : -ENOENT; 1664 } 1665 1666 static int b53_arl_op(struct b53_device *dev, int op, int port, 1667 const unsigned char *addr, u16 vid, bool is_valid) 1668 { 1669 struct b53_arl_entry ent; 1670 u32 fwd_entry; 1671 u64 mac, mac_vid = 0; 1672 u8 idx = 0; 1673 int ret; 1674 1675 /* Convert the array into a 64-bit MAC */ 1676 mac = ether_addr_to_u64(addr); 1677 1678 /* Perform a read for the given MAC and VID */ 1679 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac); 1680 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid); 1681 1682 /* Issue a read operation for this MAC */ 1683 ret = b53_arl_rw_op(dev, 1); 1684 if (ret) 1685 return ret; 1686 1687 ret = b53_arl_read(dev, mac, vid, &ent, &idx); 1688 1689 /* If this is a read, just finish now */ 1690 if (op) 1691 return ret; 1692 1693 switch (ret) { 1694 case -ETIMEDOUT: 1695 return ret; 1696 case -ENOSPC: 1697 dev_dbg(dev->dev, "{%pM,%.4d} no space left in ARL\n", 1698 addr, vid); 1699 return is_valid ? ret : 0; 1700 case -ENOENT: 1701 /* We could not find a matching MAC, so reset to a new entry */ 1702 dev_dbg(dev->dev, "{%pM,%.4d} not found, using idx: %d\n", 1703 addr, vid, idx); 1704 fwd_entry = 0; 1705 break; 1706 default: 1707 dev_dbg(dev->dev, "{%pM,%.4d} found, using idx: %d\n", 1708 addr, vid, idx); 1709 break; 1710 } 1711 1712 /* For multicast address, the port is a bitmask and the validity 1713 * is determined by having at least one port being still active 1714 */ 1715 if (!is_multicast_ether_addr(addr)) { 1716 ent.port = port; 1717 ent.is_valid = is_valid; 1718 } else { 1719 if (is_valid) 1720 ent.port |= BIT(port); 1721 else 1722 ent.port &= ~BIT(port); 1723 1724 ent.is_valid = !!(ent.port); 1725 } 1726 1727 ent.vid = vid; 1728 ent.is_static = true; 1729 ent.is_age = false; 1730 memcpy(ent.mac, addr, ETH_ALEN); 1731 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent); 1732 1733 b53_write64(dev, B53_ARLIO_PAGE, 1734 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid); 1735 b53_write32(dev, B53_ARLIO_PAGE, 1736 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry); 1737 1738 return b53_arl_rw_op(dev, 0); 1739 } 1740 1741 int b53_fdb_add(struct dsa_switch *ds, int port, 1742 const unsigned char *addr, u16 vid, 1743 struct dsa_db db) 1744 { 1745 struct b53_device *priv = ds->priv; 1746 int ret; 1747 1748 /* 5325 and 5365 require some more massaging, but could 1749 * be supported eventually 1750 */ 1751 if (is5325(priv) || is5365(priv)) 1752 return -EOPNOTSUPP; 1753 1754 mutex_lock(&priv->arl_mutex); 1755 ret = b53_arl_op(priv, 0, port, addr, vid, true); 1756 mutex_unlock(&priv->arl_mutex); 1757 1758 return ret; 1759 } 1760 EXPORT_SYMBOL(b53_fdb_add); 1761 1762 int b53_fdb_del(struct dsa_switch *ds, int port, 1763 const unsigned char *addr, u16 vid, 1764 struct dsa_db db) 1765 { 1766 struct b53_device *priv = ds->priv; 1767 int ret; 1768 1769 mutex_lock(&priv->arl_mutex); 1770 ret = b53_arl_op(priv, 0, port, addr, vid, false); 1771 mutex_unlock(&priv->arl_mutex); 1772 1773 return ret; 1774 } 1775 EXPORT_SYMBOL(b53_fdb_del); 1776 1777 static int b53_arl_search_wait(struct b53_device *dev) 1778 { 1779 unsigned int timeout = 1000; 1780 u8 reg; 1781 1782 do { 1783 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®); 1784 if (!(reg & ARL_SRCH_STDN)) 1785 return 0; 1786 1787 if (reg & ARL_SRCH_VLID) 1788 return 0; 1789 1790 usleep_range(1000, 2000); 1791 } while (timeout--); 1792 1793 return -ETIMEDOUT; 1794 } 1795 1796 static void b53_arl_search_rd(struct b53_device *dev, u8 idx, 1797 struct b53_arl_entry *ent) 1798 { 1799 u64 mac_vid; 1800 u32 fwd_entry; 1801 1802 b53_read64(dev, B53_ARLIO_PAGE, 1803 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid); 1804 b53_read32(dev, B53_ARLIO_PAGE, 1805 B53_ARL_SRCH_RSTL(idx), &fwd_entry); 1806 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1807 } 1808 1809 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent, 1810 dsa_fdb_dump_cb_t *cb, void *data) 1811 { 1812 if (!ent->is_valid) 1813 return 0; 1814 1815 if (port != ent->port) 1816 return 0; 1817 1818 return cb(ent->mac, ent->vid, ent->is_static, data); 1819 } 1820 1821 int b53_fdb_dump(struct dsa_switch *ds, int port, 1822 dsa_fdb_dump_cb_t *cb, void *data) 1823 { 1824 struct b53_device *priv = ds->priv; 1825 struct b53_arl_entry results[2]; 1826 unsigned int count = 0; 1827 int ret; 1828 u8 reg; 1829 1830 mutex_lock(&priv->arl_mutex); 1831 1832 /* Start search operation */ 1833 reg = ARL_SRCH_STDN; 1834 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg); 1835 1836 do { 1837 ret = b53_arl_search_wait(priv); 1838 if (ret) 1839 break; 1840 1841 b53_arl_search_rd(priv, 0, &results[0]); 1842 ret = b53_fdb_copy(port, &results[0], cb, data); 1843 if (ret) 1844 break; 1845 1846 if (priv->num_arl_bins > 2) { 1847 b53_arl_search_rd(priv, 1, &results[1]); 1848 ret = b53_fdb_copy(port, &results[1], cb, data); 1849 if (ret) 1850 break; 1851 1852 if (!results[0].is_valid && !results[1].is_valid) 1853 break; 1854 } 1855 1856 } while (count++ < b53_max_arl_entries(priv) / 2); 1857 1858 mutex_unlock(&priv->arl_mutex); 1859 1860 return 0; 1861 } 1862 EXPORT_SYMBOL(b53_fdb_dump); 1863 1864 int b53_mdb_add(struct dsa_switch *ds, int port, 1865 const struct switchdev_obj_port_mdb *mdb, 1866 struct dsa_db db) 1867 { 1868 struct b53_device *priv = ds->priv; 1869 int ret; 1870 1871 /* 5325 and 5365 require some more massaging, but could 1872 * be supported eventually 1873 */ 1874 if (is5325(priv) || is5365(priv)) 1875 return -EOPNOTSUPP; 1876 1877 mutex_lock(&priv->arl_mutex); 1878 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, true); 1879 mutex_unlock(&priv->arl_mutex); 1880 1881 return ret; 1882 } 1883 EXPORT_SYMBOL(b53_mdb_add); 1884 1885 int b53_mdb_del(struct dsa_switch *ds, int port, 1886 const struct switchdev_obj_port_mdb *mdb, 1887 struct dsa_db db) 1888 { 1889 struct b53_device *priv = ds->priv; 1890 int ret; 1891 1892 mutex_lock(&priv->arl_mutex); 1893 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, false); 1894 mutex_unlock(&priv->arl_mutex); 1895 if (ret) 1896 dev_err(ds->dev, "failed to delete MDB entry\n"); 1897 1898 return ret; 1899 } 1900 EXPORT_SYMBOL(b53_mdb_del); 1901 1902 int b53_br_join(struct dsa_switch *ds, int port, struct dsa_bridge bridge, 1903 bool *tx_fwd_offload, struct netlink_ext_ack *extack) 1904 { 1905 struct b53_device *dev = ds->priv; 1906 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 1907 u16 pvlan, reg; 1908 unsigned int i; 1909 1910 /* On 7278, port 7 which connects to the ASP should only receive 1911 * traffic from matching CFP rules. 1912 */ 1913 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7) 1914 return -EINVAL; 1915 1916 /* Make this port leave the all VLANs join since we will have proper 1917 * VLAN entries from now on 1918 */ 1919 if (is58xx(dev)) { 1920 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1921 reg &= ~BIT(port); 1922 if ((reg & BIT(cpu_port)) == BIT(cpu_port)) 1923 reg &= ~BIT(cpu_port); 1924 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1925 } 1926 1927 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1928 1929 b53_for_each_port(dev, i) { 1930 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge)) 1931 continue; 1932 1933 /* Add this local port to the remote port VLAN control 1934 * membership and update the remote port bitmask 1935 */ 1936 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1937 reg |= BIT(port); 1938 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1939 dev->ports[i].vlan_ctl_mask = reg; 1940 1941 pvlan |= BIT(i); 1942 } 1943 1944 /* Configure the local port VLAN control membership to include 1945 * remote ports and update the local port bitmask 1946 */ 1947 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1948 dev->ports[port].vlan_ctl_mask = pvlan; 1949 1950 return 0; 1951 } 1952 EXPORT_SYMBOL(b53_br_join); 1953 1954 void b53_br_leave(struct dsa_switch *ds, int port, struct dsa_bridge bridge) 1955 { 1956 struct b53_device *dev = ds->priv; 1957 struct b53_vlan *vl = &dev->vlans[0]; 1958 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 1959 unsigned int i; 1960 u16 pvlan, reg, pvid; 1961 1962 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1963 1964 b53_for_each_port(dev, i) { 1965 /* Don't touch the remaining ports */ 1966 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge)) 1967 continue; 1968 1969 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1970 reg &= ~BIT(port); 1971 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1972 dev->ports[port].vlan_ctl_mask = reg; 1973 1974 /* Prevent self removal to preserve isolation */ 1975 if (port != i) 1976 pvlan &= ~BIT(i); 1977 } 1978 1979 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1980 dev->ports[port].vlan_ctl_mask = pvlan; 1981 1982 pvid = b53_default_pvid(dev); 1983 1984 /* Make this port join all VLANs without VLAN entries */ 1985 if (is58xx(dev)) { 1986 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1987 reg |= BIT(port); 1988 if (!(reg & BIT(cpu_port))) 1989 reg |= BIT(cpu_port); 1990 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1991 } else { 1992 b53_get_vlan_entry(dev, pvid, vl); 1993 vl->members |= BIT(port) | BIT(cpu_port); 1994 vl->untag |= BIT(port) | BIT(cpu_port); 1995 b53_set_vlan_entry(dev, pvid, vl); 1996 } 1997 } 1998 EXPORT_SYMBOL(b53_br_leave); 1999 2000 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state) 2001 { 2002 struct b53_device *dev = ds->priv; 2003 u8 hw_state; 2004 u8 reg; 2005 2006 switch (state) { 2007 case BR_STATE_DISABLED: 2008 hw_state = PORT_CTRL_DIS_STATE; 2009 break; 2010 case BR_STATE_LISTENING: 2011 hw_state = PORT_CTRL_LISTEN_STATE; 2012 break; 2013 case BR_STATE_LEARNING: 2014 hw_state = PORT_CTRL_LEARN_STATE; 2015 break; 2016 case BR_STATE_FORWARDING: 2017 hw_state = PORT_CTRL_FWD_STATE; 2018 break; 2019 case BR_STATE_BLOCKING: 2020 hw_state = PORT_CTRL_BLOCK_STATE; 2021 break; 2022 default: 2023 dev_err(ds->dev, "invalid STP state: %d\n", state); 2024 return; 2025 } 2026 2027 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 2028 reg &= ~PORT_CTRL_STP_STATE_MASK; 2029 reg |= hw_state; 2030 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 2031 } 2032 EXPORT_SYMBOL(b53_br_set_stp_state); 2033 2034 void b53_br_fast_age(struct dsa_switch *ds, int port) 2035 { 2036 struct b53_device *dev = ds->priv; 2037 2038 if (b53_fast_age_port(dev, port)) 2039 dev_err(ds->dev, "fast ageing failed\n"); 2040 } 2041 EXPORT_SYMBOL(b53_br_fast_age); 2042 2043 int b53_br_flags_pre(struct dsa_switch *ds, int port, 2044 struct switchdev_brport_flags flags, 2045 struct netlink_ext_ack *extack) 2046 { 2047 if (flags.mask & ~(BR_FLOOD | BR_MCAST_FLOOD | BR_LEARNING)) 2048 return -EINVAL; 2049 2050 return 0; 2051 } 2052 EXPORT_SYMBOL(b53_br_flags_pre); 2053 2054 int b53_br_flags(struct dsa_switch *ds, int port, 2055 struct switchdev_brport_flags flags, 2056 struct netlink_ext_ack *extack) 2057 { 2058 if (flags.mask & BR_FLOOD) 2059 b53_port_set_ucast_flood(ds->priv, port, 2060 !!(flags.val & BR_FLOOD)); 2061 if (flags.mask & BR_MCAST_FLOOD) 2062 b53_port_set_mcast_flood(ds->priv, port, 2063 !!(flags.val & BR_MCAST_FLOOD)); 2064 if (flags.mask & BR_LEARNING) 2065 b53_port_set_learning(ds->priv, port, 2066 !!(flags.val & BR_LEARNING)); 2067 2068 return 0; 2069 } 2070 EXPORT_SYMBOL(b53_br_flags); 2071 2072 static bool b53_possible_cpu_port(struct dsa_switch *ds, int port) 2073 { 2074 /* Broadcom switches will accept enabling Broadcom tags on the 2075 * following ports: 5, 7 and 8, any other port is not supported 2076 */ 2077 switch (port) { 2078 case B53_CPU_PORT_25: 2079 case 7: 2080 case B53_CPU_PORT: 2081 return true; 2082 } 2083 2084 return false; 2085 } 2086 2087 static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port, 2088 enum dsa_tag_protocol tag_protocol) 2089 { 2090 bool ret = b53_possible_cpu_port(ds, port); 2091 2092 if (!ret) { 2093 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n", 2094 port); 2095 return ret; 2096 } 2097 2098 switch (tag_protocol) { 2099 case DSA_TAG_PROTO_BRCM: 2100 case DSA_TAG_PROTO_BRCM_PREPEND: 2101 dev_warn(ds->dev, 2102 "Port %d is stacked to Broadcom tag switch\n", port); 2103 ret = false; 2104 break; 2105 default: 2106 ret = true; 2107 break; 2108 } 2109 2110 return ret; 2111 } 2112 2113 enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port, 2114 enum dsa_tag_protocol mprot) 2115 { 2116 struct b53_device *dev = ds->priv; 2117 2118 if (!b53_can_enable_brcm_tags(ds, port, mprot)) { 2119 dev->tag_protocol = DSA_TAG_PROTO_NONE; 2120 goto out; 2121 } 2122 2123 /* Older models require a different 6 byte tag */ 2124 if (is5325(dev) || is5365(dev) || is63xx(dev)) { 2125 dev->tag_protocol = DSA_TAG_PROTO_BRCM_LEGACY; 2126 goto out; 2127 } 2128 2129 /* Broadcom BCM58xx chips have a flow accelerator on Port 8 2130 * which requires us to use the prepended Broadcom tag type 2131 */ 2132 if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT) { 2133 dev->tag_protocol = DSA_TAG_PROTO_BRCM_PREPEND; 2134 goto out; 2135 } 2136 2137 dev->tag_protocol = DSA_TAG_PROTO_BRCM; 2138 out: 2139 return dev->tag_protocol; 2140 } 2141 EXPORT_SYMBOL(b53_get_tag_protocol); 2142 2143 int b53_mirror_add(struct dsa_switch *ds, int port, 2144 struct dsa_mall_mirror_tc_entry *mirror, bool ingress, 2145 struct netlink_ext_ack *extack) 2146 { 2147 struct b53_device *dev = ds->priv; 2148 u16 reg, loc; 2149 2150 if (ingress) 2151 loc = B53_IG_MIR_CTL; 2152 else 2153 loc = B53_EG_MIR_CTL; 2154 2155 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 2156 reg |= BIT(port); 2157 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 2158 2159 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 2160 reg &= ~CAP_PORT_MASK; 2161 reg |= mirror->to_local_port; 2162 reg |= MIRROR_EN; 2163 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 2164 2165 return 0; 2166 } 2167 EXPORT_SYMBOL(b53_mirror_add); 2168 2169 void b53_mirror_del(struct dsa_switch *ds, int port, 2170 struct dsa_mall_mirror_tc_entry *mirror) 2171 { 2172 struct b53_device *dev = ds->priv; 2173 bool loc_disable = false, other_loc_disable = false; 2174 u16 reg, loc; 2175 2176 if (mirror->ingress) 2177 loc = B53_IG_MIR_CTL; 2178 else 2179 loc = B53_EG_MIR_CTL; 2180 2181 /* Update the desired ingress/egress register */ 2182 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 2183 reg &= ~BIT(port); 2184 if (!(reg & MIRROR_MASK)) 2185 loc_disable = true; 2186 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 2187 2188 /* Now look at the other one to know if we can disable mirroring 2189 * entirely 2190 */ 2191 if (mirror->ingress) 2192 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, ®); 2193 else 2194 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, ®); 2195 if (!(reg & MIRROR_MASK)) 2196 other_loc_disable = true; 2197 2198 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 2199 /* Both no longer have ports, let's disable mirroring */ 2200 if (loc_disable && other_loc_disable) { 2201 reg &= ~MIRROR_EN; 2202 reg &= ~mirror->to_local_port; 2203 } 2204 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 2205 } 2206 EXPORT_SYMBOL(b53_mirror_del); 2207 2208 /* Returns 0 if EEE was not enabled, or 1 otherwise 2209 */ 2210 int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy) 2211 { 2212 int ret; 2213 2214 ret = phy_init_eee(phy, false); 2215 if (ret) 2216 return 0; 2217 2218 b53_eee_enable_set(ds, port, true); 2219 2220 return 1; 2221 } 2222 EXPORT_SYMBOL(b53_eee_init); 2223 2224 int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_keee *e) 2225 { 2226 struct b53_device *dev = ds->priv; 2227 2228 if (is5325(dev) || is5365(dev)) 2229 return -EOPNOTSUPP; 2230 2231 return 0; 2232 } 2233 EXPORT_SYMBOL(b53_get_mac_eee); 2234 2235 int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_keee *e) 2236 { 2237 struct b53_device *dev = ds->priv; 2238 struct ethtool_keee *p = &dev->ports[port].eee; 2239 2240 if (is5325(dev) || is5365(dev)) 2241 return -EOPNOTSUPP; 2242 2243 p->eee_enabled = e->eee_enabled; 2244 b53_eee_enable_set(ds, port, e->eee_enabled); 2245 2246 return 0; 2247 } 2248 EXPORT_SYMBOL(b53_set_mac_eee); 2249 2250 static int b53_change_mtu(struct dsa_switch *ds, int port, int mtu) 2251 { 2252 struct b53_device *dev = ds->priv; 2253 bool enable_jumbo; 2254 bool allow_10_100; 2255 2256 if (is5325(dev) || is5365(dev)) 2257 return -EOPNOTSUPP; 2258 2259 if (!dsa_is_cpu_port(ds, port)) 2260 return 0; 2261 2262 enable_jumbo = (mtu >= JMS_MIN_SIZE); 2263 allow_10_100 = (dev->chip_id == BCM583XX_DEVICE_ID); 2264 2265 return b53_set_jumbo(dev, enable_jumbo, allow_10_100); 2266 } 2267 2268 static int b53_get_max_mtu(struct dsa_switch *ds, int port) 2269 { 2270 return JMS_MAX_SIZE; 2271 } 2272 2273 static const struct phylink_mac_ops b53_phylink_mac_ops = { 2274 .mac_select_pcs = b53_phylink_mac_select_pcs, 2275 .mac_config = b53_phylink_mac_config, 2276 .mac_link_down = b53_phylink_mac_link_down, 2277 .mac_link_up = b53_phylink_mac_link_up, 2278 }; 2279 2280 static const struct dsa_switch_ops b53_switch_ops = { 2281 .get_tag_protocol = b53_get_tag_protocol, 2282 .setup = b53_setup, 2283 .teardown = b53_teardown, 2284 .get_strings = b53_get_strings, 2285 .get_ethtool_stats = b53_get_ethtool_stats, 2286 .get_sset_count = b53_get_sset_count, 2287 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 2288 .phy_read = b53_phy_read16, 2289 .phy_write = b53_phy_write16, 2290 .phylink_get_caps = b53_phylink_get_caps, 2291 .port_enable = b53_enable_port, 2292 .port_disable = b53_disable_port, 2293 .get_mac_eee = b53_get_mac_eee, 2294 .set_mac_eee = b53_set_mac_eee, 2295 .port_bridge_join = b53_br_join, 2296 .port_bridge_leave = b53_br_leave, 2297 .port_pre_bridge_flags = b53_br_flags_pre, 2298 .port_bridge_flags = b53_br_flags, 2299 .port_stp_state_set = b53_br_set_stp_state, 2300 .port_fast_age = b53_br_fast_age, 2301 .port_vlan_filtering = b53_vlan_filtering, 2302 .port_vlan_add = b53_vlan_add, 2303 .port_vlan_del = b53_vlan_del, 2304 .port_fdb_dump = b53_fdb_dump, 2305 .port_fdb_add = b53_fdb_add, 2306 .port_fdb_del = b53_fdb_del, 2307 .port_mirror_add = b53_mirror_add, 2308 .port_mirror_del = b53_mirror_del, 2309 .port_mdb_add = b53_mdb_add, 2310 .port_mdb_del = b53_mdb_del, 2311 .port_max_mtu = b53_get_max_mtu, 2312 .port_change_mtu = b53_change_mtu, 2313 }; 2314 2315 struct b53_chip_data { 2316 u32 chip_id; 2317 const char *dev_name; 2318 u16 vlans; 2319 u16 enabled_ports; 2320 u8 imp_port; 2321 u8 cpu_port; 2322 u8 vta_regs[3]; 2323 u8 arl_bins; 2324 u16 arl_buckets; 2325 u8 duplex_reg; 2326 u8 jumbo_pm_reg; 2327 u8 jumbo_size_reg; 2328 }; 2329 2330 #define B53_VTA_REGS \ 2331 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY } 2332 #define B53_VTA_REGS_9798 \ 2333 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 } 2334 #define B53_VTA_REGS_63XX \ 2335 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX } 2336 2337 static const struct b53_chip_data b53_switch_chips[] = { 2338 { 2339 .chip_id = BCM5325_DEVICE_ID, 2340 .dev_name = "BCM5325", 2341 .vlans = 16, 2342 .enabled_ports = 0x3f, 2343 .arl_bins = 2, 2344 .arl_buckets = 1024, 2345 .imp_port = 5, 2346 .duplex_reg = B53_DUPLEX_STAT_FE, 2347 }, 2348 { 2349 .chip_id = BCM5365_DEVICE_ID, 2350 .dev_name = "BCM5365", 2351 .vlans = 256, 2352 .enabled_ports = 0x3f, 2353 .arl_bins = 2, 2354 .arl_buckets = 1024, 2355 .imp_port = 5, 2356 .duplex_reg = B53_DUPLEX_STAT_FE, 2357 }, 2358 { 2359 .chip_id = BCM5389_DEVICE_ID, 2360 .dev_name = "BCM5389", 2361 .vlans = 4096, 2362 .enabled_ports = 0x11f, 2363 .arl_bins = 4, 2364 .arl_buckets = 1024, 2365 .imp_port = 8, 2366 .vta_regs = B53_VTA_REGS, 2367 .duplex_reg = B53_DUPLEX_STAT_GE, 2368 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2369 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2370 }, 2371 { 2372 .chip_id = BCM5395_DEVICE_ID, 2373 .dev_name = "BCM5395", 2374 .vlans = 4096, 2375 .enabled_ports = 0x11f, 2376 .arl_bins = 4, 2377 .arl_buckets = 1024, 2378 .imp_port = 8, 2379 .vta_regs = B53_VTA_REGS, 2380 .duplex_reg = B53_DUPLEX_STAT_GE, 2381 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2382 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2383 }, 2384 { 2385 .chip_id = BCM5397_DEVICE_ID, 2386 .dev_name = "BCM5397", 2387 .vlans = 4096, 2388 .enabled_ports = 0x11f, 2389 .arl_bins = 4, 2390 .arl_buckets = 1024, 2391 .imp_port = 8, 2392 .vta_regs = B53_VTA_REGS_9798, 2393 .duplex_reg = B53_DUPLEX_STAT_GE, 2394 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2395 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2396 }, 2397 { 2398 .chip_id = BCM5398_DEVICE_ID, 2399 .dev_name = "BCM5398", 2400 .vlans = 4096, 2401 .enabled_ports = 0x17f, 2402 .arl_bins = 4, 2403 .arl_buckets = 1024, 2404 .imp_port = 8, 2405 .vta_regs = B53_VTA_REGS_9798, 2406 .duplex_reg = B53_DUPLEX_STAT_GE, 2407 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2408 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2409 }, 2410 { 2411 .chip_id = BCM53115_DEVICE_ID, 2412 .dev_name = "BCM53115", 2413 .vlans = 4096, 2414 .enabled_ports = 0x11f, 2415 .arl_bins = 4, 2416 .arl_buckets = 1024, 2417 .vta_regs = B53_VTA_REGS, 2418 .imp_port = 8, 2419 .duplex_reg = B53_DUPLEX_STAT_GE, 2420 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2421 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2422 }, 2423 { 2424 .chip_id = BCM53125_DEVICE_ID, 2425 .dev_name = "BCM53125", 2426 .vlans = 4096, 2427 .enabled_ports = 0x1ff, 2428 .arl_bins = 4, 2429 .arl_buckets = 1024, 2430 .imp_port = 8, 2431 .vta_regs = B53_VTA_REGS, 2432 .duplex_reg = B53_DUPLEX_STAT_GE, 2433 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2434 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2435 }, 2436 { 2437 .chip_id = BCM53128_DEVICE_ID, 2438 .dev_name = "BCM53128", 2439 .vlans = 4096, 2440 .enabled_ports = 0x1ff, 2441 .arl_bins = 4, 2442 .arl_buckets = 1024, 2443 .imp_port = 8, 2444 .vta_regs = B53_VTA_REGS, 2445 .duplex_reg = B53_DUPLEX_STAT_GE, 2446 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2447 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2448 }, 2449 { 2450 .chip_id = BCM63XX_DEVICE_ID, 2451 .dev_name = "BCM63xx", 2452 .vlans = 4096, 2453 .enabled_ports = 0, /* pdata must provide them */ 2454 .arl_bins = 4, 2455 .arl_buckets = 1024, 2456 .imp_port = 8, 2457 .vta_regs = B53_VTA_REGS_63XX, 2458 .duplex_reg = B53_DUPLEX_STAT_63XX, 2459 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, 2460 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, 2461 }, 2462 { 2463 .chip_id = BCM63268_DEVICE_ID, 2464 .dev_name = "BCM63268", 2465 .vlans = 4096, 2466 .enabled_ports = 0, /* pdata must provide them */ 2467 .arl_bins = 4, 2468 .arl_buckets = 1024, 2469 .imp_port = 8, 2470 .vta_regs = B53_VTA_REGS_63XX, 2471 .duplex_reg = B53_DUPLEX_STAT_63XX, 2472 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, 2473 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, 2474 }, 2475 { 2476 .chip_id = BCM53010_DEVICE_ID, 2477 .dev_name = "BCM53010", 2478 .vlans = 4096, 2479 .enabled_ports = 0x1bf, 2480 .arl_bins = 4, 2481 .arl_buckets = 1024, 2482 .imp_port = 8, 2483 .vta_regs = B53_VTA_REGS, 2484 .duplex_reg = B53_DUPLEX_STAT_GE, 2485 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2486 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2487 }, 2488 { 2489 .chip_id = BCM53011_DEVICE_ID, 2490 .dev_name = "BCM53011", 2491 .vlans = 4096, 2492 .enabled_ports = 0x1bf, 2493 .arl_bins = 4, 2494 .arl_buckets = 1024, 2495 .imp_port = 8, 2496 .vta_regs = B53_VTA_REGS, 2497 .duplex_reg = B53_DUPLEX_STAT_GE, 2498 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2499 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2500 }, 2501 { 2502 .chip_id = BCM53012_DEVICE_ID, 2503 .dev_name = "BCM53012", 2504 .vlans = 4096, 2505 .enabled_ports = 0x1bf, 2506 .arl_bins = 4, 2507 .arl_buckets = 1024, 2508 .imp_port = 8, 2509 .vta_regs = B53_VTA_REGS, 2510 .duplex_reg = B53_DUPLEX_STAT_GE, 2511 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2512 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2513 }, 2514 { 2515 .chip_id = BCM53018_DEVICE_ID, 2516 .dev_name = "BCM53018", 2517 .vlans = 4096, 2518 .enabled_ports = 0x1bf, 2519 .arl_bins = 4, 2520 .arl_buckets = 1024, 2521 .imp_port = 8, 2522 .vta_regs = B53_VTA_REGS, 2523 .duplex_reg = B53_DUPLEX_STAT_GE, 2524 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2525 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2526 }, 2527 { 2528 .chip_id = BCM53019_DEVICE_ID, 2529 .dev_name = "BCM53019", 2530 .vlans = 4096, 2531 .enabled_ports = 0x1bf, 2532 .arl_bins = 4, 2533 .arl_buckets = 1024, 2534 .imp_port = 8, 2535 .vta_regs = B53_VTA_REGS, 2536 .duplex_reg = B53_DUPLEX_STAT_GE, 2537 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2538 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2539 }, 2540 { 2541 .chip_id = BCM58XX_DEVICE_ID, 2542 .dev_name = "BCM585xx/586xx/88312", 2543 .vlans = 4096, 2544 .enabled_ports = 0x1ff, 2545 .arl_bins = 4, 2546 .arl_buckets = 1024, 2547 .imp_port = 8, 2548 .vta_regs = B53_VTA_REGS, 2549 .duplex_reg = B53_DUPLEX_STAT_GE, 2550 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2551 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2552 }, 2553 { 2554 .chip_id = BCM583XX_DEVICE_ID, 2555 .dev_name = "BCM583xx/11360", 2556 .vlans = 4096, 2557 .enabled_ports = 0x103, 2558 .arl_bins = 4, 2559 .arl_buckets = 1024, 2560 .imp_port = 8, 2561 .vta_regs = B53_VTA_REGS, 2562 .duplex_reg = B53_DUPLEX_STAT_GE, 2563 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2564 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2565 }, 2566 /* Starfighter 2 */ 2567 { 2568 .chip_id = BCM4908_DEVICE_ID, 2569 .dev_name = "BCM4908", 2570 .vlans = 4096, 2571 .enabled_ports = 0x1bf, 2572 .arl_bins = 4, 2573 .arl_buckets = 256, 2574 .imp_port = 8, 2575 .vta_regs = B53_VTA_REGS, 2576 .duplex_reg = B53_DUPLEX_STAT_GE, 2577 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2578 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2579 }, 2580 { 2581 .chip_id = BCM7445_DEVICE_ID, 2582 .dev_name = "BCM7445", 2583 .vlans = 4096, 2584 .enabled_ports = 0x1ff, 2585 .arl_bins = 4, 2586 .arl_buckets = 1024, 2587 .imp_port = 8, 2588 .vta_regs = B53_VTA_REGS, 2589 .duplex_reg = B53_DUPLEX_STAT_GE, 2590 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2591 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2592 }, 2593 { 2594 .chip_id = BCM7278_DEVICE_ID, 2595 .dev_name = "BCM7278", 2596 .vlans = 4096, 2597 .enabled_ports = 0x1ff, 2598 .arl_bins = 4, 2599 .arl_buckets = 256, 2600 .imp_port = 8, 2601 .vta_regs = B53_VTA_REGS, 2602 .duplex_reg = B53_DUPLEX_STAT_GE, 2603 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2604 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2605 }, 2606 { 2607 .chip_id = BCM53134_DEVICE_ID, 2608 .dev_name = "BCM53134", 2609 .vlans = 4096, 2610 .enabled_ports = 0x12f, 2611 .imp_port = 8, 2612 .cpu_port = B53_CPU_PORT, 2613 .vta_regs = B53_VTA_REGS, 2614 .arl_bins = 4, 2615 .arl_buckets = 1024, 2616 .duplex_reg = B53_DUPLEX_STAT_GE, 2617 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2618 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2619 }, 2620 }; 2621 2622 static int b53_switch_init(struct b53_device *dev) 2623 { 2624 unsigned int i; 2625 int ret; 2626 2627 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) { 2628 const struct b53_chip_data *chip = &b53_switch_chips[i]; 2629 2630 if (chip->chip_id == dev->chip_id) { 2631 if (!dev->enabled_ports) 2632 dev->enabled_ports = chip->enabled_ports; 2633 dev->name = chip->dev_name; 2634 dev->duplex_reg = chip->duplex_reg; 2635 dev->vta_regs[0] = chip->vta_regs[0]; 2636 dev->vta_regs[1] = chip->vta_regs[1]; 2637 dev->vta_regs[2] = chip->vta_regs[2]; 2638 dev->jumbo_pm_reg = chip->jumbo_pm_reg; 2639 dev->imp_port = chip->imp_port; 2640 dev->num_vlans = chip->vlans; 2641 dev->num_arl_bins = chip->arl_bins; 2642 dev->num_arl_buckets = chip->arl_buckets; 2643 break; 2644 } 2645 } 2646 2647 /* check which BCM5325x version we have */ 2648 if (is5325(dev)) { 2649 u8 vc4; 2650 2651 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 2652 2653 /* check reserved bits */ 2654 switch (vc4 & 3) { 2655 case 1: 2656 /* BCM5325E */ 2657 break; 2658 case 3: 2659 /* BCM5325F - do not use port 4 */ 2660 dev->enabled_ports &= ~BIT(4); 2661 break; 2662 default: 2663 /* On the BCM47XX SoCs this is the supported internal switch.*/ 2664 #ifndef CONFIG_BCM47XX 2665 /* BCM5325M */ 2666 return -EINVAL; 2667 #else 2668 break; 2669 #endif 2670 } 2671 } 2672 2673 dev->num_ports = fls(dev->enabled_ports); 2674 2675 dev->ds->num_ports = min_t(unsigned int, dev->num_ports, DSA_MAX_PORTS); 2676 2677 /* Include non standard CPU port built-in PHYs to be probed */ 2678 if (is539x(dev) || is531x5(dev)) { 2679 for (i = 0; i < dev->num_ports; i++) { 2680 if (!(dev->ds->phys_mii_mask & BIT(i)) && 2681 !b53_possible_cpu_port(dev->ds, i)) 2682 dev->ds->phys_mii_mask |= BIT(i); 2683 } 2684 } 2685 2686 dev->ports = devm_kcalloc(dev->dev, 2687 dev->num_ports, sizeof(struct b53_port), 2688 GFP_KERNEL); 2689 if (!dev->ports) 2690 return -ENOMEM; 2691 2692 dev->vlans = devm_kcalloc(dev->dev, 2693 dev->num_vlans, sizeof(struct b53_vlan), 2694 GFP_KERNEL); 2695 if (!dev->vlans) 2696 return -ENOMEM; 2697 2698 dev->reset_gpio = b53_switch_get_reset_gpio(dev); 2699 if (dev->reset_gpio >= 0) { 2700 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio, 2701 GPIOF_OUT_INIT_HIGH, "robo_reset"); 2702 if (ret) 2703 return ret; 2704 } 2705 2706 return 0; 2707 } 2708 2709 struct b53_device *b53_switch_alloc(struct device *base, 2710 const struct b53_io_ops *ops, 2711 void *priv) 2712 { 2713 struct dsa_switch *ds; 2714 struct b53_device *dev; 2715 2716 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 2717 if (!ds) 2718 return NULL; 2719 2720 ds->dev = base; 2721 2722 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL); 2723 if (!dev) 2724 return NULL; 2725 2726 ds->priv = dev; 2727 dev->dev = base; 2728 2729 dev->ds = ds; 2730 dev->priv = priv; 2731 dev->ops = ops; 2732 ds->ops = &b53_switch_ops; 2733 ds->phylink_mac_ops = &b53_phylink_mac_ops; 2734 dev->vlan_enabled = true; 2735 /* Let DSA handle the case were multiple bridges span the same switch 2736 * device and different VLAN awareness settings are requested, which 2737 * would be breaking filtering semantics for any of the other bridge 2738 * devices. (not hardware supported) 2739 */ 2740 ds->vlan_filtering_is_global = true; 2741 2742 mutex_init(&dev->reg_mutex); 2743 mutex_init(&dev->stats_mutex); 2744 mutex_init(&dev->arl_mutex); 2745 2746 return dev; 2747 } 2748 EXPORT_SYMBOL(b53_switch_alloc); 2749 2750 int b53_switch_detect(struct b53_device *dev) 2751 { 2752 u32 id32; 2753 u16 tmp; 2754 u8 id8; 2755 int ret; 2756 2757 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8); 2758 if (ret) 2759 return ret; 2760 2761 switch (id8) { 2762 case 0: 2763 /* BCM5325 and BCM5365 do not have this register so reads 2764 * return 0. But the read operation did succeed, so assume this 2765 * is one of them. 2766 * 2767 * Next check if we can write to the 5325's VTA register; for 2768 * 5365 it is read only. 2769 */ 2770 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf); 2771 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp); 2772 2773 if (tmp == 0xf) 2774 dev->chip_id = BCM5325_DEVICE_ID; 2775 else 2776 dev->chip_id = BCM5365_DEVICE_ID; 2777 break; 2778 case BCM5389_DEVICE_ID: 2779 case BCM5395_DEVICE_ID: 2780 case BCM5397_DEVICE_ID: 2781 case BCM5398_DEVICE_ID: 2782 dev->chip_id = id8; 2783 break; 2784 default: 2785 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32); 2786 if (ret) 2787 return ret; 2788 2789 switch (id32) { 2790 case BCM53115_DEVICE_ID: 2791 case BCM53125_DEVICE_ID: 2792 case BCM53128_DEVICE_ID: 2793 case BCM53010_DEVICE_ID: 2794 case BCM53011_DEVICE_ID: 2795 case BCM53012_DEVICE_ID: 2796 case BCM53018_DEVICE_ID: 2797 case BCM53019_DEVICE_ID: 2798 case BCM53134_DEVICE_ID: 2799 dev->chip_id = id32; 2800 break; 2801 default: 2802 dev_err(dev->dev, 2803 "unsupported switch detected (BCM53%02x/BCM%x)\n", 2804 id8, id32); 2805 return -ENODEV; 2806 } 2807 } 2808 2809 if (dev->chip_id == BCM5325_DEVICE_ID) 2810 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25, 2811 &dev->core_rev); 2812 else 2813 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID, 2814 &dev->core_rev); 2815 } 2816 EXPORT_SYMBOL(b53_switch_detect); 2817 2818 int b53_switch_register(struct b53_device *dev) 2819 { 2820 int ret; 2821 2822 if (dev->pdata) { 2823 dev->chip_id = dev->pdata->chip_id; 2824 dev->enabled_ports = dev->pdata->enabled_ports; 2825 } 2826 2827 if (!dev->chip_id && b53_switch_detect(dev)) 2828 return -EINVAL; 2829 2830 ret = b53_switch_init(dev); 2831 if (ret) 2832 return ret; 2833 2834 dev_info(dev->dev, "found switch: %s, rev %i\n", 2835 dev->name, dev->core_rev); 2836 2837 return dsa_register_switch(dev->ds); 2838 } 2839 EXPORT_SYMBOL(b53_switch_register); 2840 2841 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>"); 2842 MODULE_DESCRIPTION("B53 switch library"); 2843 MODULE_LICENSE("Dual BSD/GPL"); 2844