1 /* 2 * B53 switch driver main logic 3 * 4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org> 5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com> 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <linux/delay.h> 21 #include <linux/export.h> 22 #include <linux/gpio.h> 23 #include <linux/kernel.h> 24 #include <linux/math.h> 25 #include <linux/module.h> 26 #include <linux/platform_data/b53.h> 27 #include <linux/phy.h> 28 #include <linux/phylink.h> 29 #include <linux/etherdevice.h> 30 #include <linux/if_bridge.h> 31 #include <linux/if_vlan.h> 32 #include <net/dsa.h> 33 34 #include "b53_regs.h" 35 #include "b53_priv.h" 36 37 struct b53_mib_desc { 38 u8 size; 39 u8 offset; 40 const char *name; 41 }; 42 43 /* BCM5365 MIB counters */ 44 static const struct b53_mib_desc b53_mibs_65[] = { 45 { 8, 0x00, "TxOctets" }, 46 { 4, 0x08, "TxDropPkts" }, 47 { 4, 0x10, "TxBroadcastPkts" }, 48 { 4, 0x14, "TxMulticastPkts" }, 49 { 4, 0x18, "TxUnicastPkts" }, 50 { 4, 0x1c, "TxCollisions" }, 51 { 4, 0x20, "TxSingleCollision" }, 52 { 4, 0x24, "TxMultipleCollision" }, 53 { 4, 0x28, "TxDeferredTransmit" }, 54 { 4, 0x2c, "TxLateCollision" }, 55 { 4, 0x30, "TxExcessiveCollision" }, 56 { 4, 0x38, "TxPausePkts" }, 57 { 8, 0x44, "RxOctets" }, 58 { 4, 0x4c, "RxUndersizePkts" }, 59 { 4, 0x50, "RxPausePkts" }, 60 { 4, 0x54, "Pkts64Octets" }, 61 { 4, 0x58, "Pkts65to127Octets" }, 62 { 4, 0x5c, "Pkts128to255Octets" }, 63 { 4, 0x60, "Pkts256to511Octets" }, 64 { 4, 0x64, "Pkts512to1023Octets" }, 65 { 4, 0x68, "Pkts1024to1522Octets" }, 66 { 4, 0x6c, "RxOversizePkts" }, 67 { 4, 0x70, "RxJabbers" }, 68 { 4, 0x74, "RxAlignmentErrors" }, 69 { 4, 0x78, "RxFCSErrors" }, 70 { 8, 0x7c, "RxGoodOctets" }, 71 { 4, 0x84, "RxDropPkts" }, 72 { 4, 0x88, "RxUnicastPkts" }, 73 { 4, 0x8c, "RxMulticastPkts" }, 74 { 4, 0x90, "RxBroadcastPkts" }, 75 { 4, 0x94, "RxSAChanges" }, 76 { 4, 0x98, "RxFragments" }, 77 }; 78 79 #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65) 80 81 /* BCM63xx MIB counters */ 82 static const struct b53_mib_desc b53_mibs_63xx[] = { 83 { 8, 0x00, "TxOctets" }, 84 { 4, 0x08, "TxDropPkts" }, 85 { 4, 0x0c, "TxQoSPkts" }, 86 { 4, 0x10, "TxBroadcastPkts" }, 87 { 4, 0x14, "TxMulticastPkts" }, 88 { 4, 0x18, "TxUnicastPkts" }, 89 { 4, 0x1c, "TxCollisions" }, 90 { 4, 0x20, "TxSingleCollision" }, 91 { 4, 0x24, "TxMultipleCollision" }, 92 { 4, 0x28, "TxDeferredTransmit" }, 93 { 4, 0x2c, "TxLateCollision" }, 94 { 4, 0x30, "TxExcessiveCollision" }, 95 { 4, 0x38, "TxPausePkts" }, 96 { 8, 0x3c, "TxQoSOctets" }, 97 { 8, 0x44, "RxOctets" }, 98 { 4, 0x4c, "RxUndersizePkts" }, 99 { 4, 0x50, "RxPausePkts" }, 100 { 4, 0x54, "Pkts64Octets" }, 101 { 4, 0x58, "Pkts65to127Octets" }, 102 { 4, 0x5c, "Pkts128to255Octets" }, 103 { 4, 0x60, "Pkts256to511Octets" }, 104 { 4, 0x64, "Pkts512to1023Octets" }, 105 { 4, 0x68, "Pkts1024to1522Octets" }, 106 { 4, 0x6c, "RxOversizePkts" }, 107 { 4, 0x70, "RxJabbers" }, 108 { 4, 0x74, "RxAlignmentErrors" }, 109 { 4, 0x78, "RxFCSErrors" }, 110 { 8, 0x7c, "RxGoodOctets" }, 111 { 4, 0x84, "RxDropPkts" }, 112 { 4, 0x88, "RxUnicastPkts" }, 113 { 4, 0x8c, "RxMulticastPkts" }, 114 { 4, 0x90, "RxBroadcastPkts" }, 115 { 4, 0x94, "RxSAChanges" }, 116 { 4, 0x98, "RxFragments" }, 117 { 4, 0xa0, "RxSymbolErrors" }, 118 { 4, 0xa4, "RxQoSPkts" }, 119 { 8, 0xa8, "RxQoSOctets" }, 120 { 4, 0xb0, "Pkts1523to2047Octets" }, 121 { 4, 0xb4, "Pkts2048to4095Octets" }, 122 { 4, 0xb8, "Pkts4096to8191Octets" }, 123 { 4, 0xbc, "Pkts8192to9728Octets" }, 124 { 4, 0xc0, "RxDiscarded" }, 125 }; 126 127 #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx) 128 129 /* MIB counters */ 130 static const struct b53_mib_desc b53_mibs[] = { 131 { 8, 0x00, "TxOctets" }, 132 { 4, 0x08, "TxDropPkts" }, 133 { 4, 0x10, "TxBroadcastPkts" }, 134 { 4, 0x14, "TxMulticastPkts" }, 135 { 4, 0x18, "TxUnicastPkts" }, 136 { 4, 0x1c, "TxCollisions" }, 137 { 4, 0x20, "TxSingleCollision" }, 138 { 4, 0x24, "TxMultipleCollision" }, 139 { 4, 0x28, "TxDeferredTransmit" }, 140 { 4, 0x2c, "TxLateCollision" }, 141 { 4, 0x30, "TxExcessiveCollision" }, 142 { 4, 0x38, "TxPausePkts" }, 143 { 8, 0x50, "RxOctets" }, 144 { 4, 0x58, "RxUndersizePkts" }, 145 { 4, 0x5c, "RxPausePkts" }, 146 { 4, 0x60, "Pkts64Octets" }, 147 { 4, 0x64, "Pkts65to127Octets" }, 148 { 4, 0x68, "Pkts128to255Octets" }, 149 { 4, 0x6c, "Pkts256to511Octets" }, 150 { 4, 0x70, "Pkts512to1023Octets" }, 151 { 4, 0x74, "Pkts1024to1522Octets" }, 152 { 4, 0x78, "RxOversizePkts" }, 153 { 4, 0x7c, "RxJabbers" }, 154 { 4, 0x80, "RxAlignmentErrors" }, 155 { 4, 0x84, "RxFCSErrors" }, 156 { 8, 0x88, "RxGoodOctets" }, 157 { 4, 0x90, "RxDropPkts" }, 158 { 4, 0x94, "RxUnicastPkts" }, 159 { 4, 0x98, "RxMulticastPkts" }, 160 { 4, 0x9c, "RxBroadcastPkts" }, 161 { 4, 0xa0, "RxSAChanges" }, 162 { 4, 0xa4, "RxFragments" }, 163 { 4, 0xa8, "RxJumboPkts" }, 164 { 4, 0xac, "RxSymbolErrors" }, 165 { 4, 0xc0, "RxDiscarded" }, 166 }; 167 168 #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs) 169 170 static const struct b53_mib_desc b53_mibs_58xx[] = { 171 { 8, 0x00, "TxOctets" }, 172 { 4, 0x08, "TxDropPkts" }, 173 { 4, 0x0c, "TxQPKTQ0" }, 174 { 4, 0x10, "TxBroadcastPkts" }, 175 { 4, 0x14, "TxMulticastPkts" }, 176 { 4, 0x18, "TxUnicastPKts" }, 177 { 4, 0x1c, "TxCollisions" }, 178 { 4, 0x20, "TxSingleCollision" }, 179 { 4, 0x24, "TxMultipleCollision" }, 180 { 4, 0x28, "TxDeferredCollision" }, 181 { 4, 0x2c, "TxLateCollision" }, 182 { 4, 0x30, "TxExcessiveCollision" }, 183 { 4, 0x34, "TxFrameInDisc" }, 184 { 4, 0x38, "TxPausePkts" }, 185 { 4, 0x3c, "TxQPKTQ1" }, 186 { 4, 0x40, "TxQPKTQ2" }, 187 { 4, 0x44, "TxQPKTQ3" }, 188 { 4, 0x48, "TxQPKTQ4" }, 189 { 4, 0x4c, "TxQPKTQ5" }, 190 { 8, 0x50, "RxOctets" }, 191 { 4, 0x58, "RxUndersizePkts" }, 192 { 4, 0x5c, "RxPausePkts" }, 193 { 4, 0x60, "RxPkts64Octets" }, 194 { 4, 0x64, "RxPkts65to127Octets" }, 195 { 4, 0x68, "RxPkts128to255Octets" }, 196 { 4, 0x6c, "RxPkts256to511Octets" }, 197 { 4, 0x70, "RxPkts512to1023Octets" }, 198 { 4, 0x74, "RxPkts1024toMaxPktsOctets" }, 199 { 4, 0x78, "RxOversizePkts" }, 200 { 4, 0x7c, "RxJabbers" }, 201 { 4, 0x80, "RxAlignmentErrors" }, 202 { 4, 0x84, "RxFCSErrors" }, 203 { 8, 0x88, "RxGoodOctets" }, 204 { 4, 0x90, "RxDropPkts" }, 205 { 4, 0x94, "RxUnicastPkts" }, 206 { 4, 0x98, "RxMulticastPkts" }, 207 { 4, 0x9c, "RxBroadcastPkts" }, 208 { 4, 0xa0, "RxSAChanges" }, 209 { 4, 0xa4, "RxFragments" }, 210 { 4, 0xa8, "RxJumboPkt" }, 211 { 4, 0xac, "RxSymblErr" }, 212 { 4, 0xb0, "InRangeErrCount" }, 213 { 4, 0xb4, "OutRangeErrCount" }, 214 { 4, 0xb8, "EEELpiEvent" }, 215 { 4, 0xbc, "EEELpiDuration" }, 216 { 4, 0xc0, "RxDiscard" }, 217 { 4, 0xc8, "TxQPKTQ6" }, 218 { 4, 0xcc, "TxQPKTQ7" }, 219 { 4, 0xd0, "TxPkts64Octets" }, 220 { 4, 0xd4, "TxPkts65to127Octets" }, 221 { 4, 0xd8, "TxPkts128to255Octets" }, 222 { 4, 0xdc, "TxPkts256to511Ocets" }, 223 { 4, 0xe0, "TxPkts512to1023Ocets" }, 224 { 4, 0xe4, "TxPkts1024toMaxPktOcets" }, 225 }; 226 227 #define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx) 228 229 #define B53_MAX_MTU_25 (1536 - ETH_HLEN - VLAN_HLEN - ETH_FCS_LEN) 230 #define B53_MAX_MTU (9720 - ETH_HLEN - VLAN_HLEN - ETH_FCS_LEN) 231 232 static int b53_do_vlan_op(struct b53_device *dev, u8 op) 233 { 234 unsigned int i; 235 236 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op); 237 238 for (i = 0; i < 10; i++) { 239 u8 vta; 240 241 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta); 242 if (!(vta & VTA_START_CMD)) 243 return 0; 244 245 usleep_range(100, 200); 246 } 247 248 return -EIO; 249 } 250 251 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, 252 struct b53_vlan *vlan) 253 { 254 if (is5325(dev)) { 255 u32 entry = 0; 256 257 if (vlan->members) { 258 entry = ((vlan->untag & VA_UNTAG_MASK_25) << 259 VA_UNTAG_S_25) | vlan->members; 260 if (dev->core_rev >= 3) 261 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S; 262 else 263 entry |= VA_VALID_25; 264 } 265 266 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry); 267 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 268 VTA_RW_STATE_WR | VTA_RW_OP_EN); 269 } else if (is5365(dev)) { 270 u16 entry = 0; 271 272 if (vlan->members) 273 entry = ((vlan->untag & VA_UNTAG_MASK_65) << 274 VA_UNTAG_S_65) | vlan->members | VA_VALID_65; 275 276 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry); 277 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 278 VTA_RW_STATE_WR | VTA_RW_OP_EN); 279 } else { 280 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 281 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], 282 (vlan->untag << VTE_UNTAG_S) | vlan->members); 283 284 b53_do_vlan_op(dev, VTA_CMD_WRITE); 285 } 286 287 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n", 288 vid, vlan->members, vlan->untag); 289 } 290 291 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid, 292 struct b53_vlan *vlan) 293 { 294 if (is5325(dev)) { 295 u32 entry = 0; 296 297 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 298 VTA_RW_STATE_RD | VTA_RW_OP_EN); 299 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry); 300 301 if (dev->core_rev >= 3) 302 vlan->valid = !!(entry & VA_VALID_25_R4); 303 else 304 vlan->valid = !!(entry & VA_VALID_25); 305 vlan->members = entry & VA_MEMBER_MASK; 306 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25; 307 308 } else if (is5365(dev)) { 309 u16 entry = 0; 310 311 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 312 VTA_RW_STATE_WR | VTA_RW_OP_EN); 313 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry); 314 315 vlan->valid = !!(entry & VA_VALID_65); 316 vlan->members = entry & VA_MEMBER_MASK; 317 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65; 318 } else { 319 u32 entry = 0; 320 321 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 322 b53_do_vlan_op(dev, VTA_CMD_READ); 323 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry); 324 vlan->members = entry & VTE_MEMBERS; 325 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS; 326 vlan->valid = true; 327 } 328 } 329 330 static void b53_set_eap_mode(struct b53_device *dev, int port, int mode) 331 { 332 u64 eap_conf; 333 334 if (is5325(dev) || is5365(dev) || dev->chip_id == BCM5389_DEVICE_ID) 335 return; 336 337 b53_read64(dev, B53_EAP_PAGE, B53_PORT_EAP_CONF(port), &eap_conf); 338 339 if (is63xx(dev)) { 340 eap_conf &= ~EAP_MODE_MASK_63XX; 341 eap_conf |= (u64)mode << EAP_MODE_SHIFT_63XX; 342 } else { 343 eap_conf &= ~EAP_MODE_MASK; 344 eap_conf |= (u64)mode << EAP_MODE_SHIFT; 345 } 346 347 b53_write64(dev, B53_EAP_PAGE, B53_PORT_EAP_CONF(port), eap_conf); 348 } 349 350 static void b53_set_forwarding(struct b53_device *dev, int enable) 351 { 352 u8 mgmt; 353 354 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 355 356 if (enable) 357 mgmt |= SM_SW_FWD_EN; 358 else 359 mgmt &= ~SM_SW_FWD_EN; 360 361 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 362 363 /* Include IMP port in dumb forwarding mode 364 */ 365 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt); 366 mgmt |= B53_MII_DUMB_FWDG_EN; 367 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt); 368 369 /* Look at B53_UC_FWD_EN and B53_MC_FWD_EN to decide whether 370 * frames should be flooded or not. 371 */ 372 b53_read8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, &mgmt); 373 mgmt |= B53_UC_FWD_EN | B53_MC_FWD_EN | B53_IPMC_FWD_EN; 374 b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt); 375 } 376 377 static void b53_enable_vlan(struct b53_device *dev, int port, bool enable, 378 bool enable_filtering) 379 { 380 u8 mgmt, vc0, vc1, vc4 = 0, vc5; 381 382 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 383 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0); 384 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1); 385 386 if (is5325(dev) || is5365(dev)) { 387 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 388 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5); 389 } else if (is63xx(dev)) { 390 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4); 391 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5); 392 } else { 393 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4); 394 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5); 395 } 396 397 vc1 &= ~VC1_RX_MCST_FWD_EN; 398 399 if (enable) { 400 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID; 401 vc1 |= VC1_RX_MCST_UNTAG_EN; 402 vc4 &= ~VC4_ING_VID_CHECK_MASK; 403 if (enable_filtering) { 404 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S; 405 vc5 |= VC5_DROP_VTABLE_MISS; 406 } else { 407 vc4 |= VC4_NO_ING_VID_CHK << VC4_ING_VID_CHECK_S; 408 vc5 &= ~VC5_DROP_VTABLE_MISS; 409 } 410 411 if (is5325(dev)) 412 vc0 &= ~VC0_RESERVED_1; 413 414 if (is5325(dev) || is5365(dev)) 415 vc1 |= VC1_RX_MCST_TAG_EN; 416 417 } else { 418 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID); 419 vc1 &= ~VC1_RX_MCST_UNTAG_EN; 420 vc4 &= ~VC4_ING_VID_CHECK_MASK; 421 vc5 &= ~VC5_DROP_VTABLE_MISS; 422 423 if (is5325(dev) || is5365(dev)) 424 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 425 else 426 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S; 427 428 if (is5325(dev) || is5365(dev)) 429 vc1 &= ~VC1_RX_MCST_TAG_EN; 430 } 431 432 if (!is5325(dev) && !is5365(dev)) 433 vc5 &= ~VC5_VID_FFF_EN; 434 435 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0); 436 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1); 437 438 if (is5325(dev) || is5365(dev)) { 439 /* enable the high 8 bit vid check on 5325 */ 440 if (is5325(dev) && enable) 441 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 442 VC3_HIGH_8BIT_EN); 443 else 444 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 445 446 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4); 447 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5); 448 } else if (is63xx(dev)) { 449 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0); 450 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4); 451 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5); 452 } else { 453 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 454 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4); 455 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5); 456 } 457 458 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 459 460 dev->vlan_enabled = enable; 461 462 dev_dbg(dev->dev, "Port %d VLAN enabled: %d, filtering: %d\n", 463 port, enable, enable_filtering); 464 } 465 466 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100) 467 { 468 u32 port_mask = 0; 469 u16 max_size = JMS_MIN_SIZE; 470 471 if (is5325(dev) || is5365(dev)) 472 return -EINVAL; 473 474 if (enable) { 475 port_mask = dev->enabled_ports; 476 max_size = JMS_MAX_SIZE; 477 if (allow_10_100) 478 port_mask |= JPM_10_100_JUMBO_EN; 479 } 480 481 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask); 482 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size); 483 } 484 485 static int b53_flush_arl(struct b53_device *dev, u8 mask) 486 { 487 unsigned int i; 488 489 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 490 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask); 491 492 for (i = 0; i < 10; i++) { 493 u8 fast_age_ctrl; 494 495 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 496 &fast_age_ctrl); 497 498 if (!(fast_age_ctrl & FAST_AGE_DONE)) 499 goto out; 500 501 msleep(1); 502 } 503 504 return -ETIMEDOUT; 505 out: 506 /* Only age dynamic entries (default behavior) */ 507 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC); 508 return 0; 509 } 510 511 static int b53_fast_age_port(struct b53_device *dev, int port) 512 { 513 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port); 514 515 return b53_flush_arl(dev, FAST_AGE_PORT); 516 } 517 518 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid) 519 { 520 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid); 521 522 return b53_flush_arl(dev, FAST_AGE_VLAN); 523 } 524 525 void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port) 526 { 527 struct b53_device *dev = ds->priv; 528 unsigned int i; 529 u16 pvlan; 530 531 /* Enable the IMP port to be in the same VLAN as the other ports 532 * on a per-port basis such that we only have Port i and IMP in 533 * the same VLAN. 534 */ 535 b53_for_each_port(dev, i) { 536 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan); 537 pvlan |= BIT(cpu_port); 538 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan); 539 } 540 } 541 EXPORT_SYMBOL(b53_imp_vlan_setup); 542 543 static void b53_port_set_ucast_flood(struct b53_device *dev, int port, 544 bool unicast) 545 { 546 u16 uc; 547 548 b53_read16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, &uc); 549 if (unicast) 550 uc |= BIT(port); 551 else 552 uc &= ~BIT(port); 553 b53_write16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, uc); 554 } 555 556 static void b53_port_set_mcast_flood(struct b53_device *dev, int port, 557 bool multicast) 558 { 559 u16 mc; 560 561 b53_read16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, &mc); 562 if (multicast) 563 mc |= BIT(port); 564 else 565 mc &= ~BIT(port); 566 b53_write16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, mc); 567 568 b53_read16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, &mc); 569 if (multicast) 570 mc |= BIT(port); 571 else 572 mc &= ~BIT(port); 573 b53_write16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, mc); 574 } 575 576 static void b53_port_set_learning(struct b53_device *dev, int port, 577 bool learning) 578 { 579 u16 reg; 580 581 b53_read16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, ®); 582 if (learning) 583 reg &= ~BIT(port); 584 else 585 reg |= BIT(port); 586 b53_write16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, reg); 587 } 588 589 static void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable) 590 { 591 struct b53_device *dev = ds->priv; 592 u16 reg; 593 594 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, ®); 595 if (enable) 596 reg |= BIT(port); 597 else 598 reg &= ~BIT(port); 599 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg); 600 } 601 602 int b53_setup_port(struct dsa_switch *ds, int port) 603 { 604 struct b53_device *dev = ds->priv; 605 606 b53_port_set_ucast_flood(dev, port, true); 607 b53_port_set_mcast_flood(dev, port, true); 608 b53_port_set_learning(dev, port, false); 609 610 /* Force all traffic to go to the CPU port to prevent the ASIC from 611 * trying to forward to bridged ports on matching FDB entries, then 612 * dropping frames because it isn't allowed to forward there. 613 */ 614 if (dsa_is_user_port(ds, port)) 615 b53_set_eap_mode(dev, port, EAP_MODE_SIMPLIFIED); 616 617 return 0; 618 } 619 EXPORT_SYMBOL(b53_setup_port); 620 621 int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy) 622 { 623 struct b53_device *dev = ds->priv; 624 unsigned int cpu_port; 625 int ret = 0; 626 u16 pvlan; 627 628 if (!dsa_is_user_port(ds, port)) 629 return 0; 630 631 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 632 633 if (dev->ops->irq_enable) 634 ret = dev->ops->irq_enable(dev, port); 635 if (ret) 636 return ret; 637 638 /* Clear the Rx and Tx disable bits and set to no spanning tree */ 639 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0); 640 641 /* Set this port, and only this one to be in the default VLAN, 642 * if member of a bridge, restore its membership prior to 643 * bringing down this port. 644 */ 645 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 646 pvlan &= ~0x1ff; 647 pvlan |= BIT(port); 648 pvlan |= dev->ports[port].vlan_ctl_mask; 649 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 650 651 b53_imp_vlan_setup(ds, cpu_port); 652 653 /* If EEE was enabled, restore it */ 654 if (dev->ports[port].eee.eee_enabled) 655 b53_eee_enable_set(ds, port, true); 656 657 return 0; 658 } 659 EXPORT_SYMBOL(b53_enable_port); 660 661 void b53_disable_port(struct dsa_switch *ds, int port) 662 { 663 struct b53_device *dev = ds->priv; 664 u8 reg; 665 666 /* Disable Tx/Rx for the port */ 667 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 668 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE; 669 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 670 671 if (dev->ops->irq_disable) 672 dev->ops->irq_disable(dev, port); 673 } 674 EXPORT_SYMBOL(b53_disable_port); 675 676 void b53_brcm_hdr_setup(struct dsa_switch *ds, int port) 677 { 678 struct b53_device *dev = ds->priv; 679 bool tag_en = !(dev->tag_protocol == DSA_TAG_PROTO_NONE); 680 u8 hdr_ctl, val; 681 u16 reg; 682 683 /* Resolve which bit controls the Broadcom tag */ 684 switch (port) { 685 case 8: 686 val = BRCM_HDR_P8_EN; 687 break; 688 case 7: 689 val = BRCM_HDR_P7_EN; 690 break; 691 case 5: 692 val = BRCM_HDR_P5_EN; 693 break; 694 default: 695 val = 0; 696 break; 697 } 698 699 /* Enable management mode if tagging is requested */ 700 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &hdr_ctl); 701 if (tag_en) 702 hdr_ctl |= SM_SW_FWD_MODE; 703 else 704 hdr_ctl &= ~SM_SW_FWD_MODE; 705 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, hdr_ctl); 706 707 /* Configure the appropriate IMP port */ 708 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &hdr_ctl); 709 if (port == 8) 710 hdr_ctl |= GC_FRM_MGMT_PORT_MII; 711 else if (port == 5) 712 hdr_ctl |= GC_FRM_MGMT_PORT_M; 713 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, hdr_ctl); 714 715 /* Enable Broadcom tags for IMP port */ 716 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl); 717 if (tag_en) 718 hdr_ctl |= val; 719 else 720 hdr_ctl &= ~val; 721 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl); 722 723 /* Registers below are only accessible on newer devices */ 724 if (!is58xx(dev)) 725 return; 726 727 /* Enable reception Broadcom tag for CPU TX (switch RX) to 728 * allow us to tag outgoing frames 729 */ 730 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, ®); 731 if (tag_en) 732 reg &= ~BIT(port); 733 else 734 reg |= BIT(port); 735 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg); 736 737 /* Enable transmission of Broadcom tags from the switch (CPU RX) to 738 * allow delivering frames to the per-port net_devices 739 */ 740 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, ®); 741 if (tag_en) 742 reg &= ~BIT(port); 743 else 744 reg |= BIT(port); 745 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg); 746 } 747 EXPORT_SYMBOL(b53_brcm_hdr_setup); 748 749 static void b53_enable_cpu_port(struct b53_device *dev, int port) 750 { 751 u8 port_ctrl; 752 753 /* BCM5325 CPU port is at 8 */ 754 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25) 755 port = B53_CPU_PORT; 756 757 port_ctrl = PORT_CTRL_RX_BCST_EN | 758 PORT_CTRL_RX_MCST_EN | 759 PORT_CTRL_RX_UCST_EN; 760 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl); 761 762 b53_brcm_hdr_setup(dev->ds, port); 763 } 764 765 static void b53_enable_mib(struct b53_device *dev) 766 { 767 u8 gc; 768 769 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 770 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN); 771 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc); 772 } 773 774 static void b53_enable_stp(struct b53_device *dev) 775 { 776 u8 gc; 777 778 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 779 gc |= GC_RX_BPDU_EN; 780 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc); 781 } 782 783 static u16 b53_default_pvid(struct b53_device *dev) 784 { 785 if (is5325(dev) || is5365(dev)) 786 return 1; 787 else 788 return 0; 789 } 790 791 static bool b53_vlan_port_needs_forced_tagged(struct dsa_switch *ds, int port) 792 { 793 struct b53_device *dev = ds->priv; 794 795 return dev->tag_protocol == DSA_TAG_PROTO_NONE && dsa_is_cpu_port(ds, port); 796 } 797 798 static bool b53_vlan_port_may_join_untagged(struct dsa_switch *ds, int port) 799 { 800 struct b53_device *dev = ds->priv; 801 struct dsa_port *dp; 802 803 if (!dev->vlan_filtering) 804 return true; 805 806 dp = dsa_to_port(ds, port); 807 808 if (dsa_port_is_cpu(dp)) 809 return true; 810 811 return dp->bridge == NULL; 812 } 813 814 int b53_configure_vlan(struct dsa_switch *ds) 815 { 816 struct b53_device *dev = ds->priv; 817 struct b53_vlan vl = { 0 }; 818 struct b53_vlan *v; 819 int i, def_vid; 820 u16 vid; 821 822 def_vid = b53_default_pvid(dev); 823 824 /* clear all vlan entries */ 825 if (is5325(dev) || is5365(dev)) { 826 for (i = def_vid; i < dev->num_vlans; i++) 827 b53_set_vlan_entry(dev, i, &vl); 828 } else { 829 b53_do_vlan_op(dev, VTA_CMD_CLEAR); 830 } 831 832 b53_enable_vlan(dev, -1, dev->vlan_enabled, dev->vlan_filtering); 833 834 /* Create an untagged VLAN entry for the default PVID in case 835 * CONFIG_VLAN_8021Q is disabled and there are no calls to 836 * dsa_user_vlan_rx_add_vid() to create the default VLAN 837 * entry. Do this only when the tagging protocol is not 838 * DSA_TAG_PROTO_NONE 839 */ 840 v = &dev->vlans[def_vid]; 841 b53_for_each_port(dev, i) { 842 if (!b53_vlan_port_may_join_untagged(ds, i)) 843 continue; 844 845 vl.members |= BIT(i); 846 if (!b53_vlan_port_needs_forced_tagged(ds, i)) 847 vl.untag = vl.members; 848 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(i), 849 def_vid); 850 } 851 b53_set_vlan_entry(dev, def_vid, &vl); 852 853 if (dev->vlan_filtering) { 854 /* Upon initial call we have not set-up any VLANs, but upon 855 * system resume, we need to restore all VLAN entries. 856 */ 857 for (vid = def_vid + 1; vid < dev->num_vlans; vid++) { 858 v = &dev->vlans[vid]; 859 860 if (!v->members) 861 continue; 862 863 b53_set_vlan_entry(dev, vid, v); 864 b53_fast_age_vlan(dev, vid); 865 } 866 867 b53_for_each_port(dev, i) { 868 if (!dsa_is_cpu_port(ds, i)) 869 b53_write16(dev, B53_VLAN_PAGE, 870 B53_VLAN_PORT_DEF_TAG(i), 871 dev->ports[i].pvid); 872 } 873 } 874 875 return 0; 876 } 877 EXPORT_SYMBOL(b53_configure_vlan); 878 879 static void b53_switch_reset_gpio(struct b53_device *dev) 880 { 881 int gpio = dev->reset_gpio; 882 883 if (gpio < 0) 884 return; 885 886 /* Reset sequence: RESET low(50ms)->high(20ms) 887 */ 888 gpio_set_value(gpio, 0); 889 mdelay(50); 890 891 gpio_set_value(gpio, 1); 892 mdelay(20); 893 894 dev->current_page = 0xff; 895 } 896 897 static int b53_switch_reset(struct b53_device *dev) 898 { 899 unsigned int timeout = 1000; 900 u8 mgmt, reg; 901 902 b53_switch_reset_gpio(dev); 903 904 if (is539x(dev)) { 905 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83); 906 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00); 907 } 908 909 /* This is specific to 58xx devices here, do not use is58xx() which 910 * covers the larger Starfigther 2 family, including 7445/7278 which 911 * still use this driver as a library and need to perform the reset 912 * earlier. 913 */ 914 if (dev->chip_id == BCM58XX_DEVICE_ID || 915 dev->chip_id == BCM583XX_DEVICE_ID) { 916 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 917 reg |= SW_RST | EN_SW_RST | EN_CH_RST; 918 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg); 919 920 do { 921 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 922 if (!(reg & SW_RST)) 923 break; 924 925 usleep_range(1000, 2000); 926 } while (timeout-- > 0); 927 928 if (timeout == 0) { 929 dev_err(dev->dev, 930 "Timeout waiting for SW_RST to clear!\n"); 931 return -ETIMEDOUT; 932 } 933 } 934 935 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 936 937 if (!(mgmt & SM_SW_FWD_EN)) { 938 mgmt &= ~SM_SW_FWD_MODE; 939 mgmt |= SM_SW_FWD_EN; 940 941 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 942 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 943 944 if (!(mgmt & SM_SW_FWD_EN)) { 945 dev_err(dev->dev, "Failed to enable switch!\n"); 946 return -EINVAL; 947 } 948 } 949 950 b53_enable_mib(dev); 951 b53_enable_stp(dev); 952 953 return b53_flush_arl(dev, FAST_AGE_STATIC); 954 } 955 956 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg) 957 { 958 struct b53_device *priv = ds->priv; 959 u16 value = 0; 960 int ret; 961 962 if (priv->ops->phy_read16) 963 ret = priv->ops->phy_read16(priv, addr, reg, &value); 964 else 965 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr), 966 reg * 2, &value); 967 968 return ret ? ret : value; 969 } 970 971 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 972 { 973 struct b53_device *priv = ds->priv; 974 975 if (priv->ops->phy_write16) 976 return priv->ops->phy_write16(priv, addr, reg, val); 977 978 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val); 979 } 980 981 static int b53_reset_switch(struct b53_device *priv) 982 { 983 /* reset vlans */ 984 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans); 985 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports); 986 987 priv->serdes_lane = B53_INVALID_LANE; 988 989 return b53_switch_reset(priv); 990 } 991 992 static int b53_apply_config(struct b53_device *priv) 993 { 994 /* disable switching */ 995 b53_set_forwarding(priv, 0); 996 997 b53_configure_vlan(priv->ds); 998 999 /* enable switching */ 1000 b53_set_forwarding(priv, 1); 1001 1002 return 0; 1003 } 1004 1005 static void b53_reset_mib(struct b53_device *priv) 1006 { 1007 u8 gc; 1008 1009 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 1010 1011 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB); 1012 msleep(1); 1013 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB); 1014 msleep(1); 1015 } 1016 1017 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev) 1018 { 1019 if (is5365(dev)) 1020 return b53_mibs_65; 1021 else if (is63xx(dev)) 1022 return b53_mibs_63xx; 1023 else if (is58xx(dev)) 1024 return b53_mibs_58xx; 1025 else 1026 return b53_mibs; 1027 } 1028 1029 static unsigned int b53_get_mib_size(struct b53_device *dev) 1030 { 1031 if (is5365(dev)) 1032 return B53_MIBS_65_SIZE; 1033 else if (is63xx(dev)) 1034 return B53_MIBS_63XX_SIZE; 1035 else if (is58xx(dev)) 1036 return B53_MIBS_58XX_SIZE; 1037 else 1038 return B53_MIBS_SIZE; 1039 } 1040 1041 static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port) 1042 { 1043 /* These ports typically do not have built-in PHYs */ 1044 switch (port) { 1045 case B53_CPU_PORT_25: 1046 case 7: 1047 case B53_CPU_PORT: 1048 return NULL; 1049 } 1050 1051 return mdiobus_get_phy(ds->user_mii_bus, port); 1052 } 1053 1054 void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset, 1055 uint8_t *data) 1056 { 1057 struct b53_device *dev = ds->priv; 1058 const struct b53_mib_desc *mibs = b53_get_mib(dev); 1059 unsigned int mib_size = b53_get_mib_size(dev); 1060 struct phy_device *phydev; 1061 unsigned int i; 1062 1063 if (stringset == ETH_SS_STATS) { 1064 for (i = 0; i < mib_size; i++) 1065 ethtool_puts(&data, mibs[i].name); 1066 } else if (stringset == ETH_SS_PHY_STATS) { 1067 phydev = b53_get_phy_device(ds, port); 1068 if (!phydev) 1069 return; 1070 1071 phy_ethtool_get_strings(phydev, data); 1072 } 1073 } 1074 EXPORT_SYMBOL(b53_get_strings); 1075 1076 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) 1077 { 1078 struct b53_device *dev = ds->priv; 1079 const struct b53_mib_desc *mibs = b53_get_mib(dev); 1080 unsigned int mib_size = b53_get_mib_size(dev); 1081 const struct b53_mib_desc *s; 1082 unsigned int i; 1083 u64 val = 0; 1084 1085 if (is5365(dev) && port == 5) 1086 port = 8; 1087 1088 mutex_lock(&dev->stats_mutex); 1089 1090 for (i = 0; i < mib_size; i++) { 1091 s = &mibs[i]; 1092 1093 if (s->size == 8) { 1094 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val); 1095 } else { 1096 u32 val32; 1097 1098 b53_read32(dev, B53_MIB_PAGE(port), s->offset, 1099 &val32); 1100 val = val32; 1101 } 1102 data[i] = (u64)val; 1103 } 1104 1105 mutex_unlock(&dev->stats_mutex); 1106 } 1107 EXPORT_SYMBOL(b53_get_ethtool_stats); 1108 1109 void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data) 1110 { 1111 struct phy_device *phydev; 1112 1113 phydev = b53_get_phy_device(ds, port); 1114 if (!phydev) 1115 return; 1116 1117 phy_ethtool_get_stats(phydev, NULL, data); 1118 } 1119 EXPORT_SYMBOL(b53_get_ethtool_phy_stats); 1120 1121 int b53_get_sset_count(struct dsa_switch *ds, int port, int sset) 1122 { 1123 struct b53_device *dev = ds->priv; 1124 struct phy_device *phydev; 1125 1126 if (sset == ETH_SS_STATS) { 1127 return b53_get_mib_size(dev); 1128 } else if (sset == ETH_SS_PHY_STATS) { 1129 phydev = b53_get_phy_device(ds, port); 1130 if (!phydev) 1131 return 0; 1132 1133 return phy_ethtool_get_sset_count(phydev); 1134 } 1135 1136 return 0; 1137 } 1138 EXPORT_SYMBOL(b53_get_sset_count); 1139 1140 enum b53_devlink_resource_id { 1141 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1142 }; 1143 1144 static u64 b53_devlink_vlan_table_get(void *priv) 1145 { 1146 struct b53_device *dev = priv; 1147 struct b53_vlan *vl; 1148 unsigned int i; 1149 u64 count = 0; 1150 1151 for (i = 0; i < dev->num_vlans; i++) { 1152 vl = &dev->vlans[i]; 1153 if (vl->members) 1154 count++; 1155 } 1156 1157 return count; 1158 } 1159 1160 int b53_setup_devlink_resources(struct dsa_switch *ds) 1161 { 1162 struct devlink_resource_size_params size_params; 1163 struct b53_device *dev = ds->priv; 1164 int err; 1165 1166 devlink_resource_size_params_init(&size_params, dev->num_vlans, 1167 dev->num_vlans, 1168 1, DEVLINK_RESOURCE_UNIT_ENTRY); 1169 1170 err = dsa_devlink_resource_register(ds, "VLAN", dev->num_vlans, 1171 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1172 DEVLINK_RESOURCE_ID_PARENT_TOP, 1173 &size_params); 1174 if (err) 1175 goto out; 1176 1177 dsa_devlink_resource_occ_get_register(ds, 1178 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1179 b53_devlink_vlan_table_get, dev); 1180 1181 return 0; 1182 out: 1183 dsa_devlink_resources_unregister(ds); 1184 return err; 1185 } 1186 EXPORT_SYMBOL(b53_setup_devlink_resources); 1187 1188 static int b53_setup(struct dsa_switch *ds) 1189 { 1190 struct b53_device *dev = ds->priv; 1191 struct b53_vlan *vl; 1192 unsigned int port; 1193 u16 pvid; 1194 int ret; 1195 1196 /* Request bridge PVID untagged when DSA_TAG_PROTO_NONE is set 1197 * which forces the CPU port to be tagged in all VLANs. 1198 */ 1199 ds->untag_bridge_pvid = dev->tag_protocol == DSA_TAG_PROTO_NONE; 1200 1201 /* The switch does not tell us the original VLAN for untagged 1202 * packets, so keep the CPU port always tagged. 1203 */ 1204 ds->untag_vlan_aware_bridge_pvid = true; 1205 1206 /* Ageing time is set in seconds */ 1207 ds->ageing_time_min = 1 * 1000; 1208 ds->ageing_time_max = AGE_TIME_MAX * 1000; 1209 1210 ret = b53_reset_switch(dev); 1211 if (ret) { 1212 dev_err(ds->dev, "failed to reset switch\n"); 1213 return ret; 1214 } 1215 1216 /* setup default vlan for filtering mode */ 1217 pvid = b53_default_pvid(dev); 1218 vl = &dev->vlans[pvid]; 1219 b53_for_each_port(dev, port) { 1220 vl->members |= BIT(port); 1221 if (!b53_vlan_port_needs_forced_tagged(ds, port)) 1222 vl->untag |= BIT(port); 1223 } 1224 1225 b53_reset_mib(dev); 1226 1227 ret = b53_apply_config(dev); 1228 if (ret) { 1229 dev_err(ds->dev, "failed to apply configuration\n"); 1230 return ret; 1231 } 1232 1233 /* Configure IMP/CPU port, disable all other ports. Enabled 1234 * ports will be configured with .port_enable 1235 */ 1236 for (port = 0; port < dev->num_ports; port++) { 1237 if (dsa_is_cpu_port(ds, port)) 1238 b53_enable_cpu_port(dev, port); 1239 else 1240 b53_disable_port(ds, port); 1241 } 1242 1243 return b53_setup_devlink_resources(ds); 1244 } 1245 1246 static void b53_teardown(struct dsa_switch *ds) 1247 { 1248 dsa_devlink_resources_unregister(ds); 1249 } 1250 1251 static void b53_force_link(struct b53_device *dev, int port, int link) 1252 { 1253 u8 reg, val, off; 1254 1255 /* Override the port settings */ 1256 if (port == dev->imp_port) { 1257 off = B53_PORT_OVERRIDE_CTRL; 1258 val = PORT_OVERRIDE_EN; 1259 } else { 1260 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 1261 val = GMII_PO_EN; 1262 } 1263 1264 b53_read8(dev, B53_CTRL_PAGE, off, ®); 1265 reg |= val; 1266 if (link) 1267 reg |= PORT_OVERRIDE_LINK; 1268 else 1269 reg &= ~PORT_OVERRIDE_LINK; 1270 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1271 } 1272 1273 static void b53_force_port_config(struct b53_device *dev, int port, 1274 int speed, int duplex, 1275 bool tx_pause, bool rx_pause) 1276 { 1277 u8 reg, val, off; 1278 1279 /* Override the port settings */ 1280 if (port == dev->imp_port) { 1281 off = B53_PORT_OVERRIDE_CTRL; 1282 val = PORT_OVERRIDE_EN; 1283 } else { 1284 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 1285 val = GMII_PO_EN; 1286 } 1287 1288 b53_read8(dev, B53_CTRL_PAGE, off, ®); 1289 reg |= val; 1290 if (duplex == DUPLEX_FULL) 1291 reg |= PORT_OVERRIDE_FULL_DUPLEX; 1292 else 1293 reg &= ~PORT_OVERRIDE_FULL_DUPLEX; 1294 1295 switch (speed) { 1296 case 2000: 1297 reg |= PORT_OVERRIDE_SPEED_2000M; 1298 fallthrough; 1299 case SPEED_1000: 1300 reg |= PORT_OVERRIDE_SPEED_1000M; 1301 break; 1302 case SPEED_100: 1303 reg |= PORT_OVERRIDE_SPEED_100M; 1304 break; 1305 case SPEED_10: 1306 reg |= PORT_OVERRIDE_SPEED_10M; 1307 break; 1308 default: 1309 dev_err(dev->dev, "unknown speed: %d\n", speed); 1310 return; 1311 } 1312 1313 if (rx_pause) 1314 reg |= PORT_OVERRIDE_RX_FLOW; 1315 if (tx_pause) 1316 reg |= PORT_OVERRIDE_TX_FLOW; 1317 1318 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1319 } 1320 1321 static void b53_adjust_63xx_rgmii(struct dsa_switch *ds, int port, 1322 phy_interface_t interface) 1323 { 1324 struct b53_device *dev = ds->priv; 1325 u8 rgmii_ctrl = 0, off; 1326 1327 if (port == dev->imp_port) 1328 off = B53_RGMII_CTRL_IMP; 1329 else 1330 off = B53_RGMII_CTRL_P(port); 1331 1332 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl); 1333 1334 switch (interface) { 1335 case PHY_INTERFACE_MODE_RGMII_ID: 1336 rgmii_ctrl |= (RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC); 1337 break; 1338 case PHY_INTERFACE_MODE_RGMII_RXID: 1339 rgmii_ctrl &= ~(RGMII_CTRL_DLL_TXC); 1340 rgmii_ctrl |= RGMII_CTRL_DLL_RXC; 1341 break; 1342 case PHY_INTERFACE_MODE_RGMII_TXID: 1343 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC); 1344 rgmii_ctrl |= RGMII_CTRL_DLL_TXC; 1345 break; 1346 case PHY_INTERFACE_MODE_RGMII: 1347 default: 1348 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC); 1349 break; 1350 } 1351 1352 if (port != dev->imp_port) { 1353 if (is63268(dev)) 1354 rgmii_ctrl |= RGMII_CTRL_MII_OVERRIDE; 1355 1356 rgmii_ctrl |= RGMII_CTRL_ENABLE_GMII; 1357 } 1358 1359 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl); 1360 1361 dev_dbg(ds->dev, "Configured port %d for %s\n", port, 1362 phy_modes(interface)); 1363 } 1364 1365 static void b53_adjust_531x5_rgmii(struct dsa_switch *ds, int port, 1366 phy_interface_t interface) 1367 { 1368 struct b53_device *dev = ds->priv; 1369 u8 rgmii_ctrl = 0, off; 1370 1371 if (port == dev->imp_port) 1372 off = B53_RGMII_CTRL_IMP; 1373 else 1374 off = B53_RGMII_CTRL_P(port); 1375 1376 /* Configure the port RGMII clock delay by DLL disabled and 1377 * tx_clk aligned timing (restoring to reset defaults) 1378 */ 1379 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl); 1380 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC | 1381 RGMII_CTRL_TIMING_SEL); 1382 1383 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make 1384 * sure that we enable the port TX clock internal delay to 1385 * account for this internal delay that is inserted, otherwise 1386 * the switch won't be able to receive correctly. 1387 * 1388 * PHY_INTERFACE_MODE_RGMII means that we are not introducing 1389 * any delay neither on transmission nor reception, so the 1390 * BCM53125 must also be configured accordingly to account for 1391 * the lack of delay and introduce 1392 * 1393 * The BCM53125 switch has its RX clock and TX clock control 1394 * swapped, hence the reason why we modify the TX clock path in 1395 * the "RGMII" case 1396 */ 1397 if (interface == PHY_INTERFACE_MODE_RGMII_TXID) 1398 rgmii_ctrl |= RGMII_CTRL_DLL_TXC; 1399 if (interface == PHY_INTERFACE_MODE_RGMII) 1400 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC; 1401 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL; 1402 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl); 1403 1404 dev_info(ds->dev, "Configured port %d for %s\n", port, 1405 phy_modes(interface)); 1406 } 1407 1408 static void b53_adjust_5325_mii(struct dsa_switch *ds, int port) 1409 { 1410 struct b53_device *dev = ds->priv; 1411 u8 reg = 0; 1412 1413 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1414 ®); 1415 1416 /* reverse mii needs to be enabled */ 1417 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1418 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1419 reg | PORT_OVERRIDE_RV_MII_25); 1420 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1421 ®); 1422 1423 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1424 dev_err(ds->dev, 1425 "Failed to enable reverse MII mode\n"); 1426 return; 1427 } 1428 } 1429 } 1430 1431 void b53_port_event(struct dsa_switch *ds, int port) 1432 { 1433 struct b53_device *dev = ds->priv; 1434 bool link; 1435 u16 sts; 1436 1437 b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts); 1438 link = !!(sts & BIT(port)); 1439 dsa_port_phylink_mac_change(ds, port, link); 1440 } 1441 EXPORT_SYMBOL(b53_port_event); 1442 1443 static void b53_phylink_get_caps(struct dsa_switch *ds, int port, 1444 struct phylink_config *config) 1445 { 1446 struct b53_device *dev = ds->priv; 1447 1448 /* Internal ports need GMII for PHYLIB */ 1449 __set_bit(PHY_INTERFACE_MODE_GMII, config->supported_interfaces); 1450 1451 /* These switches appear to support MII and RevMII too, but beyond 1452 * this, the code gives very few clues. FIXME: We probably need more 1453 * interface modes here. 1454 * 1455 * According to b53_srab_mux_init(), ports 3..5 can support: 1456 * SGMII, MII, GMII, RGMII or INTERNAL depending on the MUX setting. 1457 * However, the interface mode read from the MUX configuration is 1458 * not passed back to DSA, so phylink uses NA. 1459 * DT can specify RGMII for ports 0, 1. 1460 * For MDIO, port 8 can be RGMII_TXID. 1461 */ 1462 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 1463 __set_bit(PHY_INTERFACE_MODE_REVMII, config->supported_interfaces); 1464 1465 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 1466 MAC_10 | MAC_100; 1467 1468 /* 5325/5365 are not capable of gigabit speeds, everything else is. 1469 * Note: the original code also exclulded Gigagbit for MII, RevMII 1470 * and 802.3z modes. MII and RevMII are not able to work above 100M, 1471 * so will be excluded by the generic validator implementation. 1472 * However, the exclusion of Gigabit for 802.3z just seems wrong. 1473 */ 1474 if (!(is5325(dev) || is5365(dev))) 1475 config->mac_capabilities |= MAC_1000; 1476 1477 /* Get the implementation specific capabilities */ 1478 if (dev->ops->phylink_get_caps) 1479 dev->ops->phylink_get_caps(dev, port, config); 1480 } 1481 1482 static struct phylink_pcs *b53_phylink_mac_select_pcs(struct phylink_config *config, 1483 phy_interface_t interface) 1484 { 1485 struct dsa_port *dp = dsa_phylink_to_port(config); 1486 struct b53_device *dev = dp->ds->priv; 1487 1488 if (!dev->ops->phylink_mac_select_pcs) 1489 return NULL; 1490 1491 return dev->ops->phylink_mac_select_pcs(dev, dp->index, interface); 1492 } 1493 1494 static void b53_phylink_mac_config(struct phylink_config *config, 1495 unsigned int mode, 1496 const struct phylink_link_state *state) 1497 { 1498 struct dsa_port *dp = dsa_phylink_to_port(config); 1499 phy_interface_t interface = state->interface; 1500 struct dsa_switch *ds = dp->ds; 1501 struct b53_device *dev = ds->priv; 1502 int port = dp->index; 1503 1504 if (is63xx(dev) && port >= B53_63XX_RGMII0) 1505 b53_adjust_63xx_rgmii(ds, port, interface); 1506 1507 if (mode == MLO_AN_FIXED) { 1508 if (is531x5(dev) && phy_interface_mode_is_rgmii(interface)) 1509 b53_adjust_531x5_rgmii(ds, port, interface); 1510 1511 /* configure MII port if necessary */ 1512 if (is5325(dev)) 1513 b53_adjust_5325_mii(ds, port); 1514 } 1515 } 1516 1517 static void b53_phylink_mac_link_down(struct phylink_config *config, 1518 unsigned int mode, 1519 phy_interface_t interface) 1520 { 1521 struct dsa_port *dp = dsa_phylink_to_port(config); 1522 struct b53_device *dev = dp->ds->priv; 1523 int port = dp->index; 1524 1525 if (mode == MLO_AN_PHY) 1526 return; 1527 1528 if (mode == MLO_AN_FIXED) { 1529 b53_force_link(dev, port, false); 1530 return; 1531 } 1532 1533 if (phy_interface_mode_is_8023z(interface) && 1534 dev->ops->serdes_link_set) 1535 dev->ops->serdes_link_set(dev, port, mode, interface, false); 1536 } 1537 1538 static void b53_phylink_mac_link_up(struct phylink_config *config, 1539 struct phy_device *phydev, 1540 unsigned int mode, 1541 phy_interface_t interface, 1542 int speed, int duplex, 1543 bool tx_pause, bool rx_pause) 1544 { 1545 struct dsa_port *dp = dsa_phylink_to_port(config); 1546 struct dsa_switch *ds = dp->ds; 1547 struct b53_device *dev = ds->priv; 1548 struct ethtool_keee *p = &dev->ports[dp->index].eee; 1549 int port = dp->index; 1550 1551 if (mode == MLO_AN_PHY) { 1552 /* Re-negotiate EEE if it was enabled already */ 1553 p->eee_enabled = b53_eee_init(ds, port, phydev); 1554 return; 1555 } 1556 1557 if (mode == MLO_AN_FIXED) { 1558 /* Force flow control on BCM5301x's CPU port */ 1559 if (is5301x(dev) && dsa_is_cpu_port(ds, port)) 1560 tx_pause = rx_pause = true; 1561 1562 b53_force_port_config(dev, port, speed, duplex, 1563 tx_pause, rx_pause); 1564 b53_force_link(dev, port, true); 1565 return; 1566 } 1567 1568 if (phy_interface_mode_is_8023z(interface) && 1569 dev->ops->serdes_link_set) 1570 dev->ops->serdes_link_set(dev, port, mode, interface, true); 1571 } 1572 1573 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1574 struct netlink_ext_ack *extack) 1575 { 1576 struct b53_device *dev = ds->priv; 1577 1578 if (dev->vlan_filtering != vlan_filtering) { 1579 dev->vlan_filtering = vlan_filtering; 1580 b53_apply_config(dev); 1581 } 1582 1583 return 0; 1584 } 1585 EXPORT_SYMBOL(b53_vlan_filtering); 1586 1587 static int b53_vlan_prepare(struct dsa_switch *ds, int port, 1588 const struct switchdev_obj_port_vlan *vlan) 1589 { 1590 struct b53_device *dev = ds->priv; 1591 1592 if ((is5325(dev) || is5365(dev)) && vlan->vid == 0) 1593 return -EOPNOTSUPP; 1594 1595 /* Port 7 on 7278 connects to the ASP's UniMAC which is not capable of 1596 * receiving VLAN tagged frames at all, we can still allow the port to 1597 * be configured for egress untagged. 1598 */ 1599 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7 && 1600 !(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)) 1601 return -EINVAL; 1602 1603 if (vlan->vid >= dev->num_vlans) 1604 return -ERANGE; 1605 1606 b53_enable_vlan(dev, port, true, dev->vlan_filtering); 1607 1608 return 0; 1609 } 1610 1611 int b53_vlan_add(struct dsa_switch *ds, int port, 1612 const struct switchdev_obj_port_vlan *vlan, 1613 struct netlink_ext_ack *extack) 1614 { 1615 struct b53_device *dev = ds->priv; 1616 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1617 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1618 struct b53_vlan *vl; 1619 u16 old_pvid, new_pvid; 1620 int err; 1621 1622 err = b53_vlan_prepare(ds, port, vlan); 1623 if (err) 1624 return err; 1625 1626 if (vlan->vid == 0) 1627 return 0; 1628 1629 old_pvid = dev->ports[port].pvid; 1630 if (pvid) 1631 new_pvid = vlan->vid; 1632 else if (!pvid && vlan->vid == old_pvid) 1633 new_pvid = b53_default_pvid(dev); 1634 else 1635 new_pvid = old_pvid; 1636 dev->ports[port].pvid = new_pvid; 1637 1638 vl = &dev->vlans[vlan->vid]; 1639 1640 if (dsa_is_cpu_port(ds, port)) 1641 untagged = false; 1642 1643 vl->members |= BIT(port); 1644 if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port)) 1645 vl->untag |= BIT(port); 1646 else 1647 vl->untag &= ~BIT(port); 1648 1649 if (!dev->vlan_filtering) 1650 return 0; 1651 1652 b53_set_vlan_entry(dev, vlan->vid, vl); 1653 b53_fast_age_vlan(dev, vlan->vid); 1654 1655 if (!dsa_is_cpu_port(ds, port) && new_pvid != old_pvid) { 1656 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), 1657 new_pvid); 1658 b53_fast_age_vlan(dev, old_pvid); 1659 } 1660 1661 return 0; 1662 } 1663 EXPORT_SYMBOL(b53_vlan_add); 1664 1665 int b53_vlan_del(struct dsa_switch *ds, int port, 1666 const struct switchdev_obj_port_vlan *vlan) 1667 { 1668 struct b53_device *dev = ds->priv; 1669 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1670 struct b53_vlan *vl; 1671 u16 pvid; 1672 1673 if (vlan->vid == 0) 1674 return 0; 1675 1676 pvid = dev->ports[port].pvid; 1677 1678 vl = &dev->vlans[vlan->vid]; 1679 1680 vl->members &= ~BIT(port); 1681 1682 if (pvid == vlan->vid) 1683 pvid = b53_default_pvid(dev); 1684 dev->ports[port].pvid = pvid; 1685 1686 if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port)) 1687 vl->untag &= ~(BIT(port)); 1688 1689 if (!dev->vlan_filtering) 1690 return 0; 1691 1692 b53_set_vlan_entry(dev, vlan->vid, vl); 1693 b53_fast_age_vlan(dev, vlan->vid); 1694 1695 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid); 1696 b53_fast_age_vlan(dev, pvid); 1697 1698 return 0; 1699 } 1700 EXPORT_SYMBOL(b53_vlan_del); 1701 1702 /* Address Resolution Logic routines. Caller must hold &dev->arl_mutex. */ 1703 static int b53_arl_op_wait(struct b53_device *dev) 1704 { 1705 unsigned int timeout = 10; 1706 u8 reg; 1707 1708 do { 1709 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1710 if (!(reg & ARLTBL_START_DONE)) 1711 return 0; 1712 1713 usleep_range(1000, 2000); 1714 } while (timeout--); 1715 1716 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg); 1717 1718 return -ETIMEDOUT; 1719 } 1720 1721 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op) 1722 { 1723 u8 reg; 1724 1725 if (op > ARLTBL_RW) 1726 return -EINVAL; 1727 1728 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1729 reg |= ARLTBL_START_DONE; 1730 if (op) 1731 reg |= ARLTBL_RW; 1732 else 1733 reg &= ~ARLTBL_RW; 1734 if (dev->vlan_enabled) 1735 reg &= ~ARLTBL_IVL_SVL_SELECT; 1736 else 1737 reg |= ARLTBL_IVL_SVL_SELECT; 1738 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg); 1739 1740 return b53_arl_op_wait(dev); 1741 } 1742 1743 static int b53_arl_read(struct b53_device *dev, u64 mac, 1744 u16 vid, struct b53_arl_entry *ent, u8 *idx) 1745 { 1746 DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES); 1747 unsigned int i; 1748 int ret; 1749 1750 ret = b53_arl_op_wait(dev); 1751 if (ret) 1752 return ret; 1753 1754 bitmap_zero(free_bins, dev->num_arl_bins); 1755 1756 /* Read the bins */ 1757 for (i = 0; i < dev->num_arl_bins; i++) { 1758 u64 mac_vid; 1759 u32 fwd_entry; 1760 1761 b53_read64(dev, B53_ARLIO_PAGE, 1762 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid); 1763 b53_read32(dev, B53_ARLIO_PAGE, 1764 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry); 1765 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1766 1767 if (!(fwd_entry & ARLTBL_VALID)) { 1768 set_bit(i, free_bins); 1769 continue; 1770 } 1771 if ((mac_vid & ARLTBL_MAC_MASK) != mac) 1772 continue; 1773 if (dev->vlan_enabled && 1774 ((mac_vid >> ARLTBL_VID_S) & ARLTBL_VID_MASK) != vid) 1775 continue; 1776 *idx = i; 1777 return 0; 1778 } 1779 1780 *idx = find_first_bit(free_bins, dev->num_arl_bins); 1781 return *idx >= dev->num_arl_bins ? -ENOSPC : -ENOENT; 1782 } 1783 1784 static int b53_arl_op(struct b53_device *dev, int op, int port, 1785 const unsigned char *addr, u16 vid, bool is_valid) 1786 { 1787 struct b53_arl_entry ent; 1788 u32 fwd_entry; 1789 u64 mac, mac_vid = 0; 1790 u8 idx = 0; 1791 int ret; 1792 1793 /* Convert the array into a 64-bit MAC */ 1794 mac = ether_addr_to_u64(addr); 1795 1796 /* Perform a read for the given MAC and VID */ 1797 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac); 1798 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid); 1799 1800 /* Issue a read operation for this MAC */ 1801 ret = b53_arl_rw_op(dev, 1); 1802 if (ret) 1803 return ret; 1804 1805 ret = b53_arl_read(dev, mac, vid, &ent, &idx); 1806 1807 /* If this is a read, just finish now */ 1808 if (op) 1809 return ret; 1810 1811 switch (ret) { 1812 case -ETIMEDOUT: 1813 return ret; 1814 case -ENOSPC: 1815 dev_dbg(dev->dev, "{%pM,%.4d} no space left in ARL\n", 1816 addr, vid); 1817 return is_valid ? ret : 0; 1818 case -ENOENT: 1819 /* We could not find a matching MAC, so reset to a new entry */ 1820 dev_dbg(dev->dev, "{%pM,%.4d} not found, using idx: %d\n", 1821 addr, vid, idx); 1822 fwd_entry = 0; 1823 break; 1824 default: 1825 dev_dbg(dev->dev, "{%pM,%.4d} found, using idx: %d\n", 1826 addr, vid, idx); 1827 break; 1828 } 1829 1830 /* For multicast address, the port is a bitmask and the validity 1831 * is determined by having at least one port being still active 1832 */ 1833 if (!is_multicast_ether_addr(addr)) { 1834 ent.port = port; 1835 ent.is_valid = is_valid; 1836 } else { 1837 if (is_valid) 1838 ent.port |= BIT(port); 1839 else 1840 ent.port &= ~BIT(port); 1841 1842 ent.is_valid = !!(ent.port); 1843 } 1844 1845 ent.vid = vid; 1846 ent.is_static = true; 1847 ent.is_age = false; 1848 memcpy(ent.mac, addr, ETH_ALEN); 1849 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent); 1850 1851 b53_write64(dev, B53_ARLIO_PAGE, 1852 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid); 1853 b53_write32(dev, B53_ARLIO_PAGE, 1854 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry); 1855 1856 return b53_arl_rw_op(dev, 0); 1857 } 1858 1859 int b53_fdb_add(struct dsa_switch *ds, int port, 1860 const unsigned char *addr, u16 vid, 1861 struct dsa_db db) 1862 { 1863 struct b53_device *priv = ds->priv; 1864 int ret; 1865 1866 /* 5325 and 5365 require some more massaging, but could 1867 * be supported eventually 1868 */ 1869 if (is5325(priv) || is5365(priv)) 1870 return -EOPNOTSUPP; 1871 1872 mutex_lock(&priv->arl_mutex); 1873 ret = b53_arl_op(priv, 0, port, addr, vid, true); 1874 mutex_unlock(&priv->arl_mutex); 1875 1876 return ret; 1877 } 1878 EXPORT_SYMBOL(b53_fdb_add); 1879 1880 int b53_fdb_del(struct dsa_switch *ds, int port, 1881 const unsigned char *addr, u16 vid, 1882 struct dsa_db db) 1883 { 1884 struct b53_device *priv = ds->priv; 1885 int ret; 1886 1887 mutex_lock(&priv->arl_mutex); 1888 ret = b53_arl_op(priv, 0, port, addr, vid, false); 1889 mutex_unlock(&priv->arl_mutex); 1890 1891 return ret; 1892 } 1893 EXPORT_SYMBOL(b53_fdb_del); 1894 1895 static int b53_arl_search_wait(struct b53_device *dev) 1896 { 1897 unsigned int timeout = 1000; 1898 u8 reg; 1899 1900 do { 1901 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®); 1902 if (!(reg & ARL_SRCH_STDN)) 1903 return 0; 1904 1905 if (reg & ARL_SRCH_VLID) 1906 return 0; 1907 1908 usleep_range(1000, 2000); 1909 } while (timeout--); 1910 1911 return -ETIMEDOUT; 1912 } 1913 1914 static void b53_arl_search_rd(struct b53_device *dev, u8 idx, 1915 struct b53_arl_entry *ent) 1916 { 1917 u64 mac_vid; 1918 u32 fwd_entry; 1919 1920 b53_read64(dev, B53_ARLIO_PAGE, 1921 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid); 1922 b53_read32(dev, B53_ARLIO_PAGE, 1923 B53_ARL_SRCH_RSTL(idx), &fwd_entry); 1924 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1925 } 1926 1927 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent, 1928 dsa_fdb_dump_cb_t *cb, void *data) 1929 { 1930 if (!ent->is_valid) 1931 return 0; 1932 1933 if (port != ent->port) 1934 return 0; 1935 1936 return cb(ent->mac, ent->vid, ent->is_static, data); 1937 } 1938 1939 int b53_fdb_dump(struct dsa_switch *ds, int port, 1940 dsa_fdb_dump_cb_t *cb, void *data) 1941 { 1942 struct b53_device *priv = ds->priv; 1943 struct b53_arl_entry results[2]; 1944 unsigned int count = 0; 1945 int ret; 1946 u8 reg; 1947 1948 mutex_lock(&priv->arl_mutex); 1949 1950 /* Start search operation */ 1951 reg = ARL_SRCH_STDN; 1952 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg); 1953 1954 do { 1955 ret = b53_arl_search_wait(priv); 1956 if (ret) 1957 break; 1958 1959 b53_arl_search_rd(priv, 0, &results[0]); 1960 ret = b53_fdb_copy(port, &results[0], cb, data); 1961 if (ret) 1962 break; 1963 1964 if (priv->num_arl_bins > 2) { 1965 b53_arl_search_rd(priv, 1, &results[1]); 1966 ret = b53_fdb_copy(port, &results[1], cb, data); 1967 if (ret) 1968 break; 1969 1970 if (!results[0].is_valid && !results[1].is_valid) 1971 break; 1972 } 1973 1974 } while (count++ < b53_max_arl_entries(priv) / 2); 1975 1976 mutex_unlock(&priv->arl_mutex); 1977 1978 return 0; 1979 } 1980 EXPORT_SYMBOL(b53_fdb_dump); 1981 1982 int b53_mdb_add(struct dsa_switch *ds, int port, 1983 const struct switchdev_obj_port_mdb *mdb, 1984 struct dsa_db db) 1985 { 1986 struct b53_device *priv = ds->priv; 1987 int ret; 1988 1989 /* 5325 and 5365 require some more massaging, but could 1990 * be supported eventually 1991 */ 1992 if (is5325(priv) || is5365(priv)) 1993 return -EOPNOTSUPP; 1994 1995 mutex_lock(&priv->arl_mutex); 1996 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, true); 1997 mutex_unlock(&priv->arl_mutex); 1998 1999 return ret; 2000 } 2001 EXPORT_SYMBOL(b53_mdb_add); 2002 2003 int b53_mdb_del(struct dsa_switch *ds, int port, 2004 const struct switchdev_obj_port_mdb *mdb, 2005 struct dsa_db db) 2006 { 2007 struct b53_device *priv = ds->priv; 2008 int ret; 2009 2010 mutex_lock(&priv->arl_mutex); 2011 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, false); 2012 mutex_unlock(&priv->arl_mutex); 2013 if (ret) 2014 dev_err(ds->dev, "failed to delete MDB entry\n"); 2015 2016 return ret; 2017 } 2018 EXPORT_SYMBOL(b53_mdb_del); 2019 2020 int b53_br_join(struct dsa_switch *ds, int port, struct dsa_bridge bridge, 2021 bool *tx_fwd_offload, struct netlink_ext_ack *extack) 2022 { 2023 struct b53_device *dev = ds->priv; 2024 struct b53_vlan *vl; 2025 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 2026 u16 pvlan, reg, pvid; 2027 unsigned int i; 2028 2029 /* On 7278, port 7 which connects to the ASP should only receive 2030 * traffic from matching CFP rules. 2031 */ 2032 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7) 2033 return -EINVAL; 2034 2035 pvid = b53_default_pvid(dev); 2036 vl = &dev->vlans[pvid]; 2037 2038 if (dev->vlan_filtering) { 2039 /* Make this port leave the all VLANs join since we will have 2040 * proper VLAN entries from now on 2041 */ 2042 if (is58xx(dev)) { 2043 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, 2044 ®); 2045 reg &= ~BIT(port); 2046 if ((reg & BIT(cpu_port)) == BIT(cpu_port)) 2047 reg &= ~BIT(cpu_port); 2048 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, 2049 reg); 2050 } 2051 2052 b53_get_vlan_entry(dev, pvid, vl); 2053 vl->members &= ~BIT(port); 2054 if (vl->members == BIT(cpu_port)) 2055 vl->members &= ~BIT(cpu_port); 2056 vl->untag = vl->members; 2057 b53_set_vlan_entry(dev, pvid, vl); 2058 } 2059 2060 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 2061 2062 b53_for_each_port(dev, i) { 2063 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge)) 2064 continue; 2065 2066 /* Add this local port to the remote port VLAN control 2067 * membership and update the remote port bitmask 2068 */ 2069 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 2070 reg |= BIT(port); 2071 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 2072 dev->ports[i].vlan_ctl_mask = reg; 2073 2074 pvlan |= BIT(i); 2075 } 2076 2077 /* Disable redirection of unknown SA to the CPU port */ 2078 b53_set_eap_mode(dev, port, EAP_MODE_BASIC); 2079 2080 /* Configure the local port VLAN control membership to include 2081 * remote ports and update the local port bitmask 2082 */ 2083 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 2084 dev->ports[port].vlan_ctl_mask = pvlan; 2085 2086 return 0; 2087 } 2088 EXPORT_SYMBOL(b53_br_join); 2089 2090 void b53_br_leave(struct dsa_switch *ds, int port, struct dsa_bridge bridge) 2091 { 2092 struct b53_device *dev = ds->priv; 2093 struct b53_vlan *vl; 2094 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 2095 unsigned int i; 2096 u16 pvlan, reg, pvid; 2097 2098 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 2099 2100 b53_for_each_port(dev, i) { 2101 /* Don't touch the remaining ports */ 2102 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge)) 2103 continue; 2104 2105 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 2106 reg &= ~BIT(port); 2107 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 2108 dev->ports[port].vlan_ctl_mask = reg; 2109 2110 /* Prevent self removal to preserve isolation */ 2111 if (port != i) 2112 pvlan &= ~BIT(i); 2113 } 2114 2115 /* Enable redirection of unknown SA to the CPU port */ 2116 b53_set_eap_mode(dev, port, EAP_MODE_SIMPLIFIED); 2117 2118 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 2119 dev->ports[port].vlan_ctl_mask = pvlan; 2120 2121 pvid = b53_default_pvid(dev); 2122 vl = &dev->vlans[pvid]; 2123 2124 if (dev->vlan_filtering) { 2125 /* Make this port join all VLANs without VLAN entries */ 2126 if (is58xx(dev)) { 2127 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 2128 reg |= BIT(port); 2129 if (!(reg & BIT(cpu_port))) 2130 reg |= BIT(cpu_port); 2131 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 2132 } 2133 2134 b53_get_vlan_entry(dev, pvid, vl); 2135 vl->members |= BIT(port) | BIT(cpu_port); 2136 vl->untag |= BIT(port) | BIT(cpu_port); 2137 b53_set_vlan_entry(dev, pvid, vl); 2138 } 2139 } 2140 EXPORT_SYMBOL(b53_br_leave); 2141 2142 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state) 2143 { 2144 struct b53_device *dev = ds->priv; 2145 u8 hw_state; 2146 u8 reg; 2147 2148 switch (state) { 2149 case BR_STATE_DISABLED: 2150 hw_state = PORT_CTRL_DIS_STATE; 2151 break; 2152 case BR_STATE_LISTENING: 2153 hw_state = PORT_CTRL_LISTEN_STATE; 2154 break; 2155 case BR_STATE_LEARNING: 2156 hw_state = PORT_CTRL_LEARN_STATE; 2157 break; 2158 case BR_STATE_FORWARDING: 2159 hw_state = PORT_CTRL_FWD_STATE; 2160 break; 2161 case BR_STATE_BLOCKING: 2162 hw_state = PORT_CTRL_BLOCK_STATE; 2163 break; 2164 default: 2165 dev_err(ds->dev, "invalid STP state: %d\n", state); 2166 return; 2167 } 2168 2169 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 2170 reg &= ~PORT_CTRL_STP_STATE_MASK; 2171 reg |= hw_state; 2172 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 2173 } 2174 EXPORT_SYMBOL(b53_br_set_stp_state); 2175 2176 void b53_br_fast_age(struct dsa_switch *ds, int port) 2177 { 2178 struct b53_device *dev = ds->priv; 2179 2180 if (b53_fast_age_port(dev, port)) 2181 dev_err(ds->dev, "fast ageing failed\n"); 2182 } 2183 EXPORT_SYMBOL(b53_br_fast_age); 2184 2185 int b53_br_flags_pre(struct dsa_switch *ds, int port, 2186 struct switchdev_brport_flags flags, 2187 struct netlink_ext_ack *extack) 2188 { 2189 if (flags.mask & ~(BR_FLOOD | BR_MCAST_FLOOD | BR_LEARNING)) 2190 return -EINVAL; 2191 2192 return 0; 2193 } 2194 EXPORT_SYMBOL(b53_br_flags_pre); 2195 2196 int b53_br_flags(struct dsa_switch *ds, int port, 2197 struct switchdev_brport_flags flags, 2198 struct netlink_ext_ack *extack) 2199 { 2200 if (flags.mask & BR_FLOOD) 2201 b53_port_set_ucast_flood(ds->priv, port, 2202 !!(flags.val & BR_FLOOD)); 2203 if (flags.mask & BR_MCAST_FLOOD) 2204 b53_port_set_mcast_flood(ds->priv, port, 2205 !!(flags.val & BR_MCAST_FLOOD)); 2206 if (flags.mask & BR_LEARNING) 2207 b53_port_set_learning(ds->priv, port, 2208 !!(flags.val & BR_LEARNING)); 2209 2210 return 0; 2211 } 2212 EXPORT_SYMBOL(b53_br_flags); 2213 2214 static bool b53_possible_cpu_port(struct dsa_switch *ds, int port) 2215 { 2216 /* Broadcom switches will accept enabling Broadcom tags on the 2217 * following ports: 5, 7 and 8, any other port is not supported 2218 */ 2219 switch (port) { 2220 case B53_CPU_PORT_25: 2221 case 7: 2222 case B53_CPU_PORT: 2223 return true; 2224 } 2225 2226 return false; 2227 } 2228 2229 static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port, 2230 enum dsa_tag_protocol tag_protocol) 2231 { 2232 bool ret = b53_possible_cpu_port(ds, port); 2233 2234 if (!ret) { 2235 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n", 2236 port); 2237 return ret; 2238 } 2239 2240 switch (tag_protocol) { 2241 case DSA_TAG_PROTO_BRCM: 2242 case DSA_TAG_PROTO_BRCM_PREPEND: 2243 dev_warn(ds->dev, 2244 "Port %d is stacked to Broadcom tag switch\n", port); 2245 ret = false; 2246 break; 2247 default: 2248 ret = true; 2249 break; 2250 } 2251 2252 return ret; 2253 } 2254 2255 enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port, 2256 enum dsa_tag_protocol mprot) 2257 { 2258 struct b53_device *dev = ds->priv; 2259 2260 if (!b53_can_enable_brcm_tags(ds, port, mprot)) { 2261 dev->tag_protocol = DSA_TAG_PROTO_NONE; 2262 goto out; 2263 } 2264 2265 /* Older models require a different 6 byte tag */ 2266 if (is5325(dev) || is5365(dev) || is63xx(dev)) { 2267 dev->tag_protocol = DSA_TAG_PROTO_BRCM_LEGACY; 2268 goto out; 2269 } 2270 2271 /* Broadcom BCM58xx chips have a flow accelerator on Port 8 2272 * which requires us to use the prepended Broadcom tag type 2273 */ 2274 if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT) { 2275 dev->tag_protocol = DSA_TAG_PROTO_BRCM_PREPEND; 2276 goto out; 2277 } 2278 2279 dev->tag_protocol = DSA_TAG_PROTO_BRCM; 2280 out: 2281 return dev->tag_protocol; 2282 } 2283 EXPORT_SYMBOL(b53_get_tag_protocol); 2284 2285 int b53_mirror_add(struct dsa_switch *ds, int port, 2286 struct dsa_mall_mirror_tc_entry *mirror, bool ingress, 2287 struct netlink_ext_ack *extack) 2288 { 2289 struct b53_device *dev = ds->priv; 2290 u16 reg, loc; 2291 2292 if (ingress) 2293 loc = B53_IG_MIR_CTL; 2294 else 2295 loc = B53_EG_MIR_CTL; 2296 2297 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 2298 reg |= BIT(port); 2299 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 2300 2301 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 2302 reg &= ~CAP_PORT_MASK; 2303 reg |= mirror->to_local_port; 2304 reg |= MIRROR_EN; 2305 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 2306 2307 return 0; 2308 } 2309 EXPORT_SYMBOL(b53_mirror_add); 2310 2311 void b53_mirror_del(struct dsa_switch *ds, int port, 2312 struct dsa_mall_mirror_tc_entry *mirror) 2313 { 2314 struct b53_device *dev = ds->priv; 2315 bool loc_disable = false, other_loc_disable = false; 2316 u16 reg, loc; 2317 2318 if (mirror->ingress) 2319 loc = B53_IG_MIR_CTL; 2320 else 2321 loc = B53_EG_MIR_CTL; 2322 2323 /* Update the desired ingress/egress register */ 2324 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 2325 reg &= ~BIT(port); 2326 if (!(reg & MIRROR_MASK)) 2327 loc_disable = true; 2328 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 2329 2330 /* Now look at the other one to know if we can disable mirroring 2331 * entirely 2332 */ 2333 if (mirror->ingress) 2334 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, ®); 2335 else 2336 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, ®); 2337 if (!(reg & MIRROR_MASK)) 2338 other_loc_disable = true; 2339 2340 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 2341 /* Both no longer have ports, let's disable mirroring */ 2342 if (loc_disable && other_loc_disable) { 2343 reg &= ~MIRROR_EN; 2344 reg &= ~mirror->to_local_port; 2345 } 2346 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 2347 } 2348 EXPORT_SYMBOL(b53_mirror_del); 2349 2350 /* Returns 0 if EEE was not enabled, or 1 otherwise 2351 */ 2352 int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy) 2353 { 2354 int ret; 2355 2356 ret = phy_init_eee(phy, false); 2357 if (ret) 2358 return 0; 2359 2360 b53_eee_enable_set(ds, port, true); 2361 2362 return 1; 2363 } 2364 EXPORT_SYMBOL(b53_eee_init); 2365 2366 bool b53_support_eee(struct dsa_switch *ds, int port) 2367 { 2368 struct b53_device *dev = ds->priv; 2369 2370 return !is5325(dev) && !is5365(dev); 2371 } 2372 EXPORT_SYMBOL(b53_support_eee); 2373 2374 int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_keee *e) 2375 { 2376 struct b53_device *dev = ds->priv; 2377 struct ethtool_keee *p = &dev->ports[port].eee; 2378 2379 p->eee_enabled = e->eee_enabled; 2380 b53_eee_enable_set(ds, port, e->eee_enabled); 2381 2382 return 0; 2383 } 2384 EXPORT_SYMBOL(b53_set_mac_eee); 2385 2386 static int b53_change_mtu(struct dsa_switch *ds, int port, int mtu) 2387 { 2388 struct b53_device *dev = ds->priv; 2389 bool enable_jumbo; 2390 bool allow_10_100; 2391 2392 if (is5325(dev) || is5365(dev)) 2393 return 0; 2394 2395 if (!dsa_is_cpu_port(ds, port)) 2396 return 0; 2397 2398 enable_jumbo = (mtu > ETH_DATA_LEN); 2399 allow_10_100 = !is63xx(dev); 2400 2401 return b53_set_jumbo(dev, enable_jumbo, allow_10_100); 2402 } 2403 2404 static int b53_get_max_mtu(struct dsa_switch *ds, int port) 2405 { 2406 struct b53_device *dev = ds->priv; 2407 2408 if (is5325(dev) || is5365(dev)) 2409 return B53_MAX_MTU_25; 2410 2411 return B53_MAX_MTU; 2412 } 2413 2414 int b53_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 2415 { 2416 struct b53_device *dev = ds->priv; 2417 u32 atc; 2418 int reg; 2419 2420 if (is63xx(dev)) 2421 reg = B53_AGING_TIME_CONTROL_63XX; 2422 else 2423 reg = B53_AGING_TIME_CONTROL; 2424 2425 atc = DIV_ROUND_CLOSEST(msecs, 1000); 2426 2427 if (!is5325(dev) && !is5365(dev)) 2428 atc |= AGE_CHANGE; 2429 2430 b53_write32(dev, B53_MGMT_PAGE, reg, atc); 2431 2432 return 0; 2433 } 2434 EXPORT_SYMBOL_GPL(b53_set_ageing_time); 2435 2436 static const struct phylink_mac_ops b53_phylink_mac_ops = { 2437 .mac_select_pcs = b53_phylink_mac_select_pcs, 2438 .mac_config = b53_phylink_mac_config, 2439 .mac_link_down = b53_phylink_mac_link_down, 2440 .mac_link_up = b53_phylink_mac_link_up, 2441 }; 2442 2443 static const struct dsa_switch_ops b53_switch_ops = { 2444 .get_tag_protocol = b53_get_tag_protocol, 2445 .setup = b53_setup, 2446 .teardown = b53_teardown, 2447 .get_strings = b53_get_strings, 2448 .get_ethtool_stats = b53_get_ethtool_stats, 2449 .get_sset_count = b53_get_sset_count, 2450 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 2451 .phy_read = b53_phy_read16, 2452 .phy_write = b53_phy_write16, 2453 .phylink_get_caps = b53_phylink_get_caps, 2454 .port_setup = b53_setup_port, 2455 .port_enable = b53_enable_port, 2456 .port_disable = b53_disable_port, 2457 .support_eee = b53_support_eee, 2458 .set_mac_eee = b53_set_mac_eee, 2459 .set_ageing_time = b53_set_ageing_time, 2460 .port_bridge_join = b53_br_join, 2461 .port_bridge_leave = b53_br_leave, 2462 .port_pre_bridge_flags = b53_br_flags_pre, 2463 .port_bridge_flags = b53_br_flags, 2464 .port_stp_state_set = b53_br_set_stp_state, 2465 .port_fast_age = b53_br_fast_age, 2466 .port_vlan_filtering = b53_vlan_filtering, 2467 .port_vlan_add = b53_vlan_add, 2468 .port_vlan_del = b53_vlan_del, 2469 .port_fdb_dump = b53_fdb_dump, 2470 .port_fdb_add = b53_fdb_add, 2471 .port_fdb_del = b53_fdb_del, 2472 .port_mirror_add = b53_mirror_add, 2473 .port_mirror_del = b53_mirror_del, 2474 .port_mdb_add = b53_mdb_add, 2475 .port_mdb_del = b53_mdb_del, 2476 .port_max_mtu = b53_get_max_mtu, 2477 .port_change_mtu = b53_change_mtu, 2478 }; 2479 2480 struct b53_chip_data { 2481 u32 chip_id; 2482 const char *dev_name; 2483 u16 vlans; 2484 u16 enabled_ports; 2485 u8 imp_port; 2486 u8 cpu_port; 2487 u8 vta_regs[3]; 2488 u8 arl_bins; 2489 u16 arl_buckets; 2490 u8 duplex_reg; 2491 u8 jumbo_pm_reg; 2492 u8 jumbo_size_reg; 2493 }; 2494 2495 #define B53_VTA_REGS \ 2496 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY } 2497 #define B53_VTA_REGS_9798 \ 2498 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 } 2499 #define B53_VTA_REGS_63XX \ 2500 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX } 2501 2502 static const struct b53_chip_data b53_switch_chips[] = { 2503 { 2504 .chip_id = BCM5325_DEVICE_ID, 2505 .dev_name = "BCM5325", 2506 .vlans = 16, 2507 .enabled_ports = 0x3f, 2508 .arl_bins = 2, 2509 .arl_buckets = 1024, 2510 .imp_port = 5, 2511 .duplex_reg = B53_DUPLEX_STAT_FE, 2512 }, 2513 { 2514 .chip_id = BCM5365_DEVICE_ID, 2515 .dev_name = "BCM5365", 2516 .vlans = 256, 2517 .enabled_ports = 0x3f, 2518 .arl_bins = 2, 2519 .arl_buckets = 1024, 2520 .imp_port = 5, 2521 .duplex_reg = B53_DUPLEX_STAT_FE, 2522 }, 2523 { 2524 .chip_id = BCM5389_DEVICE_ID, 2525 .dev_name = "BCM5389", 2526 .vlans = 4096, 2527 .enabled_ports = 0x11f, 2528 .arl_bins = 4, 2529 .arl_buckets = 1024, 2530 .imp_port = 8, 2531 .vta_regs = B53_VTA_REGS, 2532 .duplex_reg = B53_DUPLEX_STAT_GE, 2533 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2534 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2535 }, 2536 { 2537 .chip_id = BCM5395_DEVICE_ID, 2538 .dev_name = "BCM5395", 2539 .vlans = 4096, 2540 .enabled_ports = 0x11f, 2541 .arl_bins = 4, 2542 .arl_buckets = 1024, 2543 .imp_port = 8, 2544 .vta_regs = B53_VTA_REGS, 2545 .duplex_reg = B53_DUPLEX_STAT_GE, 2546 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2547 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2548 }, 2549 { 2550 .chip_id = BCM5397_DEVICE_ID, 2551 .dev_name = "BCM5397", 2552 .vlans = 4096, 2553 .enabled_ports = 0x11f, 2554 .arl_bins = 4, 2555 .arl_buckets = 1024, 2556 .imp_port = 8, 2557 .vta_regs = B53_VTA_REGS_9798, 2558 .duplex_reg = B53_DUPLEX_STAT_GE, 2559 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2560 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2561 }, 2562 { 2563 .chip_id = BCM5398_DEVICE_ID, 2564 .dev_name = "BCM5398", 2565 .vlans = 4096, 2566 .enabled_ports = 0x17f, 2567 .arl_bins = 4, 2568 .arl_buckets = 1024, 2569 .imp_port = 8, 2570 .vta_regs = B53_VTA_REGS_9798, 2571 .duplex_reg = B53_DUPLEX_STAT_GE, 2572 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2573 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2574 }, 2575 { 2576 .chip_id = BCM53101_DEVICE_ID, 2577 .dev_name = "BCM53101", 2578 .vlans = 4096, 2579 .enabled_ports = 0x11f, 2580 .arl_bins = 4, 2581 .arl_buckets = 512, 2582 .vta_regs = B53_VTA_REGS, 2583 .imp_port = 8, 2584 .duplex_reg = B53_DUPLEX_STAT_GE, 2585 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2586 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2587 }, 2588 { 2589 .chip_id = BCM53115_DEVICE_ID, 2590 .dev_name = "BCM53115", 2591 .vlans = 4096, 2592 .enabled_ports = 0x11f, 2593 .arl_bins = 4, 2594 .arl_buckets = 1024, 2595 .vta_regs = B53_VTA_REGS, 2596 .imp_port = 8, 2597 .duplex_reg = B53_DUPLEX_STAT_GE, 2598 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2599 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2600 }, 2601 { 2602 .chip_id = BCM53125_DEVICE_ID, 2603 .dev_name = "BCM53125", 2604 .vlans = 4096, 2605 .enabled_ports = 0x1ff, 2606 .arl_bins = 4, 2607 .arl_buckets = 1024, 2608 .imp_port = 8, 2609 .vta_regs = B53_VTA_REGS, 2610 .duplex_reg = B53_DUPLEX_STAT_GE, 2611 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2612 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2613 }, 2614 { 2615 .chip_id = BCM53128_DEVICE_ID, 2616 .dev_name = "BCM53128", 2617 .vlans = 4096, 2618 .enabled_ports = 0x1ff, 2619 .arl_bins = 4, 2620 .arl_buckets = 1024, 2621 .imp_port = 8, 2622 .vta_regs = B53_VTA_REGS, 2623 .duplex_reg = B53_DUPLEX_STAT_GE, 2624 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2625 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2626 }, 2627 { 2628 .chip_id = BCM63XX_DEVICE_ID, 2629 .dev_name = "BCM63xx", 2630 .vlans = 4096, 2631 .enabled_ports = 0, /* pdata must provide them */ 2632 .arl_bins = 4, 2633 .arl_buckets = 1024, 2634 .imp_port = 8, 2635 .vta_regs = B53_VTA_REGS_63XX, 2636 .duplex_reg = B53_DUPLEX_STAT_63XX, 2637 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, 2638 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, 2639 }, 2640 { 2641 .chip_id = BCM63268_DEVICE_ID, 2642 .dev_name = "BCM63268", 2643 .vlans = 4096, 2644 .enabled_ports = 0, /* pdata must provide them */ 2645 .arl_bins = 4, 2646 .arl_buckets = 1024, 2647 .imp_port = 8, 2648 .vta_regs = B53_VTA_REGS_63XX, 2649 .duplex_reg = B53_DUPLEX_STAT_63XX, 2650 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, 2651 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, 2652 }, 2653 { 2654 .chip_id = BCM53010_DEVICE_ID, 2655 .dev_name = "BCM53010", 2656 .vlans = 4096, 2657 .enabled_ports = 0x1bf, 2658 .arl_bins = 4, 2659 .arl_buckets = 1024, 2660 .imp_port = 8, 2661 .vta_regs = B53_VTA_REGS, 2662 .duplex_reg = B53_DUPLEX_STAT_GE, 2663 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2664 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2665 }, 2666 { 2667 .chip_id = BCM53011_DEVICE_ID, 2668 .dev_name = "BCM53011", 2669 .vlans = 4096, 2670 .enabled_ports = 0x1bf, 2671 .arl_bins = 4, 2672 .arl_buckets = 1024, 2673 .imp_port = 8, 2674 .vta_regs = B53_VTA_REGS, 2675 .duplex_reg = B53_DUPLEX_STAT_GE, 2676 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2677 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2678 }, 2679 { 2680 .chip_id = BCM53012_DEVICE_ID, 2681 .dev_name = "BCM53012", 2682 .vlans = 4096, 2683 .enabled_ports = 0x1bf, 2684 .arl_bins = 4, 2685 .arl_buckets = 1024, 2686 .imp_port = 8, 2687 .vta_regs = B53_VTA_REGS, 2688 .duplex_reg = B53_DUPLEX_STAT_GE, 2689 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2690 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2691 }, 2692 { 2693 .chip_id = BCM53018_DEVICE_ID, 2694 .dev_name = "BCM53018", 2695 .vlans = 4096, 2696 .enabled_ports = 0x1bf, 2697 .arl_bins = 4, 2698 .arl_buckets = 1024, 2699 .imp_port = 8, 2700 .vta_regs = B53_VTA_REGS, 2701 .duplex_reg = B53_DUPLEX_STAT_GE, 2702 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2703 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2704 }, 2705 { 2706 .chip_id = BCM53019_DEVICE_ID, 2707 .dev_name = "BCM53019", 2708 .vlans = 4096, 2709 .enabled_ports = 0x1bf, 2710 .arl_bins = 4, 2711 .arl_buckets = 1024, 2712 .imp_port = 8, 2713 .vta_regs = B53_VTA_REGS, 2714 .duplex_reg = B53_DUPLEX_STAT_GE, 2715 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2716 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2717 }, 2718 { 2719 .chip_id = BCM58XX_DEVICE_ID, 2720 .dev_name = "BCM585xx/586xx/88312", 2721 .vlans = 4096, 2722 .enabled_ports = 0x1ff, 2723 .arl_bins = 4, 2724 .arl_buckets = 1024, 2725 .imp_port = 8, 2726 .vta_regs = B53_VTA_REGS, 2727 .duplex_reg = B53_DUPLEX_STAT_GE, 2728 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2729 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2730 }, 2731 { 2732 .chip_id = BCM583XX_DEVICE_ID, 2733 .dev_name = "BCM583xx/11360", 2734 .vlans = 4096, 2735 .enabled_ports = 0x103, 2736 .arl_bins = 4, 2737 .arl_buckets = 1024, 2738 .imp_port = 8, 2739 .vta_regs = B53_VTA_REGS, 2740 .duplex_reg = B53_DUPLEX_STAT_GE, 2741 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2742 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2743 }, 2744 /* Starfighter 2 */ 2745 { 2746 .chip_id = BCM4908_DEVICE_ID, 2747 .dev_name = "BCM4908", 2748 .vlans = 4096, 2749 .enabled_ports = 0x1bf, 2750 .arl_bins = 4, 2751 .arl_buckets = 256, 2752 .imp_port = 8, 2753 .vta_regs = B53_VTA_REGS, 2754 .duplex_reg = B53_DUPLEX_STAT_GE, 2755 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2756 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2757 }, 2758 { 2759 .chip_id = BCM7445_DEVICE_ID, 2760 .dev_name = "BCM7445", 2761 .vlans = 4096, 2762 .enabled_ports = 0x1ff, 2763 .arl_bins = 4, 2764 .arl_buckets = 1024, 2765 .imp_port = 8, 2766 .vta_regs = B53_VTA_REGS, 2767 .duplex_reg = B53_DUPLEX_STAT_GE, 2768 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2769 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2770 }, 2771 { 2772 .chip_id = BCM7278_DEVICE_ID, 2773 .dev_name = "BCM7278", 2774 .vlans = 4096, 2775 .enabled_ports = 0x1ff, 2776 .arl_bins = 4, 2777 .arl_buckets = 256, 2778 .imp_port = 8, 2779 .vta_regs = B53_VTA_REGS, 2780 .duplex_reg = B53_DUPLEX_STAT_GE, 2781 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2782 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2783 }, 2784 { 2785 .chip_id = BCM53134_DEVICE_ID, 2786 .dev_name = "BCM53134", 2787 .vlans = 4096, 2788 .enabled_ports = 0x12f, 2789 .imp_port = 8, 2790 .cpu_port = B53_CPU_PORT, 2791 .vta_regs = B53_VTA_REGS, 2792 .arl_bins = 4, 2793 .arl_buckets = 1024, 2794 .duplex_reg = B53_DUPLEX_STAT_GE, 2795 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2796 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2797 }, 2798 }; 2799 2800 static int b53_switch_init(struct b53_device *dev) 2801 { 2802 unsigned int i; 2803 int ret; 2804 2805 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) { 2806 const struct b53_chip_data *chip = &b53_switch_chips[i]; 2807 2808 if (chip->chip_id == dev->chip_id) { 2809 if (!dev->enabled_ports) 2810 dev->enabled_ports = chip->enabled_ports; 2811 dev->name = chip->dev_name; 2812 dev->duplex_reg = chip->duplex_reg; 2813 dev->vta_regs[0] = chip->vta_regs[0]; 2814 dev->vta_regs[1] = chip->vta_regs[1]; 2815 dev->vta_regs[2] = chip->vta_regs[2]; 2816 dev->jumbo_pm_reg = chip->jumbo_pm_reg; 2817 dev->imp_port = chip->imp_port; 2818 dev->num_vlans = chip->vlans; 2819 dev->num_arl_bins = chip->arl_bins; 2820 dev->num_arl_buckets = chip->arl_buckets; 2821 break; 2822 } 2823 } 2824 2825 /* check which BCM5325x version we have */ 2826 if (is5325(dev)) { 2827 u8 vc4; 2828 2829 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 2830 2831 /* check reserved bits */ 2832 switch (vc4 & 3) { 2833 case 1: 2834 /* BCM5325E */ 2835 break; 2836 case 3: 2837 /* BCM5325F - do not use port 4 */ 2838 dev->enabled_ports &= ~BIT(4); 2839 break; 2840 default: 2841 /* On the BCM47XX SoCs this is the supported internal switch.*/ 2842 #ifndef CONFIG_BCM47XX 2843 /* BCM5325M */ 2844 return -EINVAL; 2845 #else 2846 break; 2847 #endif 2848 } 2849 } 2850 2851 dev->num_ports = fls(dev->enabled_ports); 2852 2853 dev->ds->num_ports = min_t(unsigned int, dev->num_ports, DSA_MAX_PORTS); 2854 2855 /* Include non standard CPU port built-in PHYs to be probed */ 2856 if (is539x(dev) || is531x5(dev)) { 2857 for (i = 0; i < dev->num_ports; i++) { 2858 if (!(dev->ds->phys_mii_mask & BIT(i)) && 2859 !b53_possible_cpu_port(dev->ds, i)) 2860 dev->ds->phys_mii_mask |= BIT(i); 2861 } 2862 } 2863 2864 dev->ports = devm_kcalloc(dev->dev, 2865 dev->num_ports, sizeof(struct b53_port), 2866 GFP_KERNEL); 2867 if (!dev->ports) 2868 return -ENOMEM; 2869 2870 dev->vlans = devm_kcalloc(dev->dev, 2871 dev->num_vlans, sizeof(struct b53_vlan), 2872 GFP_KERNEL); 2873 if (!dev->vlans) 2874 return -ENOMEM; 2875 2876 dev->reset_gpio = b53_switch_get_reset_gpio(dev); 2877 if (dev->reset_gpio >= 0) { 2878 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio, 2879 GPIOF_OUT_INIT_HIGH, "robo_reset"); 2880 if (ret) 2881 return ret; 2882 } 2883 2884 return 0; 2885 } 2886 2887 struct b53_device *b53_switch_alloc(struct device *base, 2888 const struct b53_io_ops *ops, 2889 void *priv) 2890 { 2891 struct dsa_switch *ds; 2892 struct b53_device *dev; 2893 2894 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 2895 if (!ds) 2896 return NULL; 2897 2898 ds->dev = base; 2899 2900 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL); 2901 if (!dev) 2902 return NULL; 2903 2904 ds->priv = dev; 2905 dev->dev = base; 2906 2907 dev->ds = ds; 2908 dev->priv = priv; 2909 dev->ops = ops; 2910 ds->ops = &b53_switch_ops; 2911 ds->phylink_mac_ops = &b53_phylink_mac_ops; 2912 dev->vlan_enabled = true; 2913 dev->vlan_filtering = false; 2914 /* Let DSA handle the case were multiple bridges span the same switch 2915 * device and different VLAN awareness settings are requested, which 2916 * would be breaking filtering semantics for any of the other bridge 2917 * devices. (not hardware supported) 2918 */ 2919 ds->vlan_filtering_is_global = true; 2920 2921 mutex_init(&dev->reg_mutex); 2922 mutex_init(&dev->stats_mutex); 2923 mutex_init(&dev->arl_mutex); 2924 2925 return dev; 2926 } 2927 EXPORT_SYMBOL(b53_switch_alloc); 2928 2929 int b53_switch_detect(struct b53_device *dev) 2930 { 2931 u32 id32; 2932 u16 tmp; 2933 u8 id8; 2934 int ret; 2935 2936 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8); 2937 if (ret) 2938 return ret; 2939 2940 switch (id8) { 2941 case 0: 2942 /* BCM5325 and BCM5365 do not have this register so reads 2943 * return 0. But the read operation did succeed, so assume this 2944 * is one of them. 2945 * 2946 * Next check if we can write to the 5325's VTA register; for 2947 * 5365 it is read only. 2948 */ 2949 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf); 2950 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp); 2951 2952 if (tmp == 0xf) 2953 dev->chip_id = BCM5325_DEVICE_ID; 2954 else 2955 dev->chip_id = BCM5365_DEVICE_ID; 2956 break; 2957 case BCM5389_DEVICE_ID: 2958 case BCM5395_DEVICE_ID: 2959 case BCM5397_DEVICE_ID: 2960 case BCM5398_DEVICE_ID: 2961 dev->chip_id = id8; 2962 break; 2963 default: 2964 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32); 2965 if (ret) 2966 return ret; 2967 2968 switch (id32) { 2969 case BCM53101_DEVICE_ID: 2970 case BCM53115_DEVICE_ID: 2971 case BCM53125_DEVICE_ID: 2972 case BCM53128_DEVICE_ID: 2973 case BCM53010_DEVICE_ID: 2974 case BCM53011_DEVICE_ID: 2975 case BCM53012_DEVICE_ID: 2976 case BCM53018_DEVICE_ID: 2977 case BCM53019_DEVICE_ID: 2978 case BCM53134_DEVICE_ID: 2979 dev->chip_id = id32; 2980 break; 2981 default: 2982 dev_err(dev->dev, 2983 "unsupported switch detected (BCM53%02x/BCM%x)\n", 2984 id8, id32); 2985 return -ENODEV; 2986 } 2987 } 2988 2989 if (dev->chip_id == BCM5325_DEVICE_ID) 2990 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25, 2991 &dev->core_rev); 2992 else 2993 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID, 2994 &dev->core_rev); 2995 } 2996 EXPORT_SYMBOL(b53_switch_detect); 2997 2998 int b53_switch_register(struct b53_device *dev) 2999 { 3000 int ret; 3001 3002 if (dev->pdata) { 3003 dev->chip_id = dev->pdata->chip_id; 3004 dev->enabled_ports = dev->pdata->enabled_ports; 3005 } 3006 3007 if (!dev->chip_id && b53_switch_detect(dev)) 3008 return -EINVAL; 3009 3010 ret = b53_switch_init(dev); 3011 if (ret) 3012 return ret; 3013 3014 dev_info(dev->dev, "found switch: %s, rev %i\n", 3015 dev->name, dev->core_rev); 3016 3017 return dsa_register_switch(dev->ds); 3018 } 3019 EXPORT_SYMBOL(b53_switch_register); 3020 3021 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>"); 3022 MODULE_DESCRIPTION("B53 switch library"); 3023 MODULE_LICENSE("Dual BSD/GPL"); 3024