1 /* 2 * B53 switch driver main logic 3 * 4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org> 5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com> 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <linux/delay.h> 21 #include <linux/export.h> 22 #include <linux/gpio.h> 23 #include <linux/kernel.h> 24 #include <linux/math.h> 25 #include <linux/module.h> 26 #include <linux/platform_data/b53.h> 27 #include <linux/phy.h> 28 #include <linux/phylink.h> 29 #include <linux/etherdevice.h> 30 #include <linux/if_bridge.h> 31 #include <linux/if_vlan.h> 32 #include <net/dsa.h> 33 34 #include "b53_regs.h" 35 #include "b53_priv.h" 36 37 struct b53_mib_desc { 38 u8 size; 39 u8 offset; 40 const char *name; 41 }; 42 43 /* BCM5365 MIB counters */ 44 static const struct b53_mib_desc b53_mibs_65[] = { 45 { 8, 0x00, "TxOctets" }, 46 { 4, 0x08, "TxDropPkts" }, 47 { 4, 0x10, "TxBroadcastPkts" }, 48 { 4, 0x14, "TxMulticastPkts" }, 49 { 4, 0x18, "TxUnicastPkts" }, 50 { 4, 0x1c, "TxCollisions" }, 51 { 4, 0x20, "TxSingleCollision" }, 52 { 4, 0x24, "TxMultipleCollision" }, 53 { 4, 0x28, "TxDeferredTransmit" }, 54 { 4, 0x2c, "TxLateCollision" }, 55 { 4, 0x30, "TxExcessiveCollision" }, 56 { 4, 0x38, "TxPausePkts" }, 57 { 8, 0x44, "RxOctets" }, 58 { 4, 0x4c, "RxUndersizePkts" }, 59 { 4, 0x50, "RxPausePkts" }, 60 { 4, 0x54, "Pkts64Octets" }, 61 { 4, 0x58, "Pkts65to127Octets" }, 62 { 4, 0x5c, "Pkts128to255Octets" }, 63 { 4, 0x60, "Pkts256to511Octets" }, 64 { 4, 0x64, "Pkts512to1023Octets" }, 65 { 4, 0x68, "Pkts1024to1522Octets" }, 66 { 4, 0x6c, "RxOversizePkts" }, 67 { 4, 0x70, "RxJabbers" }, 68 { 4, 0x74, "RxAlignmentErrors" }, 69 { 4, 0x78, "RxFCSErrors" }, 70 { 8, 0x7c, "RxGoodOctets" }, 71 { 4, 0x84, "RxDropPkts" }, 72 { 4, 0x88, "RxUnicastPkts" }, 73 { 4, 0x8c, "RxMulticastPkts" }, 74 { 4, 0x90, "RxBroadcastPkts" }, 75 { 4, 0x94, "RxSAChanges" }, 76 { 4, 0x98, "RxFragments" }, 77 }; 78 79 #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65) 80 81 /* BCM63xx MIB counters */ 82 static const struct b53_mib_desc b53_mibs_63xx[] = { 83 { 8, 0x00, "TxOctets" }, 84 { 4, 0x08, "TxDropPkts" }, 85 { 4, 0x0c, "TxQoSPkts" }, 86 { 4, 0x10, "TxBroadcastPkts" }, 87 { 4, 0x14, "TxMulticastPkts" }, 88 { 4, 0x18, "TxUnicastPkts" }, 89 { 4, 0x1c, "TxCollisions" }, 90 { 4, 0x20, "TxSingleCollision" }, 91 { 4, 0x24, "TxMultipleCollision" }, 92 { 4, 0x28, "TxDeferredTransmit" }, 93 { 4, 0x2c, "TxLateCollision" }, 94 { 4, 0x30, "TxExcessiveCollision" }, 95 { 4, 0x38, "TxPausePkts" }, 96 { 8, 0x3c, "TxQoSOctets" }, 97 { 8, 0x44, "RxOctets" }, 98 { 4, 0x4c, "RxUndersizePkts" }, 99 { 4, 0x50, "RxPausePkts" }, 100 { 4, 0x54, "Pkts64Octets" }, 101 { 4, 0x58, "Pkts65to127Octets" }, 102 { 4, 0x5c, "Pkts128to255Octets" }, 103 { 4, 0x60, "Pkts256to511Octets" }, 104 { 4, 0x64, "Pkts512to1023Octets" }, 105 { 4, 0x68, "Pkts1024to1522Octets" }, 106 { 4, 0x6c, "RxOversizePkts" }, 107 { 4, 0x70, "RxJabbers" }, 108 { 4, 0x74, "RxAlignmentErrors" }, 109 { 4, 0x78, "RxFCSErrors" }, 110 { 8, 0x7c, "RxGoodOctets" }, 111 { 4, 0x84, "RxDropPkts" }, 112 { 4, 0x88, "RxUnicastPkts" }, 113 { 4, 0x8c, "RxMulticastPkts" }, 114 { 4, 0x90, "RxBroadcastPkts" }, 115 { 4, 0x94, "RxSAChanges" }, 116 { 4, 0x98, "RxFragments" }, 117 { 4, 0xa0, "RxSymbolErrors" }, 118 { 4, 0xa4, "RxQoSPkts" }, 119 { 8, 0xa8, "RxQoSOctets" }, 120 { 4, 0xb0, "Pkts1523to2047Octets" }, 121 { 4, 0xb4, "Pkts2048to4095Octets" }, 122 { 4, 0xb8, "Pkts4096to8191Octets" }, 123 { 4, 0xbc, "Pkts8192to9728Octets" }, 124 { 4, 0xc0, "RxDiscarded" }, 125 }; 126 127 #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx) 128 129 /* MIB counters */ 130 static const struct b53_mib_desc b53_mibs[] = { 131 { 8, 0x00, "TxOctets" }, 132 { 4, 0x08, "TxDropPkts" }, 133 { 4, 0x10, "TxBroadcastPkts" }, 134 { 4, 0x14, "TxMulticastPkts" }, 135 { 4, 0x18, "TxUnicastPkts" }, 136 { 4, 0x1c, "TxCollisions" }, 137 { 4, 0x20, "TxSingleCollision" }, 138 { 4, 0x24, "TxMultipleCollision" }, 139 { 4, 0x28, "TxDeferredTransmit" }, 140 { 4, 0x2c, "TxLateCollision" }, 141 { 4, 0x30, "TxExcessiveCollision" }, 142 { 4, 0x38, "TxPausePkts" }, 143 { 8, 0x50, "RxOctets" }, 144 { 4, 0x58, "RxUndersizePkts" }, 145 { 4, 0x5c, "RxPausePkts" }, 146 { 4, 0x60, "Pkts64Octets" }, 147 { 4, 0x64, "Pkts65to127Octets" }, 148 { 4, 0x68, "Pkts128to255Octets" }, 149 { 4, 0x6c, "Pkts256to511Octets" }, 150 { 4, 0x70, "Pkts512to1023Octets" }, 151 { 4, 0x74, "Pkts1024to1522Octets" }, 152 { 4, 0x78, "RxOversizePkts" }, 153 { 4, 0x7c, "RxJabbers" }, 154 { 4, 0x80, "RxAlignmentErrors" }, 155 { 4, 0x84, "RxFCSErrors" }, 156 { 8, 0x88, "RxGoodOctets" }, 157 { 4, 0x90, "RxDropPkts" }, 158 { 4, 0x94, "RxUnicastPkts" }, 159 { 4, 0x98, "RxMulticastPkts" }, 160 { 4, 0x9c, "RxBroadcastPkts" }, 161 { 4, 0xa0, "RxSAChanges" }, 162 { 4, 0xa4, "RxFragments" }, 163 { 4, 0xa8, "RxJumboPkts" }, 164 { 4, 0xac, "RxSymbolErrors" }, 165 { 4, 0xc0, "RxDiscarded" }, 166 }; 167 168 #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs) 169 170 static const struct b53_mib_desc b53_mibs_58xx[] = { 171 { 8, 0x00, "TxOctets" }, 172 { 4, 0x08, "TxDropPkts" }, 173 { 4, 0x0c, "TxQPKTQ0" }, 174 { 4, 0x10, "TxBroadcastPkts" }, 175 { 4, 0x14, "TxMulticastPkts" }, 176 { 4, 0x18, "TxUnicastPKts" }, 177 { 4, 0x1c, "TxCollisions" }, 178 { 4, 0x20, "TxSingleCollision" }, 179 { 4, 0x24, "TxMultipleCollision" }, 180 { 4, 0x28, "TxDeferredCollision" }, 181 { 4, 0x2c, "TxLateCollision" }, 182 { 4, 0x30, "TxExcessiveCollision" }, 183 { 4, 0x34, "TxFrameInDisc" }, 184 { 4, 0x38, "TxPausePkts" }, 185 { 4, 0x3c, "TxQPKTQ1" }, 186 { 4, 0x40, "TxQPKTQ2" }, 187 { 4, 0x44, "TxQPKTQ3" }, 188 { 4, 0x48, "TxQPKTQ4" }, 189 { 4, 0x4c, "TxQPKTQ5" }, 190 { 8, 0x50, "RxOctets" }, 191 { 4, 0x58, "RxUndersizePkts" }, 192 { 4, 0x5c, "RxPausePkts" }, 193 { 4, 0x60, "RxPkts64Octets" }, 194 { 4, 0x64, "RxPkts65to127Octets" }, 195 { 4, 0x68, "RxPkts128to255Octets" }, 196 { 4, 0x6c, "RxPkts256to511Octets" }, 197 { 4, 0x70, "RxPkts512to1023Octets" }, 198 { 4, 0x74, "RxPkts1024toMaxPktsOctets" }, 199 { 4, 0x78, "RxOversizePkts" }, 200 { 4, 0x7c, "RxJabbers" }, 201 { 4, 0x80, "RxAlignmentErrors" }, 202 { 4, 0x84, "RxFCSErrors" }, 203 { 8, 0x88, "RxGoodOctets" }, 204 { 4, 0x90, "RxDropPkts" }, 205 { 4, 0x94, "RxUnicastPkts" }, 206 { 4, 0x98, "RxMulticastPkts" }, 207 { 4, 0x9c, "RxBroadcastPkts" }, 208 { 4, 0xa0, "RxSAChanges" }, 209 { 4, 0xa4, "RxFragments" }, 210 { 4, 0xa8, "RxJumboPkt" }, 211 { 4, 0xac, "RxSymblErr" }, 212 { 4, 0xb0, "InRangeErrCount" }, 213 { 4, 0xb4, "OutRangeErrCount" }, 214 { 4, 0xb8, "EEELpiEvent" }, 215 { 4, 0xbc, "EEELpiDuration" }, 216 { 4, 0xc0, "RxDiscard" }, 217 { 4, 0xc8, "TxQPKTQ6" }, 218 { 4, 0xcc, "TxQPKTQ7" }, 219 { 4, 0xd0, "TxPkts64Octets" }, 220 { 4, 0xd4, "TxPkts65to127Octets" }, 221 { 4, 0xd8, "TxPkts128to255Octets" }, 222 { 4, 0xdc, "TxPkts256to511Ocets" }, 223 { 4, 0xe0, "TxPkts512to1023Ocets" }, 224 { 4, 0xe4, "TxPkts1024toMaxPktOcets" }, 225 }; 226 227 #define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx) 228 229 #define B53_MAX_MTU_25 (1536 - ETH_HLEN - VLAN_HLEN - ETH_FCS_LEN) 230 #define B53_MAX_MTU (9720 - ETH_HLEN - VLAN_HLEN - ETH_FCS_LEN) 231 232 static int b53_do_vlan_op(struct b53_device *dev, u8 op) 233 { 234 unsigned int i; 235 236 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op); 237 238 for (i = 0; i < 10; i++) { 239 u8 vta; 240 241 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta); 242 if (!(vta & VTA_START_CMD)) 243 return 0; 244 245 usleep_range(100, 200); 246 } 247 248 return -EIO; 249 } 250 251 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, 252 struct b53_vlan *vlan) 253 { 254 if (is5325(dev)) { 255 u32 entry = 0; 256 257 if (vlan->members) { 258 entry = ((vlan->untag & VA_UNTAG_MASK_25) << 259 VA_UNTAG_S_25) | vlan->members; 260 if (dev->core_rev >= 3) 261 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S; 262 else 263 entry |= VA_VALID_25; 264 } 265 266 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry); 267 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 268 VTA_RW_STATE_WR | VTA_RW_OP_EN); 269 } else if (is5365(dev)) { 270 u16 entry = 0; 271 272 if (vlan->members) 273 entry = ((vlan->untag & VA_UNTAG_MASK_65) << 274 VA_UNTAG_S_65) | vlan->members | VA_VALID_65; 275 276 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry); 277 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 278 VTA_RW_STATE_WR | VTA_RW_OP_EN); 279 } else { 280 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 281 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], 282 (vlan->untag << VTE_UNTAG_S) | vlan->members); 283 284 b53_do_vlan_op(dev, VTA_CMD_WRITE); 285 } 286 287 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n", 288 vid, vlan->members, vlan->untag); 289 } 290 291 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid, 292 struct b53_vlan *vlan) 293 { 294 if (is5325(dev)) { 295 u32 entry = 0; 296 297 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 298 VTA_RW_STATE_RD | VTA_RW_OP_EN); 299 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry); 300 301 if (dev->core_rev >= 3) 302 vlan->valid = !!(entry & VA_VALID_25_R4); 303 else 304 vlan->valid = !!(entry & VA_VALID_25); 305 vlan->members = entry & VA_MEMBER_MASK; 306 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25; 307 308 } else if (is5365(dev)) { 309 u16 entry = 0; 310 311 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 312 VTA_RW_STATE_WR | VTA_RW_OP_EN); 313 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry); 314 315 vlan->valid = !!(entry & VA_VALID_65); 316 vlan->members = entry & VA_MEMBER_MASK; 317 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65; 318 } else { 319 u32 entry = 0; 320 321 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 322 b53_do_vlan_op(dev, VTA_CMD_READ); 323 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry); 324 vlan->members = entry & VTE_MEMBERS; 325 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS; 326 vlan->valid = true; 327 } 328 } 329 330 static void b53_set_forwarding(struct b53_device *dev, int enable) 331 { 332 u8 mgmt; 333 334 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 335 336 if (enable) 337 mgmt |= SM_SW_FWD_EN; 338 else 339 mgmt &= ~SM_SW_FWD_EN; 340 341 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 342 343 /* Include IMP port in dumb forwarding mode 344 */ 345 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt); 346 mgmt |= B53_MII_DUMB_FWDG_EN; 347 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt); 348 349 /* Look at B53_UC_FWD_EN and B53_MC_FWD_EN to decide whether 350 * frames should be flooded or not. 351 */ 352 b53_read8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, &mgmt); 353 mgmt |= B53_UC_FWD_EN | B53_MC_FWD_EN | B53_IPMC_FWD_EN; 354 b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt); 355 } 356 357 static void b53_enable_vlan(struct b53_device *dev, int port, bool enable, 358 bool enable_filtering) 359 { 360 u8 mgmt, vc0, vc1, vc4 = 0, vc5; 361 362 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 363 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0); 364 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1); 365 366 if (is5325(dev) || is5365(dev)) { 367 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 368 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5); 369 } else if (is63xx(dev)) { 370 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4); 371 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5); 372 } else { 373 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4); 374 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5); 375 } 376 377 vc1 &= ~VC1_RX_MCST_FWD_EN; 378 379 if (enable) { 380 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID; 381 vc1 |= VC1_RX_MCST_UNTAG_EN; 382 vc4 &= ~VC4_ING_VID_CHECK_MASK; 383 if (enable_filtering) { 384 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S; 385 vc5 |= VC5_DROP_VTABLE_MISS; 386 } else { 387 vc4 |= VC4_NO_ING_VID_CHK << VC4_ING_VID_CHECK_S; 388 vc5 &= ~VC5_DROP_VTABLE_MISS; 389 } 390 391 if (is5325(dev)) 392 vc0 &= ~VC0_RESERVED_1; 393 394 if (is5325(dev) || is5365(dev)) 395 vc1 |= VC1_RX_MCST_TAG_EN; 396 397 } else { 398 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID); 399 vc1 &= ~VC1_RX_MCST_UNTAG_EN; 400 vc4 &= ~VC4_ING_VID_CHECK_MASK; 401 vc5 &= ~VC5_DROP_VTABLE_MISS; 402 403 if (is5325(dev) || is5365(dev)) 404 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 405 else 406 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S; 407 408 if (is5325(dev) || is5365(dev)) 409 vc1 &= ~VC1_RX_MCST_TAG_EN; 410 } 411 412 if (!is5325(dev) && !is5365(dev)) 413 vc5 &= ~VC5_VID_FFF_EN; 414 415 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0); 416 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1); 417 418 if (is5325(dev) || is5365(dev)) { 419 /* enable the high 8 bit vid check on 5325 */ 420 if (is5325(dev) && enable) 421 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 422 VC3_HIGH_8BIT_EN); 423 else 424 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 425 426 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4); 427 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5); 428 } else if (is63xx(dev)) { 429 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0); 430 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4); 431 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5); 432 } else { 433 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 434 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4); 435 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5); 436 } 437 438 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 439 440 dev->vlan_enabled = enable; 441 442 dev_dbg(dev->dev, "Port %d VLAN enabled: %d, filtering: %d\n", 443 port, enable, enable_filtering); 444 } 445 446 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100) 447 { 448 u32 port_mask = 0; 449 u16 max_size = JMS_MIN_SIZE; 450 451 if (is5325(dev) || is5365(dev)) 452 return -EINVAL; 453 454 if (enable) { 455 port_mask = dev->enabled_ports; 456 max_size = JMS_MAX_SIZE; 457 if (allow_10_100) 458 port_mask |= JPM_10_100_JUMBO_EN; 459 } 460 461 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask); 462 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size); 463 } 464 465 static int b53_flush_arl(struct b53_device *dev, u8 mask) 466 { 467 unsigned int i; 468 469 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 470 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask); 471 472 for (i = 0; i < 10; i++) { 473 u8 fast_age_ctrl; 474 475 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 476 &fast_age_ctrl); 477 478 if (!(fast_age_ctrl & FAST_AGE_DONE)) 479 goto out; 480 481 msleep(1); 482 } 483 484 return -ETIMEDOUT; 485 out: 486 /* Only age dynamic entries (default behavior) */ 487 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC); 488 return 0; 489 } 490 491 static int b53_fast_age_port(struct b53_device *dev, int port) 492 { 493 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port); 494 495 return b53_flush_arl(dev, FAST_AGE_PORT); 496 } 497 498 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid) 499 { 500 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid); 501 502 return b53_flush_arl(dev, FAST_AGE_VLAN); 503 } 504 505 void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port) 506 { 507 struct b53_device *dev = ds->priv; 508 unsigned int i; 509 u16 pvlan; 510 511 /* Enable the IMP port to be in the same VLAN as the other ports 512 * on a per-port basis such that we only have Port i and IMP in 513 * the same VLAN. 514 */ 515 b53_for_each_port(dev, i) { 516 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan); 517 pvlan |= BIT(cpu_port); 518 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan); 519 } 520 } 521 EXPORT_SYMBOL(b53_imp_vlan_setup); 522 523 static void b53_port_set_ucast_flood(struct b53_device *dev, int port, 524 bool unicast) 525 { 526 u16 uc; 527 528 b53_read16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, &uc); 529 if (unicast) 530 uc |= BIT(port); 531 else 532 uc &= ~BIT(port); 533 b53_write16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, uc); 534 } 535 536 static void b53_port_set_mcast_flood(struct b53_device *dev, int port, 537 bool multicast) 538 { 539 u16 mc; 540 541 b53_read16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, &mc); 542 if (multicast) 543 mc |= BIT(port); 544 else 545 mc &= ~BIT(port); 546 b53_write16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, mc); 547 548 b53_read16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, &mc); 549 if (multicast) 550 mc |= BIT(port); 551 else 552 mc &= ~BIT(port); 553 b53_write16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, mc); 554 } 555 556 static void b53_port_set_learning(struct b53_device *dev, int port, 557 bool learning) 558 { 559 u16 reg; 560 561 b53_read16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, ®); 562 if (learning) 563 reg &= ~BIT(port); 564 else 565 reg |= BIT(port); 566 b53_write16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, reg); 567 } 568 569 static void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable) 570 { 571 struct b53_device *dev = ds->priv; 572 u16 reg; 573 574 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, ®); 575 if (enable) 576 reg |= BIT(port); 577 else 578 reg &= ~BIT(port); 579 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg); 580 } 581 582 int b53_setup_port(struct dsa_switch *ds, int port) 583 { 584 struct b53_device *dev = ds->priv; 585 586 b53_port_set_ucast_flood(dev, port, true); 587 b53_port_set_mcast_flood(dev, port, true); 588 b53_port_set_learning(dev, port, false); 589 590 return 0; 591 } 592 EXPORT_SYMBOL(b53_setup_port); 593 594 int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy) 595 { 596 struct b53_device *dev = ds->priv; 597 unsigned int cpu_port; 598 int ret = 0; 599 u16 pvlan; 600 601 if (!dsa_is_user_port(ds, port)) 602 return 0; 603 604 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 605 606 if (dev->ops->irq_enable) 607 ret = dev->ops->irq_enable(dev, port); 608 if (ret) 609 return ret; 610 611 /* Clear the Rx and Tx disable bits and set to no spanning tree */ 612 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0); 613 614 /* Set this port, and only this one to be in the default VLAN, 615 * if member of a bridge, restore its membership prior to 616 * bringing down this port. 617 */ 618 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 619 pvlan &= ~0x1ff; 620 pvlan |= BIT(port); 621 pvlan |= dev->ports[port].vlan_ctl_mask; 622 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 623 624 b53_imp_vlan_setup(ds, cpu_port); 625 626 /* If EEE was enabled, restore it */ 627 if (dev->ports[port].eee.eee_enabled) 628 b53_eee_enable_set(ds, port, true); 629 630 return 0; 631 } 632 EXPORT_SYMBOL(b53_enable_port); 633 634 void b53_disable_port(struct dsa_switch *ds, int port) 635 { 636 struct b53_device *dev = ds->priv; 637 u8 reg; 638 639 /* Disable Tx/Rx for the port */ 640 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 641 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE; 642 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 643 644 if (dev->ops->irq_disable) 645 dev->ops->irq_disable(dev, port); 646 } 647 EXPORT_SYMBOL(b53_disable_port); 648 649 void b53_brcm_hdr_setup(struct dsa_switch *ds, int port) 650 { 651 struct b53_device *dev = ds->priv; 652 bool tag_en = !(dev->tag_protocol == DSA_TAG_PROTO_NONE); 653 u8 hdr_ctl, val; 654 u16 reg; 655 656 /* Resolve which bit controls the Broadcom tag */ 657 switch (port) { 658 case 8: 659 val = BRCM_HDR_P8_EN; 660 break; 661 case 7: 662 val = BRCM_HDR_P7_EN; 663 break; 664 case 5: 665 val = BRCM_HDR_P5_EN; 666 break; 667 default: 668 val = 0; 669 break; 670 } 671 672 /* Enable management mode if tagging is requested */ 673 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &hdr_ctl); 674 if (tag_en) 675 hdr_ctl |= SM_SW_FWD_MODE; 676 else 677 hdr_ctl &= ~SM_SW_FWD_MODE; 678 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, hdr_ctl); 679 680 /* Configure the appropriate IMP port */ 681 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &hdr_ctl); 682 if (port == 8) 683 hdr_ctl |= GC_FRM_MGMT_PORT_MII; 684 else if (port == 5) 685 hdr_ctl |= GC_FRM_MGMT_PORT_M; 686 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, hdr_ctl); 687 688 /* Enable Broadcom tags for IMP port */ 689 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl); 690 if (tag_en) 691 hdr_ctl |= val; 692 else 693 hdr_ctl &= ~val; 694 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl); 695 696 /* Registers below are only accessible on newer devices */ 697 if (!is58xx(dev)) 698 return; 699 700 /* Enable reception Broadcom tag for CPU TX (switch RX) to 701 * allow us to tag outgoing frames 702 */ 703 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, ®); 704 if (tag_en) 705 reg &= ~BIT(port); 706 else 707 reg |= BIT(port); 708 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg); 709 710 /* Enable transmission of Broadcom tags from the switch (CPU RX) to 711 * allow delivering frames to the per-port net_devices 712 */ 713 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, ®); 714 if (tag_en) 715 reg &= ~BIT(port); 716 else 717 reg |= BIT(port); 718 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg); 719 } 720 EXPORT_SYMBOL(b53_brcm_hdr_setup); 721 722 static void b53_enable_cpu_port(struct b53_device *dev, int port) 723 { 724 u8 port_ctrl; 725 726 /* BCM5325 CPU port is at 8 */ 727 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25) 728 port = B53_CPU_PORT; 729 730 port_ctrl = PORT_CTRL_RX_BCST_EN | 731 PORT_CTRL_RX_MCST_EN | 732 PORT_CTRL_RX_UCST_EN; 733 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl); 734 735 b53_brcm_hdr_setup(dev->ds, port); 736 } 737 738 static void b53_enable_mib(struct b53_device *dev) 739 { 740 u8 gc; 741 742 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 743 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN); 744 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc); 745 } 746 747 static void b53_enable_stp(struct b53_device *dev) 748 { 749 u8 gc; 750 751 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 752 gc |= GC_RX_BPDU_EN; 753 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc); 754 } 755 756 static u16 b53_default_pvid(struct b53_device *dev) 757 { 758 if (is5325(dev) || is5365(dev)) 759 return 1; 760 else 761 return 0; 762 } 763 764 static bool b53_vlan_port_needs_forced_tagged(struct dsa_switch *ds, int port) 765 { 766 struct b53_device *dev = ds->priv; 767 768 return dev->tag_protocol == DSA_TAG_PROTO_NONE && dsa_is_cpu_port(ds, port); 769 } 770 771 static bool b53_vlan_port_may_join_untagged(struct dsa_switch *ds, int port) 772 { 773 struct b53_device *dev = ds->priv; 774 struct dsa_port *dp; 775 776 if (!dev->vlan_filtering) 777 return true; 778 779 dp = dsa_to_port(ds, port); 780 781 if (dsa_port_is_cpu(dp)) 782 return true; 783 784 return dp->bridge == NULL; 785 } 786 787 int b53_configure_vlan(struct dsa_switch *ds) 788 { 789 struct b53_device *dev = ds->priv; 790 struct b53_vlan vl = { 0 }; 791 struct b53_vlan *v; 792 int i, def_vid; 793 u16 vid; 794 795 def_vid = b53_default_pvid(dev); 796 797 /* clear all vlan entries */ 798 if (is5325(dev) || is5365(dev)) { 799 for (i = def_vid; i < dev->num_vlans; i++) 800 b53_set_vlan_entry(dev, i, &vl); 801 } else { 802 b53_do_vlan_op(dev, VTA_CMD_CLEAR); 803 } 804 805 b53_enable_vlan(dev, -1, dev->vlan_enabled, dev->vlan_filtering); 806 807 /* Create an untagged VLAN entry for the default PVID in case 808 * CONFIG_VLAN_8021Q is disabled and there are no calls to 809 * dsa_user_vlan_rx_add_vid() to create the default VLAN 810 * entry. Do this only when the tagging protocol is not 811 * DSA_TAG_PROTO_NONE 812 */ 813 v = &dev->vlans[def_vid]; 814 b53_for_each_port(dev, i) { 815 if (!b53_vlan_port_may_join_untagged(ds, i)) 816 continue; 817 818 vl.members |= BIT(i); 819 if (!b53_vlan_port_needs_forced_tagged(ds, i)) 820 vl.untag = vl.members; 821 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(i), 822 def_vid); 823 } 824 b53_set_vlan_entry(dev, def_vid, &vl); 825 826 if (dev->vlan_filtering) { 827 /* Upon initial call we have not set-up any VLANs, but upon 828 * system resume, we need to restore all VLAN entries. 829 */ 830 for (vid = def_vid + 1; vid < dev->num_vlans; vid++) { 831 v = &dev->vlans[vid]; 832 833 if (!v->members) 834 continue; 835 836 b53_set_vlan_entry(dev, vid, v); 837 b53_fast_age_vlan(dev, vid); 838 } 839 840 b53_for_each_port(dev, i) { 841 if (!dsa_is_cpu_port(ds, i)) 842 b53_write16(dev, B53_VLAN_PAGE, 843 B53_VLAN_PORT_DEF_TAG(i), 844 dev->ports[i].pvid); 845 } 846 } 847 848 return 0; 849 } 850 EXPORT_SYMBOL(b53_configure_vlan); 851 852 static void b53_switch_reset_gpio(struct b53_device *dev) 853 { 854 int gpio = dev->reset_gpio; 855 856 if (gpio < 0) 857 return; 858 859 /* Reset sequence: RESET low(50ms)->high(20ms) 860 */ 861 gpio_set_value(gpio, 0); 862 mdelay(50); 863 864 gpio_set_value(gpio, 1); 865 mdelay(20); 866 867 dev->current_page = 0xff; 868 } 869 870 static int b53_switch_reset(struct b53_device *dev) 871 { 872 unsigned int timeout = 1000; 873 u8 mgmt, reg; 874 875 b53_switch_reset_gpio(dev); 876 877 if (is539x(dev)) { 878 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83); 879 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00); 880 } 881 882 /* This is specific to 58xx devices here, do not use is58xx() which 883 * covers the larger Starfigther 2 family, including 7445/7278 which 884 * still use this driver as a library and need to perform the reset 885 * earlier. 886 */ 887 if (dev->chip_id == BCM58XX_DEVICE_ID || 888 dev->chip_id == BCM583XX_DEVICE_ID) { 889 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 890 reg |= SW_RST | EN_SW_RST | EN_CH_RST; 891 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg); 892 893 do { 894 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 895 if (!(reg & SW_RST)) 896 break; 897 898 usleep_range(1000, 2000); 899 } while (timeout-- > 0); 900 901 if (timeout == 0) { 902 dev_err(dev->dev, 903 "Timeout waiting for SW_RST to clear!\n"); 904 return -ETIMEDOUT; 905 } 906 } 907 908 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 909 910 if (!(mgmt & SM_SW_FWD_EN)) { 911 mgmt &= ~SM_SW_FWD_MODE; 912 mgmt |= SM_SW_FWD_EN; 913 914 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 915 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 916 917 if (!(mgmt & SM_SW_FWD_EN)) { 918 dev_err(dev->dev, "Failed to enable switch!\n"); 919 return -EINVAL; 920 } 921 } 922 923 b53_enable_mib(dev); 924 b53_enable_stp(dev); 925 926 return b53_flush_arl(dev, FAST_AGE_STATIC); 927 } 928 929 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg) 930 { 931 struct b53_device *priv = ds->priv; 932 u16 value = 0; 933 int ret; 934 935 if (priv->ops->phy_read16) 936 ret = priv->ops->phy_read16(priv, addr, reg, &value); 937 else 938 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr), 939 reg * 2, &value); 940 941 return ret ? ret : value; 942 } 943 944 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 945 { 946 struct b53_device *priv = ds->priv; 947 948 if (priv->ops->phy_write16) 949 return priv->ops->phy_write16(priv, addr, reg, val); 950 951 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val); 952 } 953 954 static int b53_reset_switch(struct b53_device *priv) 955 { 956 /* reset vlans */ 957 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans); 958 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports); 959 960 priv->serdes_lane = B53_INVALID_LANE; 961 962 return b53_switch_reset(priv); 963 } 964 965 static int b53_apply_config(struct b53_device *priv) 966 { 967 /* disable switching */ 968 b53_set_forwarding(priv, 0); 969 970 b53_configure_vlan(priv->ds); 971 972 /* enable switching */ 973 b53_set_forwarding(priv, 1); 974 975 return 0; 976 } 977 978 static void b53_reset_mib(struct b53_device *priv) 979 { 980 u8 gc; 981 982 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 983 984 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB); 985 msleep(1); 986 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB); 987 msleep(1); 988 } 989 990 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev) 991 { 992 if (is5365(dev)) 993 return b53_mibs_65; 994 else if (is63xx(dev)) 995 return b53_mibs_63xx; 996 else if (is58xx(dev)) 997 return b53_mibs_58xx; 998 else 999 return b53_mibs; 1000 } 1001 1002 static unsigned int b53_get_mib_size(struct b53_device *dev) 1003 { 1004 if (is5365(dev)) 1005 return B53_MIBS_65_SIZE; 1006 else if (is63xx(dev)) 1007 return B53_MIBS_63XX_SIZE; 1008 else if (is58xx(dev)) 1009 return B53_MIBS_58XX_SIZE; 1010 else 1011 return B53_MIBS_SIZE; 1012 } 1013 1014 static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port) 1015 { 1016 /* These ports typically do not have built-in PHYs */ 1017 switch (port) { 1018 case B53_CPU_PORT_25: 1019 case 7: 1020 case B53_CPU_PORT: 1021 return NULL; 1022 } 1023 1024 return mdiobus_get_phy(ds->user_mii_bus, port); 1025 } 1026 1027 void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset, 1028 uint8_t *data) 1029 { 1030 struct b53_device *dev = ds->priv; 1031 const struct b53_mib_desc *mibs = b53_get_mib(dev); 1032 unsigned int mib_size = b53_get_mib_size(dev); 1033 struct phy_device *phydev; 1034 unsigned int i; 1035 1036 if (stringset == ETH_SS_STATS) { 1037 for (i = 0; i < mib_size; i++) 1038 ethtool_puts(&data, mibs[i].name); 1039 } else if (stringset == ETH_SS_PHY_STATS) { 1040 phydev = b53_get_phy_device(ds, port); 1041 if (!phydev) 1042 return; 1043 1044 phy_ethtool_get_strings(phydev, data); 1045 } 1046 } 1047 EXPORT_SYMBOL(b53_get_strings); 1048 1049 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) 1050 { 1051 struct b53_device *dev = ds->priv; 1052 const struct b53_mib_desc *mibs = b53_get_mib(dev); 1053 unsigned int mib_size = b53_get_mib_size(dev); 1054 const struct b53_mib_desc *s; 1055 unsigned int i; 1056 u64 val = 0; 1057 1058 if (is5365(dev) && port == 5) 1059 port = 8; 1060 1061 mutex_lock(&dev->stats_mutex); 1062 1063 for (i = 0; i < mib_size; i++) { 1064 s = &mibs[i]; 1065 1066 if (s->size == 8) { 1067 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val); 1068 } else { 1069 u32 val32; 1070 1071 b53_read32(dev, B53_MIB_PAGE(port), s->offset, 1072 &val32); 1073 val = val32; 1074 } 1075 data[i] = (u64)val; 1076 } 1077 1078 mutex_unlock(&dev->stats_mutex); 1079 } 1080 EXPORT_SYMBOL(b53_get_ethtool_stats); 1081 1082 void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data) 1083 { 1084 struct phy_device *phydev; 1085 1086 phydev = b53_get_phy_device(ds, port); 1087 if (!phydev) 1088 return; 1089 1090 phy_ethtool_get_stats(phydev, NULL, data); 1091 } 1092 EXPORT_SYMBOL(b53_get_ethtool_phy_stats); 1093 1094 int b53_get_sset_count(struct dsa_switch *ds, int port, int sset) 1095 { 1096 struct b53_device *dev = ds->priv; 1097 struct phy_device *phydev; 1098 1099 if (sset == ETH_SS_STATS) { 1100 return b53_get_mib_size(dev); 1101 } else if (sset == ETH_SS_PHY_STATS) { 1102 phydev = b53_get_phy_device(ds, port); 1103 if (!phydev) 1104 return 0; 1105 1106 return phy_ethtool_get_sset_count(phydev); 1107 } 1108 1109 return 0; 1110 } 1111 EXPORT_SYMBOL(b53_get_sset_count); 1112 1113 enum b53_devlink_resource_id { 1114 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1115 }; 1116 1117 static u64 b53_devlink_vlan_table_get(void *priv) 1118 { 1119 struct b53_device *dev = priv; 1120 struct b53_vlan *vl; 1121 unsigned int i; 1122 u64 count = 0; 1123 1124 for (i = 0; i < dev->num_vlans; i++) { 1125 vl = &dev->vlans[i]; 1126 if (vl->members) 1127 count++; 1128 } 1129 1130 return count; 1131 } 1132 1133 int b53_setup_devlink_resources(struct dsa_switch *ds) 1134 { 1135 struct devlink_resource_size_params size_params; 1136 struct b53_device *dev = ds->priv; 1137 int err; 1138 1139 devlink_resource_size_params_init(&size_params, dev->num_vlans, 1140 dev->num_vlans, 1141 1, DEVLINK_RESOURCE_UNIT_ENTRY); 1142 1143 err = dsa_devlink_resource_register(ds, "VLAN", dev->num_vlans, 1144 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1145 DEVLINK_RESOURCE_ID_PARENT_TOP, 1146 &size_params); 1147 if (err) 1148 goto out; 1149 1150 dsa_devlink_resource_occ_get_register(ds, 1151 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1152 b53_devlink_vlan_table_get, dev); 1153 1154 return 0; 1155 out: 1156 dsa_devlink_resources_unregister(ds); 1157 return err; 1158 } 1159 EXPORT_SYMBOL(b53_setup_devlink_resources); 1160 1161 static int b53_setup(struct dsa_switch *ds) 1162 { 1163 struct b53_device *dev = ds->priv; 1164 struct b53_vlan *vl; 1165 unsigned int port; 1166 u16 pvid; 1167 int ret; 1168 1169 /* Request bridge PVID untagged when DSA_TAG_PROTO_NONE is set 1170 * which forces the CPU port to be tagged in all VLANs. 1171 */ 1172 ds->untag_bridge_pvid = dev->tag_protocol == DSA_TAG_PROTO_NONE; 1173 1174 /* The switch does not tell us the original VLAN for untagged 1175 * packets, so keep the CPU port always tagged. 1176 */ 1177 ds->untag_vlan_aware_bridge_pvid = true; 1178 1179 /* Ageing time is set in seconds */ 1180 ds->ageing_time_min = 1 * 1000; 1181 ds->ageing_time_max = AGE_TIME_MAX * 1000; 1182 1183 ret = b53_reset_switch(dev); 1184 if (ret) { 1185 dev_err(ds->dev, "failed to reset switch\n"); 1186 return ret; 1187 } 1188 1189 /* setup default vlan for filtering mode */ 1190 pvid = b53_default_pvid(dev); 1191 vl = &dev->vlans[pvid]; 1192 b53_for_each_port(dev, port) { 1193 vl->members |= BIT(port); 1194 if (!b53_vlan_port_needs_forced_tagged(ds, port)) 1195 vl->untag |= BIT(port); 1196 } 1197 1198 b53_reset_mib(dev); 1199 1200 ret = b53_apply_config(dev); 1201 if (ret) { 1202 dev_err(ds->dev, "failed to apply configuration\n"); 1203 return ret; 1204 } 1205 1206 /* Configure IMP/CPU port, disable all other ports. Enabled 1207 * ports will be configured with .port_enable 1208 */ 1209 for (port = 0; port < dev->num_ports; port++) { 1210 if (dsa_is_cpu_port(ds, port)) 1211 b53_enable_cpu_port(dev, port); 1212 else 1213 b53_disable_port(ds, port); 1214 } 1215 1216 return b53_setup_devlink_resources(ds); 1217 } 1218 1219 static void b53_teardown(struct dsa_switch *ds) 1220 { 1221 dsa_devlink_resources_unregister(ds); 1222 } 1223 1224 static void b53_force_link(struct b53_device *dev, int port, int link) 1225 { 1226 u8 reg, val, off; 1227 1228 /* Override the port settings */ 1229 if (port == dev->imp_port) { 1230 off = B53_PORT_OVERRIDE_CTRL; 1231 val = PORT_OVERRIDE_EN; 1232 } else { 1233 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 1234 val = GMII_PO_EN; 1235 } 1236 1237 b53_read8(dev, B53_CTRL_PAGE, off, ®); 1238 reg |= val; 1239 if (link) 1240 reg |= PORT_OVERRIDE_LINK; 1241 else 1242 reg &= ~PORT_OVERRIDE_LINK; 1243 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1244 } 1245 1246 static void b53_force_port_config(struct b53_device *dev, int port, 1247 int speed, int duplex, 1248 bool tx_pause, bool rx_pause) 1249 { 1250 u8 reg, val, off; 1251 1252 /* Override the port settings */ 1253 if (port == dev->imp_port) { 1254 off = B53_PORT_OVERRIDE_CTRL; 1255 val = PORT_OVERRIDE_EN; 1256 } else { 1257 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 1258 val = GMII_PO_EN; 1259 } 1260 1261 b53_read8(dev, B53_CTRL_PAGE, off, ®); 1262 reg |= val; 1263 if (duplex == DUPLEX_FULL) 1264 reg |= PORT_OVERRIDE_FULL_DUPLEX; 1265 else 1266 reg &= ~PORT_OVERRIDE_FULL_DUPLEX; 1267 1268 switch (speed) { 1269 case 2000: 1270 reg |= PORT_OVERRIDE_SPEED_2000M; 1271 fallthrough; 1272 case SPEED_1000: 1273 reg |= PORT_OVERRIDE_SPEED_1000M; 1274 break; 1275 case SPEED_100: 1276 reg |= PORT_OVERRIDE_SPEED_100M; 1277 break; 1278 case SPEED_10: 1279 reg |= PORT_OVERRIDE_SPEED_10M; 1280 break; 1281 default: 1282 dev_err(dev->dev, "unknown speed: %d\n", speed); 1283 return; 1284 } 1285 1286 if (rx_pause) 1287 reg |= PORT_OVERRIDE_RX_FLOW; 1288 if (tx_pause) 1289 reg |= PORT_OVERRIDE_TX_FLOW; 1290 1291 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1292 } 1293 1294 static void b53_adjust_63xx_rgmii(struct dsa_switch *ds, int port, 1295 phy_interface_t interface) 1296 { 1297 struct b53_device *dev = ds->priv; 1298 u8 rgmii_ctrl = 0, off; 1299 1300 if (port == dev->imp_port) 1301 off = B53_RGMII_CTRL_IMP; 1302 else 1303 off = B53_RGMII_CTRL_P(port); 1304 1305 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl); 1306 1307 switch (interface) { 1308 case PHY_INTERFACE_MODE_RGMII_ID: 1309 rgmii_ctrl |= (RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC); 1310 break; 1311 case PHY_INTERFACE_MODE_RGMII_RXID: 1312 rgmii_ctrl &= ~(RGMII_CTRL_DLL_TXC); 1313 rgmii_ctrl |= RGMII_CTRL_DLL_RXC; 1314 break; 1315 case PHY_INTERFACE_MODE_RGMII_TXID: 1316 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC); 1317 rgmii_ctrl |= RGMII_CTRL_DLL_TXC; 1318 break; 1319 case PHY_INTERFACE_MODE_RGMII: 1320 default: 1321 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC); 1322 break; 1323 } 1324 1325 if (port != dev->imp_port) { 1326 if (is63268(dev)) 1327 rgmii_ctrl |= RGMII_CTRL_MII_OVERRIDE; 1328 1329 rgmii_ctrl |= RGMII_CTRL_ENABLE_GMII; 1330 } 1331 1332 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl); 1333 1334 dev_dbg(ds->dev, "Configured port %d for %s\n", port, 1335 phy_modes(interface)); 1336 } 1337 1338 static void b53_adjust_531x5_rgmii(struct dsa_switch *ds, int port, 1339 phy_interface_t interface) 1340 { 1341 struct b53_device *dev = ds->priv; 1342 u8 rgmii_ctrl = 0, off; 1343 1344 if (port == dev->imp_port) 1345 off = B53_RGMII_CTRL_IMP; 1346 else 1347 off = B53_RGMII_CTRL_P(port); 1348 1349 /* Configure the port RGMII clock delay by DLL disabled and 1350 * tx_clk aligned timing (restoring to reset defaults) 1351 */ 1352 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl); 1353 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC | 1354 RGMII_CTRL_TIMING_SEL); 1355 1356 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make 1357 * sure that we enable the port TX clock internal delay to 1358 * account for this internal delay that is inserted, otherwise 1359 * the switch won't be able to receive correctly. 1360 * 1361 * PHY_INTERFACE_MODE_RGMII means that we are not introducing 1362 * any delay neither on transmission nor reception, so the 1363 * BCM53125 must also be configured accordingly to account for 1364 * the lack of delay and introduce 1365 * 1366 * The BCM53125 switch has its RX clock and TX clock control 1367 * swapped, hence the reason why we modify the TX clock path in 1368 * the "RGMII" case 1369 */ 1370 if (interface == PHY_INTERFACE_MODE_RGMII_TXID) 1371 rgmii_ctrl |= RGMII_CTRL_DLL_TXC; 1372 if (interface == PHY_INTERFACE_MODE_RGMII) 1373 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC; 1374 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL; 1375 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl); 1376 1377 dev_info(ds->dev, "Configured port %d for %s\n", port, 1378 phy_modes(interface)); 1379 } 1380 1381 static void b53_adjust_5325_mii(struct dsa_switch *ds, int port) 1382 { 1383 struct b53_device *dev = ds->priv; 1384 u8 reg = 0; 1385 1386 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1387 ®); 1388 1389 /* reverse mii needs to be enabled */ 1390 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1391 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1392 reg | PORT_OVERRIDE_RV_MII_25); 1393 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1394 ®); 1395 1396 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1397 dev_err(ds->dev, 1398 "Failed to enable reverse MII mode\n"); 1399 return; 1400 } 1401 } 1402 } 1403 1404 void b53_port_event(struct dsa_switch *ds, int port) 1405 { 1406 struct b53_device *dev = ds->priv; 1407 bool link; 1408 u16 sts; 1409 1410 b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts); 1411 link = !!(sts & BIT(port)); 1412 dsa_port_phylink_mac_change(ds, port, link); 1413 } 1414 EXPORT_SYMBOL(b53_port_event); 1415 1416 static void b53_phylink_get_caps(struct dsa_switch *ds, int port, 1417 struct phylink_config *config) 1418 { 1419 struct b53_device *dev = ds->priv; 1420 1421 /* Internal ports need GMII for PHYLIB */ 1422 __set_bit(PHY_INTERFACE_MODE_GMII, config->supported_interfaces); 1423 1424 /* These switches appear to support MII and RevMII too, but beyond 1425 * this, the code gives very few clues. FIXME: We probably need more 1426 * interface modes here. 1427 * 1428 * According to b53_srab_mux_init(), ports 3..5 can support: 1429 * SGMII, MII, GMII, RGMII or INTERNAL depending on the MUX setting. 1430 * However, the interface mode read from the MUX configuration is 1431 * not passed back to DSA, so phylink uses NA. 1432 * DT can specify RGMII for ports 0, 1. 1433 * For MDIO, port 8 can be RGMII_TXID. 1434 */ 1435 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 1436 __set_bit(PHY_INTERFACE_MODE_REVMII, config->supported_interfaces); 1437 1438 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 1439 MAC_10 | MAC_100; 1440 1441 /* 5325/5365 are not capable of gigabit speeds, everything else is. 1442 * Note: the original code also exclulded Gigagbit for MII, RevMII 1443 * and 802.3z modes. MII and RevMII are not able to work above 100M, 1444 * so will be excluded by the generic validator implementation. 1445 * However, the exclusion of Gigabit for 802.3z just seems wrong. 1446 */ 1447 if (!(is5325(dev) || is5365(dev))) 1448 config->mac_capabilities |= MAC_1000; 1449 1450 /* Get the implementation specific capabilities */ 1451 if (dev->ops->phylink_get_caps) 1452 dev->ops->phylink_get_caps(dev, port, config); 1453 } 1454 1455 static struct phylink_pcs *b53_phylink_mac_select_pcs(struct phylink_config *config, 1456 phy_interface_t interface) 1457 { 1458 struct dsa_port *dp = dsa_phylink_to_port(config); 1459 struct b53_device *dev = dp->ds->priv; 1460 1461 if (!dev->ops->phylink_mac_select_pcs) 1462 return NULL; 1463 1464 return dev->ops->phylink_mac_select_pcs(dev, dp->index, interface); 1465 } 1466 1467 static void b53_phylink_mac_config(struct phylink_config *config, 1468 unsigned int mode, 1469 const struct phylink_link_state *state) 1470 { 1471 struct dsa_port *dp = dsa_phylink_to_port(config); 1472 phy_interface_t interface = state->interface; 1473 struct dsa_switch *ds = dp->ds; 1474 struct b53_device *dev = ds->priv; 1475 int port = dp->index; 1476 1477 if (is63xx(dev) && port >= B53_63XX_RGMII0) 1478 b53_adjust_63xx_rgmii(ds, port, interface); 1479 1480 if (mode == MLO_AN_FIXED) { 1481 if (is531x5(dev) && phy_interface_mode_is_rgmii(interface)) 1482 b53_adjust_531x5_rgmii(ds, port, interface); 1483 1484 /* configure MII port if necessary */ 1485 if (is5325(dev)) 1486 b53_adjust_5325_mii(ds, port); 1487 } 1488 } 1489 1490 static void b53_phylink_mac_link_down(struct phylink_config *config, 1491 unsigned int mode, 1492 phy_interface_t interface) 1493 { 1494 struct dsa_port *dp = dsa_phylink_to_port(config); 1495 struct b53_device *dev = dp->ds->priv; 1496 int port = dp->index; 1497 1498 if (mode == MLO_AN_PHY) 1499 return; 1500 1501 if (mode == MLO_AN_FIXED) { 1502 b53_force_link(dev, port, false); 1503 return; 1504 } 1505 1506 if (phy_interface_mode_is_8023z(interface) && 1507 dev->ops->serdes_link_set) 1508 dev->ops->serdes_link_set(dev, port, mode, interface, false); 1509 } 1510 1511 static void b53_phylink_mac_link_up(struct phylink_config *config, 1512 struct phy_device *phydev, 1513 unsigned int mode, 1514 phy_interface_t interface, 1515 int speed, int duplex, 1516 bool tx_pause, bool rx_pause) 1517 { 1518 struct dsa_port *dp = dsa_phylink_to_port(config); 1519 struct dsa_switch *ds = dp->ds; 1520 struct b53_device *dev = ds->priv; 1521 struct ethtool_keee *p = &dev->ports[dp->index].eee; 1522 int port = dp->index; 1523 1524 if (mode == MLO_AN_PHY) { 1525 /* Re-negotiate EEE if it was enabled already */ 1526 p->eee_enabled = b53_eee_init(ds, port, phydev); 1527 return; 1528 } 1529 1530 if (mode == MLO_AN_FIXED) { 1531 /* Force flow control on BCM5301x's CPU port */ 1532 if (is5301x(dev) && dsa_is_cpu_port(ds, port)) 1533 tx_pause = rx_pause = true; 1534 1535 b53_force_port_config(dev, port, speed, duplex, 1536 tx_pause, rx_pause); 1537 b53_force_link(dev, port, true); 1538 return; 1539 } 1540 1541 if (phy_interface_mode_is_8023z(interface) && 1542 dev->ops->serdes_link_set) 1543 dev->ops->serdes_link_set(dev, port, mode, interface, true); 1544 } 1545 1546 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1547 struct netlink_ext_ack *extack) 1548 { 1549 struct b53_device *dev = ds->priv; 1550 1551 if (dev->vlan_filtering != vlan_filtering) { 1552 dev->vlan_filtering = vlan_filtering; 1553 b53_apply_config(dev); 1554 } 1555 1556 return 0; 1557 } 1558 EXPORT_SYMBOL(b53_vlan_filtering); 1559 1560 static int b53_vlan_prepare(struct dsa_switch *ds, int port, 1561 const struct switchdev_obj_port_vlan *vlan) 1562 { 1563 struct b53_device *dev = ds->priv; 1564 1565 if ((is5325(dev) || is5365(dev)) && vlan->vid == 0) 1566 return -EOPNOTSUPP; 1567 1568 /* Port 7 on 7278 connects to the ASP's UniMAC which is not capable of 1569 * receiving VLAN tagged frames at all, we can still allow the port to 1570 * be configured for egress untagged. 1571 */ 1572 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7 && 1573 !(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)) 1574 return -EINVAL; 1575 1576 if (vlan->vid >= dev->num_vlans) 1577 return -ERANGE; 1578 1579 b53_enable_vlan(dev, port, true, dev->vlan_filtering); 1580 1581 return 0; 1582 } 1583 1584 int b53_vlan_add(struct dsa_switch *ds, int port, 1585 const struct switchdev_obj_port_vlan *vlan, 1586 struct netlink_ext_ack *extack) 1587 { 1588 struct b53_device *dev = ds->priv; 1589 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1590 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1591 struct b53_vlan *vl; 1592 u16 old_pvid, new_pvid; 1593 int err; 1594 1595 err = b53_vlan_prepare(ds, port, vlan); 1596 if (err) 1597 return err; 1598 1599 if (vlan->vid == 0) 1600 return 0; 1601 1602 old_pvid = dev->ports[port].pvid; 1603 if (pvid) 1604 new_pvid = vlan->vid; 1605 else if (!pvid && vlan->vid == old_pvid) 1606 new_pvid = b53_default_pvid(dev); 1607 else 1608 new_pvid = old_pvid; 1609 dev->ports[port].pvid = new_pvid; 1610 1611 vl = &dev->vlans[vlan->vid]; 1612 1613 if (dsa_is_cpu_port(ds, port)) 1614 untagged = false; 1615 1616 vl->members |= BIT(port); 1617 if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port)) 1618 vl->untag |= BIT(port); 1619 else 1620 vl->untag &= ~BIT(port); 1621 1622 if (!dev->vlan_filtering) 1623 return 0; 1624 1625 b53_set_vlan_entry(dev, vlan->vid, vl); 1626 b53_fast_age_vlan(dev, vlan->vid); 1627 1628 if (!dsa_is_cpu_port(ds, port) && new_pvid != old_pvid) { 1629 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), 1630 new_pvid); 1631 b53_fast_age_vlan(dev, old_pvid); 1632 } 1633 1634 return 0; 1635 } 1636 EXPORT_SYMBOL(b53_vlan_add); 1637 1638 int b53_vlan_del(struct dsa_switch *ds, int port, 1639 const struct switchdev_obj_port_vlan *vlan) 1640 { 1641 struct b53_device *dev = ds->priv; 1642 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1643 struct b53_vlan *vl; 1644 u16 pvid; 1645 1646 if (vlan->vid == 0) 1647 return 0; 1648 1649 pvid = dev->ports[port].pvid; 1650 1651 vl = &dev->vlans[vlan->vid]; 1652 1653 vl->members &= ~BIT(port); 1654 1655 if (pvid == vlan->vid) 1656 pvid = b53_default_pvid(dev); 1657 dev->ports[port].pvid = pvid; 1658 1659 if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port)) 1660 vl->untag &= ~(BIT(port)); 1661 1662 if (!dev->vlan_filtering) 1663 return 0; 1664 1665 b53_set_vlan_entry(dev, vlan->vid, vl); 1666 b53_fast_age_vlan(dev, vlan->vid); 1667 1668 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid); 1669 b53_fast_age_vlan(dev, pvid); 1670 1671 return 0; 1672 } 1673 EXPORT_SYMBOL(b53_vlan_del); 1674 1675 /* Address Resolution Logic routines. Caller must hold &dev->arl_mutex. */ 1676 static int b53_arl_op_wait(struct b53_device *dev) 1677 { 1678 unsigned int timeout = 10; 1679 u8 reg; 1680 1681 do { 1682 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1683 if (!(reg & ARLTBL_START_DONE)) 1684 return 0; 1685 1686 usleep_range(1000, 2000); 1687 } while (timeout--); 1688 1689 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg); 1690 1691 return -ETIMEDOUT; 1692 } 1693 1694 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op) 1695 { 1696 u8 reg; 1697 1698 if (op > ARLTBL_RW) 1699 return -EINVAL; 1700 1701 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1702 reg |= ARLTBL_START_DONE; 1703 if (op) 1704 reg |= ARLTBL_RW; 1705 else 1706 reg &= ~ARLTBL_RW; 1707 if (dev->vlan_enabled) 1708 reg &= ~ARLTBL_IVL_SVL_SELECT; 1709 else 1710 reg |= ARLTBL_IVL_SVL_SELECT; 1711 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg); 1712 1713 return b53_arl_op_wait(dev); 1714 } 1715 1716 static int b53_arl_read(struct b53_device *dev, u64 mac, 1717 u16 vid, struct b53_arl_entry *ent, u8 *idx) 1718 { 1719 DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES); 1720 unsigned int i; 1721 int ret; 1722 1723 ret = b53_arl_op_wait(dev); 1724 if (ret) 1725 return ret; 1726 1727 bitmap_zero(free_bins, dev->num_arl_bins); 1728 1729 /* Read the bins */ 1730 for (i = 0; i < dev->num_arl_bins; i++) { 1731 u64 mac_vid; 1732 u32 fwd_entry; 1733 1734 b53_read64(dev, B53_ARLIO_PAGE, 1735 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid); 1736 b53_read32(dev, B53_ARLIO_PAGE, 1737 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry); 1738 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1739 1740 if (!(fwd_entry & ARLTBL_VALID)) { 1741 set_bit(i, free_bins); 1742 continue; 1743 } 1744 if ((mac_vid & ARLTBL_MAC_MASK) != mac) 1745 continue; 1746 if (dev->vlan_enabled && 1747 ((mac_vid >> ARLTBL_VID_S) & ARLTBL_VID_MASK) != vid) 1748 continue; 1749 *idx = i; 1750 return 0; 1751 } 1752 1753 *idx = find_first_bit(free_bins, dev->num_arl_bins); 1754 return *idx >= dev->num_arl_bins ? -ENOSPC : -ENOENT; 1755 } 1756 1757 static int b53_arl_op(struct b53_device *dev, int op, int port, 1758 const unsigned char *addr, u16 vid, bool is_valid) 1759 { 1760 struct b53_arl_entry ent; 1761 u32 fwd_entry; 1762 u64 mac, mac_vid = 0; 1763 u8 idx = 0; 1764 int ret; 1765 1766 /* Convert the array into a 64-bit MAC */ 1767 mac = ether_addr_to_u64(addr); 1768 1769 /* Perform a read for the given MAC and VID */ 1770 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac); 1771 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid); 1772 1773 /* Issue a read operation for this MAC */ 1774 ret = b53_arl_rw_op(dev, 1); 1775 if (ret) 1776 return ret; 1777 1778 ret = b53_arl_read(dev, mac, vid, &ent, &idx); 1779 1780 /* If this is a read, just finish now */ 1781 if (op) 1782 return ret; 1783 1784 switch (ret) { 1785 case -ETIMEDOUT: 1786 return ret; 1787 case -ENOSPC: 1788 dev_dbg(dev->dev, "{%pM,%.4d} no space left in ARL\n", 1789 addr, vid); 1790 return is_valid ? ret : 0; 1791 case -ENOENT: 1792 /* We could not find a matching MAC, so reset to a new entry */ 1793 dev_dbg(dev->dev, "{%pM,%.4d} not found, using idx: %d\n", 1794 addr, vid, idx); 1795 fwd_entry = 0; 1796 break; 1797 default: 1798 dev_dbg(dev->dev, "{%pM,%.4d} found, using idx: %d\n", 1799 addr, vid, idx); 1800 break; 1801 } 1802 1803 /* For multicast address, the port is a bitmask and the validity 1804 * is determined by having at least one port being still active 1805 */ 1806 if (!is_multicast_ether_addr(addr)) { 1807 ent.port = port; 1808 ent.is_valid = is_valid; 1809 } else { 1810 if (is_valid) 1811 ent.port |= BIT(port); 1812 else 1813 ent.port &= ~BIT(port); 1814 1815 ent.is_valid = !!(ent.port); 1816 } 1817 1818 ent.vid = vid; 1819 ent.is_static = true; 1820 ent.is_age = false; 1821 memcpy(ent.mac, addr, ETH_ALEN); 1822 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent); 1823 1824 b53_write64(dev, B53_ARLIO_PAGE, 1825 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid); 1826 b53_write32(dev, B53_ARLIO_PAGE, 1827 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry); 1828 1829 return b53_arl_rw_op(dev, 0); 1830 } 1831 1832 int b53_fdb_add(struct dsa_switch *ds, int port, 1833 const unsigned char *addr, u16 vid, 1834 struct dsa_db db) 1835 { 1836 struct b53_device *priv = ds->priv; 1837 int ret; 1838 1839 /* 5325 and 5365 require some more massaging, but could 1840 * be supported eventually 1841 */ 1842 if (is5325(priv) || is5365(priv)) 1843 return -EOPNOTSUPP; 1844 1845 mutex_lock(&priv->arl_mutex); 1846 ret = b53_arl_op(priv, 0, port, addr, vid, true); 1847 mutex_unlock(&priv->arl_mutex); 1848 1849 return ret; 1850 } 1851 EXPORT_SYMBOL(b53_fdb_add); 1852 1853 int b53_fdb_del(struct dsa_switch *ds, int port, 1854 const unsigned char *addr, u16 vid, 1855 struct dsa_db db) 1856 { 1857 struct b53_device *priv = ds->priv; 1858 int ret; 1859 1860 mutex_lock(&priv->arl_mutex); 1861 ret = b53_arl_op(priv, 0, port, addr, vid, false); 1862 mutex_unlock(&priv->arl_mutex); 1863 1864 return ret; 1865 } 1866 EXPORT_SYMBOL(b53_fdb_del); 1867 1868 static int b53_arl_search_wait(struct b53_device *dev) 1869 { 1870 unsigned int timeout = 1000; 1871 u8 reg; 1872 1873 do { 1874 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®); 1875 if (!(reg & ARL_SRCH_STDN)) 1876 return 0; 1877 1878 if (reg & ARL_SRCH_VLID) 1879 return 0; 1880 1881 usleep_range(1000, 2000); 1882 } while (timeout--); 1883 1884 return -ETIMEDOUT; 1885 } 1886 1887 static void b53_arl_search_rd(struct b53_device *dev, u8 idx, 1888 struct b53_arl_entry *ent) 1889 { 1890 u64 mac_vid; 1891 u32 fwd_entry; 1892 1893 b53_read64(dev, B53_ARLIO_PAGE, 1894 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid); 1895 b53_read32(dev, B53_ARLIO_PAGE, 1896 B53_ARL_SRCH_RSTL(idx), &fwd_entry); 1897 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1898 } 1899 1900 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent, 1901 dsa_fdb_dump_cb_t *cb, void *data) 1902 { 1903 if (!ent->is_valid) 1904 return 0; 1905 1906 if (port != ent->port) 1907 return 0; 1908 1909 return cb(ent->mac, ent->vid, ent->is_static, data); 1910 } 1911 1912 int b53_fdb_dump(struct dsa_switch *ds, int port, 1913 dsa_fdb_dump_cb_t *cb, void *data) 1914 { 1915 struct b53_device *priv = ds->priv; 1916 struct b53_arl_entry results[2]; 1917 unsigned int count = 0; 1918 int ret; 1919 u8 reg; 1920 1921 mutex_lock(&priv->arl_mutex); 1922 1923 /* Start search operation */ 1924 reg = ARL_SRCH_STDN; 1925 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg); 1926 1927 do { 1928 ret = b53_arl_search_wait(priv); 1929 if (ret) 1930 break; 1931 1932 b53_arl_search_rd(priv, 0, &results[0]); 1933 ret = b53_fdb_copy(port, &results[0], cb, data); 1934 if (ret) 1935 break; 1936 1937 if (priv->num_arl_bins > 2) { 1938 b53_arl_search_rd(priv, 1, &results[1]); 1939 ret = b53_fdb_copy(port, &results[1], cb, data); 1940 if (ret) 1941 break; 1942 1943 if (!results[0].is_valid && !results[1].is_valid) 1944 break; 1945 } 1946 1947 } while (count++ < b53_max_arl_entries(priv) / 2); 1948 1949 mutex_unlock(&priv->arl_mutex); 1950 1951 return 0; 1952 } 1953 EXPORT_SYMBOL(b53_fdb_dump); 1954 1955 int b53_mdb_add(struct dsa_switch *ds, int port, 1956 const struct switchdev_obj_port_mdb *mdb, 1957 struct dsa_db db) 1958 { 1959 struct b53_device *priv = ds->priv; 1960 int ret; 1961 1962 /* 5325 and 5365 require some more massaging, but could 1963 * be supported eventually 1964 */ 1965 if (is5325(priv) || is5365(priv)) 1966 return -EOPNOTSUPP; 1967 1968 mutex_lock(&priv->arl_mutex); 1969 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, true); 1970 mutex_unlock(&priv->arl_mutex); 1971 1972 return ret; 1973 } 1974 EXPORT_SYMBOL(b53_mdb_add); 1975 1976 int b53_mdb_del(struct dsa_switch *ds, int port, 1977 const struct switchdev_obj_port_mdb *mdb, 1978 struct dsa_db db) 1979 { 1980 struct b53_device *priv = ds->priv; 1981 int ret; 1982 1983 mutex_lock(&priv->arl_mutex); 1984 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, false); 1985 mutex_unlock(&priv->arl_mutex); 1986 if (ret) 1987 dev_err(ds->dev, "failed to delete MDB entry\n"); 1988 1989 return ret; 1990 } 1991 EXPORT_SYMBOL(b53_mdb_del); 1992 1993 int b53_br_join(struct dsa_switch *ds, int port, struct dsa_bridge bridge, 1994 bool *tx_fwd_offload, struct netlink_ext_ack *extack) 1995 { 1996 struct b53_device *dev = ds->priv; 1997 struct b53_vlan *vl; 1998 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 1999 u16 pvlan, reg, pvid; 2000 unsigned int i; 2001 2002 /* On 7278, port 7 which connects to the ASP should only receive 2003 * traffic from matching CFP rules. 2004 */ 2005 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7) 2006 return -EINVAL; 2007 2008 pvid = b53_default_pvid(dev); 2009 vl = &dev->vlans[pvid]; 2010 2011 if (dev->vlan_filtering) { 2012 /* Make this port leave the all VLANs join since we will have 2013 * proper VLAN entries from now on 2014 */ 2015 if (is58xx(dev)) { 2016 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, 2017 ®); 2018 reg &= ~BIT(port); 2019 if ((reg & BIT(cpu_port)) == BIT(cpu_port)) 2020 reg &= ~BIT(cpu_port); 2021 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, 2022 reg); 2023 } 2024 2025 b53_get_vlan_entry(dev, pvid, vl); 2026 vl->members &= ~BIT(port); 2027 if (vl->members == BIT(cpu_port)) 2028 vl->members &= ~BIT(cpu_port); 2029 vl->untag = vl->members; 2030 b53_set_vlan_entry(dev, pvid, vl); 2031 } 2032 2033 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 2034 2035 b53_for_each_port(dev, i) { 2036 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge)) 2037 continue; 2038 2039 /* Add this local port to the remote port VLAN control 2040 * membership and update the remote port bitmask 2041 */ 2042 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 2043 reg |= BIT(port); 2044 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 2045 dev->ports[i].vlan_ctl_mask = reg; 2046 2047 pvlan |= BIT(i); 2048 } 2049 2050 /* Configure the local port VLAN control membership to include 2051 * remote ports and update the local port bitmask 2052 */ 2053 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 2054 dev->ports[port].vlan_ctl_mask = pvlan; 2055 2056 return 0; 2057 } 2058 EXPORT_SYMBOL(b53_br_join); 2059 2060 void b53_br_leave(struct dsa_switch *ds, int port, struct dsa_bridge bridge) 2061 { 2062 struct b53_device *dev = ds->priv; 2063 struct b53_vlan *vl; 2064 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 2065 unsigned int i; 2066 u16 pvlan, reg, pvid; 2067 2068 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 2069 2070 b53_for_each_port(dev, i) { 2071 /* Don't touch the remaining ports */ 2072 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge)) 2073 continue; 2074 2075 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 2076 reg &= ~BIT(port); 2077 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 2078 dev->ports[port].vlan_ctl_mask = reg; 2079 2080 /* Prevent self removal to preserve isolation */ 2081 if (port != i) 2082 pvlan &= ~BIT(i); 2083 } 2084 2085 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 2086 dev->ports[port].vlan_ctl_mask = pvlan; 2087 2088 pvid = b53_default_pvid(dev); 2089 vl = &dev->vlans[pvid]; 2090 2091 if (dev->vlan_filtering) { 2092 /* Make this port join all VLANs without VLAN entries */ 2093 if (is58xx(dev)) { 2094 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 2095 reg |= BIT(port); 2096 if (!(reg & BIT(cpu_port))) 2097 reg |= BIT(cpu_port); 2098 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 2099 } 2100 2101 b53_get_vlan_entry(dev, pvid, vl); 2102 vl->members |= BIT(port) | BIT(cpu_port); 2103 vl->untag |= BIT(port) | BIT(cpu_port); 2104 b53_set_vlan_entry(dev, pvid, vl); 2105 } 2106 } 2107 EXPORT_SYMBOL(b53_br_leave); 2108 2109 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state) 2110 { 2111 struct b53_device *dev = ds->priv; 2112 u8 hw_state; 2113 u8 reg; 2114 2115 switch (state) { 2116 case BR_STATE_DISABLED: 2117 hw_state = PORT_CTRL_DIS_STATE; 2118 break; 2119 case BR_STATE_LISTENING: 2120 hw_state = PORT_CTRL_LISTEN_STATE; 2121 break; 2122 case BR_STATE_LEARNING: 2123 hw_state = PORT_CTRL_LEARN_STATE; 2124 break; 2125 case BR_STATE_FORWARDING: 2126 hw_state = PORT_CTRL_FWD_STATE; 2127 break; 2128 case BR_STATE_BLOCKING: 2129 hw_state = PORT_CTRL_BLOCK_STATE; 2130 break; 2131 default: 2132 dev_err(ds->dev, "invalid STP state: %d\n", state); 2133 return; 2134 } 2135 2136 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 2137 reg &= ~PORT_CTRL_STP_STATE_MASK; 2138 reg |= hw_state; 2139 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 2140 } 2141 EXPORT_SYMBOL(b53_br_set_stp_state); 2142 2143 void b53_br_fast_age(struct dsa_switch *ds, int port) 2144 { 2145 struct b53_device *dev = ds->priv; 2146 2147 if (b53_fast_age_port(dev, port)) 2148 dev_err(ds->dev, "fast ageing failed\n"); 2149 } 2150 EXPORT_SYMBOL(b53_br_fast_age); 2151 2152 int b53_br_flags_pre(struct dsa_switch *ds, int port, 2153 struct switchdev_brport_flags flags, 2154 struct netlink_ext_ack *extack) 2155 { 2156 if (flags.mask & ~(BR_FLOOD | BR_MCAST_FLOOD | BR_LEARNING)) 2157 return -EINVAL; 2158 2159 return 0; 2160 } 2161 EXPORT_SYMBOL(b53_br_flags_pre); 2162 2163 int b53_br_flags(struct dsa_switch *ds, int port, 2164 struct switchdev_brport_flags flags, 2165 struct netlink_ext_ack *extack) 2166 { 2167 if (flags.mask & BR_FLOOD) 2168 b53_port_set_ucast_flood(ds->priv, port, 2169 !!(flags.val & BR_FLOOD)); 2170 if (flags.mask & BR_MCAST_FLOOD) 2171 b53_port_set_mcast_flood(ds->priv, port, 2172 !!(flags.val & BR_MCAST_FLOOD)); 2173 if (flags.mask & BR_LEARNING) 2174 b53_port_set_learning(ds->priv, port, 2175 !!(flags.val & BR_LEARNING)); 2176 2177 return 0; 2178 } 2179 EXPORT_SYMBOL(b53_br_flags); 2180 2181 static bool b53_possible_cpu_port(struct dsa_switch *ds, int port) 2182 { 2183 /* Broadcom switches will accept enabling Broadcom tags on the 2184 * following ports: 5, 7 and 8, any other port is not supported 2185 */ 2186 switch (port) { 2187 case B53_CPU_PORT_25: 2188 case 7: 2189 case B53_CPU_PORT: 2190 return true; 2191 } 2192 2193 return false; 2194 } 2195 2196 static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port, 2197 enum dsa_tag_protocol tag_protocol) 2198 { 2199 bool ret = b53_possible_cpu_port(ds, port); 2200 2201 if (!ret) { 2202 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n", 2203 port); 2204 return ret; 2205 } 2206 2207 switch (tag_protocol) { 2208 case DSA_TAG_PROTO_BRCM: 2209 case DSA_TAG_PROTO_BRCM_PREPEND: 2210 dev_warn(ds->dev, 2211 "Port %d is stacked to Broadcom tag switch\n", port); 2212 ret = false; 2213 break; 2214 default: 2215 ret = true; 2216 break; 2217 } 2218 2219 return ret; 2220 } 2221 2222 enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port, 2223 enum dsa_tag_protocol mprot) 2224 { 2225 struct b53_device *dev = ds->priv; 2226 2227 if (!b53_can_enable_brcm_tags(ds, port, mprot)) { 2228 dev->tag_protocol = DSA_TAG_PROTO_NONE; 2229 goto out; 2230 } 2231 2232 /* Older models require a different 6 byte tag */ 2233 if (is5325(dev) || is5365(dev) || is63xx(dev)) { 2234 dev->tag_protocol = DSA_TAG_PROTO_BRCM_LEGACY; 2235 goto out; 2236 } 2237 2238 /* Broadcom BCM58xx chips have a flow accelerator on Port 8 2239 * which requires us to use the prepended Broadcom tag type 2240 */ 2241 if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT) { 2242 dev->tag_protocol = DSA_TAG_PROTO_BRCM_PREPEND; 2243 goto out; 2244 } 2245 2246 dev->tag_protocol = DSA_TAG_PROTO_BRCM; 2247 out: 2248 return dev->tag_protocol; 2249 } 2250 EXPORT_SYMBOL(b53_get_tag_protocol); 2251 2252 int b53_mirror_add(struct dsa_switch *ds, int port, 2253 struct dsa_mall_mirror_tc_entry *mirror, bool ingress, 2254 struct netlink_ext_ack *extack) 2255 { 2256 struct b53_device *dev = ds->priv; 2257 u16 reg, loc; 2258 2259 if (ingress) 2260 loc = B53_IG_MIR_CTL; 2261 else 2262 loc = B53_EG_MIR_CTL; 2263 2264 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 2265 reg |= BIT(port); 2266 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 2267 2268 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 2269 reg &= ~CAP_PORT_MASK; 2270 reg |= mirror->to_local_port; 2271 reg |= MIRROR_EN; 2272 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 2273 2274 return 0; 2275 } 2276 EXPORT_SYMBOL(b53_mirror_add); 2277 2278 void b53_mirror_del(struct dsa_switch *ds, int port, 2279 struct dsa_mall_mirror_tc_entry *mirror) 2280 { 2281 struct b53_device *dev = ds->priv; 2282 bool loc_disable = false, other_loc_disable = false; 2283 u16 reg, loc; 2284 2285 if (mirror->ingress) 2286 loc = B53_IG_MIR_CTL; 2287 else 2288 loc = B53_EG_MIR_CTL; 2289 2290 /* Update the desired ingress/egress register */ 2291 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 2292 reg &= ~BIT(port); 2293 if (!(reg & MIRROR_MASK)) 2294 loc_disable = true; 2295 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 2296 2297 /* Now look at the other one to know if we can disable mirroring 2298 * entirely 2299 */ 2300 if (mirror->ingress) 2301 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, ®); 2302 else 2303 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, ®); 2304 if (!(reg & MIRROR_MASK)) 2305 other_loc_disable = true; 2306 2307 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 2308 /* Both no longer have ports, let's disable mirroring */ 2309 if (loc_disable && other_loc_disable) { 2310 reg &= ~MIRROR_EN; 2311 reg &= ~mirror->to_local_port; 2312 } 2313 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 2314 } 2315 EXPORT_SYMBOL(b53_mirror_del); 2316 2317 /* Returns 0 if EEE was not enabled, or 1 otherwise 2318 */ 2319 int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy) 2320 { 2321 int ret; 2322 2323 ret = phy_init_eee(phy, false); 2324 if (ret) 2325 return 0; 2326 2327 b53_eee_enable_set(ds, port, true); 2328 2329 return 1; 2330 } 2331 EXPORT_SYMBOL(b53_eee_init); 2332 2333 bool b53_support_eee(struct dsa_switch *ds, int port) 2334 { 2335 struct b53_device *dev = ds->priv; 2336 2337 return !is5325(dev) && !is5365(dev); 2338 } 2339 EXPORT_SYMBOL(b53_support_eee); 2340 2341 int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_keee *e) 2342 { 2343 struct b53_device *dev = ds->priv; 2344 struct ethtool_keee *p = &dev->ports[port].eee; 2345 2346 p->eee_enabled = e->eee_enabled; 2347 b53_eee_enable_set(ds, port, e->eee_enabled); 2348 2349 return 0; 2350 } 2351 EXPORT_SYMBOL(b53_set_mac_eee); 2352 2353 static int b53_change_mtu(struct dsa_switch *ds, int port, int mtu) 2354 { 2355 struct b53_device *dev = ds->priv; 2356 bool enable_jumbo; 2357 bool allow_10_100; 2358 2359 if (is5325(dev) || is5365(dev)) 2360 return 0; 2361 2362 if (!dsa_is_cpu_port(ds, port)) 2363 return 0; 2364 2365 enable_jumbo = (mtu > ETH_DATA_LEN); 2366 allow_10_100 = !is63xx(dev); 2367 2368 return b53_set_jumbo(dev, enable_jumbo, allow_10_100); 2369 } 2370 2371 static int b53_get_max_mtu(struct dsa_switch *ds, int port) 2372 { 2373 struct b53_device *dev = ds->priv; 2374 2375 if (is5325(dev) || is5365(dev)) 2376 return B53_MAX_MTU_25; 2377 2378 return B53_MAX_MTU; 2379 } 2380 2381 int b53_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 2382 { 2383 struct b53_device *dev = ds->priv; 2384 u32 atc; 2385 int reg; 2386 2387 if (is63xx(dev)) 2388 reg = B53_AGING_TIME_CONTROL_63XX; 2389 else 2390 reg = B53_AGING_TIME_CONTROL; 2391 2392 atc = DIV_ROUND_CLOSEST(msecs, 1000); 2393 2394 if (!is5325(dev) && !is5365(dev)) 2395 atc |= AGE_CHANGE; 2396 2397 b53_write32(dev, B53_MGMT_PAGE, reg, atc); 2398 2399 return 0; 2400 } 2401 EXPORT_SYMBOL_GPL(b53_set_ageing_time); 2402 2403 static const struct phylink_mac_ops b53_phylink_mac_ops = { 2404 .mac_select_pcs = b53_phylink_mac_select_pcs, 2405 .mac_config = b53_phylink_mac_config, 2406 .mac_link_down = b53_phylink_mac_link_down, 2407 .mac_link_up = b53_phylink_mac_link_up, 2408 }; 2409 2410 static const struct dsa_switch_ops b53_switch_ops = { 2411 .get_tag_protocol = b53_get_tag_protocol, 2412 .setup = b53_setup, 2413 .teardown = b53_teardown, 2414 .get_strings = b53_get_strings, 2415 .get_ethtool_stats = b53_get_ethtool_stats, 2416 .get_sset_count = b53_get_sset_count, 2417 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 2418 .phy_read = b53_phy_read16, 2419 .phy_write = b53_phy_write16, 2420 .phylink_get_caps = b53_phylink_get_caps, 2421 .port_setup = b53_setup_port, 2422 .port_enable = b53_enable_port, 2423 .port_disable = b53_disable_port, 2424 .support_eee = b53_support_eee, 2425 .set_mac_eee = b53_set_mac_eee, 2426 .set_ageing_time = b53_set_ageing_time, 2427 .port_bridge_join = b53_br_join, 2428 .port_bridge_leave = b53_br_leave, 2429 .port_pre_bridge_flags = b53_br_flags_pre, 2430 .port_bridge_flags = b53_br_flags, 2431 .port_stp_state_set = b53_br_set_stp_state, 2432 .port_fast_age = b53_br_fast_age, 2433 .port_vlan_filtering = b53_vlan_filtering, 2434 .port_vlan_add = b53_vlan_add, 2435 .port_vlan_del = b53_vlan_del, 2436 .port_fdb_dump = b53_fdb_dump, 2437 .port_fdb_add = b53_fdb_add, 2438 .port_fdb_del = b53_fdb_del, 2439 .port_mirror_add = b53_mirror_add, 2440 .port_mirror_del = b53_mirror_del, 2441 .port_mdb_add = b53_mdb_add, 2442 .port_mdb_del = b53_mdb_del, 2443 .port_max_mtu = b53_get_max_mtu, 2444 .port_change_mtu = b53_change_mtu, 2445 }; 2446 2447 struct b53_chip_data { 2448 u32 chip_id; 2449 const char *dev_name; 2450 u16 vlans; 2451 u16 enabled_ports; 2452 u8 imp_port; 2453 u8 cpu_port; 2454 u8 vta_regs[3]; 2455 u8 arl_bins; 2456 u16 arl_buckets; 2457 u8 duplex_reg; 2458 u8 jumbo_pm_reg; 2459 u8 jumbo_size_reg; 2460 }; 2461 2462 #define B53_VTA_REGS \ 2463 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY } 2464 #define B53_VTA_REGS_9798 \ 2465 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 } 2466 #define B53_VTA_REGS_63XX \ 2467 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX } 2468 2469 static const struct b53_chip_data b53_switch_chips[] = { 2470 { 2471 .chip_id = BCM5325_DEVICE_ID, 2472 .dev_name = "BCM5325", 2473 .vlans = 16, 2474 .enabled_ports = 0x3f, 2475 .arl_bins = 2, 2476 .arl_buckets = 1024, 2477 .imp_port = 5, 2478 .duplex_reg = B53_DUPLEX_STAT_FE, 2479 }, 2480 { 2481 .chip_id = BCM5365_DEVICE_ID, 2482 .dev_name = "BCM5365", 2483 .vlans = 256, 2484 .enabled_ports = 0x3f, 2485 .arl_bins = 2, 2486 .arl_buckets = 1024, 2487 .imp_port = 5, 2488 .duplex_reg = B53_DUPLEX_STAT_FE, 2489 }, 2490 { 2491 .chip_id = BCM5389_DEVICE_ID, 2492 .dev_name = "BCM5389", 2493 .vlans = 4096, 2494 .enabled_ports = 0x11f, 2495 .arl_bins = 4, 2496 .arl_buckets = 1024, 2497 .imp_port = 8, 2498 .vta_regs = B53_VTA_REGS, 2499 .duplex_reg = B53_DUPLEX_STAT_GE, 2500 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2501 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2502 }, 2503 { 2504 .chip_id = BCM5395_DEVICE_ID, 2505 .dev_name = "BCM5395", 2506 .vlans = 4096, 2507 .enabled_ports = 0x11f, 2508 .arl_bins = 4, 2509 .arl_buckets = 1024, 2510 .imp_port = 8, 2511 .vta_regs = B53_VTA_REGS, 2512 .duplex_reg = B53_DUPLEX_STAT_GE, 2513 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2514 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2515 }, 2516 { 2517 .chip_id = BCM5397_DEVICE_ID, 2518 .dev_name = "BCM5397", 2519 .vlans = 4096, 2520 .enabled_ports = 0x11f, 2521 .arl_bins = 4, 2522 .arl_buckets = 1024, 2523 .imp_port = 8, 2524 .vta_regs = B53_VTA_REGS_9798, 2525 .duplex_reg = B53_DUPLEX_STAT_GE, 2526 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2527 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2528 }, 2529 { 2530 .chip_id = BCM5398_DEVICE_ID, 2531 .dev_name = "BCM5398", 2532 .vlans = 4096, 2533 .enabled_ports = 0x17f, 2534 .arl_bins = 4, 2535 .arl_buckets = 1024, 2536 .imp_port = 8, 2537 .vta_regs = B53_VTA_REGS_9798, 2538 .duplex_reg = B53_DUPLEX_STAT_GE, 2539 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2540 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2541 }, 2542 { 2543 .chip_id = BCM53101_DEVICE_ID, 2544 .dev_name = "BCM53101", 2545 .vlans = 4096, 2546 .enabled_ports = 0x11f, 2547 .arl_bins = 4, 2548 .arl_buckets = 512, 2549 .vta_regs = B53_VTA_REGS, 2550 .imp_port = 8, 2551 .duplex_reg = B53_DUPLEX_STAT_GE, 2552 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2553 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2554 }, 2555 { 2556 .chip_id = BCM53115_DEVICE_ID, 2557 .dev_name = "BCM53115", 2558 .vlans = 4096, 2559 .enabled_ports = 0x11f, 2560 .arl_bins = 4, 2561 .arl_buckets = 1024, 2562 .vta_regs = B53_VTA_REGS, 2563 .imp_port = 8, 2564 .duplex_reg = B53_DUPLEX_STAT_GE, 2565 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2566 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2567 }, 2568 { 2569 .chip_id = BCM53125_DEVICE_ID, 2570 .dev_name = "BCM53125", 2571 .vlans = 4096, 2572 .enabled_ports = 0x1ff, 2573 .arl_bins = 4, 2574 .arl_buckets = 1024, 2575 .imp_port = 8, 2576 .vta_regs = B53_VTA_REGS, 2577 .duplex_reg = B53_DUPLEX_STAT_GE, 2578 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2579 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2580 }, 2581 { 2582 .chip_id = BCM53128_DEVICE_ID, 2583 .dev_name = "BCM53128", 2584 .vlans = 4096, 2585 .enabled_ports = 0x1ff, 2586 .arl_bins = 4, 2587 .arl_buckets = 1024, 2588 .imp_port = 8, 2589 .vta_regs = B53_VTA_REGS, 2590 .duplex_reg = B53_DUPLEX_STAT_GE, 2591 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2592 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2593 }, 2594 { 2595 .chip_id = BCM63XX_DEVICE_ID, 2596 .dev_name = "BCM63xx", 2597 .vlans = 4096, 2598 .enabled_ports = 0, /* pdata must provide them */ 2599 .arl_bins = 4, 2600 .arl_buckets = 1024, 2601 .imp_port = 8, 2602 .vta_regs = B53_VTA_REGS_63XX, 2603 .duplex_reg = B53_DUPLEX_STAT_63XX, 2604 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, 2605 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, 2606 }, 2607 { 2608 .chip_id = BCM63268_DEVICE_ID, 2609 .dev_name = "BCM63268", 2610 .vlans = 4096, 2611 .enabled_ports = 0, /* pdata must provide them */ 2612 .arl_bins = 4, 2613 .arl_buckets = 1024, 2614 .imp_port = 8, 2615 .vta_regs = B53_VTA_REGS_63XX, 2616 .duplex_reg = B53_DUPLEX_STAT_63XX, 2617 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, 2618 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, 2619 }, 2620 { 2621 .chip_id = BCM53010_DEVICE_ID, 2622 .dev_name = "BCM53010", 2623 .vlans = 4096, 2624 .enabled_ports = 0x1bf, 2625 .arl_bins = 4, 2626 .arl_buckets = 1024, 2627 .imp_port = 8, 2628 .vta_regs = B53_VTA_REGS, 2629 .duplex_reg = B53_DUPLEX_STAT_GE, 2630 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2631 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2632 }, 2633 { 2634 .chip_id = BCM53011_DEVICE_ID, 2635 .dev_name = "BCM53011", 2636 .vlans = 4096, 2637 .enabled_ports = 0x1bf, 2638 .arl_bins = 4, 2639 .arl_buckets = 1024, 2640 .imp_port = 8, 2641 .vta_regs = B53_VTA_REGS, 2642 .duplex_reg = B53_DUPLEX_STAT_GE, 2643 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2644 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2645 }, 2646 { 2647 .chip_id = BCM53012_DEVICE_ID, 2648 .dev_name = "BCM53012", 2649 .vlans = 4096, 2650 .enabled_ports = 0x1bf, 2651 .arl_bins = 4, 2652 .arl_buckets = 1024, 2653 .imp_port = 8, 2654 .vta_regs = B53_VTA_REGS, 2655 .duplex_reg = B53_DUPLEX_STAT_GE, 2656 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2657 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2658 }, 2659 { 2660 .chip_id = BCM53018_DEVICE_ID, 2661 .dev_name = "BCM53018", 2662 .vlans = 4096, 2663 .enabled_ports = 0x1bf, 2664 .arl_bins = 4, 2665 .arl_buckets = 1024, 2666 .imp_port = 8, 2667 .vta_regs = B53_VTA_REGS, 2668 .duplex_reg = B53_DUPLEX_STAT_GE, 2669 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2670 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2671 }, 2672 { 2673 .chip_id = BCM53019_DEVICE_ID, 2674 .dev_name = "BCM53019", 2675 .vlans = 4096, 2676 .enabled_ports = 0x1bf, 2677 .arl_bins = 4, 2678 .arl_buckets = 1024, 2679 .imp_port = 8, 2680 .vta_regs = B53_VTA_REGS, 2681 .duplex_reg = B53_DUPLEX_STAT_GE, 2682 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2683 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2684 }, 2685 { 2686 .chip_id = BCM58XX_DEVICE_ID, 2687 .dev_name = "BCM585xx/586xx/88312", 2688 .vlans = 4096, 2689 .enabled_ports = 0x1ff, 2690 .arl_bins = 4, 2691 .arl_buckets = 1024, 2692 .imp_port = 8, 2693 .vta_regs = B53_VTA_REGS, 2694 .duplex_reg = B53_DUPLEX_STAT_GE, 2695 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2696 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2697 }, 2698 { 2699 .chip_id = BCM583XX_DEVICE_ID, 2700 .dev_name = "BCM583xx/11360", 2701 .vlans = 4096, 2702 .enabled_ports = 0x103, 2703 .arl_bins = 4, 2704 .arl_buckets = 1024, 2705 .imp_port = 8, 2706 .vta_regs = B53_VTA_REGS, 2707 .duplex_reg = B53_DUPLEX_STAT_GE, 2708 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2709 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2710 }, 2711 /* Starfighter 2 */ 2712 { 2713 .chip_id = BCM4908_DEVICE_ID, 2714 .dev_name = "BCM4908", 2715 .vlans = 4096, 2716 .enabled_ports = 0x1bf, 2717 .arl_bins = 4, 2718 .arl_buckets = 256, 2719 .imp_port = 8, 2720 .vta_regs = B53_VTA_REGS, 2721 .duplex_reg = B53_DUPLEX_STAT_GE, 2722 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2723 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2724 }, 2725 { 2726 .chip_id = BCM7445_DEVICE_ID, 2727 .dev_name = "BCM7445", 2728 .vlans = 4096, 2729 .enabled_ports = 0x1ff, 2730 .arl_bins = 4, 2731 .arl_buckets = 1024, 2732 .imp_port = 8, 2733 .vta_regs = B53_VTA_REGS, 2734 .duplex_reg = B53_DUPLEX_STAT_GE, 2735 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2736 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2737 }, 2738 { 2739 .chip_id = BCM7278_DEVICE_ID, 2740 .dev_name = "BCM7278", 2741 .vlans = 4096, 2742 .enabled_ports = 0x1ff, 2743 .arl_bins = 4, 2744 .arl_buckets = 256, 2745 .imp_port = 8, 2746 .vta_regs = B53_VTA_REGS, 2747 .duplex_reg = B53_DUPLEX_STAT_GE, 2748 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2749 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2750 }, 2751 { 2752 .chip_id = BCM53134_DEVICE_ID, 2753 .dev_name = "BCM53134", 2754 .vlans = 4096, 2755 .enabled_ports = 0x12f, 2756 .imp_port = 8, 2757 .cpu_port = B53_CPU_PORT, 2758 .vta_regs = B53_VTA_REGS, 2759 .arl_bins = 4, 2760 .arl_buckets = 1024, 2761 .duplex_reg = B53_DUPLEX_STAT_GE, 2762 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2763 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2764 }, 2765 }; 2766 2767 static int b53_switch_init(struct b53_device *dev) 2768 { 2769 unsigned int i; 2770 int ret; 2771 2772 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) { 2773 const struct b53_chip_data *chip = &b53_switch_chips[i]; 2774 2775 if (chip->chip_id == dev->chip_id) { 2776 if (!dev->enabled_ports) 2777 dev->enabled_ports = chip->enabled_ports; 2778 dev->name = chip->dev_name; 2779 dev->duplex_reg = chip->duplex_reg; 2780 dev->vta_regs[0] = chip->vta_regs[0]; 2781 dev->vta_regs[1] = chip->vta_regs[1]; 2782 dev->vta_regs[2] = chip->vta_regs[2]; 2783 dev->jumbo_pm_reg = chip->jumbo_pm_reg; 2784 dev->imp_port = chip->imp_port; 2785 dev->num_vlans = chip->vlans; 2786 dev->num_arl_bins = chip->arl_bins; 2787 dev->num_arl_buckets = chip->arl_buckets; 2788 break; 2789 } 2790 } 2791 2792 /* check which BCM5325x version we have */ 2793 if (is5325(dev)) { 2794 u8 vc4; 2795 2796 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 2797 2798 /* check reserved bits */ 2799 switch (vc4 & 3) { 2800 case 1: 2801 /* BCM5325E */ 2802 break; 2803 case 3: 2804 /* BCM5325F - do not use port 4 */ 2805 dev->enabled_ports &= ~BIT(4); 2806 break; 2807 default: 2808 /* On the BCM47XX SoCs this is the supported internal switch.*/ 2809 #ifndef CONFIG_BCM47XX 2810 /* BCM5325M */ 2811 return -EINVAL; 2812 #else 2813 break; 2814 #endif 2815 } 2816 } 2817 2818 dev->num_ports = fls(dev->enabled_ports); 2819 2820 dev->ds->num_ports = min_t(unsigned int, dev->num_ports, DSA_MAX_PORTS); 2821 2822 /* Include non standard CPU port built-in PHYs to be probed */ 2823 if (is539x(dev) || is531x5(dev)) { 2824 for (i = 0; i < dev->num_ports; i++) { 2825 if (!(dev->ds->phys_mii_mask & BIT(i)) && 2826 !b53_possible_cpu_port(dev->ds, i)) 2827 dev->ds->phys_mii_mask |= BIT(i); 2828 } 2829 } 2830 2831 dev->ports = devm_kcalloc(dev->dev, 2832 dev->num_ports, sizeof(struct b53_port), 2833 GFP_KERNEL); 2834 if (!dev->ports) 2835 return -ENOMEM; 2836 2837 dev->vlans = devm_kcalloc(dev->dev, 2838 dev->num_vlans, sizeof(struct b53_vlan), 2839 GFP_KERNEL); 2840 if (!dev->vlans) 2841 return -ENOMEM; 2842 2843 dev->reset_gpio = b53_switch_get_reset_gpio(dev); 2844 if (dev->reset_gpio >= 0) { 2845 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio, 2846 GPIOF_OUT_INIT_HIGH, "robo_reset"); 2847 if (ret) 2848 return ret; 2849 } 2850 2851 return 0; 2852 } 2853 2854 struct b53_device *b53_switch_alloc(struct device *base, 2855 const struct b53_io_ops *ops, 2856 void *priv) 2857 { 2858 struct dsa_switch *ds; 2859 struct b53_device *dev; 2860 2861 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 2862 if (!ds) 2863 return NULL; 2864 2865 ds->dev = base; 2866 2867 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL); 2868 if (!dev) 2869 return NULL; 2870 2871 ds->priv = dev; 2872 dev->dev = base; 2873 2874 dev->ds = ds; 2875 dev->priv = priv; 2876 dev->ops = ops; 2877 ds->ops = &b53_switch_ops; 2878 ds->phylink_mac_ops = &b53_phylink_mac_ops; 2879 dev->vlan_enabled = true; 2880 dev->vlan_filtering = false; 2881 /* Let DSA handle the case were multiple bridges span the same switch 2882 * device and different VLAN awareness settings are requested, which 2883 * would be breaking filtering semantics for any of the other bridge 2884 * devices. (not hardware supported) 2885 */ 2886 ds->vlan_filtering_is_global = true; 2887 2888 mutex_init(&dev->reg_mutex); 2889 mutex_init(&dev->stats_mutex); 2890 mutex_init(&dev->arl_mutex); 2891 2892 return dev; 2893 } 2894 EXPORT_SYMBOL(b53_switch_alloc); 2895 2896 int b53_switch_detect(struct b53_device *dev) 2897 { 2898 u32 id32; 2899 u16 tmp; 2900 u8 id8; 2901 int ret; 2902 2903 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8); 2904 if (ret) 2905 return ret; 2906 2907 switch (id8) { 2908 case 0: 2909 /* BCM5325 and BCM5365 do not have this register so reads 2910 * return 0. But the read operation did succeed, so assume this 2911 * is one of them. 2912 * 2913 * Next check if we can write to the 5325's VTA register; for 2914 * 5365 it is read only. 2915 */ 2916 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf); 2917 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp); 2918 2919 if (tmp == 0xf) 2920 dev->chip_id = BCM5325_DEVICE_ID; 2921 else 2922 dev->chip_id = BCM5365_DEVICE_ID; 2923 break; 2924 case BCM5389_DEVICE_ID: 2925 case BCM5395_DEVICE_ID: 2926 case BCM5397_DEVICE_ID: 2927 case BCM5398_DEVICE_ID: 2928 dev->chip_id = id8; 2929 break; 2930 default: 2931 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32); 2932 if (ret) 2933 return ret; 2934 2935 switch (id32) { 2936 case BCM53101_DEVICE_ID: 2937 case BCM53115_DEVICE_ID: 2938 case BCM53125_DEVICE_ID: 2939 case BCM53128_DEVICE_ID: 2940 case BCM53010_DEVICE_ID: 2941 case BCM53011_DEVICE_ID: 2942 case BCM53012_DEVICE_ID: 2943 case BCM53018_DEVICE_ID: 2944 case BCM53019_DEVICE_ID: 2945 case BCM53134_DEVICE_ID: 2946 dev->chip_id = id32; 2947 break; 2948 default: 2949 dev_err(dev->dev, 2950 "unsupported switch detected (BCM53%02x/BCM%x)\n", 2951 id8, id32); 2952 return -ENODEV; 2953 } 2954 } 2955 2956 if (dev->chip_id == BCM5325_DEVICE_ID) 2957 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25, 2958 &dev->core_rev); 2959 else 2960 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID, 2961 &dev->core_rev); 2962 } 2963 EXPORT_SYMBOL(b53_switch_detect); 2964 2965 int b53_switch_register(struct b53_device *dev) 2966 { 2967 int ret; 2968 2969 if (dev->pdata) { 2970 dev->chip_id = dev->pdata->chip_id; 2971 dev->enabled_ports = dev->pdata->enabled_ports; 2972 } 2973 2974 if (!dev->chip_id && b53_switch_detect(dev)) 2975 return -EINVAL; 2976 2977 ret = b53_switch_init(dev); 2978 if (ret) 2979 return ret; 2980 2981 dev_info(dev->dev, "found switch: %s, rev %i\n", 2982 dev->name, dev->core_rev); 2983 2984 return dsa_register_switch(dev->ds); 2985 } 2986 EXPORT_SYMBOL(b53_switch_register); 2987 2988 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>"); 2989 MODULE_DESCRIPTION("B53 switch library"); 2990 MODULE_LICENSE("Dual BSD/GPL"); 2991