1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* Xilinx CAN device driver 3 * 4 * Copyright (C) 2012 - 2022 Xilinx, Inc. 5 * Copyright (C) 2009 PetaLogix. All rights reserved. 6 * Copyright (C) 2017 - 2018 Sandvik Mining and Construction Oy 7 * 8 * Description: 9 * This driver is developed for Axi CAN IP and for Zynq CANPS Controller. 10 */ 11 12 #include <linux/bitfield.h> 13 #include <linux/clk.h> 14 #include <linux/errno.h> 15 #include <linux/ethtool.h> 16 #include <linux/init.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/netdevice.h> 22 #include <linux/of.h> 23 #include <linux/of_device.h> 24 #include <linux/platform_device.h> 25 #include <linux/skbuff.h> 26 #include <linux/spinlock.h> 27 #include <linux/string.h> 28 #include <linux/types.h> 29 #include <linux/can/dev.h> 30 #include <linux/can/error.h> 31 #include <linux/phy/phy.h> 32 #include <linux/pm_runtime.h> 33 34 #define DRIVER_NAME "xilinx_can" 35 36 /* CAN registers set */ 37 enum xcan_reg { 38 XCAN_SRR_OFFSET = 0x00, /* Software reset */ 39 XCAN_MSR_OFFSET = 0x04, /* Mode select */ 40 XCAN_BRPR_OFFSET = 0x08, /* Baud rate prescaler */ 41 XCAN_BTR_OFFSET = 0x0C, /* Bit timing */ 42 XCAN_ECR_OFFSET = 0x10, /* Error counter */ 43 XCAN_ESR_OFFSET = 0x14, /* Error status */ 44 XCAN_SR_OFFSET = 0x18, /* Status */ 45 XCAN_ISR_OFFSET = 0x1C, /* Interrupt status */ 46 XCAN_IER_OFFSET = 0x20, /* Interrupt enable */ 47 XCAN_ICR_OFFSET = 0x24, /* Interrupt clear */ 48 49 /* not on CAN FD cores */ 50 XCAN_TXFIFO_OFFSET = 0x30, /* TX FIFO base */ 51 XCAN_RXFIFO_OFFSET = 0x50, /* RX FIFO base */ 52 XCAN_AFR_OFFSET = 0x60, /* Acceptance Filter */ 53 54 /* only on CAN FD cores */ 55 XCAN_F_BRPR_OFFSET = 0x088, /* Data Phase Baud Rate 56 * Prescaler 57 */ 58 XCAN_F_BTR_OFFSET = 0x08C, /* Data Phase Bit Timing */ 59 XCAN_TRR_OFFSET = 0x0090, /* TX Buffer Ready Request */ 60 XCAN_AFR_EXT_OFFSET = 0x00E0, /* Acceptance Filter */ 61 XCAN_FSR_OFFSET = 0x00E8, /* RX FIFO Status */ 62 XCAN_TXMSG_BASE_OFFSET = 0x0100, /* TX Message Space */ 63 XCAN_RXMSG_BASE_OFFSET = 0x1100, /* RX Message Space */ 64 XCAN_RXMSG_2_BASE_OFFSET = 0x2100, /* RX Message Space */ 65 XCAN_AFR_2_MASK_OFFSET = 0x0A00, /* Acceptance Filter MASK */ 66 XCAN_AFR_2_ID_OFFSET = 0x0A04, /* Acceptance Filter ID */ 67 }; 68 69 #define XCAN_FRAME_ID_OFFSET(frame_base) ((frame_base) + 0x00) 70 #define XCAN_FRAME_DLC_OFFSET(frame_base) ((frame_base) + 0x04) 71 #define XCAN_FRAME_DW1_OFFSET(frame_base) ((frame_base) + 0x08) 72 #define XCAN_FRAME_DW2_OFFSET(frame_base) ((frame_base) + 0x0C) 73 #define XCANFD_FRAME_DW_OFFSET(frame_base) ((frame_base) + 0x08) 74 75 #define XCAN_CANFD_FRAME_SIZE 0x48 76 #define XCAN_TXMSG_FRAME_OFFSET(n) (XCAN_TXMSG_BASE_OFFSET + \ 77 XCAN_CANFD_FRAME_SIZE * (n)) 78 #define XCAN_RXMSG_FRAME_OFFSET(n) (XCAN_RXMSG_BASE_OFFSET + \ 79 XCAN_CANFD_FRAME_SIZE * (n)) 80 #define XCAN_RXMSG_2_FRAME_OFFSET(n) (XCAN_RXMSG_2_BASE_OFFSET + \ 81 XCAN_CANFD_FRAME_SIZE * (n)) 82 83 /* the single TX mailbox used by this driver on CAN FD HW */ 84 #define XCAN_TX_MAILBOX_IDX 0 85 86 /* CAN register bit masks - XCAN_<REG>_<BIT>_MASK */ 87 #define XCAN_SRR_CEN_MASK 0x00000002 /* CAN enable */ 88 #define XCAN_SRR_RESET_MASK 0x00000001 /* Soft Reset the CAN core */ 89 #define XCAN_MSR_LBACK_MASK 0x00000002 /* Loop back mode select */ 90 #define XCAN_MSR_SLEEP_MASK 0x00000001 /* Sleep mode select */ 91 #define XCAN_BRPR_BRP_MASK 0x000000FF /* Baud rate prescaler */ 92 #define XCAN_BRPR_TDCO_MASK GENMASK(12, 8) /* TDCO */ 93 #define XCAN_2_BRPR_TDCO_MASK GENMASK(13, 8) /* TDCO for CANFD 2.0 */ 94 #define XCAN_BTR_SJW_MASK 0x00000180 /* Synchronous jump width */ 95 #define XCAN_BTR_TS2_MASK 0x00000070 /* Time segment 2 */ 96 #define XCAN_BTR_TS1_MASK 0x0000000F /* Time segment 1 */ 97 #define XCAN_BTR_SJW_MASK_CANFD 0x000F0000 /* Synchronous jump width */ 98 #define XCAN_BTR_TS2_MASK_CANFD 0x00000F00 /* Time segment 2 */ 99 #define XCAN_BTR_TS1_MASK_CANFD 0x0000003F /* Time segment 1 */ 100 #define XCAN_ECR_REC_MASK 0x0000FF00 /* Receive error counter */ 101 #define XCAN_ECR_TEC_MASK 0x000000FF /* Transmit error counter */ 102 #define XCAN_ESR_ACKER_MASK 0x00000010 /* ACK error */ 103 #define XCAN_ESR_BERR_MASK 0x00000008 /* Bit error */ 104 #define XCAN_ESR_STER_MASK 0x00000004 /* Stuff error */ 105 #define XCAN_ESR_FMER_MASK 0x00000002 /* Form error */ 106 #define XCAN_ESR_CRCER_MASK 0x00000001 /* CRC error */ 107 #define XCAN_SR_TDCV_MASK GENMASK(22, 16) /* TDCV Value */ 108 #define XCAN_SR_TXFLL_MASK 0x00000400 /* TX FIFO is full */ 109 #define XCAN_SR_ESTAT_MASK 0x00000180 /* Error status */ 110 #define XCAN_SR_ERRWRN_MASK 0x00000040 /* Error warning */ 111 #define XCAN_SR_NORMAL_MASK 0x00000008 /* Normal mode */ 112 #define XCAN_SR_LBACK_MASK 0x00000002 /* Loop back mode */ 113 #define XCAN_SR_CONFIG_MASK 0x00000001 /* Configuration mode */ 114 #define XCAN_IXR_RXMNF_MASK 0x00020000 /* RX match not finished */ 115 #define XCAN_IXR_TXFEMP_MASK 0x00004000 /* TX FIFO Empty */ 116 #define XCAN_IXR_WKUP_MASK 0x00000800 /* Wake up interrupt */ 117 #define XCAN_IXR_SLP_MASK 0x00000400 /* Sleep interrupt */ 118 #define XCAN_IXR_BSOFF_MASK 0x00000200 /* Bus off interrupt */ 119 #define XCAN_IXR_ERROR_MASK 0x00000100 /* Error interrupt */ 120 #define XCAN_IXR_RXNEMP_MASK 0x00000080 /* RX FIFO NotEmpty intr */ 121 #define XCAN_IXR_RXOFLW_MASK 0x00000040 /* RX FIFO Overflow intr */ 122 #define XCAN_IXR_RXOK_MASK 0x00000010 /* Message received intr */ 123 #define XCAN_IXR_TXFLL_MASK 0x00000004 /* Tx FIFO Full intr */ 124 #define XCAN_IXR_TXOK_MASK 0x00000002 /* TX successful intr */ 125 #define XCAN_IXR_ARBLST_MASK 0x00000001 /* Arbitration lost intr */ 126 #define XCAN_IDR_ID1_MASK 0xFFE00000 /* Standard msg identifier */ 127 #define XCAN_IDR_SRR_MASK 0x00100000 /* Substitute remote TXreq */ 128 #define XCAN_IDR_IDE_MASK 0x00080000 /* Identifier extension */ 129 #define XCAN_IDR_ID2_MASK 0x0007FFFE /* Extended message ident */ 130 #define XCAN_IDR_RTR_MASK 0x00000001 /* Remote TX request */ 131 #define XCAN_DLCR_DLC_MASK 0xF0000000 /* Data length code */ 132 #define XCAN_FSR_FL_MASK 0x00003F00 /* RX Fill Level */ 133 #define XCAN_2_FSR_FL_MASK 0x00007F00 /* RX Fill Level */ 134 #define XCAN_FSR_IRI_MASK 0x00000080 /* RX Increment Read Index */ 135 #define XCAN_FSR_RI_MASK 0x0000001F /* RX Read Index */ 136 #define XCAN_2_FSR_RI_MASK 0x0000003F /* RX Read Index */ 137 #define XCAN_DLCR_EDL_MASK 0x08000000 /* EDL Mask in DLC */ 138 #define XCAN_DLCR_BRS_MASK 0x04000000 /* BRS Mask in DLC */ 139 140 /* CAN register bit shift - XCAN_<REG>_<BIT>_SHIFT */ 141 #define XCAN_BRPR_TDC_ENABLE BIT(16) /* Transmitter Delay Compensation (TDC) Enable */ 142 #define XCAN_BTR_SJW_SHIFT 7 /* Synchronous jump width */ 143 #define XCAN_BTR_TS2_SHIFT 4 /* Time segment 2 */ 144 #define XCAN_BTR_SJW_SHIFT_CANFD 16 /* Synchronous jump width */ 145 #define XCAN_BTR_TS2_SHIFT_CANFD 8 /* Time segment 2 */ 146 #define XCAN_IDR_ID1_SHIFT 21 /* Standard Messg Identifier */ 147 #define XCAN_IDR_ID2_SHIFT 1 /* Extended Message Identifier */ 148 #define XCAN_DLCR_DLC_SHIFT 28 /* Data length code */ 149 #define XCAN_ESR_REC_SHIFT 8 /* Rx Error Count */ 150 151 /* CAN frame length constants */ 152 #define XCAN_FRAME_MAX_DATA_LEN 8 153 #define XCANFD_DW_BYTES 4 154 #define XCAN_TIMEOUT (1 * HZ) 155 156 /* TX-FIFO-empty interrupt available */ 157 #define XCAN_FLAG_TXFEMP 0x0001 158 /* RX Match Not Finished interrupt available */ 159 #define XCAN_FLAG_RXMNF 0x0002 160 /* Extended acceptance filters with control at 0xE0 */ 161 #define XCAN_FLAG_EXT_FILTERS 0x0004 162 /* TX mailboxes instead of TX FIFO */ 163 #define XCAN_FLAG_TX_MAILBOXES 0x0008 164 /* RX FIFO with each buffer in separate registers at 0x1100 165 * instead of the regular FIFO at 0x50 166 */ 167 #define XCAN_FLAG_RX_FIFO_MULTI 0x0010 168 #define XCAN_FLAG_CANFD_2 0x0020 169 170 enum xcan_ip_type { 171 XAXI_CAN = 0, 172 XZYNQ_CANPS, 173 XAXI_CANFD, 174 XAXI_CANFD_2_0, 175 }; 176 177 struct xcan_devtype_data { 178 enum xcan_ip_type cantype; 179 unsigned int flags; 180 const struct can_bittiming_const *bittiming_const; 181 const char *bus_clk_name; 182 unsigned int btr_ts2_shift; 183 unsigned int btr_sjw_shift; 184 }; 185 186 /** 187 * struct xcan_priv - This definition define CAN driver instance 188 * @can: CAN private data structure. 189 * @tx_lock: Lock for synchronizing TX interrupt handling 190 * @tx_head: Tx CAN packets ready to send on the queue 191 * @tx_tail: Tx CAN packets successfully sended on the queue 192 * @tx_max: Maximum number packets the driver can send 193 * @napi: NAPI structure 194 * @read_reg: For reading data from CAN registers 195 * @write_reg: For writing data to CAN registers 196 * @dev: Network device data structure 197 * @reg_base: Ioremapped address to registers 198 * @irq_flags: For request_irq() 199 * @bus_clk: Pointer to struct clk 200 * @can_clk: Pointer to struct clk 201 * @devtype: Device type specific constants 202 * @transceiver: Optional pointer to associated CAN transceiver 203 */ 204 struct xcan_priv { 205 struct can_priv can; 206 spinlock_t tx_lock; /* Lock for synchronizing TX interrupt handling */ 207 unsigned int tx_head; 208 unsigned int tx_tail; 209 unsigned int tx_max; 210 struct napi_struct napi; 211 u32 (*read_reg)(const struct xcan_priv *priv, enum xcan_reg reg); 212 void (*write_reg)(const struct xcan_priv *priv, enum xcan_reg reg, 213 u32 val); 214 struct device *dev; 215 void __iomem *reg_base; 216 unsigned long irq_flags; 217 struct clk *bus_clk; 218 struct clk *can_clk; 219 struct xcan_devtype_data devtype; 220 struct phy *transceiver; 221 }; 222 223 /* CAN Bittiming constants as per Xilinx CAN specs */ 224 static const struct can_bittiming_const xcan_bittiming_const = { 225 .name = DRIVER_NAME, 226 .tseg1_min = 1, 227 .tseg1_max = 16, 228 .tseg2_min = 1, 229 .tseg2_max = 8, 230 .sjw_max = 4, 231 .brp_min = 1, 232 .brp_max = 256, 233 .brp_inc = 1, 234 }; 235 236 /* AXI CANFD Arbitration Bittiming constants as per AXI CANFD 1.0 spec */ 237 static const struct can_bittiming_const xcan_bittiming_const_canfd = { 238 .name = DRIVER_NAME, 239 .tseg1_min = 1, 240 .tseg1_max = 64, 241 .tseg2_min = 1, 242 .tseg2_max = 16, 243 .sjw_max = 16, 244 .brp_min = 1, 245 .brp_max = 256, 246 .brp_inc = 1, 247 }; 248 249 /* AXI CANFD Data Bittiming constants as per AXI CANFD 1.0 specs */ 250 static const struct can_bittiming_const xcan_data_bittiming_const_canfd = { 251 .name = DRIVER_NAME, 252 .tseg1_min = 1, 253 .tseg1_max = 16, 254 .tseg2_min = 1, 255 .tseg2_max = 8, 256 .sjw_max = 8, 257 .brp_min = 1, 258 .brp_max = 256, 259 .brp_inc = 1, 260 }; 261 262 /* AXI CANFD 2.0 Arbitration Bittiming constants as per AXI CANFD 2.0 spec */ 263 static const struct can_bittiming_const xcan_bittiming_const_canfd2 = { 264 .name = DRIVER_NAME, 265 .tseg1_min = 1, 266 .tseg1_max = 256, 267 .tseg2_min = 1, 268 .tseg2_max = 128, 269 .sjw_max = 128, 270 .brp_min = 1, 271 .brp_max = 256, 272 .brp_inc = 1, 273 }; 274 275 /* AXI CANFD 2.0 Data Bittiming constants as per AXI CANFD 2.0 spec */ 276 static const struct can_bittiming_const xcan_data_bittiming_const_canfd2 = { 277 .name = DRIVER_NAME, 278 .tseg1_min = 1, 279 .tseg1_max = 32, 280 .tseg2_min = 1, 281 .tseg2_max = 16, 282 .sjw_max = 16, 283 .brp_min = 1, 284 .brp_max = 256, 285 .brp_inc = 1, 286 }; 287 288 /* Transmission Delay Compensation constants for CANFD 1.0 */ 289 static const struct can_tdc_const xcan_tdc_const_canfd = { 290 .tdcv_min = 0, 291 .tdcv_max = 0, /* Manual mode not supported. */ 292 .tdco_min = 0, 293 .tdco_max = 32, 294 .tdcf_min = 0, /* Filter window not supported */ 295 .tdcf_max = 0, 296 }; 297 298 /* Transmission Delay Compensation constants for CANFD 2.0 */ 299 static const struct can_tdc_const xcan_tdc_const_canfd2 = { 300 .tdcv_min = 0, 301 .tdcv_max = 0, /* Manual mode not supported. */ 302 .tdco_min = 0, 303 .tdco_max = 64, 304 .tdcf_min = 0, /* Filter window not supported */ 305 .tdcf_max = 0, 306 }; 307 308 /** 309 * xcan_write_reg_le - Write a value to the device register little endian 310 * @priv: Driver private data structure 311 * @reg: Register offset 312 * @val: Value to write at the Register offset 313 * 314 * Write data to the paricular CAN register 315 */ 316 static void xcan_write_reg_le(const struct xcan_priv *priv, enum xcan_reg reg, 317 u32 val) 318 { 319 iowrite32(val, priv->reg_base + reg); 320 } 321 322 /** 323 * xcan_read_reg_le - Read a value from the device register little endian 324 * @priv: Driver private data structure 325 * @reg: Register offset 326 * 327 * Read data from the particular CAN register 328 * Return: value read from the CAN register 329 */ 330 static u32 xcan_read_reg_le(const struct xcan_priv *priv, enum xcan_reg reg) 331 { 332 return ioread32(priv->reg_base + reg); 333 } 334 335 /** 336 * xcan_write_reg_be - Write a value to the device register big endian 337 * @priv: Driver private data structure 338 * @reg: Register offset 339 * @val: Value to write at the Register offset 340 * 341 * Write data to the paricular CAN register 342 */ 343 static void xcan_write_reg_be(const struct xcan_priv *priv, enum xcan_reg reg, 344 u32 val) 345 { 346 iowrite32be(val, priv->reg_base + reg); 347 } 348 349 /** 350 * xcan_read_reg_be - Read a value from the device register big endian 351 * @priv: Driver private data structure 352 * @reg: Register offset 353 * 354 * Read data from the particular CAN register 355 * Return: value read from the CAN register 356 */ 357 static u32 xcan_read_reg_be(const struct xcan_priv *priv, enum xcan_reg reg) 358 { 359 return ioread32be(priv->reg_base + reg); 360 } 361 362 /** 363 * xcan_rx_int_mask - Get the mask for the receive interrupt 364 * @priv: Driver private data structure 365 * 366 * Return: The receive interrupt mask used by the driver on this HW 367 */ 368 static u32 xcan_rx_int_mask(const struct xcan_priv *priv) 369 { 370 /* RXNEMP is better suited for our use case as it cannot be cleared 371 * while the FIFO is non-empty, but CAN FD HW does not have it 372 */ 373 if (priv->devtype.flags & XCAN_FLAG_RX_FIFO_MULTI) 374 return XCAN_IXR_RXOK_MASK; 375 else 376 return XCAN_IXR_RXNEMP_MASK; 377 } 378 379 /** 380 * set_reset_mode - Resets the CAN device mode 381 * @ndev: Pointer to net_device structure 382 * 383 * This is the driver reset mode routine.The driver 384 * enters into configuration mode. 385 * 386 * Return: 0 on success and failure value on error 387 */ 388 static int set_reset_mode(struct net_device *ndev) 389 { 390 struct xcan_priv *priv = netdev_priv(ndev); 391 unsigned long timeout; 392 393 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK); 394 395 timeout = jiffies + XCAN_TIMEOUT; 396 while (!(priv->read_reg(priv, XCAN_SR_OFFSET) & XCAN_SR_CONFIG_MASK)) { 397 if (time_after(jiffies, timeout)) { 398 netdev_warn(ndev, "timed out for config mode\n"); 399 return -ETIMEDOUT; 400 } 401 usleep_range(500, 10000); 402 } 403 404 /* reset clears FIFOs */ 405 priv->tx_head = 0; 406 priv->tx_tail = 0; 407 408 return 0; 409 } 410 411 /** 412 * xcan_set_bittiming - CAN set bit timing routine 413 * @ndev: Pointer to net_device structure 414 * 415 * This is the driver set bittiming routine. 416 * Return: 0 on success and failure value on error 417 */ 418 static int xcan_set_bittiming(struct net_device *ndev) 419 { 420 struct xcan_priv *priv = netdev_priv(ndev); 421 struct can_bittiming *bt = &priv->can.bittiming; 422 struct can_bittiming *dbt = &priv->can.data_bittiming; 423 u32 btr0, btr1; 424 u32 is_config_mode; 425 426 /* Check whether Xilinx CAN is in configuration mode. 427 * It cannot set bit timing if Xilinx CAN is not in configuration mode. 428 */ 429 is_config_mode = priv->read_reg(priv, XCAN_SR_OFFSET) & 430 XCAN_SR_CONFIG_MASK; 431 if (!is_config_mode) { 432 netdev_alert(ndev, 433 "BUG! Cannot set bittiming - CAN is not in config mode\n"); 434 return -EPERM; 435 } 436 437 /* Setting Baud Rate prescaler value in BRPR Register */ 438 btr0 = (bt->brp - 1); 439 440 /* Setting Time Segment 1 in BTR Register */ 441 btr1 = (bt->prop_seg + bt->phase_seg1 - 1); 442 443 /* Setting Time Segment 2 in BTR Register */ 444 btr1 |= (bt->phase_seg2 - 1) << priv->devtype.btr_ts2_shift; 445 446 /* Setting Synchronous jump width in BTR Register */ 447 btr1 |= (bt->sjw - 1) << priv->devtype.btr_sjw_shift; 448 449 priv->write_reg(priv, XCAN_BRPR_OFFSET, btr0); 450 priv->write_reg(priv, XCAN_BTR_OFFSET, btr1); 451 452 if (priv->devtype.cantype == XAXI_CANFD || 453 priv->devtype.cantype == XAXI_CANFD_2_0) { 454 /* Setting Baud Rate prescaler value in F_BRPR Register */ 455 btr0 = dbt->brp - 1; 456 if (can_tdc_is_enabled(&priv->can)) { 457 if (priv->devtype.cantype == XAXI_CANFD) 458 btr0 |= FIELD_PREP(XCAN_BRPR_TDCO_MASK, priv->can.tdc.tdco) | 459 XCAN_BRPR_TDC_ENABLE; 460 else 461 btr0 |= FIELD_PREP(XCAN_2_BRPR_TDCO_MASK, priv->can.tdc.tdco) | 462 XCAN_BRPR_TDC_ENABLE; 463 } 464 465 /* Setting Time Segment 1 in BTR Register */ 466 btr1 = dbt->prop_seg + dbt->phase_seg1 - 1; 467 468 /* Setting Time Segment 2 in BTR Register */ 469 btr1 |= (dbt->phase_seg2 - 1) << priv->devtype.btr_ts2_shift; 470 471 /* Setting Synchronous jump width in BTR Register */ 472 btr1 |= (dbt->sjw - 1) << priv->devtype.btr_sjw_shift; 473 474 priv->write_reg(priv, XCAN_F_BRPR_OFFSET, btr0); 475 priv->write_reg(priv, XCAN_F_BTR_OFFSET, btr1); 476 } 477 478 netdev_dbg(ndev, "BRPR=0x%08x, BTR=0x%08x\n", 479 priv->read_reg(priv, XCAN_BRPR_OFFSET), 480 priv->read_reg(priv, XCAN_BTR_OFFSET)); 481 482 return 0; 483 } 484 485 /** 486 * xcan_chip_start - This the drivers start routine 487 * @ndev: Pointer to net_device structure 488 * 489 * This is the drivers start routine. 490 * Based on the State of the CAN device it puts 491 * the CAN device into a proper mode. 492 * 493 * Return: 0 on success and failure value on error 494 */ 495 static int xcan_chip_start(struct net_device *ndev) 496 { 497 struct xcan_priv *priv = netdev_priv(ndev); 498 u32 reg_msr; 499 int err; 500 u32 ier; 501 502 /* Check if it is in reset mode */ 503 err = set_reset_mode(ndev); 504 if (err < 0) 505 return err; 506 507 err = xcan_set_bittiming(ndev); 508 if (err < 0) 509 return err; 510 511 /* Enable interrupts 512 * 513 * We enable the ERROR interrupt even with 514 * CAN_CTRLMODE_BERR_REPORTING disabled as there is no 515 * dedicated interrupt for a state change to 516 * ERROR_WARNING/ERROR_PASSIVE. 517 */ 518 ier = XCAN_IXR_TXOK_MASK | XCAN_IXR_BSOFF_MASK | 519 XCAN_IXR_WKUP_MASK | XCAN_IXR_SLP_MASK | 520 XCAN_IXR_ERROR_MASK | XCAN_IXR_RXOFLW_MASK | 521 XCAN_IXR_ARBLST_MASK | xcan_rx_int_mask(priv); 522 523 if (priv->devtype.flags & XCAN_FLAG_RXMNF) 524 ier |= XCAN_IXR_RXMNF_MASK; 525 526 priv->write_reg(priv, XCAN_IER_OFFSET, ier); 527 528 /* Check whether it is loopback mode or normal mode */ 529 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 530 reg_msr = XCAN_MSR_LBACK_MASK; 531 else 532 reg_msr = 0x0; 533 534 /* enable the first extended filter, if any, as cores with extended 535 * filtering default to non-receipt if all filters are disabled 536 */ 537 if (priv->devtype.flags & XCAN_FLAG_EXT_FILTERS) 538 priv->write_reg(priv, XCAN_AFR_EXT_OFFSET, 0x00000001); 539 540 priv->write_reg(priv, XCAN_MSR_OFFSET, reg_msr); 541 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_CEN_MASK); 542 543 netdev_dbg(ndev, "status:#x%08x\n", 544 priv->read_reg(priv, XCAN_SR_OFFSET)); 545 546 priv->can.state = CAN_STATE_ERROR_ACTIVE; 547 return 0; 548 } 549 550 /** 551 * xcan_do_set_mode - This sets the mode of the driver 552 * @ndev: Pointer to net_device structure 553 * @mode: Tells the mode of the driver 554 * 555 * This check the drivers state and calls the corresponding modes to set. 556 * 557 * Return: 0 on success and failure value on error 558 */ 559 static int xcan_do_set_mode(struct net_device *ndev, enum can_mode mode) 560 { 561 int ret; 562 563 switch (mode) { 564 case CAN_MODE_START: 565 ret = xcan_chip_start(ndev); 566 if (ret < 0) { 567 netdev_err(ndev, "xcan_chip_start failed!\n"); 568 return ret; 569 } 570 netif_wake_queue(ndev); 571 break; 572 default: 573 ret = -EOPNOTSUPP; 574 break; 575 } 576 577 return ret; 578 } 579 580 /** 581 * xcan_write_frame - Write a frame to HW 582 * @ndev: Pointer to net_device structure 583 * @skb: sk_buff pointer that contains data to be Txed 584 * @frame_offset: Register offset to write the frame to 585 */ 586 static void xcan_write_frame(struct net_device *ndev, struct sk_buff *skb, 587 int frame_offset) 588 { 589 u32 id, dlc, data[2] = {0, 0}; 590 struct canfd_frame *cf = (struct canfd_frame *)skb->data; 591 u32 ramoff, dwindex = 0, i; 592 struct xcan_priv *priv = netdev_priv(ndev); 593 594 /* Watch carefully on the bit sequence */ 595 if (cf->can_id & CAN_EFF_FLAG) { 596 /* Extended CAN ID format */ 597 id = ((cf->can_id & CAN_EFF_MASK) << XCAN_IDR_ID2_SHIFT) & 598 XCAN_IDR_ID2_MASK; 599 id |= (((cf->can_id & CAN_EFF_MASK) >> 600 (CAN_EFF_ID_BITS - CAN_SFF_ID_BITS)) << 601 XCAN_IDR_ID1_SHIFT) & XCAN_IDR_ID1_MASK; 602 603 /* The substibute remote TX request bit should be "1" 604 * for extended frames as in the Xilinx CAN datasheet 605 */ 606 id |= XCAN_IDR_IDE_MASK | XCAN_IDR_SRR_MASK; 607 608 if (cf->can_id & CAN_RTR_FLAG) 609 /* Extended frames remote TX request */ 610 id |= XCAN_IDR_RTR_MASK; 611 } else { 612 /* Standard CAN ID format */ 613 id = ((cf->can_id & CAN_SFF_MASK) << XCAN_IDR_ID1_SHIFT) & 614 XCAN_IDR_ID1_MASK; 615 616 if (cf->can_id & CAN_RTR_FLAG) 617 /* Standard frames remote TX request */ 618 id |= XCAN_IDR_SRR_MASK; 619 } 620 621 dlc = can_fd_len2dlc(cf->len) << XCAN_DLCR_DLC_SHIFT; 622 if (can_is_canfd_skb(skb)) { 623 if (cf->flags & CANFD_BRS) 624 dlc |= XCAN_DLCR_BRS_MASK; 625 dlc |= XCAN_DLCR_EDL_MASK; 626 } 627 628 if (!(priv->devtype.flags & XCAN_FLAG_TX_MAILBOXES) && 629 (priv->devtype.flags & XCAN_FLAG_TXFEMP)) 630 can_put_echo_skb(skb, ndev, priv->tx_head % priv->tx_max, 0); 631 else 632 can_put_echo_skb(skb, ndev, 0, 0); 633 634 priv->tx_head++; 635 636 priv->write_reg(priv, XCAN_FRAME_ID_OFFSET(frame_offset), id); 637 /* If the CAN frame is RTR frame this write triggers transmission 638 * (not on CAN FD) 639 */ 640 priv->write_reg(priv, XCAN_FRAME_DLC_OFFSET(frame_offset), dlc); 641 if (priv->devtype.cantype == XAXI_CANFD || 642 priv->devtype.cantype == XAXI_CANFD_2_0) { 643 for (i = 0; i < cf->len; i += 4) { 644 ramoff = XCANFD_FRAME_DW_OFFSET(frame_offset) + 645 (dwindex * XCANFD_DW_BYTES); 646 priv->write_reg(priv, ramoff, 647 be32_to_cpup((__be32 *)(cf->data + i))); 648 dwindex++; 649 } 650 } else { 651 if (cf->len > 0) 652 data[0] = be32_to_cpup((__be32 *)(cf->data + 0)); 653 if (cf->len > 4) 654 data[1] = be32_to_cpup((__be32 *)(cf->data + 4)); 655 656 if (!(cf->can_id & CAN_RTR_FLAG)) { 657 priv->write_reg(priv, 658 XCAN_FRAME_DW1_OFFSET(frame_offset), 659 data[0]); 660 /* If the CAN frame is Standard/Extended frame this 661 * write triggers transmission (not on CAN FD) 662 */ 663 priv->write_reg(priv, 664 XCAN_FRAME_DW2_OFFSET(frame_offset), 665 data[1]); 666 } 667 } 668 } 669 670 /** 671 * xcan_start_xmit_fifo - Starts the transmission (FIFO mode) 672 * @skb: sk_buff pointer that contains data to be Txed 673 * @ndev: Pointer to net_device structure 674 * 675 * Return: 0 on success, -ENOSPC if FIFO is full. 676 */ 677 static int xcan_start_xmit_fifo(struct sk_buff *skb, struct net_device *ndev) 678 { 679 struct xcan_priv *priv = netdev_priv(ndev); 680 unsigned long flags; 681 682 /* Check if the TX buffer is full */ 683 if (unlikely(priv->read_reg(priv, XCAN_SR_OFFSET) & 684 XCAN_SR_TXFLL_MASK)) 685 return -ENOSPC; 686 687 spin_lock_irqsave(&priv->tx_lock, flags); 688 689 xcan_write_frame(ndev, skb, XCAN_TXFIFO_OFFSET); 690 691 /* Clear TX-FIFO-empty interrupt for xcan_tx_interrupt() */ 692 if (priv->tx_max > 1) 693 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXFEMP_MASK); 694 695 /* Check if the TX buffer is full */ 696 if ((priv->tx_head - priv->tx_tail) == priv->tx_max) 697 netif_stop_queue(ndev); 698 699 spin_unlock_irqrestore(&priv->tx_lock, flags); 700 701 return 0; 702 } 703 704 /** 705 * xcan_start_xmit_mailbox - Starts the transmission (mailbox mode) 706 * @skb: sk_buff pointer that contains data to be Txed 707 * @ndev: Pointer to net_device structure 708 * 709 * Return: 0 on success, -ENOSPC if there is no space 710 */ 711 static int xcan_start_xmit_mailbox(struct sk_buff *skb, struct net_device *ndev) 712 { 713 struct xcan_priv *priv = netdev_priv(ndev); 714 unsigned long flags; 715 716 if (unlikely(priv->read_reg(priv, XCAN_TRR_OFFSET) & 717 BIT(XCAN_TX_MAILBOX_IDX))) 718 return -ENOSPC; 719 720 spin_lock_irqsave(&priv->tx_lock, flags); 721 722 xcan_write_frame(ndev, skb, 723 XCAN_TXMSG_FRAME_OFFSET(XCAN_TX_MAILBOX_IDX)); 724 725 /* Mark buffer as ready for transmit */ 726 priv->write_reg(priv, XCAN_TRR_OFFSET, BIT(XCAN_TX_MAILBOX_IDX)); 727 728 netif_stop_queue(ndev); 729 730 spin_unlock_irqrestore(&priv->tx_lock, flags); 731 732 return 0; 733 } 734 735 /** 736 * xcan_start_xmit - Starts the transmission 737 * @skb: sk_buff pointer that contains data to be Txed 738 * @ndev: Pointer to net_device structure 739 * 740 * This function is invoked from upper layers to initiate transmission. 741 * 742 * Return: NETDEV_TX_OK on success and NETDEV_TX_BUSY when the tx queue is full 743 */ 744 static netdev_tx_t xcan_start_xmit(struct sk_buff *skb, struct net_device *ndev) 745 { 746 struct xcan_priv *priv = netdev_priv(ndev); 747 int ret; 748 749 if (can_dev_dropped_skb(ndev, skb)) 750 return NETDEV_TX_OK; 751 752 if (priv->devtype.flags & XCAN_FLAG_TX_MAILBOXES) 753 ret = xcan_start_xmit_mailbox(skb, ndev); 754 else 755 ret = xcan_start_xmit_fifo(skb, ndev); 756 757 if (ret < 0) { 758 netdev_err(ndev, "BUG!, TX full when queue awake!\n"); 759 netif_stop_queue(ndev); 760 return NETDEV_TX_BUSY; 761 } 762 763 return NETDEV_TX_OK; 764 } 765 766 /** 767 * xcan_rx - Is called from CAN isr to complete the received 768 * frame processing 769 * @ndev: Pointer to net_device structure 770 * @frame_base: Register offset to the frame to be read 771 * 772 * This function is invoked from the CAN isr(poll) to process the Rx frames. It 773 * does minimal processing and invokes "netif_receive_skb" to complete further 774 * processing. 775 * Return: 1 on success and 0 on failure. 776 */ 777 static int xcan_rx(struct net_device *ndev, int frame_base) 778 { 779 struct xcan_priv *priv = netdev_priv(ndev); 780 struct net_device_stats *stats = &ndev->stats; 781 struct can_frame *cf; 782 struct sk_buff *skb; 783 u32 id_xcan, dlc, data[2] = {0, 0}; 784 785 skb = alloc_can_skb(ndev, &cf); 786 if (unlikely(!skb)) { 787 stats->rx_dropped++; 788 return 0; 789 } 790 791 /* Read a frame from Xilinx zynq CANPS */ 792 id_xcan = priv->read_reg(priv, XCAN_FRAME_ID_OFFSET(frame_base)); 793 dlc = priv->read_reg(priv, XCAN_FRAME_DLC_OFFSET(frame_base)) >> 794 XCAN_DLCR_DLC_SHIFT; 795 796 /* Change Xilinx CAN data length format to socketCAN data format */ 797 cf->len = can_cc_dlc2len(dlc); 798 799 /* Change Xilinx CAN ID format to socketCAN ID format */ 800 if (id_xcan & XCAN_IDR_IDE_MASK) { 801 /* The received frame is an Extended format frame */ 802 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> 3; 803 cf->can_id |= (id_xcan & XCAN_IDR_ID2_MASK) >> 804 XCAN_IDR_ID2_SHIFT; 805 cf->can_id |= CAN_EFF_FLAG; 806 if (id_xcan & XCAN_IDR_RTR_MASK) 807 cf->can_id |= CAN_RTR_FLAG; 808 } else { 809 /* The received frame is a standard format frame */ 810 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> 811 XCAN_IDR_ID1_SHIFT; 812 if (id_xcan & XCAN_IDR_SRR_MASK) 813 cf->can_id |= CAN_RTR_FLAG; 814 } 815 816 /* DW1/DW2 must always be read to remove message from RXFIFO */ 817 data[0] = priv->read_reg(priv, XCAN_FRAME_DW1_OFFSET(frame_base)); 818 data[1] = priv->read_reg(priv, XCAN_FRAME_DW2_OFFSET(frame_base)); 819 820 if (!(cf->can_id & CAN_RTR_FLAG)) { 821 /* Change Xilinx CAN data format to socketCAN data format */ 822 if (cf->len > 0) 823 *(__be32 *)(cf->data) = cpu_to_be32(data[0]); 824 if (cf->len > 4) 825 *(__be32 *)(cf->data + 4) = cpu_to_be32(data[1]); 826 827 stats->rx_bytes += cf->len; 828 } 829 stats->rx_packets++; 830 831 netif_receive_skb(skb); 832 833 return 1; 834 } 835 836 /** 837 * xcanfd_rx - Is called from CAN isr to complete the received 838 * frame processing 839 * @ndev: Pointer to net_device structure 840 * @frame_base: Register offset to the frame to be read 841 * 842 * This function is invoked from the CAN isr(poll) to process the Rx frames. It 843 * does minimal processing and invokes "netif_receive_skb" to complete further 844 * processing. 845 * Return: 1 on success and 0 on failure. 846 */ 847 static int xcanfd_rx(struct net_device *ndev, int frame_base) 848 { 849 struct xcan_priv *priv = netdev_priv(ndev); 850 struct net_device_stats *stats = &ndev->stats; 851 struct canfd_frame *cf; 852 struct sk_buff *skb; 853 u32 id_xcan, dlc, data[2] = {0, 0}, dwindex = 0, i, dw_offset; 854 855 id_xcan = priv->read_reg(priv, XCAN_FRAME_ID_OFFSET(frame_base)); 856 dlc = priv->read_reg(priv, XCAN_FRAME_DLC_OFFSET(frame_base)); 857 if (dlc & XCAN_DLCR_EDL_MASK) 858 skb = alloc_canfd_skb(ndev, &cf); 859 else 860 skb = alloc_can_skb(ndev, (struct can_frame **)&cf); 861 862 if (unlikely(!skb)) { 863 stats->rx_dropped++; 864 return 0; 865 } 866 867 /* Change Xilinx CANFD data length format to socketCAN data 868 * format 869 */ 870 if (dlc & XCAN_DLCR_EDL_MASK) 871 cf->len = can_fd_dlc2len((dlc & XCAN_DLCR_DLC_MASK) >> 872 XCAN_DLCR_DLC_SHIFT); 873 else 874 cf->len = can_cc_dlc2len((dlc & XCAN_DLCR_DLC_MASK) >> 875 XCAN_DLCR_DLC_SHIFT); 876 877 /* Change Xilinx CAN ID format to socketCAN ID format */ 878 if (id_xcan & XCAN_IDR_IDE_MASK) { 879 /* The received frame is an Extended format frame */ 880 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> 3; 881 cf->can_id |= (id_xcan & XCAN_IDR_ID2_MASK) >> 882 XCAN_IDR_ID2_SHIFT; 883 cf->can_id |= CAN_EFF_FLAG; 884 if (id_xcan & XCAN_IDR_RTR_MASK) 885 cf->can_id |= CAN_RTR_FLAG; 886 } else { 887 /* The received frame is a standard format frame */ 888 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> 889 XCAN_IDR_ID1_SHIFT; 890 if (!(dlc & XCAN_DLCR_EDL_MASK) && (id_xcan & 891 XCAN_IDR_SRR_MASK)) 892 cf->can_id |= CAN_RTR_FLAG; 893 } 894 895 /* Check the frame received is FD or not*/ 896 if (dlc & XCAN_DLCR_EDL_MASK) { 897 for (i = 0; i < cf->len; i += 4) { 898 dw_offset = XCANFD_FRAME_DW_OFFSET(frame_base) + 899 (dwindex * XCANFD_DW_BYTES); 900 data[0] = priv->read_reg(priv, dw_offset); 901 *(__be32 *)(cf->data + i) = cpu_to_be32(data[0]); 902 dwindex++; 903 } 904 } else { 905 for (i = 0; i < cf->len; i += 4) { 906 dw_offset = XCANFD_FRAME_DW_OFFSET(frame_base); 907 data[0] = priv->read_reg(priv, dw_offset + i); 908 *(__be32 *)(cf->data + i) = cpu_to_be32(data[0]); 909 } 910 } 911 912 if (!(cf->can_id & CAN_RTR_FLAG)) 913 stats->rx_bytes += cf->len; 914 stats->rx_packets++; 915 916 netif_receive_skb(skb); 917 918 return 1; 919 } 920 921 /** 922 * xcan_current_error_state - Get current error state from HW 923 * @ndev: Pointer to net_device structure 924 * 925 * Checks the current CAN error state from the HW. Note that this 926 * only checks for ERROR_PASSIVE and ERROR_WARNING. 927 * 928 * Return: 929 * ERROR_PASSIVE or ERROR_WARNING if either is active, ERROR_ACTIVE 930 * otherwise. 931 */ 932 static enum can_state xcan_current_error_state(struct net_device *ndev) 933 { 934 struct xcan_priv *priv = netdev_priv(ndev); 935 u32 status = priv->read_reg(priv, XCAN_SR_OFFSET); 936 937 if ((status & XCAN_SR_ESTAT_MASK) == XCAN_SR_ESTAT_MASK) 938 return CAN_STATE_ERROR_PASSIVE; 939 else if (status & XCAN_SR_ERRWRN_MASK) 940 return CAN_STATE_ERROR_WARNING; 941 else 942 return CAN_STATE_ERROR_ACTIVE; 943 } 944 945 /** 946 * xcan_set_error_state - Set new CAN error state 947 * @ndev: Pointer to net_device structure 948 * @new_state: The new CAN state to be set 949 * @cf: Error frame to be populated or NULL 950 * 951 * Set new CAN error state for the device, updating statistics and 952 * populating the error frame if given. 953 */ 954 static void xcan_set_error_state(struct net_device *ndev, 955 enum can_state new_state, 956 struct can_frame *cf) 957 { 958 struct xcan_priv *priv = netdev_priv(ndev); 959 u32 ecr = priv->read_reg(priv, XCAN_ECR_OFFSET); 960 u32 txerr = ecr & XCAN_ECR_TEC_MASK; 961 u32 rxerr = (ecr & XCAN_ECR_REC_MASK) >> XCAN_ESR_REC_SHIFT; 962 enum can_state tx_state = txerr >= rxerr ? new_state : 0; 963 enum can_state rx_state = txerr <= rxerr ? new_state : 0; 964 965 /* non-ERROR states are handled elsewhere */ 966 if (WARN_ON(new_state > CAN_STATE_ERROR_PASSIVE)) 967 return; 968 969 can_change_state(ndev, cf, tx_state, rx_state); 970 971 if (cf) { 972 cf->can_id |= CAN_ERR_CNT; 973 cf->data[6] = txerr; 974 cf->data[7] = rxerr; 975 } 976 } 977 978 /** 979 * xcan_update_error_state_after_rxtx - Update CAN error state after RX/TX 980 * @ndev: Pointer to net_device structure 981 * 982 * If the device is in a ERROR-WARNING or ERROR-PASSIVE state, check if 983 * the performed RX/TX has caused it to drop to a lesser state and set 984 * the interface state accordingly. 985 */ 986 static void xcan_update_error_state_after_rxtx(struct net_device *ndev) 987 { 988 struct xcan_priv *priv = netdev_priv(ndev); 989 enum can_state old_state = priv->can.state; 990 enum can_state new_state; 991 992 /* changing error state due to successful frame RX/TX can only 993 * occur from these states 994 */ 995 if (old_state != CAN_STATE_ERROR_WARNING && 996 old_state != CAN_STATE_ERROR_PASSIVE) 997 return; 998 999 new_state = xcan_current_error_state(ndev); 1000 1001 if (new_state != old_state) { 1002 struct sk_buff *skb; 1003 struct can_frame *cf; 1004 1005 skb = alloc_can_err_skb(ndev, &cf); 1006 1007 xcan_set_error_state(ndev, new_state, skb ? cf : NULL); 1008 1009 if (skb) 1010 netif_rx(skb); 1011 } 1012 } 1013 1014 /** 1015 * xcan_err_interrupt - error frame Isr 1016 * @ndev: net_device pointer 1017 * @isr: interrupt status register value 1018 * 1019 * This is the CAN error interrupt and it will 1020 * check the type of error and forward the error 1021 * frame to upper layers. 1022 */ 1023 static void xcan_err_interrupt(struct net_device *ndev, u32 isr) 1024 { 1025 struct xcan_priv *priv = netdev_priv(ndev); 1026 struct net_device_stats *stats = &ndev->stats; 1027 struct can_frame cf = { }; 1028 u32 err_status; 1029 1030 err_status = priv->read_reg(priv, XCAN_ESR_OFFSET); 1031 priv->write_reg(priv, XCAN_ESR_OFFSET, err_status); 1032 1033 if (isr & XCAN_IXR_BSOFF_MASK) { 1034 priv->can.state = CAN_STATE_BUS_OFF; 1035 priv->can.can_stats.bus_off++; 1036 /* Leave device in Config Mode in bus-off state */ 1037 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK); 1038 can_bus_off(ndev); 1039 cf.can_id |= CAN_ERR_BUSOFF; 1040 } else { 1041 enum can_state new_state = xcan_current_error_state(ndev); 1042 1043 if (new_state != priv->can.state) 1044 xcan_set_error_state(ndev, new_state, &cf); 1045 } 1046 1047 /* Check for Arbitration lost interrupt */ 1048 if (isr & XCAN_IXR_ARBLST_MASK) { 1049 priv->can.can_stats.arbitration_lost++; 1050 cf.can_id |= CAN_ERR_LOSTARB; 1051 cf.data[0] = CAN_ERR_LOSTARB_UNSPEC; 1052 } 1053 1054 /* Check for RX FIFO Overflow interrupt */ 1055 if (isr & XCAN_IXR_RXOFLW_MASK) { 1056 stats->rx_over_errors++; 1057 stats->rx_errors++; 1058 cf.can_id |= CAN_ERR_CRTL; 1059 cf.data[1] |= CAN_ERR_CRTL_RX_OVERFLOW; 1060 } 1061 1062 /* Check for RX Match Not Finished interrupt */ 1063 if (isr & XCAN_IXR_RXMNF_MASK) { 1064 stats->rx_dropped++; 1065 stats->rx_errors++; 1066 netdev_err(ndev, "RX match not finished, frame discarded\n"); 1067 cf.can_id |= CAN_ERR_CRTL; 1068 cf.data[1] |= CAN_ERR_CRTL_UNSPEC; 1069 } 1070 1071 /* Check for error interrupt */ 1072 if (isr & XCAN_IXR_ERROR_MASK) { 1073 bool berr_reporting = false; 1074 1075 if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) { 1076 berr_reporting = true; 1077 cf.can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 1078 } 1079 1080 /* Check for Ack error interrupt */ 1081 if (err_status & XCAN_ESR_ACKER_MASK) { 1082 stats->tx_errors++; 1083 if (berr_reporting) { 1084 cf.can_id |= CAN_ERR_ACK; 1085 cf.data[3] = CAN_ERR_PROT_LOC_ACK; 1086 } 1087 } 1088 1089 /* Check for Bit error interrupt */ 1090 if (err_status & XCAN_ESR_BERR_MASK) { 1091 stats->tx_errors++; 1092 if (berr_reporting) { 1093 cf.can_id |= CAN_ERR_PROT; 1094 cf.data[2] = CAN_ERR_PROT_BIT; 1095 } 1096 } 1097 1098 /* Check for Stuff error interrupt */ 1099 if (err_status & XCAN_ESR_STER_MASK) { 1100 stats->rx_errors++; 1101 if (berr_reporting) { 1102 cf.can_id |= CAN_ERR_PROT; 1103 cf.data[2] = CAN_ERR_PROT_STUFF; 1104 } 1105 } 1106 1107 /* Check for Form error interrupt */ 1108 if (err_status & XCAN_ESR_FMER_MASK) { 1109 stats->rx_errors++; 1110 if (berr_reporting) { 1111 cf.can_id |= CAN_ERR_PROT; 1112 cf.data[2] = CAN_ERR_PROT_FORM; 1113 } 1114 } 1115 1116 /* Check for CRC error interrupt */ 1117 if (err_status & XCAN_ESR_CRCER_MASK) { 1118 stats->rx_errors++; 1119 if (berr_reporting) { 1120 cf.can_id |= CAN_ERR_PROT; 1121 cf.data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; 1122 } 1123 } 1124 priv->can.can_stats.bus_error++; 1125 } 1126 1127 if (cf.can_id) { 1128 struct can_frame *skb_cf; 1129 struct sk_buff *skb = alloc_can_err_skb(ndev, &skb_cf); 1130 1131 if (skb) { 1132 skb_cf->can_id |= cf.can_id; 1133 memcpy(skb_cf->data, cf.data, CAN_ERR_DLC); 1134 netif_rx(skb); 1135 } 1136 } 1137 1138 netdev_dbg(ndev, "%s: error status register:0x%x\n", 1139 __func__, priv->read_reg(priv, XCAN_ESR_OFFSET)); 1140 } 1141 1142 /** 1143 * xcan_state_interrupt - It will check the state of the CAN device 1144 * @ndev: net_device pointer 1145 * @isr: interrupt status register value 1146 * 1147 * This will checks the state of the CAN device 1148 * and puts the device into appropriate state. 1149 */ 1150 static void xcan_state_interrupt(struct net_device *ndev, u32 isr) 1151 { 1152 struct xcan_priv *priv = netdev_priv(ndev); 1153 1154 /* Check for Sleep interrupt if set put CAN device in sleep state */ 1155 if (isr & XCAN_IXR_SLP_MASK) 1156 priv->can.state = CAN_STATE_SLEEPING; 1157 1158 /* Check for Wake up interrupt if set put CAN device in Active state */ 1159 if (isr & XCAN_IXR_WKUP_MASK) 1160 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1161 } 1162 1163 /** 1164 * xcan_rx_fifo_get_next_frame - Get register offset of next RX frame 1165 * @priv: Driver private data structure 1166 * 1167 * Return: Register offset of the next frame in RX FIFO. 1168 */ 1169 static int xcan_rx_fifo_get_next_frame(struct xcan_priv *priv) 1170 { 1171 int offset; 1172 1173 if (priv->devtype.flags & XCAN_FLAG_RX_FIFO_MULTI) { 1174 u32 fsr, mask; 1175 1176 /* clear RXOK before the is-empty check so that any newly 1177 * received frame will reassert it without a race 1178 */ 1179 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_RXOK_MASK); 1180 1181 fsr = priv->read_reg(priv, XCAN_FSR_OFFSET); 1182 1183 /* check if RX FIFO is empty */ 1184 if (priv->devtype.flags & XCAN_FLAG_CANFD_2) 1185 mask = XCAN_2_FSR_FL_MASK; 1186 else 1187 mask = XCAN_FSR_FL_MASK; 1188 1189 if (!(fsr & mask)) 1190 return -ENOENT; 1191 1192 if (priv->devtype.flags & XCAN_FLAG_CANFD_2) 1193 offset = 1194 XCAN_RXMSG_2_FRAME_OFFSET(fsr & XCAN_2_FSR_RI_MASK); 1195 else 1196 offset = 1197 XCAN_RXMSG_FRAME_OFFSET(fsr & XCAN_FSR_RI_MASK); 1198 1199 } else { 1200 /* check if RX FIFO is empty */ 1201 if (!(priv->read_reg(priv, XCAN_ISR_OFFSET) & 1202 XCAN_IXR_RXNEMP_MASK)) 1203 return -ENOENT; 1204 1205 /* frames are read from a static offset */ 1206 offset = XCAN_RXFIFO_OFFSET; 1207 } 1208 1209 return offset; 1210 } 1211 1212 /** 1213 * xcan_rx_poll - Poll routine for rx packets (NAPI) 1214 * @napi: napi structure pointer 1215 * @quota: Max number of rx packets to be processed. 1216 * 1217 * This is the poll routine for rx part. 1218 * It will process the packets maximux quota value. 1219 * 1220 * Return: number of packets received 1221 */ 1222 static int xcan_rx_poll(struct napi_struct *napi, int quota) 1223 { 1224 struct net_device *ndev = napi->dev; 1225 struct xcan_priv *priv = netdev_priv(ndev); 1226 u32 ier; 1227 int work_done = 0; 1228 int frame_offset; 1229 1230 while ((frame_offset = xcan_rx_fifo_get_next_frame(priv)) >= 0 && 1231 (work_done < quota)) { 1232 if (xcan_rx_int_mask(priv) & XCAN_IXR_RXOK_MASK) 1233 work_done += xcanfd_rx(ndev, frame_offset); 1234 else 1235 work_done += xcan_rx(ndev, frame_offset); 1236 1237 if (priv->devtype.flags & XCAN_FLAG_RX_FIFO_MULTI) 1238 /* increment read index */ 1239 priv->write_reg(priv, XCAN_FSR_OFFSET, 1240 XCAN_FSR_IRI_MASK); 1241 else 1242 /* clear rx-not-empty (will actually clear only if 1243 * empty) 1244 */ 1245 priv->write_reg(priv, XCAN_ICR_OFFSET, 1246 XCAN_IXR_RXNEMP_MASK); 1247 } 1248 1249 if (work_done) 1250 xcan_update_error_state_after_rxtx(ndev); 1251 1252 if (work_done < quota) { 1253 if (napi_complete_done(napi, work_done)) { 1254 ier = priv->read_reg(priv, XCAN_IER_OFFSET); 1255 ier |= xcan_rx_int_mask(priv); 1256 priv->write_reg(priv, XCAN_IER_OFFSET, ier); 1257 } 1258 } 1259 return work_done; 1260 } 1261 1262 /** 1263 * xcan_tx_interrupt - Tx Done Isr 1264 * @ndev: net_device pointer 1265 * @isr: Interrupt status register value 1266 */ 1267 static void xcan_tx_interrupt(struct net_device *ndev, u32 isr) 1268 { 1269 struct xcan_priv *priv = netdev_priv(ndev); 1270 struct net_device_stats *stats = &ndev->stats; 1271 unsigned int frames_in_fifo; 1272 int frames_sent = 1; /* TXOK => at least 1 frame was sent */ 1273 unsigned long flags; 1274 int retries = 0; 1275 1276 /* Synchronize with xmit as we need to know the exact number 1277 * of frames in the FIFO to stay in sync due to the TXFEMP 1278 * handling. 1279 * This also prevents a race between netif_wake_queue() and 1280 * netif_stop_queue(). 1281 */ 1282 spin_lock_irqsave(&priv->tx_lock, flags); 1283 1284 frames_in_fifo = priv->tx_head - priv->tx_tail; 1285 1286 if (WARN_ON_ONCE(frames_in_fifo == 0)) { 1287 /* clear TXOK anyway to avoid getting back here */ 1288 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK); 1289 spin_unlock_irqrestore(&priv->tx_lock, flags); 1290 return; 1291 } 1292 1293 /* Check if 2 frames were sent (TXOK only means that at least 1 1294 * frame was sent). 1295 */ 1296 if (frames_in_fifo > 1) { 1297 WARN_ON(frames_in_fifo > priv->tx_max); 1298 1299 /* Synchronize TXOK and isr so that after the loop: 1300 * (1) isr variable is up-to-date at least up to TXOK clear 1301 * time. This avoids us clearing a TXOK of a second frame 1302 * but not noticing that the FIFO is now empty and thus 1303 * marking only a single frame as sent. 1304 * (2) No TXOK is left. Having one could mean leaving a 1305 * stray TXOK as we might process the associated frame 1306 * via TXFEMP handling as we read TXFEMP *after* TXOK 1307 * clear to satisfy (1). 1308 */ 1309 while ((isr & XCAN_IXR_TXOK_MASK) && 1310 !WARN_ON(++retries == 100)) { 1311 priv->write_reg(priv, XCAN_ICR_OFFSET, 1312 XCAN_IXR_TXOK_MASK); 1313 isr = priv->read_reg(priv, XCAN_ISR_OFFSET); 1314 } 1315 1316 if (isr & XCAN_IXR_TXFEMP_MASK) { 1317 /* nothing in FIFO anymore */ 1318 frames_sent = frames_in_fifo; 1319 } 1320 } else { 1321 /* single frame in fifo, just clear TXOK */ 1322 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK); 1323 } 1324 1325 while (frames_sent--) { 1326 stats->tx_bytes += can_get_echo_skb(ndev, priv->tx_tail % 1327 priv->tx_max, NULL); 1328 priv->tx_tail++; 1329 stats->tx_packets++; 1330 } 1331 1332 netif_wake_queue(ndev); 1333 1334 spin_unlock_irqrestore(&priv->tx_lock, flags); 1335 1336 xcan_update_error_state_after_rxtx(ndev); 1337 } 1338 1339 /** 1340 * xcan_interrupt - CAN Isr 1341 * @irq: irq number 1342 * @dev_id: device id pointer 1343 * 1344 * This is the xilinx CAN Isr. It checks for the type of interrupt 1345 * and invokes the corresponding ISR. 1346 * 1347 * Return: 1348 * IRQ_NONE - If CAN device is in sleep mode, IRQ_HANDLED otherwise 1349 */ 1350 static irqreturn_t xcan_interrupt(int irq, void *dev_id) 1351 { 1352 struct net_device *ndev = (struct net_device *)dev_id; 1353 struct xcan_priv *priv = netdev_priv(ndev); 1354 u32 isr, ier; 1355 u32 isr_errors; 1356 u32 rx_int_mask = xcan_rx_int_mask(priv); 1357 1358 /* Get the interrupt status from Xilinx CAN */ 1359 isr = priv->read_reg(priv, XCAN_ISR_OFFSET); 1360 if (!isr) 1361 return IRQ_NONE; 1362 1363 /* Check for the type of interrupt and Processing it */ 1364 if (isr & (XCAN_IXR_SLP_MASK | XCAN_IXR_WKUP_MASK)) { 1365 priv->write_reg(priv, XCAN_ICR_OFFSET, (XCAN_IXR_SLP_MASK | 1366 XCAN_IXR_WKUP_MASK)); 1367 xcan_state_interrupt(ndev, isr); 1368 } 1369 1370 /* Check for Tx interrupt and Processing it */ 1371 if (isr & XCAN_IXR_TXOK_MASK) 1372 xcan_tx_interrupt(ndev, isr); 1373 1374 /* Check for the type of error interrupt and Processing it */ 1375 isr_errors = isr & (XCAN_IXR_ERROR_MASK | XCAN_IXR_RXOFLW_MASK | 1376 XCAN_IXR_BSOFF_MASK | XCAN_IXR_ARBLST_MASK | 1377 XCAN_IXR_RXMNF_MASK); 1378 if (isr_errors) { 1379 priv->write_reg(priv, XCAN_ICR_OFFSET, isr_errors); 1380 xcan_err_interrupt(ndev, isr); 1381 } 1382 1383 /* Check for the type of receive interrupt and Processing it */ 1384 if (isr & rx_int_mask) { 1385 ier = priv->read_reg(priv, XCAN_IER_OFFSET); 1386 ier &= ~rx_int_mask; 1387 priv->write_reg(priv, XCAN_IER_OFFSET, ier); 1388 napi_schedule(&priv->napi); 1389 } 1390 return IRQ_HANDLED; 1391 } 1392 1393 /** 1394 * xcan_chip_stop - Driver stop routine 1395 * @ndev: Pointer to net_device structure 1396 * 1397 * This is the drivers stop routine. It will disable the 1398 * interrupts and put the device into configuration mode. 1399 */ 1400 static void xcan_chip_stop(struct net_device *ndev) 1401 { 1402 struct xcan_priv *priv = netdev_priv(ndev); 1403 int ret; 1404 1405 /* Disable interrupts and leave the can in configuration mode */ 1406 ret = set_reset_mode(ndev); 1407 if (ret < 0) 1408 netdev_dbg(ndev, "set_reset_mode() Failed\n"); 1409 1410 priv->can.state = CAN_STATE_STOPPED; 1411 } 1412 1413 /** 1414 * xcan_open - Driver open routine 1415 * @ndev: Pointer to net_device structure 1416 * 1417 * This is the driver open routine. 1418 * Return: 0 on success and failure value on error 1419 */ 1420 static int xcan_open(struct net_device *ndev) 1421 { 1422 struct xcan_priv *priv = netdev_priv(ndev); 1423 int ret; 1424 1425 ret = phy_power_on(priv->transceiver); 1426 if (ret) 1427 return ret; 1428 1429 ret = pm_runtime_get_sync(priv->dev); 1430 if (ret < 0) { 1431 netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n", 1432 __func__, ret); 1433 goto err; 1434 } 1435 1436 ret = request_irq(ndev->irq, xcan_interrupt, priv->irq_flags, 1437 ndev->name, ndev); 1438 if (ret < 0) { 1439 netdev_err(ndev, "irq allocation for CAN failed\n"); 1440 goto err; 1441 } 1442 1443 /* Set chip into reset mode */ 1444 ret = set_reset_mode(ndev); 1445 if (ret < 0) { 1446 netdev_err(ndev, "mode resetting failed!\n"); 1447 goto err_irq; 1448 } 1449 1450 /* Common open */ 1451 ret = open_candev(ndev); 1452 if (ret) 1453 goto err_irq; 1454 1455 ret = xcan_chip_start(ndev); 1456 if (ret < 0) { 1457 netdev_err(ndev, "xcan_chip_start failed!\n"); 1458 goto err_candev; 1459 } 1460 1461 napi_enable(&priv->napi); 1462 netif_start_queue(ndev); 1463 1464 return 0; 1465 1466 err_candev: 1467 close_candev(ndev); 1468 err_irq: 1469 free_irq(ndev->irq, ndev); 1470 err: 1471 pm_runtime_put(priv->dev); 1472 phy_power_off(priv->transceiver); 1473 1474 return ret; 1475 } 1476 1477 /** 1478 * xcan_close - Driver close routine 1479 * @ndev: Pointer to net_device structure 1480 * 1481 * Return: 0 always 1482 */ 1483 static int xcan_close(struct net_device *ndev) 1484 { 1485 struct xcan_priv *priv = netdev_priv(ndev); 1486 1487 netif_stop_queue(ndev); 1488 napi_disable(&priv->napi); 1489 xcan_chip_stop(ndev); 1490 free_irq(ndev->irq, ndev); 1491 close_candev(ndev); 1492 1493 pm_runtime_put(priv->dev); 1494 phy_power_off(priv->transceiver); 1495 1496 return 0; 1497 } 1498 1499 /** 1500 * xcan_get_berr_counter - error counter routine 1501 * @ndev: Pointer to net_device structure 1502 * @bec: Pointer to can_berr_counter structure 1503 * 1504 * This is the driver error counter routine. 1505 * Return: 0 on success and failure value on error 1506 */ 1507 static int xcan_get_berr_counter(const struct net_device *ndev, 1508 struct can_berr_counter *bec) 1509 { 1510 struct xcan_priv *priv = netdev_priv(ndev); 1511 int ret; 1512 1513 ret = pm_runtime_get_sync(priv->dev); 1514 if (ret < 0) { 1515 netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n", 1516 __func__, ret); 1517 pm_runtime_put(priv->dev); 1518 return ret; 1519 } 1520 1521 bec->txerr = priv->read_reg(priv, XCAN_ECR_OFFSET) & XCAN_ECR_TEC_MASK; 1522 bec->rxerr = ((priv->read_reg(priv, XCAN_ECR_OFFSET) & 1523 XCAN_ECR_REC_MASK) >> XCAN_ESR_REC_SHIFT); 1524 1525 pm_runtime_put(priv->dev); 1526 1527 return 0; 1528 } 1529 1530 /** 1531 * xcan_get_auto_tdcv - Get Transmitter Delay Compensation Value 1532 * @ndev: Pointer to net_device structure 1533 * @tdcv: Pointer to TDCV value 1534 * 1535 * Return: 0 on success 1536 */ 1537 static int xcan_get_auto_tdcv(const struct net_device *ndev, u32 *tdcv) 1538 { 1539 struct xcan_priv *priv = netdev_priv(ndev); 1540 1541 *tdcv = FIELD_GET(XCAN_SR_TDCV_MASK, priv->read_reg(priv, XCAN_SR_OFFSET)); 1542 1543 return 0; 1544 } 1545 1546 static const struct net_device_ops xcan_netdev_ops = { 1547 .ndo_open = xcan_open, 1548 .ndo_stop = xcan_close, 1549 .ndo_start_xmit = xcan_start_xmit, 1550 .ndo_change_mtu = can_change_mtu, 1551 }; 1552 1553 static const struct ethtool_ops xcan_ethtool_ops = { 1554 .get_ts_info = ethtool_op_get_ts_info, 1555 }; 1556 1557 /** 1558 * xcan_suspend - Suspend method for the driver 1559 * @dev: Address of the device structure 1560 * 1561 * Put the driver into low power mode. 1562 * Return: 0 on success and failure value on error 1563 */ 1564 static int __maybe_unused xcan_suspend(struct device *dev) 1565 { 1566 struct net_device *ndev = dev_get_drvdata(dev); 1567 1568 if (netif_running(ndev)) { 1569 netif_stop_queue(ndev); 1570 netif_device_detach(ndev); 1571 xcan_chip_stop(ndev); 1572 } 1573 1574 return pm_runtime_force_suspend(dev); 1575 } 1576 1577 /** 1578 * xcan_resume - Resume from suspend 1579 * @dev: Address of the device structure 1580 * 1581 * Resume operation after suspend. 1582 * Return: 0 on success and failure value on error 1583 */ 1584 static int __maybe_unused xcan_resume(struct device *dev) 1585 { 1586 struct net_device *ndev = dev_get_drvdata(dev); 1587 int ret; 1588 1589 ret = pm_runtime_force_resume(dev); 1590 if (ret) { 1591 dev_err(dev, "pm_runtime_force_resume failed on resume\n"); 1592 return ret; 1593 } 1594 1595 if (netif_running(ndev)) { 1596 ret = xcan_chip_start(ndev); 1597 if (ret) { 1598 dev_err(dev, "xcan_chip_start failed on resume\n"); 1599 return ret; 1600 } 1601 1602 netif_device_attach(ndev); 1603 netif_start_queue(ndev); 1604 } 1605 1606 return 0; 1607 } 1608 1609 /** 1610 * xcan_runtime_suspend - Runtime suspend method for the driver 1611 * @dev: Address of the device structure 1612 * 1613 * Put the driver into low power mode. 1614 * Return: 0 always 1615 */ 1616 static int __maybe_unused xcan_runtime_suspend(struct device *dev) 1617 { 1618 struct net_device *ndev = dev_get_drvdata(dev); 1619 struct xcan_priv *priv = netdev_priv(ndev); 1620 1621 clk_disable_unprepare(priv->bus_clk); 1622 clk_disable_unprepare(priv->can_clk); 1623 1624 return 0; 1625 } 1626 1627 /** 1628 * xcan_runtime_resume - Runtime resume from suspend 1629 * @dev: Address of the device structure 1630 * 1631 * Resume operation after suspend. 1632 * Return: 0 on success and failure value on error 1633 */ 1634 static int __maybe_unused xcan_runtime_resume(struct device *dev) 1635 { 1636 struct net_device *ndev = dev_get_drvdata(dev); 1637 struct xcan_priv *priv = netdev_priv(ndev); 1638 int ret; 1639 1640 ret = clk_prepare_enable(priv->bus_clk); 1641 if (ret) { 1642 dev_err(dev, "Cannot enable clock.\n"); 1643 return ret; 1644 } 1645 ret = clk_prepare_enable(priv->can_clk); 1646 if (ret) { 1647 dev_err(dev, "Cannot enable clock.\n"); 1648 clk_disable_unprepare(priv->bus_clk); 1649 return ret; 1650 } 1651 1652 return 0; 1653 } 1654 1655 static const struct dev_pm_ops xcan_dev_pm_ops = { 1656 SET_SYSTEM_SLEEP_PM_OPS(xcan_suspend, xcan_resume) 1657 SET_RUNTIME_PM_OPS(xcan_runtime_suspend, xcan_runtime_resume, NULL) 1658 }; 1659 1660 static const struct xcan_devtype_data xcan_zynq_data = { 1661 .cantype = XZYNQ_CANPS, 1662 .flags = XCAN_FLAG_TXFEMP, 1663 .bittiming_const = &xcan_bittiming_const, 1664 .btr_ts2_shift = XCAN_BTR_TS2_SHIFT, 1665 .btr_sjw_shift = XCAN_BTR_SJW_SHIFT, 1666 .bus_clk_name = "pclk", 1667 }; 1668 1669 static const struct xcan_devtype_data xcan_axi_data = { 1670 .cantype = XAXI_CAN, 1671 .bittiming_const = &xcan_bittiming_const, 1672 .btr_ts2_shift = XCAN_BTR_TS2_SHIFT, 1673 .btr_sjw_shift = XCAN_BTR_SJW_SHIFT, 1674 .bus_clk_name = "s_axi_aclk", 1675 }; 1676 1677 static const struct xcan_devtype_data xcan_canfd_data = { 1678 .cantype = XAXI_CANFD, 1679 .flags = XCAN_FLAG_EXT_FILTERS | 1680 XCAN_FLAG_RXMNF | 1681 XCAN_FLAG_TX_MAILBOXES | 1682 XCAN_FLAG_RX_FIFO_MULTI, 1683 .bittiming_const = &xcan_bittiming_const_canfd, 1684 .btr_ts2_shift = XCAN_BTR_TS2_SHIFT_CANFD, 1685 .btr_sjw_shift = XCAN_BTR_SJW_SHIFT_CANFD, 1686 .bus_clk_name = "s_axi_aclk", 1687 }; 1688 1689 static const struct xcan_devtype_data xcan_canfd2_data = { 1690 .cantype = XAXI_CANFD_2_0, 1691 .flags = XCAN_FLAG_EXT_FILTERS | 1692 XCAN_FLAG_RXMNF | 1693 XCAN_FLAG_TX_MAILBOXES | 1694 XCAN_FLAG_CANFD_2 | 1695 XCAN_FLAG_RX_FIFO_MULTI, 1696 .bittiming_const = &xcan_bittiming_const_canfd2, 1697 .btr_ts2_shift = XCAN_BTR_TS2_SHIFT_CANFD, 1698 .btr_sjw_shift = XCAN_BTR_SJW_SHIFT_CANFD, 1699 .bus_clk_name = "s_axi_aclk", 1700 }; 1701 1702 /* Match table for OF platform binding */ 1703 static const struct of_device_id xcan_of_match[] = { 1704 { .compatible = "xlnx,zynq-can-1.0", .data = &xcan_zynq_data }, 1705 { .compatible = "xlnx,axi-can-1.00.a", .data = &xcan_axi_data }, 1706 { .compatible = "xlnx,canfd-1.0", .data = &xcan_canfd_data }, 1707 { .compatible = "xlnx,canfd-2.0", .data = &xcan_canfd2_data }, 1708 { /* end of list */ }, 1709 }; 1710 MODULE_DEVICE_TABLE(of, xcan_of_match); 1711 1712 /** 1713 * xcan_probe - Platform registration call 1714 * @pdev: Handle to the platform device structure 1715 * 1716 * This function does all the memory allocation and registration for the CAN 1717 * device. 1718 * 1719 * Return: 0 on success and failure value on error 1720 */ 1721 static int xcan_probe(struct platform_device *pdev) 1722 { 1723 struct net_device *ndev; 1724 struct xcan_priv *priv; 1725 struct phy *transceiver; 1726 const struct of_device_id *of_id; 1727 const struct xcan_devtype_data *devtype = &xcan_axi_data; 1728 void __iomem *addr; 1729 int ret; 1730 int rx_max, tx_max; 1731 u32 hw_tx_max = 0, hw_rx_max = 0; 1732 const char *hw_tx_max_property; 1733 1734 /* Get the virtual base address for the device */ 1735 addr = devm_platform_ioremap_resource(pdev, 0); 1736 if (IS_ERR(addr)) { 1737 ret = PTR_ERR(addr); 1738 goto err; 1739 } 1740 1741 of_id = of_match_device(xcan_of_match, &pdev->dev); 1742 if (of_id && of_id->data) 1743 devtype = of_id->data; 1744 1745 hw_tx_max_property = devtype->flags & XCAN_FLAG_TX_MAILBOXES ? 1746 "tx-mailbox-count" : "tx-fifo-depth"; 1747 1748 ret = of_property_read_u32(pdev->dev.of_node, hw_tx_max_property, 1749 &hw_tx_max); 1750 if (ret < 0) { 1751 dev_err(&pdev->dev, "missing %s property\n", 1752 hw_tx_max_property); 1753 goto err; 1754 } 1755 1756 ret = of_property_read_u32(pdev->dev.of_node, "rx-fifo-depth", 1757 &hw_rx_max); 1758 if (ret < 0) { 1759 dev_err(&pdev->dev, 1760 "missing rx-fifo-depth property (mailbox mode is not supported)\n"); 1761 goto err; 1762 } 1763 1764 /* With TX FIFO: 1765 * 1766 * There is no way to directly figure out how many frames have been 1767 * sent when the TXOK interrupt is processed. If TXFEMP 1768 * is supported, we can have 2 frames in the FIFO and use TXFEMP 1769 * to determine if 1 or 2 frames have been sent. 1770 * Theoretically we should be able to use TXFWMEMP to determine up 1771 * to 3 frames, but it seems that after putting a second frame in the 1772 * FIFO, with watermark at 2 frames, it can happen that TXFWMEMP (less 1773 * than 2 frames in FIFO) is set anyway with no TXOK (a frame was 1774 * sent), which is not a sensible state - possibly TXFWMEMP is not 1775 * completely synchronized with the rest of the bits? 1776 * 1777 * With TX mailboxes: 1778 * 1779 * HW sends frames in CAN ID priority order. To preserve FIFO ordering 1780 * we submit frames one at a time. 1781 */ 1782 if (!(devtype->flags & XCAN_FLAG_TX_MAILBOXES) && 1783 (devtype->flags & XCAN_FLAG_TXFEMP)) 1784 tx_max = min(hw_tx_max, 2U); 1785 else 1786 tx_max = 1; 1787 1788 rx_max = hw_rx_max; 1789 1790 /* Create a CAN device instance */ 1791 ndev = alloc_candev(sizeof(struct xcan_priv), tx_max); 1792 if (!ndev) 1793 return -ENOMEM; 1794 1795 priv = netdev_priv(ndev); 1796 priv->dev = &pdev->dev; 1797 priv->can.bittiming_const = devtype->bittiming_const; 1798 priv->can.do_set_mode = xcan_do_set_mode; 1799 priv->can.do_get_berr_counter = xcan_get_berr_counter; 1800 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1801 CAN_CTRLMODE_BERR_REPORTING; 1802 1803 if (devtype->cantype == XAXI_CANFD) { 1804 priv->can.data_bittiming_const = 1805 &xcan_data_bittiming_const_canfd; 1806 priv->can.tdc_const = &xcan_tdc_const_canfd; 1807 } 1808 1809 if (devtype->cantype == XAXI_CANFD_2_0) { 1810 priv->can.data_bittiming_const = 1811 &xcan_data_bittiming_const_canfd2; 1812 priv->can.tdc_const = &xcan_tdc_const_canfd2; 1813 } 1814 1815 if (devtype->cantype == XAXI_CANFD || 1816 devtype->cantype == XAXI_CANFD_2_0) { 1817 priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD | 1818 CAN_CTRLMODE_TDC_AUTO; 1819 priv->can.do_get_auto_tdcv = xcan_get_auto_tdcv; 1820 } 1821 1822 priv->reg_base = addr; 1823 priv->tx_max = tx_max; 1824 priv->devtype = *devtype; 1825 spin_lock_init(&priv->tx_lock); 1826 1827 /* Get IRQ for the device */ 1828 ret = platform_get_irq(pdev, 0); 1829 if (ret < 0) 1830 goto err_free; 1831 1832 ndev->irq = ret; 1833 1834 ndev->flags |= IFF_ECHO; /* We support local echo */ 1835 1836 platform_set_drvdata(pdev, ndev); 1837 SET_NETDEV_DEV(ndev, &pdev->dev); 1838 ndev->netdev_ops = &xcan_netdev_ops; 1839 ndev->ethtool_ops = &xcan_ethtool_ops; 1840 1841 /* Getting the CAN can_clk info */ 1842 priv->can_clk = devm_clk_get(&pdev->dev, "can_clk"); 1843 if (IS_ERR(priv->can_clk)) { 1844 ret = dev_err_probe(&pdev->dev, PTR_ERR(priv->can_clk), 1845 "device clock not found\n"); 1846 goto err_free; 1847 } 1848 1849 priv->bus_clk = devm_clk_get(&pdev->dev, devtype->bus_clk_name); 1850 if (IS_ERR(priv->bus_clk)) { 1851 ret = dev_err_probe(&pdev->dev, PTR_ERR(priv->bus_clk), 1852 "bus clock not found\n"); 1853 goto err_free; 1854 } 1855 1856 transceiver = devm_phy_optional_get(&pdev->dev, NULL); 1857 if (IS_ERR(transceiver)) { 1858 ret = PTR_ERR(transceiver); 1859 dev_err_probe(&pdev->dev, ret, "failed to get phy\n"); 1860 goto err_free; 1861 } 1862 priv->transceiver = transceiver; 1863 1864 priv->write_reg = xcan_write_reg_le; 1865 priv->read_reg = xcan_read_reg_le; 1866 1867 pm_runtime_enable(&pdev->dev); 1868 ret = pm_runtime_get_sync(&pdev->dev); 1869 if (ret < 0) { 1870 netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n", 1871 __func__, ret); 1872 goto err_disableclks; 1873 } 1874 1875 if (priv->read_reg(priv, XCAN_SR_OFFSET) != XCAN_SR_CONFIG_MASK) { 1876 priv->write_reg = xcan_write_reg_be; 1877 priv->read_reg = xcan_read_reg_be; 1878 } 1879 1880 priv->can.clock.freq = clk_get_rate(priv->can_clk); 1881 1882 netif_napi_add_weight(ndev, &priv->napi, xcan_rx_poll, rx_max); 1883 1884 ret = register_candev(ndev); 1885 if (ret) { 1886 dev_err(&pdev->dev, "fail to register failed (err=%d)\n", ret); 1887 goto err_disableclks; 1888 } 1889 1890 of_can_transceiver(ndev); 1891 pm_runtime_put(&pdev->dev); 1892 1893 if (priv->devtype.flags & XCAN_FLAG_CANFD_2) { 1894 priv->write_reg(priv, XCAN_AFR_2_ID_OFFSET, 0x00000000); 1895 priv->write_reg(priv, XCAN_AFR_2_MASK_OFFSET, 0x00000000); 1896 } 1897 1898 netdev_dbg(ndev, "reg_base=0x%p irq=%d clock=%d, tx buffers: actual %d, using %d\n", 1899 priv->reg_base, ndev->irq, priv->can.clock.freq, 1900 hw_tx_max, priv->tx_max); 1901 1902 return 0; 1903 1904 err_disableclks: 1905 pm_runtime_put(priv->dev); 1906 pm_runtime_disable(&pdev->dev); 1907 err_free: 1908 free_candev(ndev); 1909 err: 1910 return ret; 1911 } 1912 1913 /** 1914 * xcan_remove - Unregister the device after releasing the resources 1915 * @pdev: Handle to the platform device structure 1916 * 1917 * This function frees all the resources allocated to the device. 1918 * Return: 0 always 1919 */ 1920 static void xcan_remove(struct platform_device *pdev) 1921 { 1922 struct net_device *ndev = platform_get_drvdata(pdev); 1923 1924 unregister_candev(ndev); 1925 pm_runtime_disable(&pdev->dev); 1926 free_candev(ndev); 1927 } 1928 1929 static struct platform_driver xcan_driver = { 1930 .probe = xcan_probe, 1931 .remove_new = xcan_remove, 1932 .driver = { 1933 .name = DRIVER_NAME, 1934 .pm = &xcan_dev_pm_ops, 1935 .of_match_table = xcan_of_match, 1936 }, 1937 }; 1938 1939 module_platform_driver(xcan_driver); 1940 1941 MODULE_LICENSE("GPL"); 1942 MODULE_AUTHOR("Xilinx Inc"); 1943 MODULE_DESCRIPTION("Xilinx CAN interface"); 1944