1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* Xilinx CAN device driver 3 * 4 * Copyright (C) 2012 - 2014 Xilinx, Inc. 5 * Copyright (C) 2009 PetaLogix. All rights reserved. 6 * Copyright (C) 2017 - 2018 Sandvik Mining and Construction Oy 7 * 8 * Description: 9 * This driver is developed for Axi CAN IP and for Zynq CANPS Controller. 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/errno.h> 14 #include <linux/init.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/netdevice.h> 20 #include <linux/of.h> 21 #include <linux/of_device.h> 22 #include <linux/platform_device.h> 23 #include <linux/skbuff.h> 24 #include <linux/spinlock.h> 25 #include <linux/string.h> 26 #include <linux/types.h> 27 #include <linux/can/dev.h> 28 #include <linux/can/error.h> 29 #include <linux/pm_runtime.h> 30 31 #define DRIVER_NAME "xilinx_can" 32 33 /* CAN registers set */ 34 enum xcan_reg { 35 XCAN_SRR_OFFSET = 0x00, /* Software reset */ 36 XCAN_MSR_OFFSET = 0x04, /* Mode select */ 37 XCAN_BRPR_OFFSET = 0x08, /* Baud rate prescaler */ 38 XCAN_BTR_OFFSET = 0x0C, /* Bit timing */ 39 XCAN_ECR_OFFSET = 0x10, /* Error counter */ 40 XCAN_ESR_OFFSET = 0x14, /* Error status */ 41 XCAN_SR_OFFSET = 0x18, /* Status */ 42 XCAN_ISR_OFFSET = 0x1C, /* Interrupt status */ 43 XCAN_IER_OFFSET = 0x20, /* Interrupt enable */ 44 XCAN_ICR_OFFSET = 0x24, /* Interrupt clear */ 45 46 /* not on CAN FD cores */ 47 XCAN_TXFIFO_OFFSET = 0x30, /* TX FIFO base */ 48 XCAN_RXFIFO_OFFSET = 0x50, /* RX FIFO base */ 49 XCAN_AFR_OFFSET = 0x60, /* Acceptance Filter */ 50 51 /* only on CAN FD cores */ 52 XCAN_F_BRPR_OFFSET = 0x088, /* Data Phase Baud Rate 53 * Prescalar 54 */ 55 XCAN_F_BTR_OFFSET = 0x08C, /* Data Phase Bit Timing */ 56 XCAN_TRR_OFFSET = 0x0090, /* TX Buffer Ready Request */ 57 XCAN_AFR_EXT_OFFSET = 0x00E0, /* Acceptance Filter */ 58 XCAN_FSR_OFFSET = 0x00E8, /* RX FIFO Status */ 59 XCAN_TXMSG_BASE_OFFSET = 0x0100, /* TX Message Space */ 60 XCAN_RXMSG_BASE_OFFSET = 0x1100, /* RX Message Space */ 61 XCAN_RXMSG_2_BASE_OFFSET = 0x2100, /* RX Message Space */ 62 XCAN_AFR_2_MASK_OFFSET = 0x0A00, /* Acceptance Filter MASK */ 63 XCAN_AFR_2_ID_OFFSET = 0x0A04, /* Acceptance Filter ID */ 64 }; 65 66 #define XCAN_FRAME_ID_OFFSET(frame_base) ((frame_base) + 0x00) 67 #define XCAN_FRAME_DLC_OFFSET(frame_base) ((frame_base) + 0x04) 68 #define XCAN_FRAME_DW1_OFFSET(frame_base) ((frame_base) + 0x08) 69 #define XCAN_FRAME_DW2_OFFSET(frame_base) ((frame_base) + 0x0C) 70 #define XCANFD_FRAME_DW_OFFSET(frame_base) ((frame_base) + 0x08) 71 72 #define XCAN_CANFD_FRAME_SIZE 0x48 73 #define XCAN_TXMSG_FRAME_OFFSET(n) (XCAN_TXMSG_BASE_OFFSET + \ 74 XCAN_CANFD_FRAME_SIZE * (n)) 75 #define XCAN_RXMSG_FRAME_OFFSET(n) (XCAN_RXMSG_BASE_OFFSET + \ 76 XCAN_CANFD_FRAME_SIZE * (n)) 77 #define XCAN_RXMSG_2_FRAME_OFFSET(n) (XCAN_RXMSG_2_BASE_OFFSET + \ 78 XCAN_CANFD_FRAME_SIZE * (n)) 79 80 /* the single TX mailbox used by this driver on CAN FD HW */ 81 #define XCAN_TX_MAILBOX_IDX 0 82 83 /* CAN register bit masks - XCAN_<REG>_<BIT>_MASK */ 84 #define XCAN_SRR_CEN_MASK 0x00000002 /* CAN enable */ 85 #define XCAN_SRR_RESET_MASK 0x00000001 /* Soft Reset the CAN core */ 86 #define XCAN_MSR_LBACK_MASK 0x00000002 /* Loop back mode select */ 87 #define XCAN_MSR_SLEEP_MASK 0x00000001 /* Sleep mode select */ 88 #define XCAN_BRPR_BRP_MASK 0x000000FF /* Baud rate prescaler */ 89 #define XCAN_BTR_SJW_MASK 0x00000180 /* Synchronous jump width */ 90 #define XCAN_BTR_TS2_MASK 0x00000070 /* Time segment 2 */ 91 #define XCAN_BTR_TS1_MASK 0x0000000F /* Time segment 1 */ 92 #define XCAN_BTR_SJW_MASK_CANFD 0x000F0000 /* Synchronous jump width */ 93 #define XCAN_BTR_TS2_MASK_CANFD 0x00000F00 /* Time segment 2 */ 94 #define XCAN_BTR_TS1_MASK_CANFD 0x0000003F /* Time segment 1 */ 95 #define XCAN_ECR_REC_MASK 0x0000FF00 /* Receive error counter */ 96 #define XCAN_ECR_TEC_MASK 0x000000FF /* Transmit error counter */ 97 #define XCAN_ESR_ACKER_MASK 0x00000010 /* ACK error */ 98 #define XCAN_ESR_BERR_MASK 0x00000008 /* Bit error */ 99 #define XCAN_ESR_STER_MASK 0x00000004 /* Stuff error */ 100 #define XCAN_ESR_FMER_MASK 0x00000002 /* Form error */ 101 #define XCAN_ESR_CRCER_MASK 0x00000001 /* CRC error */ 102 #define XCAN_SR_TXFLL_MASK 0x00000400 /* TX FIFO is full */ 103 #define XCAN_SR_ESTAT_MASK 0x00000180 /* Error status */ 104 #define XCAN_SR_ERRWRN_MASK 0x00000040 /* Error warning */ 105 #define XCAN_SR_NORMAL_MASK 0x00000008 /* Normal mode */ 106 #define XCAN_SR_LBACK_MASK 0x00000002 /* Loop back mode */ 107 #define XCAN_SR_CONFIG_MASK 0x00000001 /* Configuration mode */ 108 #define XCAN_IXR_RXMNF_MASK 0x00020000 /* RX match not finished */ 109 #define XCAN_IXR_TXFEMP_MASK 0x00004000 /* TX FIFO Empty */ 110 #define XCAN_IXR_WKUP_MASK 0x00000800 /* Wake up interrupt */ 111 #define XCAN_IXR_SLP_MASK 0x00000400 /* Sleep interrupt */ 112 #define XCAN_IXR_BSOFF_MASK 0x00000200 /* Bus off interrupt */ 113 #define XCAN_IXR_ERROR_MASK 0x00000100 /* Error interrupt */ 114 #define XCAN_IXR_RXNEMP_MASK 0x00000080 /* RX FIFO NotEmpty intr */ 115 #define XCAN_IXR_RXOFLW_MASK 0x00000040 /* RX FIFO Overflow intr */ 116 #define XCAN_IXR_RXOK_MASK 0x00000010 /* Message received intr */ 117 #define XCAN_IXR_TXFLL_MASK 0x00000004 /* Tx FIFO Full intr */ 118 #define XCAN_IXR_TXOK_MASK 0x00000002 /* TX successful intr */ 119 #define XCAN_IXR_ARBLST_MASK 0x00000001 /* Arbitration lost intr */ 120 #define XCAN_IDR_ID1_MASK 0xFFE00000 /* Standard msg identifier */ 121 #define XCAN_IDR_SRR_MASK 0x00100000 /* Substitute remote TXreq */ 122 #define XCAN_IDR_IDE_MASK 0x00080000 /* Identifier extension */ 123 #define XCAN_IDR_ID2_MASK 0x0007FFFE /* Extended message ident */ 124 #define XCAN_IDR_RTR_MASK 0x00000001 /* Remote TX request */ 125 #define XCAN_DLCR_DLC_MASK 0xF0000000 /* Data length code */ 126 #define XCAN_FSR_FL_MASK 0x00003F00 /* RX Fill Level */ 127 #define XCAN_2_FSR_FL_MASK 0x00007F00 /* RX Fill Level */ 128 #define XCAN_FSR_IRI_MASK 0x00000080 /* RX Increment Read Index */ 129 #define XCAN_FSR_RI_MASK 0x0000001F /* RX Read Index */ 130 #define XCAN_2_FSR_RI_MASK 0x0000003F /* RX Read Index */ 131 #define XCAN_DLCR_EDL_MASK 0x08000000 /* EDL Mask in DLC */ 132 #define XCAN_DLCR_BRS_MASK 0x04000000 /* BRS Mask in DLC */ 133 134 /* CAN register bit shift - XCAN_<REG>_<BIT>_SHIFT */ 135 #define XCAN_BTR_SJW_SHIFT 7 /* Synchronous jump width */ 136 #define XCAN_BTR_TS2_SHIFT 4 /* Time segment 2 */ 137 #define XCAN_BTR_SJW_SHIFT_CANFD 16 /* Synchronous jump width */ 138 #define XCAN_BTR_TS2_SHIFT_CANFD 8 /* Time segment 2 */ 139 #define XCAN_IDR_ID1_SHIFT 21 /* Standard Messg Identifier */ 140 #define XCAN_IDR_ID2_SHIFT 1 /* Extended Message Identifier */ 141 #define XCAN_DLCR_DLC_SHIFT 28 /* Data length code */ 142 #define XCAN_ESR_REC_SHIFT 8 /* Rx Error Count */ 143 144 /* CAN frame length constants */ 145 #define XCAN_FRAME_MAX_DATA_LEN 8 146 #define XCANFD_DW_BYTES 4 147 #define XCAN_TIMEOUT (1 * HZ) 148 149 /* TX-FIFO-empty interrupt available */ 150 #define XCAN_FLAG_TXFEMP 0x0001 151 /* RX Match Not Finished interrupt available */ 152 #define XCAN_FLAG_RXMNF 0x0002 153 /* Extended acceptance filters with control at 0xE0 */ 154 #define XCAN_FLAG_EXT_FILTERS 0x0004 155 /* TX mailboxes instead of TX FIFO */ 156 #define XCAN_FLAG_TX_MAILBOXES 0x0008 157 /* RX FIFO with each buffer in separate registers at 0x1100 158 * instead of the regular FIFO at 0x50 159 */ 160 #define XCAN_FLAG_RX_FIFO_MULTI 0x0010 161 #define XCAN_FLAG_CANFD_2 0x0020 162 163 enum xcan_ip_type { 164 XAXI_CAN = 0, 165 XZYNQ_CANPS, 166 XAXI_CANFD, 167 XAXI_CANFD_2_0, 168 }; 169 170 struct xcan_devtype_data { 171 enum xcan_ip_type cantype; 172 unsigned int flags; 173 const struct can_bittiming_const *bittiming_const; 174 const char *bus_clk_name; 175 unsigned int btr_ts2_shift; 176 unsigned int btr_sjw_shift; 177 }; 178 179 /** 180 * struct xcan_priv - This definition define CAN driver instance 181 * @can: CAN private data structure. 182 * @tx_lock: Lock for synchronizing TX interrupt handling 183 * @tx_head: Tx CAN packets ready to send on the queue 184 * @tx_tail: Tx CAN packets successfully sended on the queue 185 * @tx_max: Maximum number packets the driver can send 186 * @napi: NAPI structure 187 * @read_reg: For reading data from CAN registers 188 * @write_reg: For writing data to CAN registers 189 * @dev: Network device data structure 190 * @reg_base: Ioremapped address to registers 191 * @irq_flags: For request_irq() 192 * @bus_clk: Pointer to struct clk 193 * @can_clk: Pointer to struct clk 194 * @devtype: Device type specific constants 195 */ 196 struct xcan_priv { 197 struct can_priv can; 198 spinlock_t tx_lock; /* Lock for synchronizing TX interrupt handling */ 199 unsigned int tx_head; 200 unsigned int tx_tail; 201 unsigned int tx_max; 202 struct napi_struct napi; 203 u32 (*read_reg)(const struct xcan_priv *priv, enum xcan_reg reg); 204 void (*write_reg)(const struct xcan_priv *priv, enum xcan_reg reg, 205 u32 val); 206 struct device *dev; 207 void __iomem *reg_base; 208 unsigned long irq_flags; 209 struct clk *bus_clk; 210 struct clk *can_clk; 211 struct xcan_devtype_data devtype; 212 }; 213 214 /* CAN Bittiming constants as per Xilinx CAN specs */ 215 static const struct can_bittiming_const xcan_bittiming_const = { 216 .name = DRIVER_NAME, 217 .tseg1_min = 1, 218 .tseg1_max = 16, 219 .tseg2_min = 1, 220 .tseg2_max = 8, 221 .sjw_max = 4, 222 .brp_min = 1, 223 .brp_max = 256, 224 .brp_inc = 1, 225 }; 226 227 /* AXI CANFD Arbitration Bittiming constants as per AXI CANFD 1.0 spec */ 228 static const struct can_bittiming_const xcan_bittiming_const_canfd = { 229 .name = DRIVER_NAME, 230 .tseg1_min = 1, 231 .tseg1_max = 64, 232 .tseg2_min = 1, 233 .tseg2_max = 16, 234 .sjw_max = 16, 235 .brp_min = 1, 236 .brp_max = 256, 237 .brp_inc = 1, 238 }; 239 240 /* AXI CANFD Data Bittiming constants as per AXI CANFD 1.0 specs */ 241 static const struct can_bittiming_const xcan_data_bittiming_const_canfd = { 242 .name = DRIVER_NAME, 243 .tseg1_min = 1, 244 .tseg1_max = 16, 245 .tseg2_min = 1, 246 .tseg2_max = 8, 247 .sjw_max = 8, 248 .brp_min = 1, 249 .brp_max = 256, 250 .brp_inc = 1, 251 }; 252 253 /* AXI CANFD 2.0 Arbitration Bittiming constants as per AXI CANFD 2.0 spec */ 254 static const struct can_bittiming_const xcan_bittiming_const_canfd2 = { 255 .name = DRIVER_NAME, 256 .tseg1_min = 1, 257 .tseg1_max = 256, 258 .tseg2_min = 1, 259 .tseg2_max = 128, 260 .sjw_max = 128, 261 .brp_min = 2, 262 .brp_max = 256, 263 .brp_inc = 1, 264 }; 265 266 /* AXI CANFD 2.0 Data Bittiming constants as per AXI CANFD 2.0 spec */ 267 static const struct can_bittiming_const xcan_data_bittiming_const_canfd2 = { 268 .name = DRIVER_NAME, 269 .tseg1_min = 1, 270 .tseg1_max = 32, 271 .tseg2_min = 1, 272 .tseg2_max = 16, 273 .sjw_max = 16, 274 .brp_min = 2, 275 .brp_max = 256, 276 .brp_inc = 1, 277 }; 278 279 /** 280 * xcan_write_reg_le - Write a value to the device register little endian 281 * @priv: Driver private data structure 282 * @reg: Register offset 283 * @val: Value to write at the Register offset 284 * 285 * Write data to the paricular CAN register 286 */ 287 static void xcan_write_reg_le(const struct xcan_priv *priv, enum xcan_reg reg, 288 u32 val) 289 { 290 iowrite32(val, priv->reg_base + reg); 291 } 292 293 /** 294 * xcan_read_reg_le - Read a value from the device register little endian 295 * @priv: Driver private data structure 296 * @reg: Register offset 297 * 298 * Read data from the particular CAN register 299 * Return: value read from the CAN register 300 */ 301 static u32 xcan_read_reg_le(const struct xcan_priv *priv, enum xcan_reg reg) 302 { 303 return ioread32(priv->reg_base + reg); 304 } 305 306 /** 307 * xcan_write_reg_be - Write a value to the device register big endian 308 * @priv: Driver private data structure 309 * @reg: Register offset 310 * @val: Value to write at the Register offset 311 * 312 * Write data to the paricular CAN register 313 */ 314 static void xcan_write_reg_be(const struct xcan_priv *priv, enum xcan_reg reg, 315 u32 val) 316 { 317 iowrite32be(val, priv->reg_base + reg); 318 } 319 320 /** 321 * xcan_read_reg_be - Read a value from the device register big endian 322 * @priv: Driver private data structure 323 * @reg: Register offset 324 * 325 * Read data from the particular CAN register 326 * Return: value read from the CAN register 327 */ 328 static u32 xcan_read_reg_be(const struct xcan_priv *priv, enum xcan_reg reg) 329 { 330 return ioread32be(priv->reg_base + reg); 331 } 332 333 /** 334 * xcan_rx_int_mask - Get the mask for the receive interrupt 335 * @priv: Driver private data structure 336 * 337 * Return: The receive interrupt mask used by the driver on this HW 338 */ 339 static u32 xcan_rx_int_mask(const struct xcan_priv *priv) 340 { 341 /* RXNEMP is better suited for our use case as it cannot be cleared 342 * while the FIFO is non-empty, but CAN FD HW does not have it 343 */ 344 if (priv->devtype.flags & XCAN_FLAG_RX_FIFO_MULTI) 345 return XCAN_IXR_RXOK_MASK; 346 else 347 return XCAN_IXR_RXNEMP_MASK; 348 } 349 350 /** 351 * set_reset_mode - Resets the CAN device mode 352 * @ndev: Pointer to net_device structure 353 * 354 * This is the driver reset mode routine.The driver 355 * enters into configuration mode. 356 * 357 * Return: 0 on success and failure value on error 358 */ 359 static int set_reset_mode(struct net_device *ndev) 360 { 361 struct xcan_priv *priv = netdev_priv(ndev); 362 unsigned long timeout; 363 364 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK); 365 366 timeout = jiffies + XCAN_TIMEOUT; 367 while (!(priv->read_reg(priv, XCAN_SR_OFFSET) & XCAN_SR_CONFIG_MASK)) { 368 if (time_after(jiffies, timeout)) { 369 netdev_warn(ndev, "timed out for config mode\n"); 370 return -ETIMEDOUT; 371 } 372 usleep_range(500, 10000); 373 } 374 375 /* reset clears FIFOs */ 376 priv->tx_head = 0; 377 priv->tx_tail = 0; 378 379 return 0; 380 } 381 382 /** 383 * xcan_set_bittiming - CAN set bit timing routine 384 * @ndev: Pointer to net_device structure 385 * 386 * This is the driver set bittiming routine. 387 * Return: 0 on success and failure value on error 388 */ 389 static int xcan_set_bittiming(struct net_device *ndev) 390 { 391 struct xcan_priv *priv = netdev_priv(ndev); 392 struct can_bittiming *bt = &priv->can.bittiming; 393 struct can_bittiming *dbt = &priv->can.data_bittiming; 394 u32 btr0, btr1; 395 u32 is_config_mode; 396 397 /* Check whether Xilinx CAN is in configuration mode. 398 * It cannot set bit timing if Xilinx CAN is not in configuration mode. 399 */ 400 is_config_mode = priv->read_reg(priv, XCAN_SR_OFFSET) & 401 XCAN_SR_CONFIG_MASK; 402 if (!is_config_mode) { 403 netdev_alert(ndev, 404 "BUG! Cannot set bittiming - CAN is not in config mode\n"); 405 return -EPERM; 406 } 407 408 /* Setting Baud Rate prescalar value in BRPR Register */ 409 btr0 = (bt->brp - 1); 410 411 /* Setting Time Segment 1 in BTR Register */ 412 btr1 = (bt->prop_seg + bt->phase_seg1 - 1); 413 414 /* Setting Time Segment 2 in BTR Register */ 415 btr1 |= (bt->phase_seg2 - 1) << priv->devtype.btr_ts2_shift; 416 417 /* Setting Synchronous jump width in BTR Register */ 418 btr1 |= (bt->sjw - 1) << priv->devtype.btr_sjw_shift; 419 420 priv->write_reg(priv, XCAN_BRPR_OFFSET, btr0); 421 priv->write_reg(priv, XCAN_BTR_OFFSET, btr1); 422 423 if (priv->devtype.cantype == XAXI_CANFD || 424 priv->devtype.cantype == XAXI_CANFD_2_0) { 425 /* Setting Baud Rate prescalar value in F_BRPR Register */ 426 btr0 = dbt->brp - 1; 427 428 /* Setting Time Segment 1 in BTR Register */ 429 btr1 = dbt->prop_seg + dbt->phase_seg1 - 1; 430 431 /* Setting Time Segment 2 in BTR Register */ 432 btr1 |= (dbt->phase_seg2 - 1) << priv->devtype.btr_ts2_shift; 433 434 /* Setting Synchronous jump width in BTR Register */ 435 btr1 |= (dbt->sjw - 1) << priv->devtype.btr_sjw_shift; 436 437 priv->write_reg(priv, XCAN_F_BRPR_OFFSET, btr0); 438 priv->write_reg(priv, XCAN_F_BTR_OFFSET, btr1); 439 } 440 441 netdev_dbg(ndev, "BRPR=0x%08x, BTR=0x%08x\n", 442 priv->read_reg(priv, XCAN_BRPR_OFFSET), 443 priv->read_reg(priv, XCAN_BTR_OFFSET)); 444 445 return 0; 446 } 447 448 /** 449 * xcan_chip_start - This the drivers start routine 450 * @ndev: Pointer to net_device structure 451 * 452 * This is the drivers start routine. 453 * Based on the State of the CAN device it puts 454 * the CAN device into a proper mode. 455 * 456 * Return: 0 on success and failure value on error 457 */ 458 static int xcan_chip_start(struct net_device *ndev) 459 { 460 struct xcan_priv *priv = netdev_priv(ndev); 461 u32 reg_msr; 462 int err; 463 u32 ier; 464 465 /* Check if it is in reset mode */ 466 err = set_reset_mode(ndev); 467 if (err < 0) 468 return err; 469 470 err = xcan_set_bittiming(ndev); 471 if (err < 0) 472 return err; 473 474 /* Enable interrupts 475 * 476 * We enable the ERROR interrupt even with 477 * CAN_CTRLMODE_BERR_REPORTING disabled as there is no 478 * dedicated interrupt for a state change to 479 * ERROR_WARNING/ERROR_PASSIVE. 480 */ 481 ier = XCAN_IXR_TXOK_MASK | XCAN_IXR_BSOFF_MASK | 482 XCAN_IXR_WKUP_MASK | XCAN_IXR_SLP_MASK | 483 XCAN_IXR_ERROR_MASK | XCAN_IXR_RXOFLW_MASK | 484 XCAN_IXR_ARBLST_MASK | xcan_rx_int_mask(priv); 485 486 if (priv->devtype.flags & XCAN_FLAG_RXMNF) 487 ier |= XCAN_IXR_RXMNF_MASK; 488 489 priv->write_reg(priv, XCAN_IER_OFFSET, ier); 490 491 /* Check whether it is loopback mode or normal mode */ 492 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 493 reg_msr = XCAN_MSR_LBACK_MASK; 494 else 495 reg_msr = 0x0; 496 497 /* enable the first extended filter, if any, as cores with extended 498 * filtering default to non-receipt if all filters are disabled 499 */ 500 if (priv->devtype.flags & XCAN_FLAG_EXT_FILTERS) 501 priv->write_reg(priv, XCAN_AFR_EXT_OFFSET, 0x00000001); 502 503 priv->write_reg(priv, XCAN_MSR_OFFSET, reg_msr); 504 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_CEN_MASK); 505 506 netdev_dbg(ndev, "status:#x%08x\n", 507 priv->read_reg(priv, XCAN_SR_OFFSET)); 508 509 priv->can.state = CAN_STATE_ERROR_ACTIVE; 510 return 0; 511 } 512 513 /** 514 * xcan_do_set_mode - This sets the mode of the driver 515 * @ndev: Pointer to net_device structure 516 * @mode: Tells the mode of the driver 517 * 518 * This check the drivers state and calls the corresponding modes to set. 519 * 520 * Return: 0 on success and failure value on error 521 */ 522 static int xcan_do_set_mode(struct net_device *ndev, enum can_mode mode) 523 { 524 int ret; 525 526 switch (mode) { 527 case CAN_MODE_START: 528 ret = xcan_chip_start(ndev); 529 if (ret < 0) { 530 netdev_err(ndev, "xcan_chip_start failed!\n"); 531 return ret; 532 } 533 netif_wake_queue(ndev); 534 break; 535 default: 536 ret = -EOPNOTSUPP; 537 break; 538 } 539 540 return ret; 541 } 542 543 /** 544 * xcan_write_frame - Write a frame to HW 545 * @ndev: Pointer to net_device structure 546 * @skb: sk_buff pointer that contains data to be Txed 547 * @frame_offset: Register offset to write the frame to 548 */ 549 static void xcan_write_frame(struct net_device *ndev, struct sk_buff *skb, 550 int frame_offset) 551 { 552 u32 id, dlc, data[2] = {0, 0}; 553 struct canfd_frame *cf = (struct canfd_frame *)skb->data; 554 u32 ramoff, dwindex = 0, i; 555 struct xcan_priv *priv = netdev_priv(ndev); 556 557 /* Watch carefully on the bit sequence */ 558 if (cf->can_id & CAN_EFF_FLAG) { 559 /* Extended CAN ID format */ 560 id = ((cf->can_id & CAN_EFF_MASK) << XCAN_IDR_ID2_SHIFT) & 561 XCAN_IDR_ID2_MASK; 562 id |= (((cf->can_id & CAN_EFF_MASK) >> 563 (CAN_EFF_ID_BITS - CAN_SFF_ID_BITS)) << 564 XCAN_IDR_ID1_SHIFT) & XCAN_IDR_ID1_MASK; 565 566 /* The substibute remote TX request bit should be "1" 567 * for extended frames as in the Xilinx CAN datasheet 568 */ 569 id |= XCAN_IDR_IDE_MASK | XCAN_IDR_SRR_MASK; 570 571 if (cf->can_id & CAN_RTR_FLAG) 572 /* Extended frames remote TX request */ 573 id |= XCAN_IDR_RTR_MASK; 574 } else { 575 /* Standard CAN ID format */ 576 id = ((cf->can_id & CAN_SFF_MASK) << XCAN_IDR_ID1_SHIFT) & 577 XCAN_IDR_ID1_MASK; 578 579 if (cf->can_id & CAN_RTR_FLAG) 580 /* Standard frames remote TX request */ 581 id |= XCAN_IDR_SRR_MASK; 582 } 583 584 dlc = can_fd_len2dlc(cf->len) << XCAN_DLCR_DLC_SHIFT; 585 if (can_is_canfd_skb(skb)) { 586 if (cf->flags & CANFD_BRS) 587 dlc |= XCAN_DLCR_BRS_MASK; 588 dlc |= XCAN_DLCR_EDL_MASK; 589 } 590 591 if (!(priv->devtype.flags & XCAN_FLAG_TX_MAILBOXES) && 592 (priv->devtype.flags & XCAN_FLAG_TXFEMP)) 593 can_put_echo_skb(skb, ndev, priv->tx_head % priv->tx_max, 0); 594 else 595 can_put_echo_skb(skb, ndev, 0, 0); 596 597 priv->tx_head++; 598 599 priv->write_reg(priv, XCAN_FRAME_ID_OFFSET(frame_offset), id); 600 /* If the CAN frame is RTR frame this write triggers transmission 601 * (not on CAN FD) 602 */ 603 priv->write_reg(priv, XCAN_FRAME_DLC_OFFSET(frame_offset), dlc); 604 if (priv->devtype.cantype == XAXI_CANFD || 605 priv->devtype.cantype == XAXI_CANFD_2_0) { 606 for (i = 0; i < cf->len; i += 4) { 607 ramoff = XCANFD_FRAME_DW_OFFSET(frame_offset) + 608 (dwindex * XCANFD_DW_BYTES); 609 priv->write_reg(priv, ramoff, 610 be32_to_cpup((__be32 *)(cf->data + i))); 611 dwindex++; 612 } 613 } else { 614 if (cf->len > 0) 615 data[0] = be32_to_cpup((__be32 *)(cf->data + 0)); 616 if (cf->len > 4) 617 data[1] = be32_to_cpup((__be32 *)(cf->data + 4)); 618 619 if (!(cf->can_id & CAN_RTR_FLAG)) { 620 priv->write_reg(priv, 621 XCAN_FRAME_DW1_OFFSET(frame_offset), 622 data[0]); 623 /* If the CAN frame is Standard/Extended frame this 624 * write triggers transmission (not on CAN FD) 625 */ 626 priv->write_reg(priv, 627 XCAN_FRAME_DW2_OFFSET(frame_offset), 628 data[1]); 629 } 630 } 631 } 632 633 /** 634 * xcan_start_xmit_fifo - Starts the transmission (FIFO mode) 635 * @skb: sk_buff pointer that contains data to be Txed 636 * @ndev: Pointer to net_device structure 637 * 638 * Return: 0 on success, -ENOSPC if FIFO is full. 639 */ 640 static int xcan_start_xmit_fifo(struct sk_buff *skb, struct net_device *ndev) 641 { 642 struct xcan_priv *priv = netdev_priv(ndev); 643 unsigned long flags; 644 645 /* Check if the TX buffer is full */ 646 if (unlikely(priv->read_reg(priv, XCAN_SR_OFFSET) & 647 XCAN_SR_TXFLL_MASK)) 648 return -ENOSPC; 649 650 spin_lock_irqsave(&priv->tx_lock, flags); 651 652 xcan_write_frame(ndev, skb, XCAN_TXFIFO_OFFSET); 653 654 /* Clear TX-FIFO-empty interrupt for xcan_tx_interrupt() */ 655 if (priv->tx_max > 1) 656 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXFEMP_MASK); 657 658 /* Check if the TX buffer is full */ 659 if ((priv->tx_head - priv->tx_tail) == priv->tx_max) 660 netif_stop_queue(ndev); 661 662 spin_unlock_irqrestore(&priv->tx_lock, flags); 663 664 return 0; 665 } 666 667 /** 668 * xcan_start_xmit_mailbox - Starts the transmission (mailbox mode) 669 * @skb: sk_buff pointer that contains data to be Txed 670 * @ndev: Pointer to net_device structure 671 * 672 * Return: 0 on success, -ENOSPC if there is no space 673 */ 674 static int xcan_start_xmit_mailbox(struct sk_buff *skb, struct net_device *ndev) 675 { 676 struct xcan_priv *priv = netdev_priv(ndev); 677 unsigned long flags; 678 679 if (unlikely(priv->read_reg(priv, XCAN_TRR_OFFSET) & 680 BIT(XCAN_TX_MAILBOX_IDX))) 681 return -ENOSPC; 682 683 spin_lock_irqsave(&priv->tx_lock, flags); 684 685 xcan_write_frame(ndev, skb, 686 XCAN_TXMSG_FRAME_OFFSET(XCAN_TX_MAILBOX_IDX)); 687 688 /* Mark buffer as ready for transmit */ 689 priv->write_reg(priv, XCAN_TRR_OFFSET, BIT(XCAN_TX_MAILBOX_IDX)); 690 691 netif_stop_queue(ndev); 692 693 spin_unlock_irqrestore(&priv->tx_lock, flags); 694 695 return 0; 696 } 697 698 /** 699 * xcan_start_xmit - Starts the transmission 700 * @skb: sk_buff pointer that contains data to be Txed 701 * @ndev: Pointer to net_device structure 702 * 703 * This function is invoked from upper layers to initiate transmission. 704 * 705 * Return: NETDEV_TX_OK on success and NETDEV_TX_BUSY when the tx queue is full 706 */ 707 static netdev_tx_t xcan_start_xmit(struct sk_buff *skb, struct net_device *ndev) 708 { 709 struct xcan_priv *priv = netdev_priv(ndev); 710 int ret; 711 712 if (can_dropped_invalid_skb(ndev, skb)) 713 return NETDEV_TX_OK; 714 715 if (priv->devtype.flags & XCAN_FLAG_TX_MAILBOXES) 716 ret = xcan_start_xmit_mailbox(skb, ndev); 717 else 718 ret = xcan_start_xmit_fifo(skb, ndev); 719 720 if (ret < 0) { 721 netdev_err(ndev, "BUG!, TX full when queue awake!\n"); 722 netif_stop_queue(ndev); 723 return NETDEV_TX_BUSY; 724 } 725 726 return NETDEV_TX_OK; 727 } 728 729 /** 730 * xcan_rx - Is called from CAN isr to complete the received 731 * frame processing 732 * @ndev: Pointer to net_device structure 733 * @frame_base: Register offset to the frame to be read 734 * 735 * This function is invoked from the CAN isr(poll) to process the Rx frames. It 736 * does minimal processing and invokes "netif_receive_skb" to complete further 737 * processing. 738 * Return: 1 on success and 0 on failure. 739 */ 740 static int xcan_rx(struct net_device *ndev, int frame_base) 741 { 742 struct xcan_priv *priv = netdev_priv(ndev); 743 struct net_device_stats *stats = &ndev->stats; 744 struct can_frame *cf; 745 struct sk_buff *skb; 746 u32 id_xcan, dlc, data[2] = {0, 0}; 747 748 skb = alloc_can_skb(ndev, &cf); 749 if (unlikely(!skb)) { 750 stats->rx_dropped++; 751 return 0; 752 } 753 754 /* Read a frame from Xilinx zynq CANPS */ 755 id_xcan = priv->read_reg(priv, XCAN_FRAME_ID_OFFSET(frame_base)); 756 dlc = priv->read_reg(priv, XCAN_FRAME_DLC_OFFSET(frame_base)) >> 757 XCAN_DLCR_DLC_SHIFT; 758 759 /* Change Xilinx CAN data length format to socketCAN data format */ 760 cf->len = can_cc_dlc2len(dlc); 761 762 /* Change Xilinx CAN ID format to socketCAN ID format */ 763 if (id_xcan & XCAN_IDR_IDE_MASK) { 764 /* The received frame is an Extended format frame */ 765 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> 3; 766 cf->can_id |= (id_xcan & XCAN_IDR_ID2_MASK) >> 767 XCAN_IDR_ID2_SHIFT; 768 cf->can_id |= CAN_EFF_FLAG; 769 if (id_xcan & XCAN_IDR_RTR_MASK) 770 cf->can_id |= CAN_RTR_FLAG; 771 } else { 772 /* The received frame is a standard format frame */ 773 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> 774 XCAN_IDR_ID1_SHIFT; 775 if (id_xcan & XCAN_IDR_SRR_MASK) 776 cf->can_id |= CAN_RTR_FLAG; 777 } 778 779 /* DW1/DW2 must always be read to remove message from RXFIFO */ 780 data[0] = priv->read_reg(priv, XCAN_FRAME_DW1_OFFSET(frame_base)); 781 data[1] = priv->read_reg(priv, XCAN_FRAME_DW2_OFFSET(frame_base)); 782 783 if (!(cf->can_id & CAN_RTR_FLAG)) { 784 /* Change Xilinx CAN data format to socketCAN data format */ 785 if (cf->len > 0) 786 *(__be32 *)(cf->data) = cpu_to_be32(data[0]); 787 if (cf->len > 4) 788 *(__be32 *)(cf->data + 4) = cpu_to_be32(data[1]); 789 790 stats->rx_bytes += cf->len; 791 } 792 stats->rx_packets++; 793 794 netif_receive_skb(skb); 795 796 return 1; 797 } 798 799 /** 800 * xcanfd_rx - Is called from CAN isr to complete the received 801 * frame processing 802 * @ndev: Pointer to net_device structure 803 * @frame_base: Register offset to the frame to be read 804 * 805 * This function is invoked from the CAN isr(poll) to process the Rx frames. It 806 * does minimal processing and invokes "netif_receive_skb" to complete further 807 * processing. 808 * Return: 1 on success and 0 on failure. 809 */ 810 static int xcanfd_rx(struct net_device *ndev, int frame_base) 811 { 812 struct xcan_priv *priv = netdev_priv(ndev); 813 struct net_device_stats *stats = &ndev->stats; 814 struct canfd_frame *cf; 815 struct sk_buff *skb; 816 u32 id_xcan, dlc, data[2] = {0, 0}, dwindex = 0, i, dw_offset; 817 818 id_xcan = priv->read_reg(priv, XCAN_FRAME_ID_OFFSET(frame_base)); 819 dlc = priv->read_reg(priv, XCAN_FRAME_DLC_OFFSET(frame_base)); 820 if (dlc & XCAN_DLCR_EDL_MASK) 821 skb = alloc_canfd_skb(ndev, &cf); 822 else 823 skb = alloc_can_skb(ndev, (struct can_frame **)&cf); 824 825 if (unlikely(!skb)) { 826 stats->rx_dropped++; 827 return 0; 828 } 829 830 /* Change Xilinx CANFD data length format to socketCAN data 831 * format 832 */ 833 if (dlc & XCAN_DLCR_EDL_MASK) 834 cf->len = can_fd_dlc2len((dlc & XCAN_DLCR_DLC_MASK) >> 835 XCAN_DLCR_DLC_SHIFT); 836 else 837 cf->len = can_cc_dlc2len((dlc & XCAN_DLCR_DLC_MASK) >> 838 XCAN_DLCR_DLC_SHIFT); 839 840 /* Change Xilinx CAN ID format to socketCAN ID format */ 841 if (id_xcan & XCAN_IDR_IDE_MASK) { 842 /* The received frame is an Extended format frame */ 843 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> 3; 844 cf->can_id |= (id_xcan & XCAN_IDR_ID2_MASK) >> 845 XCAN_IDR_ID2_SHIFT; 846 cf->can_id |= CAN_EFF_FLAG; 847 if (id_xcan & XCAN_IDR_RTR_MASK) 848 cf->can_id |= CAN_RTR_FLAG; 849 } else { 850 /* The received frame is a standard format frame */ 851 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> 852 XCAN_IDR_ID1_SHIFT; 853 if (!(dlc & XCAN_DLCR_EDL_MASK) && (id_xcan & 854 XCAN_IDR_SRR_MASK)) 855 cf->can_id |= CAN_RTR_FLAG; 856 } 857 858 /* Check the frame received is FD or not*/ 859 if (dlc & XCAN_DLCR_EDL_MASK) { 860 for (i = 0; i < cf->len; i += 4) { 861 dw_offset = XCANFD_FRAME_DW_OFFSET(frame_base) + 862 (dwindex * XCANFD_DW_BYTES); 863 data[0] = priv->read_reg(priv, dw_offset); 864 *(__be32 *)(cf->data + i) = cpu_to_be32(data[0]); 865 dwindex++; 866 } 867 } else { 868 for (i = 0; i < cf->len; i += 4) { 869 dw_offset = XCANFD_FRAME_DW_OFFSET(frame_base); 870 data[0] = priv->read_reg(priv, dw_offset + i); 871 *(__be32 *)(cf->data + i) = cpu_to_be32(data[0]); 872 } 873 } 874 875 if (!(cf->can_id & CAN_RTR_FLAG)) 876 stats->rx_bytes += cf->len; 877 stats->rx_packets++; 878 879 netif_receive_skb(skb); 880 881 return 1; 882 } 883 884 /** 885 * xcan_current_error_state - Get current error state from HW 886 * @ndev: Pointer to net_device structure 887 * 888 * Checks the current CAN error state from the HW. Note that this 889 * only checks for ERROR_PASSIVE and ERROR_WARNING. 890 * 891 * Return: 892 * ERROR_PASSIVE or ERROR_WARNING if either is active, ERROR_ACTIVE 893 * otherwise. 894 */ 895 static enum can_state xcan_current_error_state(struct net_device *ndev) 896 { 897 struct xcan_priv *priv = netdev_priv(ndev); 898 u32 status = priv->read_reg(priv, XCAN_SR_OFFSET); 899 900 if ((status & XCAN_SR_ESTAT_MASK) == XCAN_SR_ESTAT_MASK) 901 return CAN_STATE_ERROR_PASSIVE; 902 else if (status & XCAN_SR_ERRWRN_MASK) 903 return CAN_STATE_ERROR_WARNING; 904 else 905 return CAN_STATE_ERROR_ACTIVE; 906 } 907 908 /** 909 * xcan_set_error_state - Set new CAN error state 910 * @ndev: Pointer to net_device structure 911 * @new_state: The new CAN state to be set 912 * @cf: Error frame to be populated or NULL 913 * 914 * Set new CAN error state for the device, updating statistics and 915 * populating the error frame if given. 916 */ 917 static void xcan_set_error_state(struct net_device *ndev, 918 enum can_state new_state, 919 struct can_frame *cf) 920 { 921 struct xcan_priv *priv = netdev_priv(ndev); 922 u32 ecr = priv->read_reg(priv, XCAN_ECR_OFFSET); 923 u32 txerr = ecr & XCAN_ECR_TEC_MASK; 924 u32 rxerr = (ecr & XCAN_ECR_REC_MASK) >> XCAN_ESR_REC_SHIFT; 925 enum can_state tx_state = txerr >= rxerr ? new_state : 0; 926 enum can_state rx_state = txerr <= rxerr ? new_state : 0; 927 928 /* non-ERROR states are handled elsewhere */ 929 if (WARN_ON(new_state > CAN_STATE_ERROR_PASSIVE)) 930 return; 931 932 can_change_state(ndev, cf, tx_state, rx_state); 933 934 if (cf) { 935 cf->data[6] = txerr; 936 cf->data[7] = rxerr; 937 } 938 } 939 940 /** 941 * xcan_update_error_state_after_rxtx - Update CAN error state after RX/TX 942 * @ndev: Pointer to net_device structure 943 * 944 * If the device is in a ERROR-WARNING or ERROR-PASSIVE state, check if 945 * the performed RX/TX has caused it to drop to a lesser state and set 946 * the interface state accordingly. 947 */ 948 static void xcan_update_error_state_after_rxtx(struct net_device *ndev) 949 { 950 struct xcan_priv *priv = netdev_priv(ndev); 951 enum can_state old_state = priv->can.state; 952 enum can_state new_state; 953 954 /* changing error state due to successful frame RX/TX can only 955 * occur from these states 956 */ 957 if (old_state != CAN_STATE_ERROR_WARNING && 958 old_state != CAN_STATE_ERROR_PASSIVE) 959 return; 960 961 new_state = xcan_current_error_state(ndev); 962 963 if (new_state != old_state) { 964 struct sk_buff *skb; 965 struct can_frame *cf; 966 967 skb = alloc_can_err_skb(ndev, &cf); 968 969 xcan_set_error_state(ndev, new_state, skb ? cf : NULL); 970 971 if (skb) 972 netif_rx(skb); 973 } 974 } 975 976 /** 977 * xcan_err_interrupt - error frame Isr 978 * @ndev: net_device pointer 979 * @isr: interrupt status register value 980 * 981 * This is the CAN error interrupt and it will 982 * check the type of error and forward the error 983 * frame to upper layers. 984 */ 985 static void xcan_err_interrupt(struct net_device *ndev, u32 isr) 986 { 987 struct xcan_priv *priv = netdev_priv(ndev); 988 struct net_device_stats *stats = &ndev->stats; 989 struct can_frame cf = { }; 990 u32 err_status; 991 992 err_status = priv->read_reg(priv, XCAN_ESR_OFFSET); 993 priv->write_reg(priv, XCAN_ESR_OFFSET, err_status); 994 995 if (isr & XCAN_IXR_BSOFF_MASK) { 996 priv->can.state = CAN_STATE_BUS_OFF; 997 priv->can.can_stats.bus_off++; 998 /* Leave device in Config Mode in bus-off state */ 999 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK); 1000 can_bus_off(ndev); 1001 cf.can_id |= CAN_ERR_BUSOFF; 1002 } else { 1003 enum can_state new_state = xcan_current_error_state(ndev); 1004 1005 if (new_state != priv->can.state) 1006 xcan_set_error_state(ndev, new_state, &cf); 1007 } 1008 1009 /* Check for Arbitration lost interrupt */ 1010 if (isr & XCAN_IXR_ARBLST_MASK) { 1011 priv->can.can_stats.arbitration_lost++; 1012 cf.can_id |= CAN_ERR_LOSTARB; 1013 cf.data[0] = CAN_ERR_LOSTARB_UNSPEC; 1014 } 1015 1016 /* Check for RX FIFO Overflow interrupt */ 1017 if (isr & XCAN_IXR_RXOFLW_MASK) { 1018 stats->rx_over_errors++; 1019 stats->rx_errors++; 1020 cf.can_id |= CAN_ERR_CRTL; 1021 cf.data[1] |= CAN_ERR_CRTL_RX_OVERFLOW; 1022 } 1023 1024 /* Check for RX Match Not Finished interrupt */ 1025 if (isr & XCAN_IXR_RXMNF_MASK) { 1026 stats->rx_dropped++; 1027 stats->rx_errors++; 1028 netdev_err(ndev, "RX match not finished, frame discarded\n"); 1029 cf.can_id |= CAN_ERR_CRTL; 1030 cf.data[1] |= CAN_ERR_CRTL_UNSPEC; 1031 } 1032 1033 /* Check for error interrupt */ 1034 if (isr & XCAN_IXR_ERROR_MASK) { 1035 bool berr_reporting = false; 1036 1037 if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) { 1038 berr_reporting = true; 1039 cf.can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 1040 } 1041 1042 /* Check for Ack error interrupt */ 1043 if (err_status & XCAN_ESR_ACKER_MASK) { 1044 stats->tx_errors++; 1045 if (berr_reporting) { 1046 cf.can_id |= CAN_ERR_ACK; 1047 cf.data[3] = CAN_ERR_PROT_LOC_ACK; 1048 } 1049 } 1050 1051 /* Check for Bit error interrupt */ 1052 if (err_status & XCAN_ESR_BERR_MASK) { 1053 stats->tx_errors++; 1054 if (berr_reporting) { 1055 cf.can_id |= CAN_ERR_PROT; 1056 cf.data[2] = CAN_ERR_PROT_BIT; 1057 } 1058 } 1059 1060 /* Check for Stuff error interrupt */ 1061 if (err_status & XCAN_ESR_STER_MASK) { 1062 stats->rx_errors++; 1063 if (berr_reporting) { 1064 cf.can_id |= CAN_ERR_PROT; 1065 cf.data[2] = CAN_ERR_PROT_STUFF; 1066 } 1067 } 1068 1069 /* Check for Form error interrupt */ 1070 if (err_status & XCAN_ESR_FMER_MASK) { 1071 stats->rx_errors++; 1072 if (berr_reporting) { 1073 cf.can_id |= CAN_ERR_PROT; 1074 cf.data[2] = CAN_ERR_PROT_FORM; 1075 } 1076 } 1077 1078 /* Check for CRC error interrupt */ 1079 if (err_status & XCAN_ESR_CRCER_MASK) { 1080 stats->rx_errors++; 1081 if (berr_reporting) { 1082 cf.can_id |= CAN_ERR_PROT; 1083 cf.data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; 1084 } 1085 } 1086 priv->can.can_stats.bus_error++; 1087 } 1088 1089 if (cf.can_id) { 1090 struct can_frame *skb_cf; 1091 struct sk_buff *skb = alloc_can_err_skb(ndev, &skb_cf); 1092 1093 if (skb) { 1094 skb_cf->can_id |= cf.can_id; 1095 memcpy(skb_cf->data, cf.data, CAN_ERR_DLC); 1096 netif_rx(skb); 1097 } 1098 } 1099 1100 netdev_dbg(ndev, "%s: error status register:0x%x\n", 1101 __func__, priv->read_reg(priv, XCAN_ESR_OFFSET)); 1102 } 1103 1104 /** 1105 * xcan_state_interrupt - It will check the state of the CAN device 1106 * @ndev: net_device pointer 1107 * @isr: interrupt status register value 1108 * 1109 * This will checks the state of the CAN device 1110 * and puts the device into appropriate state. 1111 */ 1112 static void xcan_state_interrupt(struct net_device *ndev, u32 isr) 1113 { 1114 struct xcan_priv *priv = netdev_priv(ndev); 1115 1116 /* Check for Sleep interrupt if set put CAN device in sleep state */ 1117 if (isr & XCAN_IXR_SLP_MASK) 1118 priv->can.state = CAN_STATE_SLEEPING; 1119 1120 /* Check for Wake up interrupt if set put CAN device in Active state */ 1121 if (isr & XCAN_IXR_WKUP_MASK) 1122 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1123 } 1124 1125 /** 1126 * xcan_rx_fifo_get_next_frame - Get register offset of next RX frame 1127 * @priv: Driver private data structure 1128 * 1129 * Return: Register offset of the next frame in RX FIFO. 1130 */ 1131 static int xcan_rx_fifo_get_next_frame(struct xcan_priv *priv) 1132 { 1133 int offset; 1134 1135 if (priv->devtype.flags & XCAN_FLAG_RX_FIFO_MULTI) { 1136 u32 fsr, mask; 1137 1138 /* clear RXOK before the is-empty check so that any newly 1139 * received frame will reassert it without a race 1140 */ 1141 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_RXOK_MASK); 1142 1143 fsr = priv->read_reg(priv, XCAN_FSR_OFFSET); 1144 1145 /* check if RX FIFO is empty */ 1146 if (priv->devtype.flags & XCAN_FLAG_CANFD_2) 1147 mask = XCAN_2_FSR_FL_MASK; 1148 else 1149 mask = XCAN_FSR_FL_MASK; 1150 1151 if (!(fsr & mask)) 1152 return -ENOENT; 1153 1154 if (priv->devtype.flags & XCAN_FLAG_CANFD_2) 1155 offset = 1156 XCAN_RXMSG_2_FRAME_OFFSET(fsr & XCAN_2_FSR_RI_MASK); 1157 else 1158 offset = 1159 XCAN_RXMSG_FRAME_OFFSET(fsr & XCAN_FSR_RI_MASK); 1160 1161 } else { 1162 /* check if RX FIFO is empty */ 1163 if (!(priv->read_reg(priv, XCAN_ISR_OFFSET) & 1164 XCAN_IXR_RXNEMP_MASK)) 1165 return -ENOENT; 1166 1167 /* frames are read from a static offset */ 1168 offset = XCAN_RXFIFO_OFFSET; 1169 } 1170 1171 return offset; 1172 } 1173 1174 /** 1175 * xcan_rx_poll - Poll routine for rx packets (NAPI) 1176 * @napi: napi structure pointer 1177 * @quota: Max number of rx packets to be processed. 1178 * 1179 * This is the poll routine for rx part. 1180 * It will process the packets maximux quota value. 1181 * 1182 * Return: number of packets received 1183 */ 1184 static int xcan_rx_poll(struct napi_struct *napi, int quota) 1185 { 1186 struct net_device *ndev = napi->dev; 1187 struct xcan_priv *priv = netdev_priv(ndev); 1188 u32 ier; 1189 int work_done = 0; 1190 int frame_offset; 1191 1192 while ((frame_offset = xcan_rx_fifo_get_next_frame(priv)) >= 0 && 1193 (work_done < quota)) { 1194 if (xcan_rx_int_mask(priv) & XCAN_IXR_RXOK_MASK) 1195 work_done += xcanfd_rx(ndev, frame_offset); 1196 else 1197 work_done += xcan_rx(ndev, frame_offset); 1198 1199 if (priv->devtype.flags & XCAN_FLAG_RX_FIFO_MULTI) 1200 /* increment read index */ 1201 priv->write_reg(priv, XCAN_FSR_OFFSET, 1202 XCAN_FSR_IRI_MASK); 1203 else 1204 /* clear rx-not-empty (will actually clear only if 1205 * empty) 1206 */ 1207 priv->write_reg(priv, XCAN_ICR_OFFSET, 1208 XCAN_IXR_RXNEMP_MASK); 1209 } 1210 1211 if (work_done) 1212 xcan_update_error_state_after_rxtx(ndev); 1213 1214 if (work_done < quota) { 1215 if (napi_complete_done(napi, work_done)) { 1216 ier = priv->read_reg(priv, XCAN_IER_OFFSET); 1217 ier |= xcan_rx_int_mask(priv); 1218 priv->write_reg(priv, XCAN_IER_OFFSET, ier); 1219 } 1220 } 1221 return work_done; 1222 } 1223 1224 /** 1225 * xcan_tx_interrupt - Tx Done Isr 1226 * @ndev: net_device pointer 1227 * @isr: Interrupt status register value 1228 */ 1229 static void xcan_tx_interrupt(struct net_device *ndev, u32 isr) 1230 { 1231 struct xcan_priv *priv = netdev_priv(ndev); 1232 struct net_device_stats *stats = &ndev->stats; 1233 unsigned int frames_in_fifo; 1234 int frames_sent = 1; /* TXOK => at least 1 frame was sent */ 1235 unsigned long flags; 1236 int retries = 0; 1237 1238 /* Synchronize with xmit as we need to know the exact number 1239 * of frames in the FIFO to stay in sync due to the TXFEMP 1240 * handling. 1241 * This also prevents a race between netif_wake_queue() and 1242 * netif_stop_queue(). 1243 */ 1244 spin_lock_irqsave(&priv->tx_lock, flags); 1245 1246 frames_in_fifo = priv->tx_head - priv->tx_tail; 1247 1248 if (WARN_ON_ONCE(frames_in_fifo == 0)) { 1249 /* clear TXOK anyway to avoid getting back here */ 1250 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK); 1251 spin_unlock_irqrestore(&priv->tx_lock, flags); 1252 return; 1253 } 1254 1255 /* Check if 2 frames were sent (TXOK only means that at least 1 1256 * frame was sent). 1257 */ 1258 if (frames_in_fifo > 1) { 1259 WARN_ON(frames_in_fifo > priv->tx_max); 1260 1261 /* Synchronize TXOK and isr so that after the loop: 1262 * (1) isr variable is up-to-date at least up to TXOK clear 1263 * time. This avoids us clearing a TXOK of a second frame 1264 * but not noticing that the FIFO is now empty and thus 1265 * marking only a single frame as sent. 1266 * (2) No TXOK is left. Having one could mean leaving a 1267 * stray TXOK as we might process the associated frame 1268 * via TXFEMP handling as we read TXFEMP *after* TXOK 1269 * clear to satisfy (1). 1270 */ 1271 while ((isr & XCAN_IXR_TXOK_MASK) && 1272 !WARN_ON(++retries == 100)) { 1273 priv->write_reg(priv, XCAN_ICR_OFFSET, 1274 XCAN_IXR_TXOK_MASK); 1275 isr = priv->read_reg(priv, XCAN_ISR_OFFSET); 1276 } 1277 1278 if (isr & XCAN_IXR_TXFEMP_MASK) { 1279 /* nothing in FIFO anymore */ 1280 frames_sent = frames_in_fifo; 1281 } 1282 } else { 1283 /* single frame in fifo, just clear TXOK */ 1284 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK); 1285 } 1286 1287 while (frames_sent--) { 1288 stats->tx_bytes += can_get_echo_skb(ndev, priv->tx_tail % 1289 priv->tx_max, NULL); 1290 priv->tx_tail++; 1291 stats->tx_packets++; 1292 } 1293 1294 netif_wake_queue(ndev); 1295 1296 spin_unlock_irqrestore(&priv->tx_lock, flags); 1297 1298 xcan_update_error_state_after_rxtx(ndev); 1299 } 1300 1301 /** 1302 * xcan_interrupt - CAN Isr 1303 * @irq: irq number 1304 * @dev_id: device id pointer 1305 * 1306 * This is the xilinx CAN Isr. It checks for the type of interrupt 1307 * and invokes the corresponding ISR. 1308 * 1309 * Return: 1310 * IRQ_NONE - If CAN device is in sleep mode, IRQ_HANDLED otherwise 1311 */ 1312 static irqreturn_t xcan_interrupt(int irq, void *dev_id) 1313 { 1314 struct net_device *ndev = (struct net_device *)dev_id; 1315 struct xcan_priv *priv = netdev_priv(ndev); 1316 u32 isr, ier; 1317 u32 isr_errors; 1318 u32 rx_int_mask = xcan_rx_int_mask(priv); 1319 1320 /* Get the interrupt status from Xilinx CAN */ 1321 isr = priv->read_reg(priv, XCAN_ISR_OFFSET); 1322 if (!isr) 1323 return IRQ_NONE; 1324 1325 /* Check for the type of interrupt and Processing it */ 1326 if (isr & (XCAN_IXR_SLP_MASK | XCAN_IXR_WKUP_MASK)) { 1327 priv->write_reg(priv, XCAN_ICR_OFFSET, (XCAN_IXR_SLP_MASK | 1328 XCAN_IXR_WKUP_MASK)); 1329 xcan_state_interrupt(ndev, isr); 1330 } 1331 1332 /* Check for Tx interrupt and Processing it */ 1333 if (isr & XCAN_IXR_TXOK_MASK) 1334 xcan_tx_interrupt(ndev, isr); 1335 1336 /* Check for the type of error interrupt and Processing it */ 1337 isr_errors = isr & (XCAN_IXR_ERROR_MASK | XCAN_IXR_RXOFLW_MASK | 1338 XCAN_IXR_BSOFF_MASK | XCAN_IXR_ARBLST_MASK | 1339 XCAN_IXR_RXMNF_MASK); 1340 if (isr_errors) { 1341 priv->write_reg(priv, XCAN_ICR_OFFSET, isr_errors); 1342 xcan_err_interrupt(ndev, isr); 1343 } 1344 1345 /* Check for the type of receive interrupt and Processing it */ 1346 if (isr & rx_int_mask) { 1347 ier = priv->read_reg(priv, XCAN_IER_OFFSET); 1348 ier &= ~rx_int_mask; 1349 priv->write_reg(priv, XCAN_IER_OFFSET, ier); 1350 napi_schedule(&priv->napi); 1351 } 1352 return IRQ_HANDLED; 1353 } 1354 1355 /** 1356 * xcan_chip_stop - Driver stop routine 1357 * @ndev: Pointer to net_device structure 1358 * 1359 * This is the drivers stop routine. It will disable the 1360 * interrupts and put the device into configuration mode. 1361 */ 1362 static void xcan_chip_stop(struct net_device *ndev) 1363 { 1364 struct xcan_priv *priv = netdev_priv(ndev); 1365 int ret; 1366 1367 /* Disable interrupts and leave the can in configuration mode */ 1368 ret = set_reset_mode(ndev); 1369 if (ret < 0) 1370 netdev_dbg(ndev, "set_reset_mode() Failed\n"); 1371 1372 priv->can.state = CAN_STATE_STOPPED; 1373 } 1374 1375 /** 1376 * xcan_open - Driver open routine 1377 * @ndev: Pointer to net_device structure 1378 * 1379 * This is the driver open routine. 1380 * Return: 0 on success and failure value on error 1381 */ 1382 static int xcan_open(struct net_device *ndev) 1383 { 1384 struct xcan_priv *priv = netdev_priv(ndev); 1385 int ret; 1386 1387 ret = pm_runtime_get_sync(priv->dev); 1388 if (ret < 0) { 1389 netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n", 1390 __func__, ret); 1391 goto err; 1392 } 1393 1394 ret = request_irq(ndev->irq, xcan_interrupt, priv->irq_flags, 1395 ndev->name, ndev); 1396 if (ret < 0) { 1397 netdev_err(ndev, "irq allocation for CAN failed\n"); 1398 goto err; 1399 } 1400 1401 /* Set chip into reset mode */ 1402 ret = set_reset_mode(ndev); 1403 if (ret < 0) { 1404 netdev_err(ndev, "mode resetting failed!\n"); 1405 goto err_irq; 1406 } 1407 1408 /* Common open */ 1409 ret = open_candev(ndev); 1410 if (ret) 1411 goto err_irq; 1412 1413 ret = xcan_chip_start(ndev); 1414 if (ret < 0) { 1415 netdev_err(ndev, "xcan_chip_start failed!\n"); 1416 goto err_candev; 1417 } 1418 1419 napi_enable(&priv->napi); 1420 netif_start_queue(ndev); 1421 1422 return 0; 1423 1424 err_candev: 1425 close_candev(ndev); 1426 err_irq: 1427 free_irq(ndev->irq, ndev); 1428 err: 1429 pm_runtime_put(priv->dev); 1430 1431 return ret; 1432 } 1433 1434 /** 1435 * xcan_close - Driver close routine 1436 * @ndev: Pointer to net_device structure 1437 * 1438 * Return: 0 always 1439 */ 1440 static int xcan_close(struct net_device *ndev) 1441 { 1442 struct xcan_priv *priv = netdev_priv(ndev); 1443 1444 netif_stop_queue(ndev); 1445 napi_disable(&priv->napi); 1446 xcan_chip_stop(ndev); 1447 free_irq(ndev->irq, ndev); 1448 close_candev(ndev); 1449 1450 pm_runtime_put(priv->dev); 1451 1452 return 0; 1453 } 1454 1455 /** 1456 * xcan_get_berr_counter - error counter routine 1457 * @ndev: Pointer to net_device structure 1458 * @bec: Pointer to can_berr_counter structure 1459 * 1460 * This is the driver error counter routine. 1461 * Return: 0 on success and failure value on error 1462 */ 1463 static int xcan_get_berr_counter(const struct net_device *ndev, 1464 struct can_berr_counter *bec) 1465 { 1466 struct xcan_priv *priv = netdev_priv(ndev); 1467 int ret; 1468 1469 ret = pm_runtime_get_sync(priv->dev); 1470 if (ret < 0) { 1471 netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n", 1472 __func__, ret); 1473 pm_runtime_put(priv->dev); 1474 return ret; 1475 } 1476 1477 bec->txerr = priv->read_reg(priv, XCAN_ECR_OFFSET) & XCAN_ECR_TEC_MASK; 1478 bec->rxerr = ((priv->read_reg(priv, XCAN_ECR_OFFSET) & 1479 XCAN_ECR_REC_MASK) >> XCAN_ESR_REC_SHIFT); 1480 1481 pm_runtime_put(priv->dev); 1482 1483 return 0; 1484 } 1485 1486 static const struct net_device_ops xcan_netdev_ops = { 1487 .ndo_open = xcan_open, 1488 .ndo_stop = xcan_close, 1489 .ndo_start_xmit = xcan_start_xmit, 1490 .ndo_change_mtu = can_change_mtu, 1491 }; 1492 1493 /** 1494 * xcan_suspend - Suspend method for the driver 1495 * @dev: Address of the device structure 1496 * 1497 * Put the driver into low power mode. 1498 * Return: 0 on success and failure value on error 1499 */ 1500 static int __maybe_unused xcan_suspend(struct device *dev) 1501 { 1502 struct net_device *ndev = dev_get_drvdata(dev); 1503 1504 if (netif_running(ndev)) { 1505 netif_stop_queue(ndev); 1506 netif_device_detach(ndev); 1507 xcan_chip_stop(ndev); 1508 } 1509 1510 return pm_runtime_force_suspend(dev); 1511 } 1512 1513 /** 1514 * xcan_resume - Resume from suspend 1515 * @dev: Address of the device structure 1516 * 1517 * Resume operation after suspend. 1518 * Return: 0 on success and failure value on error 1519 */ 1520 static int __maybe_unused xcan_resume(struct device *dev) 1521 { 1522 struct net_device *ndev = dev_get_drvdata(dev); 1523 int ret; 1524 1525 ret = pm_runtime_force_resume(dev); 1526 if (ret) { 1527 dev_err(dev, "pm_runtime_force_resume failed on resume\n"); 1528 return ret; 1529 } 1530 1531 if (netif_running(ndev)) { 1532 ret = xcan_chip_start(ndev); 1533 if (ret) { 1534 dev_err(dev, "xcan_chip_start failed on resume\n"); 1535 return ret; 1536 } 1537 1538 netif_device_attach(ndev); 1539 netif_start_queue(ndev); 1540 } 1541 1542 return 0; 1543 } 1544 1545 /** 1546 * xcan_runtime_suspend - Runtime suspend method for the driver 1547 * @dev: Address of the device structure 1548 * 1549 * Put the driver into low power mode. 1550 * Return: 0 always 1551 */ 1552 static int __maybe_unused xcan_runtime_suspend(struct device *dev) 1553 { 1554 struct net_device *ndev = dev_get_drvdata(dev); 1555 struct xcan_priv *priv = netdev_priv(ndev); 1556 1557 clk_disable_unprepare(priv->bus_clk); 1558 clk_disable_unprepare(priv->can_clk); 1559 1560 return 0; 1561 } 1562 1563 /** 1564 * xcan_runtime_resume - Runtime resume from suspend 1565 * @dev: Address of the device structure 1566 * 1567 * Resume operation after suspend. 1568 * Return: 0 on success and failure value on error 1569 */ 1570 static int __maybe_unused xcan_runtime_resume(struct device *dev) 1571 { 1572 struct net_device *ndev = dev_get_drvdata(dev); 1573 struct xcan_priv *priv = netdev_priv(ndev); 1574 int ret; 1575 1576 ret = clk_prepare_enable(priv->bus_clk); 1577 if (ret) { 1578 dev_err(dev, "Cannot enable clock.\n"); 1579 return ret; 1580 } 1581 ret = clk_prepare_enable(priv->can_clk); 1582 if (ret) { 1583 dev_err(dev, "Cannot enable clock.\n"); 1584 clk_disable_unprepare(priv->bus_clk); 1585 return ret; 1586 } 1587 1588 return 0; 1589 } 1590 1591 static const struct dev_pm_ops xcan_dev_pm_ops = { 1592 SET_SYSTEM_SLEEP_PM_OPS(xcan_suspend, xcan_resume) 1593 SET_RUNTIME_PM_OPS(xcan_runtime_suspend, xcan_runtime_resume, NULL) 1594 }; 1595 1596 static const struct xcan_devtype_data xcan_zynq_data = { 1597 .cantype = XZYNQ_CANPS, 1598 .flags = XCAN_FLAG_TXFEMP, 1599 .bittiming_const = &xcan_bittiming_const, 1600 .btr_ts2_shift = XCAN_BTR_TS2_SHIFT, 1601 .btr_sjw_shift = XCAN_BTR_SJW_SHIFT, 1602 .bus_clk_name = "pclk", 1603 }; 1604 1605 static const struct xcan_devtype_data xcan_axi_data = { 1606 .cantype = XAXI_CAN, 1607 .bittiming_const = &xcan_bittiming_const, 1608 .btr_ts2_shift = XCAN_BTR_TS2_SHIFT, 1609 .btr_sjw_shift = XCAN_BTR_SJW_SHIFT, 1610 .bus_clk_name = "s_axi_aclk", 1611 }; 1612 1613 static const struct xcan_devtype_data xcan_canfd_data = { 1614 .cantype = XAXI_CANFD, 1615 .flags = XCAN_FLAG_EXT_FILTERS | 1616 XCAN_FLAG_RXMNF | 1617 XCAN_FLAG_TX_MAILBOXES | 1618 XCAN_FLAG_RX_FIFO_MULTI, 1619 .bittiming_const = &xcan_bittiming_const_canfd, 1620 .btr_ts2_shift = XCAN_BTR_TS2_SHIFT_CANFD, 1621 .btr_sjw_shift = XCAN_BTR_SJW_SHIFT_CANFD, 1622 .bus_clk_name = "s_axi_aclk", 1623 }; 1624 1625 static const struct xcan_devtype_data xcan_canfd2_data = { 1626 .cantype = XAXI_CANFD_2_0, 1627 .flags = XCAN_FLAG_EXT_FILTERS | 1628 XCAN_FLAG_RXMNF | 1629 XCAN_FLAG_TX_MAILBOXES | 1630 XCAN_FLAG_CANFD_2 | 1631 XCAN_FLAG_RX_FIFO_MULTI, 1632 .bittiming_const = &xcan_bittiming_const_canfd2, 1633 .btr_ts2_shift = XCAN_BTR_TS2_SHIFT_CANFD, 1634 .btr_sjw_shift = XCAN_BTR_SJW_SHIFT_CANFD, 1635 .bus_clk_name = "s_axi_aclk", 1636 }; 1637 1638 /* Match table for OF platform binding */ 1639 static const struct of_device_id xcan_of_match[] = { 1640 { .compatible = "xlnx,zynq-can-1.0", .data = &xcan_zynq_data }, 1641 { .compatible = "xlnx,axi-can-1.00.a", .data = &xcan_axi_data }, 1642 { .compatible = "xlnx,canfd-1.0", .data = &xcan_canfd_data }, 1643 { .compatible = "xlnx,canfd-2.0", .data = &xcan_canfd2_data }, 1644 { /* end of list */ }, 1645 }; 1646 MODULE_DEVICE_TABLE(of, xcan_of_match); 1647 1648 /** 1649 * xcan_probe - Platform registration call 1650 * @pdev: Handle to the platform device structure 1651 * 1652 * This function does all the memory allocation and registration for the CAN 1653 * device. 1654 * 1655 * Return: 0 on success and failure value on error 1656 */ 1657 static int xcan_probe(struct platform_device *pdev) 1658 { 1659 struct net_device *ndev; 1660 struct xcan_priv *priv; 1661 const struct of_device_id *of_id; 1662 const struct xcan_devtype_data *devtype = &xcan_axi_data; 1663 void __iomem *addr; 1664 int ret; 1665 int rx_max, tx_max; 1666 u32 hw_tx_max = 0, hw_rx_max = 0; 1667 const char *hw_tx_max_property; 1668 1669 /* Get the virtual base address for the device */ 1670 addr = devm_platform_ioremap_resource(pdev, 0); 1671 if (IS_ERR(addr)) { 1672 ret = PTR_ERR(addr); 1673 goto err; 1674 } 1675 1676 of_id = of_match_device(xcan_of_match, &pdev->dev); 1677 if (of_id && of_id->data) 1678 devtype = of_id->data; 1679 1680 hw_tx_max_property = devtype->flags & XCAN_FLAG_TX_MAILBOXES ? 1681 "tx-mailbox-count" : "tx-fifo-depth"; 1682 1683 ret = of_property_read_u32(pdev->dev.of_node, hw_tx_max_property, 1684 &hw_tx_max); 1685 if (ret < 0) { 1686 dev_err(&pdev->dev, "missing %s property\n", 1687 hw_tx_max_property); 1688 goto err; 1689 } 1690 1691 ret = of_property_read_u32(pdev->dev.of_node, "rx-fifo-depth", 1692 &hw_rx_max); 1693 if (ret < 0) { 1694 dev_err(&pdev->dev, 1695 "missing rx-fifo-depth property (mailbox mode is not supported)\n"); 1696 goto err; 1697 } 1698 1699 /* With TX FIFO: 1700 * 1701 * There is no way to directly figure out how many frames have been 1702 * sent when the TXOK interrupt is processed. If TXFEMP 1703 * is supported, we can have 2 frames in the FIFO and use TXFEMP 1704 * to determine if 1 or 2 frames have been sent. 1705 * Theoretically we should be able to use TXFWMEMP to determine up 1706 * to 3 frames, but it seems that after putting a second frame in the 1707 * FIFO, with watermark at 2 frames, it can happen that TXFWMEMP (less 1708 * than 2 frames in FIFO) is set anyway with no TXOK (a frame was 1709 * sent), which is not a sensible state - possibly TXFWMEMP is not 1710 * completely synchronized with the rest of the bits? 1711 * 1712 * With TX mailboxes: 1713 * 1714 * HW sends frames in CAN ID priority order. To preserve FIFO ordering 1715 * we submit frames one at a time. 1716 */ 1717 if (!(devtype->flags & XCAN_FLAG_TX_MAILBOXES) && 1718 (devtype->flags & XCAN_FLAG_TXFEMP)) 1719 tx_max = min(hw_tx_max, 2U); 1720 else 1721 tx_max = 1; 1722 1723 rx_max = hw_rx_max; 1724 1725 /* Create a CAN device instance */ 1726 ndev = alloc_candev(sizeof(struct xcan_priv), tx_max); 1727 if (!ndev) 1728 return -ENOMEM; 1729 1730 priv = netdev_priv(ndev); 1731 priv->dev = &pdev->dev; 1732 priv->can.bittiming_const = devtype->bittiming_const; 1733 priv->can.do_set_mode = xcan_do_set_mode; 1734 priv->can.do_get_berr_counter = xcan_get_berr_counter; 1735 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1736 CAN_CTRLMODE_BERR_REPORTING; 1737 1738 if (devtype->cantype == XAXI_CANFD) 1739 priv->can.data_bittiming_const = 1740 &xcan_data_bittiming_const_canfd; 1741 1742 if (devtype->cantype == XAXI_CANFD_2_0) 1743 priv->can.data_bittiming_const = 1744 &xcan_data_bittiming_const_canfd2; 1745 1746 if (devtype->cantype == XAXI_CANFD || 1747 devtype->cantype == XAXI_CANFD_2_0) 1748 priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD; 1749 1750 priv->reg_base = addr; 1751 priv->tx_max = tx_max; 1752 priv->devtype = *devtype; 1753 spin_lock_init(&priv->tx_lock); 1754 1755 /* Get IRQ for the device */ 1756 ret = platform_get_irq(pdev, 0); 1757 if (ret < 0) 1758 goto err_free; 1759 1760 ndev->irq = ret; 1761 1762 ndev->flags |= IFF_ECHO; /* We support local echo */ 1763 1764 platform_set_drvdata(pdev, ndev); 1765 SET_NETDEV_DEV(ndev, &pdev->dev); 1766 ndev->netdev_ops = &xcan_netdev_ops; 1767 1768 /* Getting the CAN can_clk info */ 1769 priv->can_clk = devm_clk_get(&pdev->dev, "can_clk"); 1770 if (IS_ERR(priv->can_clk)) { 1771 ret = dev_err_probe(&pdev->dev, PTR_ERR(priv->can_clk), 1772 "device clock not found\n"); 1773 goto err_free; 1774 } 1775 1776 priv->bus_clk = devm_clk_get(&pdev->dev, devtype->bus_clk_name); 1777 if (IS_ERR(priv->bus_clk)) { 1778 ret = dev_err_probe(&pdev->dev, PTR_ERR(priv->bus_clk), 1779 "bus clock not found\n"); 1780 goto err_free; 1781 } 1782 1783 priv->write_reg = xcan_write_reg_le; 1784 priv->read_reg = xcan_read_reg_le; 1785 1786 pm_runtime_enable(&pdev->dev); 1787 ret = pm_runtime_get_sync(&pdev->dev); 1788 if (ret < 0) { 1789 netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n", 1790 __func__, ret); 1791 goto err_disableclks; 1792 } 1793 1794 if (priv->read_reg(priv, XCAN_SR_OFFSET) != XCAN_SR_CONFIG_MASK) { 1795 priv->write_reg = xcan_write_reg_be; 1796 priv->read_reg = xcan_read_reg_be; 1797 } 1798 1799 priv->can.clock.freq = clk_get_rate(priv->can_clk); 1800 1801 netif_napi_add_weight(ndev, &priv->napi, xcan_rx_poll, rx_max); 1802 1803 ret = register_candev(ndev); 1804 if (ret) { 1805 dev_err(&pdev->dev, "fail to register failed (err=%d)\n", ret); 1806 goto err_disableclks; 1807 } 1808 1809 pm_runtime_put(&pdev->dev); 1810 1811 if (priv->devtype.flags & XCAN_FLAG_CANFD_2) { 1812 priv->write_reg(priv, XCAN_AFR_2_ID_OFFSET, 0x00000000); 1813 priv->write_reg(priv, XCAN_AFR_2_MASK_OFFSET, 0x00000000); 1814 } 1815 1816 netdev_dbg(ndev, "reg_base=0x%p irq=%d clock=%d, tx buffers: actual %d, using %d\n", 1817 priv->reg_base, ndev->irq, priv->can.clock.freq, 1818 hw_tx_max, priv->tx_max); 1819 1820 return 0; 1821 1822 err_disableclks: 1823 pm_runtime_put(priv->dev); 1824 pm_runtime_disable(&pdev->dev); 1825 err_free: 1826 free_candev(ndev); 1827 err: 1828 return ret; 1829 } 1830 1831 /** 1832 * xcan_remove - Unregister the device after releasing the resources 1833 * @pdev: Handle to the platform device structure 1834 * 1835 * This function frees all the resources allocated to the device. 1836 * Return: 0 always 1837 */ 1838 static int xcan_remove(struct platform_device *pdev) 1839 { 1840 struct net_device *ndev = platform_get_drvdata(pdev); 1841 1842 unregister_candev(ndev); 1843 pm_runtime_disable(&pdev->dev); 1844 free_candev(ndev); 1845 1846 return 0; 1847 } 1848 1849 static struct platform_driver xcan_driver = { 1850 .probe = xcan_probe, 1851 .remove = xcan_remove, 1852 .driver = { 1853 .name = DRIVER_NAME, 1854 .pm = &xcan_dev_pm_ops, 1855 .of_match_table = xcan_of_match, 1856 }, 1857 }; 1858 1859 module_platform_driver(xcan_driver); 1860 1861 MODULE_LICENSE("GPL"); 1862 MODULE_AUTHOR("Xilinx Inc"); 1863 MODULE_DESCRIPTION("Xilinx CAN interface"); 1864