1 /* 2 * TI HECC (CAN) device driver 3 * 4 * This driver supports TI's HECC (High End CAN Controller module) and the 5 * specs for the same is available at <http://www.ti.com> 6 * 7 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation version 2. 12 * 13 * This program is distributed as is WITHOUT ANY WARRANTY of any 14 * kind, whether express or implied; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 */ 19 20 /* 21 * Your platform definitions should specify module ram offsets and interrupt 22 * number to use as follows: 23 * 24 * static struct ti_hecc_platform_data am3517_evm_hecc_pdata = { 25 * .scc_hecc_offset = 0, 26 * .scc_ram_offset = 0x3000, 27 * .hecc_ram_offset = 0x3000, 28 * .mbx_offset = 0x2000, 29 * .int_line = 0, 30 * .revision = 1, 31 * .transceiver_switch = hecc_phy_control, 32 * }; 33 * 34 * Please see include/linux/can/platform/ti_hecc.h for description of 35 * above fields. 36 * 37 */ 38 39 #include <linux/module.h> 40 #include <linux/init.h> 41 #include <linux/kernel.h> 42 #include <linux/types.h> 43 #include <linux/interrupt.h> 44 #include <linux/errno.h> 45 #include <linux/netdevice.h> 46 #include <linux/skbuff.h> 47 #include <linux/platform_device.h> 48 #include <linux/clk.h> 49 #include <linux/io.h> 50 51 #include <linux/can/dev.h> 52 #include <linux/can/error.h> 53 #include <linux/can/led.h> 54 #include <linux/can/platform/ti_hecc.h> 55 56 #define DRV_NAME "ti_hecc" 57 #define HECC_MODULE_VERSION "0.7" 58 MODULE_VERSION(HECC_MODULE_VERSION); 59 #define DRV_DESC "TI High End CAN Controller Driver " HECC_MODULE_VERSION 60 61 /* TX / RX Mailbox Configuration */ 62 #define HECC_MAX_MAILBOXES 32 /* hardware mailboxes - do not change */ 63 #define MAX_TX_PRIO 0x3F /* hardware value - do not change */ 64 65 /* 66 * Important Note: TX mailbox configuration 67 * TX mailboxes should be restricted to the number of SKB buffers to avoid 68 * maintaining SKB buffers separately. TX mailboxes should be a power of 2 69 * for the mailbox logic to work. Top mailbox numbers are reserved for RX 70 * and lower mailboxes for TX. 71 * 72 * HECC_MAX_TX_MBOX HECC_MB_TX_SHIFT 73 * 4 (default) 2 74 * 8 3 75 * 16 4 76 */ 77 #define HECC_MB_TX_SHIFT 2 /* as per table above */ 78 #define HECC_MAX_TX_MBOX BIT(HECC_MB_TX_SHIFT) 79 80 #define HECC_TX_PRIO_SHIFT (HECC_MB_TX_SHIFT) 81 #define HECC_TX_PRIO_MASK (MAX_TX_PRIO << HECC_MB_TX_SHIFT) 82 #define HECC_TX_MB_MASK (HECC_MAX_TX_MBOX - 1) 83 #define HECC_TX_MASK ((HECC_MAX_TX_MBOX - 1) | HECC_TX_PRIO_MASK) 84 #define HECC_TX_MBOX_MASK (~(BIT(HECC_MAX_TX_MBOX) - 1)) 85 #define HECC_DEF_NAPI_WEIGHT HECC_MAX_RX_MBOX 86 87 /* 88 * Important Note: RX mailbox configuration 89 * RX mailboxes are further logically split into two - main and buffer 90 * mailboxes. The goal is to get all packets into main mailboxes as 91 * driven by mailbox number and receive priority (higher to lower) and 92 * buffer mailboxes are used to receive pkts while main mailboxes are being 93 * processed. This ensures in-order packet reception. 94 * 95 * Here are the recommended values for buffer mailbox. Note that RX mailboxes 96 * start after TX mailboxes: 97 * 98 * HECC_MAX_RX_MBOX HECC_RX_BUFFER_MBOX No of buffer mailboxes 99 * 28 12 8 100 * 16 20 4 101 */ 102 103 #define HECC_MAX_RX_MBOX (HECC_MAX_MAILBOXES - HECC_MAX_TX_MBOX) 104 #define HECC_RX_BUFFER_MBOX 12 /* as per table above */ 105 #define HECC_RX_FIRST_MBOX (HECC_MAX_MAILBOXES - 1) 106 #define HECC_RX_HIGH_MBOX_MASK (~(BIT(HECC_RX_BUFFER_MBOX) - 1)) 107 108 /* TI HECC module registers */ 109 #define HECC_CANME 0x0 /* Mailbox enable */ 110 #define HECC_CANMD 0x4 /* Mailbox direction */ 111 #define HECC_CANTRS 0x8 /* Transmit request set */ 112 #define HECC_CANTRR 0xC /* Transmit request */ 113 #define HECC_CANTA 0x10 /* Transmission acknowledge */ 114 #define HECC_CANAA 0x14 /* Abort acknowledge */ 115 #define HECC_CANRMP 0x18 /* Receive message pending */ 116 #define HECC_CANRML 0x1C /* Remote message lost */ 117 #define HECC_CANRFP 0x20 /* Remote frame pending */ 118 #define HECC_CANGAM 0x24 /* SECC only:Global acceptance mask */ 119 #define HECC_CANMC 0x28 /* Master control */ 120 #define HECC_CANBTC 0x2C /* Bit timing configuration */ 121 #define HECC_CANES 0x30 /* Error and status */ 122 #define HECC_CANTEC 0x34 /* Transmit error counter */ 123 #define HECC_CANREC 0x38 /* Receive error counter */ 124 #define HECC_CANGIF0 0x3C /* Global interrupt flag 0 */ 125 #define HECC_CANGIM 0x40 /* Global interrupt mask */ 126 #define HECC_CANGIF1 0x44 /* Global interrupt flag 1 */ 127 #define HECC_CANMIM 0x48 /* Mailbox interrupt mask */ 128 #define HECC_CANMIL 0x4C /* Mailbox interrupt level */ 129 #define HECC_CANOPC 0x50 /* Overwrite protection control */ 130 #define HECC_CANTIOC 0x54 /* Transmit I/O control */ 131 #define HECC_CANRIOC 0x58 /* Receive I/O control */ 132 #define HECC_CANLNT 0x5C /* HECC only: Local network time */ 133 #define HECC_CANTOC 0x60 /* HECC only: Time-out control */ 134 #define HECC_CANTOS 0x64 /* HECC only: Time-out status */ 135 #define HECC_CANTIOCE 0x68 /* SCC only:Enhanced TX I/O control */ 136 #define HECC_CANRIOCE 0x6C /* SCC only:Enhanced RX I/O control */ 137 138 /* Mailbox registers */ 139 #define HECC_CANMID 0x0 140 #define HECC_CANMCF 0x4 141 #define HECC_CANMDL 0x8 142 #define HECC_CANMDH 0xC 143 144 #define HECC_SET_REG 0xFFFFFFFF 145 #define HECC_CANID_MASK 0x3FF /* 18 bits mask for extended id's */ 146 #define HECC_CCE_WAIT_COUNT 100 /* Wait for ~1 sec for CCE bit */ 147 148 #define HECC_CANMC_SCM BIT(13) /* SCC compat mode */ 149 #define HECC_CANMC_CCR BIT(12) /* Change config request */ 150 #define HECC_CANMC_PDR BIT(11) /* Local Power down - for sleep mode */ 151 #define HECC_CANMC_ABO BIT(7) /* Auto Bus On */ 152 #define HECC_CANMC_STM BIT(6) /* Self test mode - loopback */ 153 #define HECC_CANMC_SRES BIT(5) /* Software reset */ 154 155 #define HECC_CANTIOC_EN BIT(3) /* Enable CAN TX I/O pin */ 156 #define HECC_CANRIOC_EN BIT(3) /* Enable CAN RX I/O pin */ 157 158 #define HECC_CANMID_IDE BIT(31) /* Extended frame format */ 159 #define HECC_CANMID_AME BIT(30) /* Acceptance mask enable */ 160 #define HECC_CANMID_AAM BIT(29) /* Auto answer mode */ 161 162 #define HECC_CANES_FE BIT(24) /* form error */ 163 #define HECC_CANES_BE BIT(23) /* bit error */ 164 #define HECC_CANES_SA1 BIT(22) /* stuck at dominant error */ 165 #define HECC_CANES_CRCE BIT(21) /* CRC error */ 166 #define HECC_CANES_SE BIT(20) /* stuff bit error */ 167 #define HECC_CANES_ACKE BIT(19) /* ack error */ 168 #define HECC_CANES_BO BIT(18) /* Bus off status */ 169 #define HECC_CANES_EP BIT(17) /* Error passive status */ 170 #define HECC_CANES_EW BIT(16) /* Error warning status */ 171 #define HECC_CANES_SMA BIT(5) /* suspend mode ack */ 172 #define HECC_CANES_CCE BIT(4) /* Change config enabled */ 173 #define HECC_CANES_PDA BIT(3) /* Power down mode ack */ 174 175 #define HECC_CANBTC_SAM BIT(7) /* sample points */ 176 177 #define HECC_BUS_ERROR (HECC_CANES_FE | HECC_CANES_BE |\ 178 HECC_CANES_CRCE | HECC_CANES_SE |\ 179 HECC_CANES_ACKE) 180 181 #define HECC_CANMCF_RTR BIT(4) /* Remote transmit request */ 182 183 #define HECC_CANGIF_MAIF BIT(17) /* Message alarm interrupt */ 184 #define HECC_CANGIF_TCOIF BIT(16) /* Timer counter overflow int */ 185 #define HECC_CANGIF_GMIF BIT(15) /* Global mailbox interrupt */ 186 #define HECC_CANGIF_AAIF BIT(14) /* Abort ack interrupt */ 187 #define HECC_CANGIF_WDIF BIT(13) /* Write denied interrupt */ 188 #define HECC_CANGIF_WUIF BIT(12) /* Wake up interrupt */ 189 #define HECC_CANGIF_RMLIF BIT(11) /* Receive message lost interrupt */ 190 #define HECC_CANGIF_BOIF BIT(10) /* Bus off interrupt */ 191 #define HECC_CANGIF_EPIF BIT(9) /* Error passive interrupt */ 192 #define HECC_CANGIF_WLIF BIT(8) /* Warning level interrupt */ 193 #define HECC_CANGIF_MBOX_MASK 0x1F /* Mailbox number mask */ 194 #define HECC_CANGIM_I1EN BIT(1) /* Int line 1 enable */ 195 #define HECC_CANGIM_I0EN BIT(0) /* Int line 0 enable */ 196 #define HECC_CANGIM_DEF_MASK 0x700 /* only busoff/warning/passive */ 197 #define HECC_CANGIM_SIL BIT(2) /* system interrupts to int line 1 */ 198 199 /* CAN Bittiming constants as per HECC specs */ 200 static const struct can_bittiming_const ti_hecc_bittiming_const = { 201 .name = DRV_NAME, 202 .tseg1_min = 1, 203 .tseg1_max = 16, 204 .tseg2_min = 1, 205 .tseg2_max = 8, 206 .sjw_max = 4, 207 .brp_min = 1, 208 .brp_max = 256, 209 .brp_inc = 1, 210 }; 211 212 struct ti_hecc_priv { 213 struct can_priv can; /* MUST be first member/field */ 214 struct napi_struct napi; 215 struct net_device *ndev; 216 struct clk *clk; 217 void __iomem *base; 218 u32 scc_ram_offset; 219 u32 hecc_ram_offset; 220 u32 mbx_offset; 221 u32 int_line; 222 spinlock_t mbx_lock; /* CANME register needs protection */ 223 u32 tx_head; 224 u32 tx_tail; 225 u32 rx_next; 226 void (*transceiver_switch)(int); 227 }; 228 229 static inline int get_tx_head_mb(struct ti_hecc_priv *priv) 230 { 231 return priv->tx_head & HECC_TX_MB_MASK; 232 } 233 234 static inline int get_tx_tail_mb(struct ti_hecc_priv *priv) 235 { 236 return priv->tx_tail & HECC_TX_MB_MASK; 237 } 238 239 static inline int get_tx_head_prio(struct ti_hecc_priv *priv) 240 { 241 return (priv->tx_head >> HECC_TX_PRIO_SHIFT) & MAX_TX_PRIO; 242 } 243 244 static inline void hecc_write_lam(struct ti_hecc_priv *priv, u32 mbxno, u32 val) 245 { 246 __raw_writel(val, priv->base + priv->hecc_ram_offset + mbxno * 4); 247 } 248 249 static inline void hecc_write_mbx(struct ti_hecc_priv *priv, u32 mbxno, 250 u32 reg, u32 val) 251 { 252 __raw_writel(val, priv->base + priv->mbx_offset + mbxno * 0x10 + 253 reg); 254 } 255 256 static inline u32 hecc_read_mbx(struct ti_hecc_priv *priv, u32 mbxno, u32 reg) 257 { 258 return __raw_readl(priv->base + priv->mbx_offset + mbxno * 0x10 + 259 reg); 260 } 261 262 static inline void hecc_write(struct ti_hecc_priv *priv, u32 reg, u32 val) 263 { 264 __raw_writel(val, priv->base + reg); 265 } 266 267 static inline u32 hecc_read(struct ti_hecc_priv *priv, int reg) 268 { 269 return __raw_readl(priv->base + reg); 270 } 271 272 static inline void hecc_set_bit(struct ti_hecc_priv *priv, int reg, 273 u32 bit_mask) 274 { 275 hecc_write(priv, reg, hecc_read(priv, reg) | bit_mask); 276 } 277 278 static inline void hecc_clear_bit(struct ti_hecc_priv *priv, int reg, 279 u32 bit_mask) 280 { 281 hecc_write(priv, reg, hecc_read(priv, reg) & ~bit_mask); 282 } 283 284 static inline u32 hecc_get_bit(struct ti_hecc_priv *priv, int reg, u32 bit_mask) 285 { 286 return (hecc_read(priv, reg) & bit_mask) ? 1 : 0; 287 } 288 289 static int ti_hecc_set_btc(struct ti_hecc_priv *priv) 290 { 291 struct can_bittiming *bit_timing = &priv->can.bittiming; 292 u32 can_btc; 293 294 can_btc = (bit_timing->phase_seg2 - 1) & 0x7; 295 can_btc |= ((bit_timing->phase_seg1 + bit_timing->prop_seg - 1) 296 & 0xF) << 3; 297 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) { 298 if (bit_timing->brp > 4) 299 can_btc |= HECC_CANBTC_SAM; 300 else 301 netdev_warn(priv->ndev, "WARN: Triple" 302 "sampling not set due to h/w limitations"); 303 } 304 can_btc |= ((bit_timing->sjw - 1) & 0x3) << 8; 305 can_btc |= ((bit_timing->brp - 1) & 0xFF) << 16; 306 307 /* ERM being set to 0 by default meaning resync at falling edge */ 308 309 hecc_write(priv, HECC_CANBTC, can_btc); 310 netdev_info(priv->ndev, "setting CANBTC=%#x\n", can_btc); 311 312 return 0; 313 } 314 315 static void ti_hecc_transceiver_switch(const struct ti_hecc_priv *priv, 316 int on) 317 { 318 if (priv->transceiver_switch) 319 priv->transceiver_switch(on); 320 } 321 322 static void ti_hecc_reset(struct net_device *ndev) 323 { 324 u32 cnt; 325 struct ti_hecc_priv *priv = netdev_priv(ndev); 326 327 netdev_dbg(ndev, "resetting hecc ...\n"); 328 hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_SRES); 329 330 /* Set change control request and wait till enabled */ 331 hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_CCR); 332 333 /* 334 * INFO: It has been observed that at times CCE bit may not be 335 * set and hw seems to be ok even if this bit is not set so 336 * timing out with a timing of 1ms to respect the specs 337 */ 338 cnt = HECC_CCE_WAIT_COUNT; 339 while (!hecc_get_bit(priv, HECC_CANES, HECC_CANES_CCE) && cnt != 0) { 340 --cnt; 341 udelay(10); 342 } 343 344 /* 345 * Note: On HECC, BTC can be programmed only in initialization mode, so 346 * it is expected that the can bittiming parameters are set via ip 347 * utility before the device is opened 348 */ 349 ti_hecc_set_btc(priv); 350 351 /* Clear CCR (and CANMC register) and wait for CCE = 0 enable */ 352 hecc_write(priv, HECC_CANMC, 0); 353 354 /* 355 * INFO: CAN net stack handles bus off and hence disabling auto-bus-on 356 * hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_ABO); 357 */ 358 359 /* 360 * INFO: It has been observed that at times CCE bit may not be 361 * set and hw seems to be ok even if this bit is not set so 362 */ 363 cnt = HECC_CCE_WAIT_COUNT; 364 while (hecc_get_bit(priv, HECC_CANES, HECC_CANES_CCE) && cnt != 0) { 365 --cnt; 366 udelay(10); 367 } 368 369 /* Enable TX and RX I/O Control pins */ 370 hecc_write(priv, HECC_CANTIOC, HECC_CANTIOC_EN); 371 hecc_write(priv, HECC_CANRIOC, HECC_CANRIOC_EN); 372 373 /* Clear registers for clean operation */ 374 hecc_write(priv, HECC_CANTA, HECC_SET_REG); 375 hecc_write(priv, HECC_CANRMP, HECC_SET_REG); 376 hecc_write(priv, HECC_CANGIF0, HECC_SET_REG); 377 hecc_write(priv, HECC_CANGIF1, HECC_SET_REG); 378 hecc_write(priv, HECC_CANME, 0); 379 hecc_write(priv, HECC_CANMD, 0); 380 381 /* SCC compat mode NOT supported (and not needed too) */ 382 hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_SCM); 383 } 384 385 static void ti_hecc_start(struct net_device *ndev) 386 { 387 struct ti_hecc_priv *priv = netdev_priv(ndev); 388 u32 cnt, mbxno, mbx_mask; 389 390 /* put HECC in initialization mode and set btc */ 391 ti_hecc_reset(ndev); 392 393 priv->tx_head = priv->tx_tail = HECC_TX_MASK; 394 priv->rx_next = HECC_RX_FIRST_MBOX; 395 396 /* Enable local and global acceptance mask registers */ 397 hecc_write(priv, HECC_CANGAM, HECC_SET_REG); 398 399 /* Prepare configured mailboxes to receive messages */ 400 for (cnt = 0; cnt < HECC_MAX_RX_MBOX; cnt++) { 401 mbxno = HECC_MAX_MAILBOXES - 1 - cnt; 402 mbx_mask = BIT(mbxno); 403 hecc_clear_bit(priv, HECC_CANME, mbx_mask); 404 hecc_write_mbx(priv, mbxno, HECC_CANMID, HECC_CANMID_AME); 405 hecc_write_lam(priv, mbxno, HECC_SET_REG); 406 hecc_set_bit(priv, HECC_CANMD, mbx_mask); 407 hecc_set_bit(priv, HECC_CANME, mbx_mask); 408 hecc_set_bit(priv, HECC_CANMIM, mbx_mask); 409 } 410 411 /* Prevent message over-write & Enable interrupts */ 412 hecc_write(priv, HECC_CANOPC, HECC_SET_REG); 413 if (priv->int_line) { 414 hecc_write(priv, HECC_CANMIL, HECC_SET_REG); 415 hecc_write(priv, HECC_CANGIM, HECC_CANGIM_DEF_MASK | 416 HECC_CANGIM_I1EN | HECC_CANGIM_SIL); 417 } else { 418 hecc_write(priv, HECC_CANMIL, 0); 419 hecc_write(priv, HECC_CANGIM, 420 HECC_CANGIM_DEF_MASK | HECC_CANGIM_I0EN); 421 } 422 priv->can.state = CAN_STATE_ERROR_ACTIVE; 423 } 424 425 static void ti_hecc_stop(struct net_device *ndev) 426 { 427 struct ti_hecc_priv *priv = netdev_priv(ndev); 428 429 /* Disable interrupts and disable mailboxes */ 430 hecc_write(priv, HECC_CANGIM, 0); 431 hecc_write(priv, HECC_CANMIM, 0); 432 hecc_write(priv, HECC_CANME, 0); 433 priv->can.state = CAN_STATE_STOPPED; 434 } 435 436 static int ti_hecc_do_set_mode(struct net_device *ndev, enum can_mode mode) 437 { 438 int ret = 0; 439 440 switch (mode) { 441 case CAN_MODE_START: 442 ti_hecc_start(ndev); 443 netif_wake_queue(ndev); 444 break; 445 default: 446 ret = -EOPNOTSUPP; 447 break; 448 } 449 450 return ret; 451 } 452 453 static int ti_hecc_get_berr_counter(const struct net_device *ndev, 454 struct can_berr_counter *bec) 455 { 456 struct ti_hecc_priv *priv = netdev_priv(ndev); 457 458 bec->txerr = hecc_read(priv, HECC_CANTEC); 459 bec->rxerr = hecc_read(priv, HECC_CANREC); 460 461 return 0; 462 } 463 464 /* 465 * ti_hecc_xmit: HECC Transmit 466 * 467 * The transmit mailboxes start from 0 to HECC_MAX_TX_MBOX. In HECC the 468 * priority of the mailbox for tranmission is dependent upon priority setting 469 * field in mailbox registers. The mailbox with highest value in priority field 470 * is transmitted first. Only when two mailboxes have the same value in 471 * priority field the highest numbered mailbox is transmitted first. 472 * 473 * To utilize the HECC priority feature as described above we start with the 474 * highest numbered mailbox with highest priority level and move on to the next 475 * mailbox with the same priority level and so on. Once we loop through all the 476 * transmit mailboxes we choose the next priority level (lower) and so on 477 * until we reach the lowest priority level on the lowest numbered mailbox 478 * when we stop transmission until all mailboxes are transmitted and then 479 * restart at highest numbered mailbox with highest priority. 480 * 481 * Two counters (head and tail) are used to track the next mailbox to transmit 482 * and to track the echo buffer for already transmitted mailbox. The queue 483 * is stopped when all the mailboxes are busy or when there is a priority 484 * value roll-over happens. 485 */ 486 static netdev_tx_t ti_hecc_xmit(struct sk_buff *skb, struct net_device *ndev) 487 { 488 struct ti_hecc_priv *priv = netdev_priv(ndev); 489 struct can_frame *cf = (struct can_frame *)skb->data; 490 u32 mbxno, mbx_mask, data; 491 unsigned long flags; 492 493 if (can_dropped_invalid_skb(ndev, skb)) 494 return NETDEV_TX_OK; 495 496 mbxno = get_tx_head_mb(priv); 497 mbx_mask = BIT(mbxno); 498 spin_lock_irqsave(&priv->mbx_lock, flags); 499 if (unlikely(hecc_read(priv, HECC_CANME) & mbx_mask)) { 500 spin_unlock_irqrestore(&priv->mbx_lock, flags); 501 netif_stop_queue(ndev); 502 netdev_err(priv->ndev, 503 "BUG: TX mbx not ready tx_head=%08X, tx_tail=%08X\n", 504 priv->tx_head, priv->tx_tail); 505 return NETDEV_TX_BUSY; 506 } 507 spin_unlock_irqrestore(&priv->mbx_lock, flags); 508 509 /* Prepare mailbox for transmission */ 510 data = cf->can_dlc | (get_tx_head_prio(priv) << 8); 511 if (cf->can_id & CAN_RTR_FLAG) /* Remote transmission request */ 512 data |= HECC_CANMCF_RTR; 513 hecc_write_mbx(priv, mbxno, HECC_CANMCF, data); 514 515 if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */ 516 data = (cf->can_id & CAN_EFF_MASK) | HECC_CANMID_IDE; 517 else /* Standard frame format */ 518 data = (cf->can_id & CAN_SFF_MASK) << 18; 519 hecc_write_mbx(priv, mbxno, HECC_CANMID, data); 520 hecc_write_mbx(priv, mbxno, HECC_CANMDL, 521 be32_to_cpu(*(u32 *)(cf->data))); 522 if (cf->can_dlc > 4) 523 hecc_write_mbx(priv, mbxno, HECC_CANMDH, 524 be32_to_cpu(*(u32 *)(cf->data + 4))); 525 else 526 *(u32 *)(cf->data + 4) = 0; 527 can_put_echo_skb(skb, ndev, mbxno); 528 529 spin_lock_irqsave(&priv->mbx_lock, flags); 530 --priv->tx_head; 531 if ((hecc_read(priv, HECC_CANME) & BIT(get_tx_head_mb(priv))) || 532 (priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK) { 533 netif_stop_queue(ndev); 534 } 535 hecc_set_bit(priv, HECC_CANME, mbx_mask); 536 spin_unlock_irqrestore(&priv->mbx_lock, flags); 537 538 hecc_clear_bit(priv, HECC_CANMD, mbx_mask); 539 hecc_set_bit(priv, HECC_CANMIM, mbx_mask); 540 hecc_write(priv, HECC_CANTRS, mbx_mask); 541 542 return NETDEV_TX_OK; 543 } 544 545 static int ti_hecc_rx_pkt(struct ti_hecc_priv *priv, int mbxno) 546 { 547 struct net_device_stats *stats = &priv->ndev->stats; 548 struct can_frame *cf; 549 struct sk_buff *skb; 550 u32 data, mbx_mask; 551 unsigned long flags; 552 553 skb = alloc_can_skb(priv->ndev, &cf); 554 if (!skb) { 555 if (printk_ratelimit()) 556 netdev_err(priv->ndev, 557 "ti_hecc_rx_pkt: alloc_can_skb() failed\n"); 558 return -ENOMEM; 559 } 560 561 mbx_mask = BIT(mbxno); 562 data = hecc_read_mbx(priv, mbxno, HECC_CANMID); 563 if (data & HECC_CANMID_IDE) 564 cf->can_id = (data & CAN_EFF_MASK) | CAN_EFF_FLAG; 565 else 566 cf->can_id = (data >> 18) & CAN_SFF_MASK; 567 data = hecc_read_mbx(priv, mbxno, HECC_CANMCF); 568 if (data & HECC_CANMCF_RTR) 569 cf->can_id |= CAN_RTR_FLAG; 570 cf->can_dlc = get_can_dlc(data & 0xF); 571 data = hecc_read_mbx(priv, mbxno, HECC_CANMDL); 572 *(u32 *)(cf->data) = cpu_to_be32(data); 573 if (cf->can_dlc > 4) { 574 data = hecc_read_mbx(priv, mbxno, HECC_CANMDH); 575 *(u32 *)(cf->data + 4) = cpu_to_be32(data); 576 } else { 577 *(u32 *)(cf->data + 4) = 0; 578 } 579 spin_lock_irqsave(&priv->mbx_lock, flags); 580 hecc_clear_bit(priv, HECC_CANME, mbx_mask); 581 hecc_write(priv, HECC_CANRMP, mbx_mask); 582 /* enable mailbox only if it is part of rx buffer mailboxes */ 583 if (priv->rx_next < HECC_RX_BUFFER_MBOX) 584 hecc_set_bit(priv, HECC_CANME, mbx_mask); 585 spin_unlock_irqrestore(&priv->mbx_lock, flags); 586 587 stats->rx_bytes += cf->can_dlc; 588 can_led_event(priv->ndev, CAN_LED_EVENT_RX); 589 netif_receive_skb(skb); 590 stats->rx_packets++; 591 592 return 0; 593 } 594 595 /* 596 * ti_hecc_rx_poll - HECC receive pkts 597 * 598 * The receive mailboxes start from highest numbered mailbox till last xmit 599 * mailbox. On CAN frame reception the hardware places the data into highest 600 * numbered mailbox that matches the CAN ID filter. Since all receive mailboxes 601 * have same filtering (ALL CAN frames) packets will arrive in the highest 602 * available RX mailbox and we need to ensure in-order packet reception. 603 * 604 * To ensure the packets are received in the right order we logically divide 605 * the RX mailboxes into main and buffer mailboxes. Packets are received as per 606 * mailbox priotity (higher to lower) in the main bank and once it is full we 607 * disable further reception into main mailboxes. While the main mailboxes are 608 * processed in NAPI, further packets are received in buffer mailboxes. 609 * 610 * We maintain a RX next mailbox counter to process packets and once all main 611 * mailboxe packets are passed to the upper stack we enable all of them but 612 * continue to process packets received in buffer mailboxes. With each packet 613 * received from buffer mailbox we enable it immediately so as to handle the 614 * overflow from higher mailboxes. 615 */ 616 static int ti_hecc_rx_poll(struct napi_struct *napi, int quota) 617 { 618 struct net_device *ndev = napi->dev; 619 struct ti_hecc_priv *priv = netdev_priv(ndev); 620 u32 num_pkts = 0; 621 u32 mbx_mask; 622 unsigned long pending_pkts, flags; 623 624 if (!netif_running(ndev)) 625 return 0; 626 627 while ((pending_pkts = hecc_read(priv, HECC_CANRMP)) && 628 num_pkts < quota) { 629 mbx_mask = BIT(priv->rx_next); /* next rx mailbox to process */ 630 if (mbx_mask & pending_pkts) { 631 if (ti_hecc_rx_pkt(priv, priv->rx_next) < 0) 632 return num_pkts; 633 ++num_pkts; 634 } else if (priv->rx_next > HECC_RX_BUFFER_MBOX) { 635 break; /* pkt not received yet */ 636 } 637 --priv->rx_next; 638 if (priv->rx_next == HECC_RX_BUFFER_MBOX) { 639 /* enable high bank mailboxes */ 640 spin_lock_irqsave(&priv->mbx_lock, flags); 641 mbx_mask = hecc_read(priv, HECC_CANME); 642 mbx_mask |= HECC_RX_HIGH_MBOX_MASK; 643 hecc_write(priv, HECC_CANME, mbx_mask); 644 spin_unlock_irqrestore(&priv->mbx_lock, flags); 645 } else if (priv->rx_next == HECC_MAX_TX_MBOX - 1) { 646 priv->rx_next = HECC_RX_FIRST_MBOX; 647 break; 648 } 649 } 650 651 /* Enable packet interrupt if all pkts are handled */ 652 if (hecc_read(priv, HECC_CANRMP) == 0) { 653 napi_complete(napi); 654 /* Re-enable RX mailbox interrupts */ 655 mbx_mask = hecc_read(priv, HECC_CANMIM); 656 mbx_mask |= HECC_TX_MBOX_MASK; 657 hecc_write(priv, HECC_CANMIM, mbx_mask); 658 } 659 660 return num_pkts; 661 } 662 663 static int ti_hecc_error(struct net_device *ndev, int int_status, 664 int err_status) 665 { 666 struct ti_hecc_priv *priv = netdev_priv(ndev); 667 struct net_device_stats *stats = &ndev->stats; 668 struct can_frame *cf; 669 struct sk_buff *skb; 670 671 /* propagate the error condition to the can stack */ 672 skb = alloc_can_err_skb(ndev, &cf); 673 if (!skb) { 674 if (printk_ratelimit()) 675 netdev_err(priv->ndev, 676 "ti_hecc_error: alloc_can_err_skb() failed\n"); 677 return -ENOMEM; 678 } 679 680 if (int_status & HECC_CANGIF_WLIF) { /* warning level int */ 681 if ((int_status & HECC_CANGIF_BOIF) == 0) { 682 priv->can.state = CAN_STATE_ERROR_WARNING; 683 ++priv->can.can_stats.error_warning; 684 cf->can_id |= CAN_ERR_CRTL; 685 if (hecc_read(priv, HECC_CANTEC) > 96) 686 cf->data[1] |= CAN_ERR_CRTL_TX_WARNING; 687 if (hecc_read(priv, HECC_CANREC) > 96) 688 cf->data[1] |= CAN_ERR_CRTL_RX_WARNING; 689 } 690 hecc_set_bit(priv, HECC_CANES, HECC_CANES_EW); 691 netdev_dbg(priv->ndev, "Error Warning interrupt\n"); 692 hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR); 693 } 694 695 if (int_status & HECC_CANGIF_EPIF) { /* error passive int */ 696 if ((int_status & HECC_CANGIF_BOIF) == 0) { 697 priv->can.state = CAN_STATE_ERROR_PASSIVE; 698 ++priv->can.can_stats.error_passive; 699 cf->can_id |= CAN_ERR_CRTL; 700 if (hecc_read(priv, HECC_CANTEC) > 127) 701 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 702 if (hecc_read(priv, HECC_CANREC) > 127) 703 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 704 } 705 hecc_set_bit(priv, HECC_CANES, HECC_CANES_EP); 706 netdev_dbg(priv->ndev, "Error passive interrupt\n"); 707 hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR); 708 } 709 710 /* 711 * Need to check busoff condition in error status register too to 712 * ensure warning interrupts don't hog the system 713 */ 714 if ((int_status & HECC_CANGIF_BOIF) || (err_status & HECC_CANES_BO)) { 715 priv->can.state = CAN_STATE_BUS_OFF; 716 cf->can_id |= CAN_ERR_BUSOFF; 717 hecc_set_bit(priv, HECC_CANES, HECC_CANES_BO); 718 hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR); 719 /* Disable all interrupts in bus-off to avoid int hog */ 720 hecc_write(priv, HECC_CANGIM, 0); 721 can_bus_off(ndev); 722 } 723 724 if (err_status & HECC_BUS_ERROR) { 725 ++priv->can.can_stats.bus_error; 726 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT; 727 cf->data[2] |= CAN_ERR_PROT_UNSPEC; 728 if (err_status & HECC_CANES_FE) { 729 hecc_set_bit(priv, HECC_CANES, HECC_CANES_FE); 730 cf->data[2] |= CAN_ERR_PROT_FORM; 731 } 732 if (err_status & HECC_CANES_BE) { 733 hecc_set_bit(priv, HECC_CANES, HECC_CANES_BE); 734 cf->data[2] |= CAN_ERR_PROT_BIT; 735 } 736 if (err_status & HECC_CANES_SE) { 737 hecc_set_bit(priv, HECC_CANES, HECC_CANES_SE); 738 cf->data[2] |= CAN_ERR_PROT_STUFF; 739 } 740 if (err_status & HECC_CANES_CRCE) { 741 hecc_set_bit(priv, HECC_CANES, HECC_CANES_CRCE); 742 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ | 743 CAN_ERR_PROT_LOC_CRC_DEL; 744 } 745 if (err_status & HECC_CANES_ACKE) { 746 hecc_set_bit(priv, HECC_CANES, HECC_CANES_ACKE); 747 cf->data[3] |= CAN_ERR_PROT_LOC_ACK | 748 CAN_ERR_PROT_LOC_ACK_DEL; 749 } 750 } 751 752 netif_rx(skb); 753 stats->rx_packets++; 754 stats->rx_bytes += cf->can_dlc; 755 756 return 0; 757 } 758 759 static irqreturn_t ti_hecc_interrupt(int irq, void *dev_id) 760 { 761 struct net_device *ndev = (struct net_device *)dev_id; 762 struct ti_hecc_priv *priv = netdev_priv(ndev); 763 struct net_device_stats *stats = &ndev->stats; 764 u32 mbxno, mbx_mask, int_status, err_status; 765 unsigned long ack, flags; 766 767 int_status = hecc_read(priv, 768 (priv->int_line) ? HECC_CANGIF1 : HECC_CANGIF0); 769 770 if (!int_status) 771 return IRQ_NONE; 772 773 err_status = hecc_read(priv, HECC_CANES); 774 if (err_status & (HECC_BUS_ERROR | HECC_CANES_BO | 775 HECC_CANES_EP | HECC_CANES_EW)) 776 ti_hecc_error(ndev, int_status, err_status); 777 778 if (int_status & HECC_CANGIF_GMIF) { 779 while (priv->tx_tail - priv->tx_head > 0) { 780 mbxno = get_tx_tail_mb(priv); 781 mbx_mask = BIT(mbxno); 782 if (!(mbx_mask & hecc_read(priv, HECC_CANTA))) 783 break; 784 hecc_clear_bit(priv, HECC_CANMIM, mbx_mask); 785 hecc_write(priv, HECC_CANTA, mbx_mask); 786 spin_lock_irqsave(&priv->mbx_lock, flags); 787 hecc_clear_bit(priv, HECC_CANME, mbx_mask); 788 spin_unlock_irqrestore(&priv->mbx_lock, flags); 789 stats->tx_bytes += hecc_read_mbx(priv, mbxno, 790 HECC_CANMCF) & 0xF; 791 stats->tx_packets++; 792 can_led_event(ndev, CAN_LED_EVENT_TX); 793 can_get_echo_skb(ndev, mbxno); 794 --priv->tx_tail; 795 } 796 797 /* restart queue if wrap-up or if queue stalled on last pkt */ 798 if (((priv->tx_head == priv->tx_tail) && 799 ((priv->tx_head & HECC_TX_MASK) != HECC_TX_MASK)) || 800 (((priv->tx_tail & HECC_TX_MASK) == HECC_TX_MASK) && 801 ((priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK))) 802 netif_wake_queue(ndev); 803 804 /* Disable RX mailbox interrupts and let NAPI reenable them */ 805 if (hecc_read(priv, HECC_CANRMP)) { 806 ack = hecc_read(priv, HECC_CANMIM); 807 ack &= BIT(HECC_MAX_TX_MBOX) - 1; 808 hecc_write(priv, HECC_CANMIM, ack); 809 napi_schedule(&priv->napi); 810 } 811 } 812 813 /* clear all interrupt conditions - read back to avoid spurious ints */ 814 if (priv->int_line) { 815 hecc_write(priv, HECC_CANGIF1, HECC_SET_REG); 816 int_status = hecc_read(priv, HECC_CANGIF1); 817 } else { 818 hecc_write(priv, HECC_CANGIF0, HECC_SET_REG); 819 int_status = hecc_read(priv, HECC_CANGIF0); 820 } 821 822 return IRQ_HANDLED; 823 } 824 825 static int ti_hecc_open(struct net_device *ndev) 826 { 827 struct ti_hecc_priv *priv = netdev_priv(ndev); 828 int err; 829 830 err = request_irq(ndev->irq, ti_hecc_interrupt, IRQF_SHARED, 831 ndev->name, ndev); 832 if (err) { 833 netdev_err(ndev, "error requesting interrupt\n"); 834 return err; 835 } 836 837 ti_hecc_transceiver_switch(priv, 1); 838 839 /* Open common can device */ 840 err = open_candev(ndev); 841 if (err) { 842 netdev_err(ndev, "open_candev() failed %d\n", err); 843 ti_hecc_transceiver_switch(priv, 0); 844 free_irq(ndev->irq, ndev); 845 return err; 846 } 847 848 can_led_event(ndev, CAN_LED_EVENT_OPEN); 849 850 ti_hecc_start(ndev); 851 napi_enable(&priv->napi); 852 netif_start_queue(ndev); 853 854 return 0; 855 } 856 857 static int ti_hecc_close(struct net_device *ndev) 858 { 859 struct ti_hecc_priv *priv = netdev_priv(ndev); 860 861 netif_stop_queue(ndev); 862 napi_disable(&priv->napi); 863 ti_hecc_stop(ndev); 864 free_irq(ndev->irq, ndev); 865 close_candev(ndev); 866 ti_hecc_transceiver_switch(priv, 0); 867 868 can_led_event(ndev, CAN_LED_EVENT_STOP); 869 870 return 0; 871 } 872 873 static const struct net_device_ops ti_hecc_netdev_ops = { 874 .ndo_open = ti_hecc_open, 875 .ndo_stop = ti_hecc_close, 876 .ndo_start_xmit = ti_hecc_xmit, 877 }; 878 879 static int ti_hecc_probe(struct platform_device *pdev) 880 { 881 struct net_device *ndev = (struct net_device *)0; 882 struct ti_hecc_priv *priv; 883 struct ti_hecc_platform_data *pdata; 884 struct resource *mem, *irq; 885 void __iomem *addr; 886 int err = -ENODEV; 887 888 pdata = dev_get_platdata(&pdev->dev); 889 if (!pdata) { 890 dev_err(&pdev->dev, "No platform data\n"); 891 goto probe_exit; 892 } 893 894 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 895 if (!mem) { 896 dev_err(&pdev->dev, "No mem resources\n"); 897 goto probe_exit; 898 } 899 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 900 if (!irq) { 901 dev_err(&pdev->dev, "No irq resource\n"); 902 goto probe_exit; 903 } 904 if (!request_mem_region(mem->start, resource_size(mem), pdev->name)) { 905 dev_err(&pdev->dev, "HECC region already claimed\n"); 906 err = -EBUSY; 907 goto probe_exit; 908 } 909 addr = ioremap(mem->start, resource_size(mem)); 910 if (!addr) { 911 dev_err(&pdev->dev, "ioremap failed\n"); 912 err = -ENOMEM; 913 goto probe_exit_free_region; 914 } 915 916 ndev = alloc_candev(sizeof(struct ti_hecc_priv), HECC_MAX_TX_MBOX); 917 if (!ndev) { 918 dev_err(&pdev->dev, "alloc_candev failed\n"); 919 err = -ENOMEM; 920 goto probe_exit_iounmap; 921 } 922 923 priv = netdev_priv(ndev); 924 priv->ndev = ndev; 925 priv->base = addr; 926 priv->scc_ram_offset = pdata->scc_ram_offset; 927 priv->hecc_ram_offset = pdata->hecc_ram_offset; 928 priv->mbx_offset = pdata->mbx_offset; 929 priv->int_line = pdata->int_line; 930 priv->transceiver_switch = pdata->transceiver_switch; 931 932 priv->can.bittiming_const = &ti_hecc_bittiming_const; 933 priv->can.do_set_mode = ti_hecc_do_set_mode; 934 priv->can.do_get_berr_counter = ti_hecc_get_berr_counter; 935 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES; 936 937 spin_lock_init(&priv->mbx_lock); 938 ndev->irq = irq->start; 939 ndev->flags |= IFF_ECHO; 940 platform_set_drvdata(pdev, ndev); 941 SET_NETDEV_DEV(ndev, &pdev->dev); 942 ndev->netdev_ops = &ti_hecc_netdev_ops; 943 944 priv->clk = clk_get(&pdev->dev, "hecc_ck"); 945 if (IS_ERR(priv->clk)) { 946 dev_err(&pdev->dev, "No clock available\n"); 947 err = PTR_ERR(priv->clk); 948 priv->clk = NULL; 949 goto probe_exit_candev; 950 } 951 priv->can.clock.freq = clk_get_rate(priv->clk); 952 netif_napi_add(ndev, &priv->napi, ti_hecc_rx_poll, 953 HECC_DEF_NAPI_WEIGHT); 954 955 clk_enable(priv->clk); 956 err = register_candev(ndev); 957 if (err) { 958 dev_err(&pdev->dev, "register_candev() failed\n"); 959 goto probe_exit_clk; 960 } 961 962 devm_can_led_init(ndev); 963 964 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%u)\n", 965 priv->base, (u32) ndev->irq); 966 967 return 0; 968 969 probe_exit_clk: 970 clk_put(priv->clk); 971 probe_exit_candev: 972 free_candev(ndev); 973 probe_exit_iounmap: 974 iounmap(addr); 975 probe_exit_free_region: 976 release_mem_region(mem->start, resource_size(mem)); 977 probe_exit: 978 return err; 979 } 980 981 static int ti_hecc_remove(struct platform_device *pdev) 982 { 983 struct resource *res; 984 struct net_device *ndev = platform_get_drvdata(pdev); 985 struct ti_hecc_priv *priv = netdev_priv(ndev); 986 987 unregister_candev(ndev); 988 clk_disable(priv->clk); 989 clk_put(priv->clk); 990 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 991 iounmap(priv->base); 992 release_mem_region(res->start, resource_size(res)); 993 free_candev(ndev); 994 995 return 0; 996 } 997 998 999 #ifdef CONFIG_PM 1000 static int ti_hecc_suspend(struct platform_device *pdev, pm_message_t state) 1001 { 1002 struct net_device *dev = platform_get_drvdata(pdev); 1003 struct ti_hecc_priv *priv = netdev_priv(dev); 1004 1005 if (netif_running(dev)) { 1006 netif_stop_queue(dev); 1007 netif_device_detach(dev); 1008 } 1009 1010 hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_PDR); 1011 priv->can.state = CAN_STATE_SLEEPING; 1012 1013 clk_disable(priv->clk); 1014 1015 return 0; 1016 } 1017 1018 static int ti_hecc_resume(struct platform_device *pdev) 1019 { 1020 struct net_device *dev = platform_get_drvdata(pdev); 1021 struct ti_hecc_priv *priv = netdev_priv(dev); 1022 1023 clk_enable(priv->clk); 1024 1025 hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_PDR); 1026 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1027 1028 if (netif_running(dev)) { 1029 netif_device_attach(dev); 1030 netif_start_queue(dev); 1031 } 1032 1033 return 0; 1034 } 1035 #else 1036 #define ti_hecc_suspend NULL 1037 #define ti_hecc_resume NULL 1038 #endif 1039 1040 /* TI HECC netdevice driver: platform driver structure */ 1041 static struct platform_driver ti_hecc_driver = { 1042 .driver = { 1043 .name = DRV_NAME, 1044 .owner = THIS_MODULE, 1045 }, 1046 .probe = ti_hecc_probe, 1047 .remove = ti_hecc_remove, 1048 .suspend = ti_hecc_suspend, 1049 .resume = ti_hecc_resume, 1050 }; 1051 1052 module_platform_driver(ti_hecc_driver); 1053 1054 MODULE_AUTHOR("Anant Gole <anantgole@ti.com>"); 1055 MODULE_LICENSE("GPL v2"); 1056 MODULE_DESCRIPTION(DRV_DESC); 1057 MODULE_ALIAS("platform:" DRV_NAME); 1058