1 /* 2 * TI HECC (CAN) device driver 3 * 4 * This driver supports TI's HECC (High End CAN Controller module) and the 5 * specs for the same is available at <http://www.ti.com> 6 * 7 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ 8 * Copyright (C) 2019 Jeroen Hofstee <jhofstee@victronenergy.com> 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation version 2. 13 * 14 * This program is distributed as is WITHOUT ANY WARRANTY of any 15 * kind, whether express or implied; without even the implied warranty 16 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 */ 20 21 #include <linux/module.h> 22 #include <linux/kernel.h> 23 #include <linux/types.h> 24 #include <linux/interrupt.h> 25 #include <linux/errno.h> 26 #include <linux/netdevice.h> 27 #include <linux/skbuff.h> 28 #include <linux/platform_device.h> 29 #include <linux/clk.h> 30 #include <linux/io.h> 31 #include <linux/of.h> 32 #include <linux/of_device.h> 33 #include <linux/regulator/consumer.h> 34 35 #include <linux/can/dev.h> 36 #include <linux/can/error.h> 37 #include <linux/can/led.h> 38 #include <linux/can/rx-offload.h> 39 40 #define DRV_NAME "ti_hecc" 41 #define HECC_MODULE_VERSION "0.7" 42 MODULE_VERSION(HECC_MODULE_VERSION); 43 #define DRV_DESC "TI High End CAN Controller Driver " HECC_MODULE_VERSION 44 45 /* TX / RX Mailbox Configuration */ 46 #define HECC_MAX_MAILBOXES 32 /* hardware mailboxes - do not change */ 47 #define MAX_TX_PRIO 0x3F /* hardware value - do not change */ 48 49 /* 50 * Important Note: TX mailbox configuration 51 * TX mailboxes should be restricted to the number of SKB buffers to avoid 52 * maintaining SKB buffers separately. TX mailboxes should be a power of 2 53 * for the mailbox logic to work. Top mailbox numbers are reserved for RX 54 * and lower mailboxes for TX. 55 * 56 * HECC_MAX_TX_MBOX HECC_MB_TX_SHIFT 57 * 4 (default) 2 58 * 8 3 59 * 16 4 60 */ 61 #define HECC_MB_TX_SHIFT 2 /* as per table above */ 62 #define HECC_MAX_TX_MBOX BIT(HECC_MB_TX_SHIFT) 63 64 #define HECC_TX_PRIO_SHIFT (HECC_MB_TX_SHIFT) 65 #define HECC_TX_PRIO_MASK (MAX_TX_PRIO << HECC_MB_TX_SHIFT) 66 #define HECC_TX_MB_MASK (HECC_MAX_TX_MBOX - 1) 67 #define HECC_TX_MASK ((HECC_MAX_TX_MBOX - 1) | HECC_TX_PRIO_MASK) 68 69 /* RX mailbox configuration 70 * 71 * The remaining mailboxes are used for reception and are delivered 72 * based on their timestamp, to avoid a hardware race when CANME is 73 * changed while CAN-bus traffic is being received. 74 */ 75 #define HECC_MAX_RX_MBOX (HECC_MAX_MAILBOXES - HECC_MAX_TX_MBOX) 76 #define HECC_RX_FIRST_MBOX (HECC_MAX_MAILBOXES - 1) 77 78 /* TI HECC module registers */ 79 #define HECC_CANME 0x0 /* Mailbox enable */ 80 #define HECC_CANMD 0x4 /* Mailbox direction */ 81 #define HECC_CANTRS 0x8 /* Transmit request set */ 82 #define HECC_CANTRR 0xC /* Transmit request */ 83 #define HECC_CANTA 0x10 /* Transmission acknowledge */ 84 #define HECC_CANAA 0x14 /* Abort acknowledge */ 85 #define HECC_CANRMP 0x18 /* Receive message pending */ 86 #define HECC_CANRML 0x1C /* Remote message lost */ 87 #define HECC_CANRFP 0x20 /* Remote frame pending */ 88 #define HECC_CANGAM 0x24 /* SECC only:Global acceptance mask */ 89 #define HECC_CANMC 0x28 /* Master control */ 90 #define HECC_CANBTC 0x2C /* Bit timing configuration */ 91 #define HECC_CANES 0x30 /* Error and status */ 92 #define HECC_CANTEC 0x34 /* Transmit error counter */ 93 #define HECC_CANREC 0x38 /* Receive error counter */ 94 #define HECC_CANGIF0 0x3C /* Global interrupt flag 0 */ 95 #define HECC_CANGIM 0x40 /* Global interrupt mask */ 96 #define HECC_CANGIF1 0x44 /* Global interrupt flag 1 */ 97 #define HECC_CANMIM 0x48 /* Mailbox interrupt mask */ 98 #define HECC_CANMIL 0x4C /* Mailbox interrupt level */ 99 #define HECC_CANOPC 0x50 /* Overwrite protection control */ 100 #define HECC_CANTIOC 0x54 /* Transmit I/O control */ 101 #define HECC_CANRIOC 0x58 /* Receive I/O control */ 102 #define HECC_CANLNT 0x5C /* HECC only: Local network time */ 103 #define HECC_CANTOC 0x60 /* HECC only: Time-out control */ 104 #define HECC_CANTOS 0x64 /* HECC only: Time-out status */ 105 #define HECC_CANTIOCE 0x68 /* SCC only:Enhanced TX I/O control */ 106 #define HECC_CANRIOCE 0x6C /* SCC only:Enhanced RX I/O control */ 107 108 /* TI HECC RAM registers */ 109 #define HECC_CANMOTS 0x80 /* Message object time stamp */ 110 111 /* Mailbox registers */ 112 #define HECC_CANMID 0x0 113 #define HECC_CANMCF 0x4 114 #define HECC_CANMDL 0x8 115 #define HECC_CANMDH 0xC 116 117 #define HECC_SET_REG 0xFFFFFFFF 118 #define HECC_CANID_MASK 0x3FF /* 18 bits mask for extended id's */ 119 #define HECC_CCE_WAIT_COUNT 100 /* Wait for ~1 sec for CCE bit */ 120 121 #define HECC_CANMC_SCM BIT(13) /* SCC compat mode */ 122 #define HECC_CANMC_CCR BIT(12) /* Change config request */ 123 #define HECC_CANMC_PDR BIT(11) /* Local Power down - for sleep mode */ 124 #define HECC_CANMC_ABO BIT(7) /* Auto Bus On */ 125 #define HECC_CANMC_STM BIT(6) /* Self test mode - loopback */ 126 #define HECC_CANMC_SRES BIT(5) /* Software reset */ 127 128 #define HECC_CANTIOC_EN BIT(3) /* Enable CAN TX I/O pin */ 129 #define HECC_CANRIOC_EN BIT(3) /* Enable CAN RX I/O pin */ 130 131 #define HECC_CANMID_IDE BIT(31) /* Extended frame format */ 132 #define HECC_CANMID_AME BIT(30) /* Acceptance mask enable */ 133 #define HECC_CANMID_AAM BIT(29) /* Auto answer mode */ 134 135 #define HECC_CANES_FE BIT(24) /* form error */ 136 #define HECC_CANES_BE BIT(23) /* bit error */ 137 #define HECC_CANES_SA1 BIT(22) /* stuck at dominant error */ 138 #define HECC_CANES_CRCE BIT(21) /* CRC error */ 139 #define HECC_CANES_SE BIT(20) /* stuff bit error */ 140 #define HECC_CANES_ACKE BIT(19) /* ack error */ 141 #define HECC_CANES_BO BIT(18) /* Bus off status */ 142 #define HECC_CANES_EP BIT(17) /* Error passive status */ 143 #define HECC_CANES_EW BIT(16) /* Error warning status */ 144 #define HECC_CANES_SMA BIT(5) /* suspend mode ack */ 145 #define HECC_CANES_CCE BIT(4) /* Change config enabled */ 146 #define HECC_CANES_PDA BIT(3) /* Power down mode ack */ 147 148 #define HECC_CANBTC_SAM BIT(7) /* sample points */ 149 150 #define HECC_BUS_ERROR (HECC_CANES_FE | HECC_CANES_BE |\ 151 HECC_CANES_CRCE | HECC_CANES_SE |\ 152 HECC_CANES_ACKE) 153 154 #define HECC_CANMCF_RTR BIT(4) /* Remote transmit request */ 155 156 #define HECC_CANGIF_MAIF BIT(17) /* Message alarm interrupt */ 157 #define HECC_CANGIF_TCOIF BIT(16) /* Timer counter overflow int */ 158 #define HECC_CANGIF_GMIF BIT(15) /* Global mailbox interrupt */ 159 #define HECC_CANGIF_AAIF BIT(14) /* Abort ack interrupt */ 160 #define HECC_CANGIF_WDIF BIT(13) /* Write denied interrupt */ 161 #define HECC_CANGIF_WUIF BIT(12) /* Wake up interrupt */ 162 #define HECC_CANGIF_RMLIF BIT(11) /* Receive message lost interrupt */ 163 #define HECC_CANGIF_BOIF BIT(10) /* Bus off interrupt */ 164 #define HECC_CANGIF_EPIF BIT(9) /* Error passive interrupt */ 165 #define HECC_CANGIF_WLIF BIT(8) /* Warning level interrupt */ 166 #define HECC_CANGIF_MBOX_MASK 0x1F /* Mailbox number mask */ 167 #define HECC_CANGIM_I1EN BIT(1) /* Int line 1 enable */ 168 #define HECC_CANGIM_I0EN BIT(0) /* Int line 0 enable */ 169 #define HECC_CANGIM_DEF_MASK 0x700 /* only busoff/warning/passive */ 170 #define HECC_CANGIM_SIL BIT(2) /* system interrupts to int line 1 */ 171 172 /* CAN Bittiming constants as per HECC specs */ 173 static const struct can_bittiming_const ti_hecc_bittiming_const = { 174 .name = DRV_NAME, 175 .tseg1_min = 1, 176 .tseg1_max = 16, 177 .tseg2_min = 1, 178 .tseg2_max = 8, 179 .sjw_max = 4, 180 .brp_min = 1, 181 .brp_max = 256, 182 .brp_inc = 1, 183 }; 184 185 struct ti_hecc_priv { 186 struct can_priv can; /* MUST be first member/field */ 187 struct can_rx_offload offload; 188 struct net_device *ndev; 189 struct clk *clk; 190 void __iomem *base; 191 void __iomem *hecc_ram; 192 void __iomem *mbx; 193 bool use_hecc1int; 194 spinlock_t mbx_lock; /* CANME register needs protection */ 195 u32 tx_head; 196 u32 tx_tail; 197 struct regulator *reg_xceiver; 198 }; 199 200 static inline int get_tx_head_mb(struct ti_hecc_priv *priv) 201 { 202 return priv->tx_head & HECC_TX_MB_MASK; 203 } 204 205 static inline int get_tx_tail_mb(struct ti_hecc_priv *priv) 206 { 207 return priv->tx_tail & HECC_TX_MB_MASK; 208 } 209 210 static inline int get_tx_head_prio(struct ti_hecc_priv *priv) 211 { 212 return (priv->tx_head >> HECC_TX_PRIO_SHIFT) & MAX_TX_PRIO; 213 } 214 215 static inline void hecc_write_lam(struct ti_hecc_priv *priv, u32 mbxno, u32 val) 216 { 217 __raw_writel(val, priv->hecc_ram + mbxno * 4); 218 } 219 220 static inline u32 hecc_read_stamp(struct ti_hecc_priv *priv, u32 mbxno) 221 { 222 return __raw_readl(priv->hecc_ram + HECC_CANMOTS + mbxno * 4); 223 } 224 225 static inline void hecc_write_mbx(struct ti_hecc_priv *priv, u32 mbxno, 226 u32 reg, u32 val) 227 { 228 __raw_writel(val, priv->mbx + mbxno * 0x10 + reg); 229 } 230 231 static inline u32 hecc_read_mbx(struct ti_hecc_priv *priv, u32 mbxno, u32 reg) 232 { 233 return __raw_readl(priv->mbx + mbxno * 0x10 + reg); 234 } 235 236 static inline void hecc_write(struct ti_hecc_priv *priv, u32 reg, u32 val) 237 { 238 __raw_writel(val, priv->base + reg); 239 } 240 241 static inline u32 hecc_read(struct ti_hecc_priv *priv, int reg) 242 { 243 return __raw_readl(priv->base + reg); 244 } 245 246 static inline void hecc_set_bit(struct ti_hecc_priv *priv, int reg, 247 u32 bit_mask) 248 { 249 hecc_write(priv, reg, hecc_read(priv, reg) | bit_mask); 250 } 251 252 static inline void hecc_clear_bit(struct ti_hecc_priv *priv, int reg, 253 u32 bit_mask) 254 { 255 hecc_write(priv, reg, hecc_read(priv, reg) & ~bit_mask); 256 } 257 258 static inline u32 hecc_get_bit(struct ti_hecc_priv *priv, int reg, u32 bit_mask) 259 { 260 return (hecc_read(priv, reg) & bit_mask) ? 1 : 0; 261 } 262 263 static int ti_hecc_set_btc(struct ti_hecc_priv *priv) 264 { 265 struct can_bittiming *bit_timing = &priv->can.bittiming; 266 u32 can_btc; 267 268 can_btc = (bit_timing->phase_seg2 - 1) & 0x7; 269 can_btc |= ((bit_timing->phase_seg1 + bit_timing->prop_seg - 1) 270 & 0xF) << 3; 271 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) { 272 if (bit_timing->brp > 4) 273 can_btc |= HECC_CANBTC_SAM; 274 else 275 netdev_warn(priv->ndev, "WARN: Triple" 276 "sampling not set due to h/w limitations"); 277 } 278 can_btc |= ((bit_timing->sjw - 1) & 0x3) << 8; 279 can_btc |= ((bit_timing->brp - 1) & 0xFF) << 16; 280 281 /* ERM being set to 0 by default meaning resync at falling edge */ 282 283 hecc_write(priv, HECC_CANBTC, can_btc); 284 netdev_info(priv->ndev, "setting CANBTC=%#x\n", can_btc); 285 286 return 0; 287 } 288 289 static int ti_hecc_transceiver_switch(const struct ti_hecc_priv *priv, 290 int on) 291 { 292 if (!priv->reg_xceiver) 293 return 0; 294 295 if (on) 296 return regulator_enable(priv->reg_xceiver); 297 else 298 return regulator_disable(priv->reg_xceiver); 299 } 300 301 static void ti_hecc_reset(struct net_device *ndev) 302 { 303 u32 cnt; 304 struct ti_hecc_priv *priv = netdev_priv(ndev); 305 306 netdev_dbg(ndev, "resetting hecc ...\n"); 307 hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_SRES); 308 309 /* Set change control request and wait till enabled */ 310 hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_CCR); 311 312 /* 313 * INFO: It has been observed that at times CCE bit may not be 314 * set and hw seems to be ok even if this bit is not set so 315 * timing out with a timing of 1ms to respect the specs 316 */ 317 cnt = HECC_CCE_WAIT_COUNT; 318 while (!hecc_get_bit(priv, HECC_CANES, HECC_CANES_CCE) && cnt != 0) { 319 --cnt; 320 udelay(10); 321 } 322 323 /* 324 * Note: On HECC, BTC can be programmed only in initialization mode, so 325 * it is expected that the can bittiming parameters are set via ip 326 * utility before the device is opened 327 */ 328 ti_hecc_set_btc(priv); 329 330 /* Clear CCR (and CANMC register) and wait for CCE = 0 enable */ 331 hecc_write(priv, HECC_CANMC, 0); 332 333 /* 334 * INFO: CAN net stack handles bus off and hence disabling auto-bus-on 335 * hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_ABO); 336 */ 337 338 /* 339 * INFO: It has been observed that at times CCE bit may not be 340 * set and hw seems to be ok even if this bit is not set so 341 */ 342 cnt = HECC_CCE_WAIT_COUNT; 343 while (hecc_get_bit(priv, HECC_CANES, HECC_CANES_CCE) && cnt != 0) { 344 --cnt; 345 udelay(10); 346 } 347 348 /* Enable TX and RX I/O Control pins */ 349 hecc_write(priv, HECC_CANTIOC, HECC_CANTIOC_EN); 350 hecc_write(priv, HECC_CANRIOC, HECC_CANRIOC_EN); 351 352 /* Clear registers for clean operation */ 353 hecc_write(priv, HECC_CANTA, HECC_SET_REG); 354 hecc_write(priv, HECC_CANRMP, HECC_SET_REG); 355 hecc_write(priv, HECC_CANGIF0, HECC_SET_REG); 356 hecc_write(priv, HECC_CANGIF1, HECC_SET_REG); 357 hecc_write(priv, HECC_CANME, 0); 358 hecc_write(priv, HECC_CANMD, 0); 359 360 /* SCC compat mode NOT supported (and not needed too) */ 361 hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_SCM); 362 } 363 364 static void ti_hecc_start(struct net_device *ndev) 365 { 366 struct ti_hecc_priv *priv = netdev_priv(ndev); 367 u32 cnt, mbxno, mbx_mask; 368 369 /* put HECC in initialization mode and set btc */ 370 ti_hecc_reset(ndev); 371 372 priv->tx_head = priv->tx_tail = HECC_TX_MASK; 373 374 /* Enable local and global acceptance mask registers */ 375 hecc_write(priv, HECC_CANGAM, HECC_SET_REG); 376 377 /* Prepare configured mailboxes to receive messages */ 378 for (cnt = 0; cnt < HECC_MAX_RX_MBOX; cnt++) { 379 mbxno = HECC_MAX_MAILBOXES - 1 - cnt; 380 mbx_mask = BIT(mbxno); 381 hecc_clear_bit(priv, HECC_CANME, mbx_mask); 382 hecc_write_mbx(priv, mbxno, HECC_CANMID, HECC_CANMID_AME); 383 hecc_write_lam(priv, mbxno, HECC_SET_REG); 384 hecc_set_bit(priv, HECC_CANMD, mbx_mask); 385 hecc_set_bit(priv, HECC_CANME, mbx_mask); 386 hecc_set_bit(priv, HECC_CANMIM, mbx_mask); 387 } 388 389 /* Prevent message over-write & Enable interrupts */ 390 hecc_write(priv, HECC_CANOPC, HECC_SET_REG); 391 if (priv->use_hecc1int) { 392 hecc_write(priv, HECC_CANMIL, HECC_SET_REG); 393 hecc_write(priv, HECC_CANGIM, HECC_CANGIM_DEF_MASK | 394 HECC_CANGIM_I1EN | HECC_CANGIM_SIL); 395 } else { 396 hecc_write(priv, HECC_CANMIL, 0); 397 hecc_write(priv, HECC_CANGIM, 398 HECC_CANGIM_DEF_MASK | HECC_CANGIM_I0EN); 399 } 400 priv->can.state = CAN_STATE_ERROR_ACTIVE; 401 } 402 403 static void ti_hecc_stop(struct net_device *ndev) 404 { 405 struct ti_hecc_priv *priv = netdev_priv(ndev); 406 407 /* Disable interrupts and disable mailboxes */ 408 hecc_write(priv, HECC_CANGIM, 0); 409 hecc_write(priv, HECC_CANMIM, 0); 410 hecc_write(priv, HECC_CANME, 0); 411 priv->can.state = CAN_STATE_STOPPED; 412 } 413 414 static int ti_hecc_do_set_mode(struct net_device *ndev, enum can_mode mode) 415 { 416 int ret = 0; 417 418 switch (mode) { 419 case CAN_MODE_START: 420 ti_hecc_start(ndev); 421 netif_wake_queue(ndev); 422 break; 423 default: 424 ret = -EOPNOTSUPP; 425 break; 426 } 427 428 return ret; 429 } 430 431 static int ti_hecc_get_berr_counter(const struct net_device *ndev, 432 struct can_berr_counter *bec) 433 { 434 struct ti_hecc_priv *priv = netdev_priv(ndev); 435 436 bec->txerr = hecc_read(priv, HECC_CANTEC); 437 bec->rxerr = hecc_read(priv, HECC_CANREC); 438 439 return 0; 440 } 441 442 /* 443 * ti_hecc_xmit: HECC Transmit 444 * 445 * The transmit mailboxes start from 0 to HECC_MAX_TX_MBOX. In HECC the 446 * priority of the mailbox for tranmission is dependent upon priority setting 447 * field in mailbox registers. The mailbox with highest value in priority field 448 * is transmitted first. Only when two mailboxes have the same value in 449 * priority field the highest numbered mailbox is transmitted first. 450 * 451 * To utilize the HECC priority feature as described above we start with the 452 * highest numbered mailbox with highest priority level and move on to the next 453 * mailbox with the same priority level and so on. Once we loop through all the 454 * transmit mailboxes we choose the next priority level (lower) and so on 455 * until we reach the lowest priority level on the lowest numbered mailbox 456 * when we stop transmission until all mailboxes are transmitted and then 457 * restart at highest numbered mailbox with highest priority. 458 * 459 * Two counters (head and tail) are used to track the next mailbox to transmit 460 * and to track the echo buffer for already transmitted mailbox. The queue 461 * is stopped when all the mailboxes are busy or when there is a priority 462 * value roll-over happens. 463 */ 464 static netdev_tx_t ti_hecc_xmit(struct sk_buff *skb, struct net_device *ndev) 465 { 466 struct ti_hecc_priv *priv = netdev_priv(ndev); 467 struct can_frame *cf = (struct can_frame *)skb->data; 468 u32 mbxno, mbx_mask, data; 469 unsigned long flags; 470 471 if (can_dropped_invalid_skb(ndev, skb)) 472 return NETDEV_TX_OK; 473 474 mbxno = get_tx_head_mb(priv); 475 mbx_mask = BIT(mbxno); 476 spin_lock_irqsave(&priv->mbx_lock, flags); 477 if (unlikely(hecc_read(priv, HECC_CANME) & mbx_mask)) { 478 spin_unlock_irqrestore(&priv->mbx_lock, flags); 479 netif_stop_queue(ndev); 480 netdev_err(priv->ndev, 481 "BUG: TX mbx not ready tx_head=%08X, tx_tail=%08X\n", 482 priv->tx_head, priv->tx_tail); 483 return NETDEV_TX_BUSY; 484 } 485 spin_unlock_irqrestore(&priv->mbx_lock, flags); 486 487 /* Prepare mailbox for transmission */ 488 data = cf->can_dlc | (get_tx_head_prio(priv) << 8); 489 if (cf->can_id & CAN_RTR_FLAG) /* Remote transmission request */ 490 data |= HECC_CANMCF_RTR; 491 hecc_write_mbx(priv, mbxno, HECC_CANMCF, data); 492 493 if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */ 494 data = (cf->can_id & CAN_EFF_MASK) | HECC_CANMID_IDE; 495 else /* Standard frame format */ 496 data = (cf->can_id & CAN_SFF_MASK) << 18; 497 hecc_write_mbx(priv, mbxno, HECC_CANMID, data); 498 hecc_write_mbx(priv, mbxno, HECC_CANMDL, 499 be32_to_cpu(*(__be32 *)(cf->data))); 500 if (cf->can_dlc > 4) 501 hecc_write_mbx(priv, mbxno, HECC_CANMDH, 502 be32_to_cpu(*(__be32 *)(cf->data + 4))); 503 else 504 *(u32 *)(cf->data + 4) = 0; 505 can_put_echo_skb(skb, ndev, mbxno); 506 507 spin_lock_irqsave(&priv->mbx_lock, flags); 508 --priv->tx_head; 509 if ((hecc_read(priv, HECC_CANME) & BIT(get_tx_head_mb(priv))) || 510 (priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK) { 511 netif_stop_queue(ndev); 512 } 513 hecc_set_bit(priv, HECC_CANME, mbx_mask); 514 spin_unlock_irqrestore(&priv->mbx_lock, flags); 515 516 hecc_clear_bit(priv, HECC_CANMD, mbx_mask); 517 hecc_set_bit(priv, HECC_CANMIM, mbx_mask); 518 hecc_write(priv, HECC_CANTRS, mbx_mask); 519 520 return NETDEV_TX_OK; 521 } 522 523 static inline struct ti_hecc_priv *rx_offload_to_priv(struct can_rx_offload *offload) 524 { 525 return container_of(offload, struct ti_hecc_priv, offload); 526 } 527 528 static unsigned int ti_hecc_mailbox_read(struct can_rx_offload *offload, 529 struct can_frame *cf, 530 u32 *timestamp, unsigned int mbxno) 531 { 532 struct ti_hecc_priv *priv = rx_offload_to_priv(offload); 533 u32 data, mbx_mask; 534 535 mbx_mask = BIT(mbxno); 536 data = hecc_read_mbx(priv, mbxno, HECC_CANMID); 537 if (data & HECC_CANMID_IDE) 538 cf->can_id = (data & CAN_EFF_MASK) | CAN_EFF_FLAG; 539 else 540 cf->can_id = (data >> 18) & CAN_SFF_MASK; 541 data = hecc_read_mbx(priv, mbxno, HECC_CANMCF); 542 if (data & HECC_CANMCF_RTR) 543 cf->can_id |= CAN_RTR_FLAG; 544 cf->can_dlc = get_can_dlc(data & 0xF); 545 data = hecc_read_mbx(priv, mbxno, HECC_CANMDL); 546 *(__be32 *)(cf->data) = cpu_to_be32(data); 547 if (cf->can_dlc > 4) { 548 data = hecc_read_mbx(priv, mbxno, HECC_CANMDH); 549 *(__be32 *)(cf->data + 4) = cpu_to_be32(data); 550 } 551 552 *timestamp = hecc_read_stamp(priv, mbxno); 553 554 return 1; 555 } 556 557 static int ti_hecc_error(struct net_device *ndev, int int_status, 558 int err_status) 559 { 560 struct ti_hecc_priv *priv = netdev_priv(ndev); 561 struct can_frame *cf; 562 struct sk_buff *skb; 563 u32 timestamp; 564 565 /* propagate the error condition to the can stack */ 566 skb = alloc_can_err_skb(ndev, &cf); 567 if (!skb) { 568 if (printk_ratelimit()) 569 netdev_err(priv->ndev, 570 "ti_hecc_error: alloc_can_err_skb() failed\n"); 571 return -ENOMEM; 572 } 573 574 if (int_status & HECC_CANGIF_WLIF) { /* warning level int */ 575 if ((int_status & HECC_CANGIF_BOIF) == 0) { 576 priv->can.state = CAN_STATE_ERROR_WARNING; 577 ++priv->can.can_stats.error_warning; 578 cf->can_id |= CAN_ERR_CRTL; 579 if (hecc_read(priv, HECC_CANTEC) > 96) 580 cf->data[1] |= CAN_ERR_CRTL_TX_WARNING; 581 if (hecc_read(priv, HECC_CANREC) > 96) 582 cf->data[1] |= CAN_ERR_CRTL_RX_WARNING; 583 } 584 hecc_set_bit(priv, HECC_CANES, HECC_CANES_EW); 585 netdev_dbg(priv->ndev, "Error Warning interrupt\n"); 586 hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR); 587 } 588 589 if (int_status & HECC_CANGIF_EPIF) { /* error passive int */ 590 if ((int_status & HECC_CANGIF_BOIF) == 0) { 591 priv->can.state = CAN_STATE_ERROR_PASSIVE; 592 ++priv->can.can_stats.error_passive; 593 cf->can_id |= CAN_ERR_CRTL; 594 if (hecc_read(priv, HECC_CANTEC) > 127) 595 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 596 if (hecc_read(priv, HECC_CANREC) > 127) 597 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 598 } 599 hecc_set_bit(priv, HECC_CANES, HECC_CANES_EP); 600 netdev_dbg(priv->ndev, "Error passive interrupt\n"); 601 hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR); 602 } 603 604 /* 605 * Need to check busoff condition in error status register too to 606 * ensure warning interrupts don't hog the system 607 */ 608 if ((int_status & HECC_CANGIF_BOIF) || (err_status & HECC_CANES_BO)) { 609 priv->can.state = CAN_STATE_BUS_OFF; 610 cf->can_id |= CAN_ERR_BUSOFF; 611 hecc_set_bit(priv, HECC_CANES, HECC_CANES_BO); 612 hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR); 613 /* Disable all interrupts in bus-off to avoid int hog */ 614 hecc_write(priv, HECC_CANGIM, 0); 615 ++priv->can.can_stats.bus_off; 616 can_bus_off(ndev); 617 } 618 619 if (err_status & HECC_BUS_ERROR) { 620 ++priv->can.can_stats.bus_error; 621 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT; 622 if (err_status & HECC_CANES_FE) { 623 hecc_set_bit(priv, HECC_CANES, HECC_CANES_FE); 624 cf->data[2] |= CAN_ERR_PROT_FORM; 625 } 626 if (err_status & HECC_CANES_BE) { 627 hecc_set_bit(priv, HECC_CANES, HECC_CANES_BE); 628 cf->data[2] |= CAN_ERR_PROT_BIT; 629 } 630 if (err_status & HECC_CANES_SE) { 631 hecc_set_bit(priv, HECC_CANES, HECC_CANES_SE); 632 cf->data[2] |= CAN_ERR_PROT_STUFF; 633 } 634 if (err_status & HECC_CANES_CRCE) { 635 hecc_set_bit(priv, HECC_CANES, HECC_CANES_CRCE); 636 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; 637 } 638 if (err_status & HECC_CANES_ACKE) { 639 hecc_set_bit(priv, HECC_CANES, HECC_CANES_ACKE); 640 cf->data[3] = CAN_ERR_PROT_LOC_ACK; 641 } 642 } 643 644 timestamp = hecc_read(priv, HECC_CANLNT); 645 can_rx_offload_queue_sorted(&priv->offload, skb, timestamp); 646 647 return 0; 648 } 649 650 static irqreturn_t ti_hecc_interrupt(int irq, void *dev_id) 651 { 652 struct net_device *ndev = (struct net_device *)dev_id; 653 struct ti_hecc_priv *priv = netdev_priv(ndev); 654 struct net_device_stats *stats = &ndev->stats; 655 u32 mbxno, mbx_mask, int_status, err_status, stamp; 656 unsigned long flags, rx_pending; 657 658 int_status = hecc_read(priv, 659 (priv->use_hecc1int) ? HECC_CANGIF1 : HECC_CANGIF0); 660 661 if (!int_status) 662 return IRQ_NONE; 663 664 err_status = hecc_read(priv, HECC_CANES); 665 if (err_status & (HECC_BUS_ERROR | HECC_CANES_BO | 666 HECC_CANES_EP | HECC_CANES_EW)) 667 ti_hecc_error(ndev, int_status, err_status); 668 669 if (int_status & HECC_CANGIF_GMIF) { 670 while (priv->tx_tail - priv->tx_head > 0) { 671 mbxno = get_tx_tail_mb(priv); 672 mbx_mask = BIT(mbxno); 673 if (!(mbx_mask & hecc_read(priv, HECC_CANTA))) 674 break; 675 hecc_clear_bit(priv, HECC_CANMIM, mbx_mask); 676 hecc_write(priv, HECC_CANTA, mbx_mask); 677 spin_lock_irqsave(&priv->mbx_lock, flags); 678 hecc_clear_bit(priv, HECC_CANME, mbx_mask); 679 spin_unlock_irqrestore(&priv->mbx_lock, flags); 680 stamp = hecc_read_stamp(priv, mbxno); 681 stats->tx_bytes += can_rx_offload_get_echo_skb(&priv->offload, 682 mbxno, stamp); 683 stats->tx_packets++; 684 can_led_event(ndev, CAN_LED_EVENT_TX); 685 --priv->tx_tail; 686 } 687 688 /* restart queue if wrap-up or if queue stalled on last pkt */ 689 if (((priv->tx_head == priv->tx_tail) && 690 ((priv->tx_head & HECC_TX_MASK) != HECC_TX_MASK)) || 691 (((priv->tx_tail & HECC_TX_MASK) == HECC_TX_MASK) && 692 ((priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK))) 693 netif_wake_queue(ndev); 694 695 /* offload RX mailboxes and let NAPI deliver them */ 696 while ((rx_pending = hecc_read(priv, HECC_CANRMP))) { 697 can_rx_offload_irq_offload_timestamp(&priv->offload, 698 rx_pending); 699 hecc_write(priv, HECC_CANRMP, rx_pending); 700 } 701 } 702 703 /* clear all interrupt conditions - read back to avoid spurious ints */ 704 if (priv->use_hecc1int) { 705 hecc_write(priv, HECC_CANGIF1, HECC_SET_REG); 706 int_status = hecc_read(priv, HECC_CANGIF1); 707 } else { 708 hecc_write(priv, HECC_CANGIF0, HECC_SET_REG); 709 int_status = hecc_read(priv, HECC_CANGIF0); 710 } 711 712 return IRQ_HANDLED; 713 } 714 715 static int ti_hecc_open(struct net_device *ndev) 716 { 717 struct ti_hecc_priv *priv = netdev_priv(ndev); 718 int err; 719 720 err = request_irq(ndev->irq, ti_hecc_interrupt, IRQF_SHARED, 721 ndev->name, ndev); 722 if (err) { 723 netdev_err(ndev, "error requesting interrupt\n"); 724 return err; 725 } 726 727 ti_hecc_transceiver_switch(priv, 1); 728 729 /* Open common can device */ 730 err = open_candev(ndev); 731 if (err) { 732 netdev_err(ndev, "open_candev() failed %d\n", err); 733 ti_hecc_transceiver_switch(priv, 0); 734 free_irq(ndev->irq, ndev); 735 return err; 736 } 737 738 can_led_event(ndev, CAN_LED_EVENT_OPEN); 739 740 ti_hecc_start(ndev); 741 can_rx_offload_enable(&priv->offload); 742 netif_start_queue(ndev); 743 744 return 0; 745 } 746 747 static int ti_hecc_close(struct net_device *ndev) 748 { 749 struct ti_hecc_priv *priv = netdev_priv(ndev); 750 751 netif_stop_queue(ndev); 752 can_rx_offload_disable(&priv->offload); 753 ti_hecc_stop(ndev); 754 free_irq(ndev->irq, ndev); 755 close_candev(ndev); 756 ti_hecc_transceiver_switch(priv, 0); 757 758 can_led_event(ndev, CAN_LED_EVENT_STOP); 759 760 return 0; 761 } 762 763 static const struct net_device_ops ti_hecc_netdev_ops = { 764 .ndo_open = ti_hecc_open, 765 .ndo_stop = ti_hecc_close, 766 .ndo_start_xmit = ti_hecc_xmit, 767 .ndo_change_mtu = can_change_mtu, 768 }; 769 770 static const struct of_device_id ti_hecc_dt_ids[] = { 771 { 772 .compatible = "ti,am3517-hecc", 773 }, 774 { } 775 }; 776 MODULE_DEVICE_TABLE(of, ti_hecc_dt_ids); 777 778 static int ti_hecc_probe(struct platform_device *pdev) 779 { 780 struct net_device *ndev = (struct net_device *)0; 781 struct ti_hecc_priv *priv; 782 struct device_node *np = pdev->dev.of_node; 783 struct resource *res, *irq; 784 struct regulator *reg_xceiver; 785 int err = -ENODEV; 786 787 if (!IS_ENABLED(CONFIG_OF) || !np) 788 return -EINVAL; 789 790 reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver"); 791 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER) 792 return -EPROBE_DEFER; 793 else if (IS_ERR(reg_xceiver)) 794 reg_xceiver = NULL; 795 796 ndev = alloc_candev(sizeof(struct ti_hecc_priv), HECC_MAX_TX_MBOX); 797 if (!ndev) { 798 dev_err(&pdev->dev, "alloc_candev failed\n"); 799 return -ENOMEM; 800 } 801 priv = netdev_priv(ndev); 802 803 /* handle hecc memory */ 804 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hecc"); 805 if (!res) { 806 dev_err(&pdev->dev, "can't get IORESOURCE_MEM hecc\n"); 807 return -EINVAL; 808 } 809 810 priv->base = devm_ioremap_resource(&pdev->dev, res); 811 if (IS_ERR(priv->base)) { 812 dev_err(&pdev->dev, "hecc ioremap failed\n"); 813 return PTR_ERR(priv->base); 814 } 815 816 /* handle hecc-ram memory */ 817 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hecc-ram"); 818 if (!res) { 819 dev_err(&pdev->dev, "can't get IORESOURCE_MEM hecc-ram\n"); 820 return -EINVAL; 821 } 822 823 priv->hecc_ram = devm_ioremap_resource(&pdev->dev, res); 824 if (IS_ERR(priv->hecc_ram)) { 825 dev_err(&pdev->dev, "hecc-ram ioremap failed\n"); 826 return PTR_ERR(priv->hecc_ram); 827 } 828 829 /* handle mbx memory */ 830 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mbx"); 831 if (!res) { 832 dev_err(&pdev->dev, "can't get IORESOURCE_MEM mbx\n"); 833 return -EINVAL; 834 } 835 836 priv->mbx = devm_ioremap_resource(&pdev->dev, res); 837 if (IS_ERR(priv->mbx)) { 838 dev_err(&pdev->dev, "mbx ioremap failed\n"); 839 return PTR_ERR(priv->mbx); 840 } 841 842 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 843 if (!irq) { 844 dev_err(&pdev->dev, "No irq resource\n"); 845 goto probe_exit; 846 } 847 848 priv->ndev = ndev; 849 priv->reg_xceiver = reg_xceiver; 850 priv->use_hecc1int = of_property_read_bool(np, "ti,use-hecc1int"); 851 852 priv->can.bittiming_const = &ti_hecc_bittiming_const; 853 priv->can.do_set_mode = ti_hecc_do_set_mode; 854 priv->can.do_get_berr_counter = ti_hecc_get_berr_counter; 855 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES; 856 857 spin_lock_init(&priv->mbx_lock); 858 ndev->irq = irq->start; 859 ndev->flags |= IFF_ECHO; 860 platform_set_drvdata(pdev, ndev); 861 SET_NETDEV_DEV(ndev, &pdev->dev); 862 ndev->netdev_ops = &ti_hecc_netdev_ops; 863 864 priv->clk = clk_get(&pdev->dev, "hecc_ck"); 865 if (IS_ERR(priv->clk)) { 866 dev_err(&pdev->dev, "No clock available\n"); 867 err = PTR_ERR(priv->clk); 868 priv->clk = NULL; 869 goto probe_exit_candev; 870 } 871 priv->can.clock.freq = clk_get_rate(priv->clk); 872 873 err = clk_prepare_enable(priv->clk); 874 if (err) { 875 dev_err(&pdev->dev, "clk_prepare_enable() failed\n"); 876 goto probe_exit_clk; 877 } 878 879 priv->offload.mailbox_read = ti_hecc_mailbox_read; 880 priv->offload.mb_first = HECC_RX_FIRST_MBOX; 881 priv->offload.mb_last = HECC_MAX_TX_MBOX; 882 err = can_rx_offload_add_timestamp(ndev, &priv->offload); 883 if (err) { 884 dev_err(&pdev->dev, "can_rx_offload_add_timestamp() failed\n"); 885 goto probe_exit_clk; 886 } 887 888 err = register_candev(ndev); 889 if (err) { 890 dev_err(&pdev->dev, "register_candev() failed\n"); 891 goto probe_exit_offload; 892 } 893 894 devm_can_led_init(ndev); 895 896 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%u)\n", 897 priv->base, (u32) ndev->irq); 898 899 return 0; 900 901 probe_exit_offload: 902 can_rx_offload_del(&priv->offload); 903 probe_exit_clk: 904 clk_put(priv->clk); 905 probe_exit_candev: 906 free_candev(ndev); 907 probe_exit: 908 return err; 909 } 910 911 static int ti_hecc_remove(struct platform_device *pdev) 912 { 913 struct net_device *ndev = platform_get_drvdata(pdev); 914 struct ti_hecc_priv *priv = netdev_priv(ndev); 915 916 unregister_candev(ndev); 917 clk_disable_unprepare(priv->clk); 918 clk_put(priv->clk); 919 can_rx_offload_del(&priv->offload); 920 free_candev(ndev); 921 922 return 0; 923 } 924 925 #ifdef CONFIG_PM 926 static int ti_hecc_suspend(struct platform_device *pdev, pm_message_t state) 927 { 928 struct net_device *dev = platform_get_drvdata(pdev); 929 struct ti_hecc_priv *priv = netdev_priv(dev); 930 931 if (netif_running(dev)) { 932 netif_stop_queue(dev); 933 netif_device_detach(dev); 934 } 935 936 hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_PDR); 937 priv->can.state = CAN_STATE_SLEEPING; 938 939 clk_disable_unprepare(priv->clk); 940 941 return 0; 942 } 943 944 static int ti_hecc_resume(struct platform_device *pdev) 945 { 946 struct net_device *dev = platform_get_drvdata(pdev); 947 struct ti_hecc_priv *priv = netdev_priv(dev); 948 int err; 949 950 err = clk_prepare_enable(priv->clk); 951 if (err) 952 return err; 953 954 hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_PDR); 955 priv->can.state = CAN_STATE_ERROR_ACTIVE; 956 957 if (netif_running(dev)) { 958 netif_device_attach(dev); 959 netif_start_queue(dev); 960 } 961 962 return 0; 963 } 964 #else 965 #define ti_hecc_suspend NULL 966 #define ti_hecc_resume NULL 967 #endif 968 969 /* TI HECC netdevice driver: platform driver structure */ 970 static struct platform_driver ti_hecc_driver = { 971 .driver = { 972 .name = DRV_NAME, 973 .of_match_table = ti_hecc_dt_ids, 974 }, 975 .probe = ti_hecc_probe, 976 .remove = ti_hecc_remove, 977 .suspend = ti_hecc_suspend, 978 .resume = ti_hecc_resume, 979 }; 980 981 module_platform_driver(ti_hecc_driver); 982 983 MODULE_AUTHOR("Anant Gole <anantgole@ti.com>"); 984 MODULE_LICENSE("GPL v2"); 985 MODULE_DESCRIPTION(DRV_DESC); 986 MODULE_ALIAS("platform:" DRV_NAME); 987