1 /* 2 * sun4i_can.c - CAN bus controller driver for Allwinner SUN4I&SUN7I based SoCs 3 * 4 * Copyright (C) 2013 Peter Chen 5 * Copyright (C) 2015 Gerhard Bertelsmann 6 * All rights reserved. 7 * 8 * Parts of this software are based on (derived from) the SJA1000 code by: 9 * Copyright (C) 2014 Oliver Hartkopp <oliver.hartkopp@volkswagen.de> 10 * Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com> 11 * Copyright (C) 2002-2007 Volkswagen Group Electronic Research 12 * Copyright (C) 2003 Matthias Brukner, Trajet Gmbh, Rebenring 33, 13 * 38106 Braunschweig, GERMANY 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 3. Neither the name of Volkswagen nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * Alternatively, provided that this notice is retained in full, this 28 * software may be distributed under the terms of the GNU General 29 * Public License ("GPL") version 2, in which case the provisions of the 30 * GPL apply INSTEAD OF those given above. 31 * 32 * The provided data structures and external interfaces from this code 33 * are not restricted to be used by modules with a GPL compatible license. 34 * 35 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 36 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 37 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 38 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 39 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 40 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 41 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 42 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 43 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 44 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 45 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 46 * DAMAGE. 47 * 48 */ 49 50 #include <linux/netdevice.h> 51 #include <linux/can.h> 52 #include <linux/can/dev.h> 53 #include <linux/can/error.h> 54 #include <linux/clk.h> 55 #include <linux/delay.h> 56 #include <linux/interrupt.h> 57 #include <linux/init.h> 58 #include <linux/io.h> 59 #include <linux/module.h> 60 #include <linux/of.h> 61 #include <linux/of_device.h> 62 #include <linux/platform_device.h> 63 #include <linux/reset.h> 64 65 #define DRV_NAME "sun4i_can" 66 67 /* Registers address (physical base address 0x01C2BC00) */ 68 #define SUN4I_REG_MSEL_ADDR 0x0000 /* CAN Mode Select */ 69 #define SUN4I_REG_CMD_ADDR 0x0004 /* CAN Command */ 70 #define SUN4I_REG_STA_ADDR 0x0008 /* CAN Status */ 71 #define SUN4I_REG_INT_ADDR 0x000c /* CAN Interrupt Flag */ 72 #define SUN4I_REG_INTEN_ADDR 0x0010 /* CAN Interrupt Enable */ 73 #define SUN4I_REG_BTIME_ADDR 0x0014 /* CAN Bus Timing 0 */ 74 #define SUN4I_REG_TEWL_ADDR 0x0018 /* CAN Tx Error Warning Limit */ 75 #define SUN4I_REG_ERRC_ADDR 0x001c /* CAN Error Counter */ 76 #define SUN4I_REG_RMCNT_ADDR 0x0020 /* CAN Receive Message Counter */ 77 #define SUN4I_REG_RBUFSA_ADDR 0x0024 /* CAN Receive Buffer Start Address */ 78 #define SUN4I_REG_BUF0_ADDR 0x0040 /* CAN Tx/Rx Buffer 0 */ 79 #define SUN4I_REG_BUF1_ADDR 0x0044 /* CAN Tx/Rx Buffer 1 */ 80 #define SUN4I_REG_BUF2_ADDR 0x0048 /* CAN Tx/Rx Buffer 2 */ 81 #define SUN4I_REG_BUF3_ADDR 0x004c /* CAN Tx/Rx Buffer 3 */ 82 #define SUN4I_REG_BUF4_ADDR 0x0050 /* CAN Tx/Rx Buffer 4 */ 83 #define SUN4I_REG_BUF5_ADDR 0x0054 /* CAN Tx/Rx Buffer 5 */ 84 #define SUN4I_REG_BUF6_ADDR 0x0058 /* CAN Tx/Rx Buffer 6 */ 85 #define SUN4I_REG_BUF7_ADDR 0x005c /* CAN Tx/Rx Buffer 7 */ 86 #define SUN4I_REG_BUF8_ADDR 0x0060 /* CAN Tx/Rx Buffer 8 */ 87 #define SUN4I_REG_BUF9_ADDR 0x0064 /* CAN Tx/Rx Buffer 9 */ 88 #define SUN4I_REG_BUF10_ADDR 0x0068 /* CAN Tx/Rx Buffer 10 */ 89 #define SUN4I_REG_BUF11_ADDR 0x006c /* CAN Tx/Rx Buffer 11 */ 90 #define SUN4I_REG_BUF12_ADDR 0x0070 /* CAN Tx/Rx Buffer 12 */ 91 #define SUN4I_REG_ACPC_ADDR 0x0040 /* CAN Acceptance Code 0 */ 92 #define SUN4I_REG_ACPM_ADDR 0x0044 /* CAN Acceptance Mask 0 */ 93 #define SUN4I_REG_RBUF_RBACK_START_ADDR 0x0180 /* CAN transmit buffer start */ 94 #define SUN4I_REG_RBUF_RBACK_END_ADDR 0x01b0 /* CAN transmit buffer end */ 95 96 /* Controller Register Description */ 97 98 /* mode select register (r/w) 99 * offset:0x0000 default:0x0000_0001 100 */ 101 #define SUN4I_MSEL_SLEEP_MODE (0x01 << 4) /* write in reset mode */ 102 #define SUN4I_MSEL_WAKE_UP (0x00 << 4) 103 #define SUN4I_MSEL_SINGLE_FILTER (0x01 << 3) /* write in reset mode */ 104 #define SUN4I_MSEL_DUAL_FILTERS (0x00 << 3) 105 #define SUN4I_MSEL_LOOPBACK_MODE BIT(2) 106 #define SUN4I_MSEL_LISTEN_ONLY_MODE BIT(1) 107 #define SUN4I_MSEL_RESET_MODE BIT(0) 108 109 /* command register (w) 110 * offset:0x0004 default:0x0000_0000 111 */ 112 #define SUN4I_CMD_BUS_OFF_REQ BIT(5) 113 #define SUN4I_CMD_SELF_RCV_REQ BIT(4) 114 #define SUN4I_CMD_CLEAR_OR_FLAG BIT(3) 115 #define SUN4I_CMD_RELEASE_RBUF BIT(2) 116 #define SUN4I_CMD_ABORT_REQ BIT(1) 117 #define SUN4I_CMD_TRANS_REQ BIT(0) 118 119 /* status register (r) 120 * offset:0x0008 default:0x0000_003c 121 */ 122 #define SUN4I_STA_BIT_ERR (0x00 << 22) 123 #define SUN4I_STA_FORM_ERR (0x01 << 22) 124 #define SUN4I_STA_STUFF_ERR (0x02 << 22) 125 #define SUN4I_STA_OTHER_ERR (0x03 << 22) 126 #define SUN4I_STA_MASK_ERR (0x03 << 22) 127 #define SUN4I_STA_ERR_DIR BIT(21) 128 #define SUN4I_STA_ERR_SEG_CODE (0x1f << 16) 129 #define SUN4I_STA_START (0x03 << 16) 130 #define SUN4I_STA_ID28_21 (0x02 << 16) 131 #define SUN4I_STA_ID20_18 (0x06 << 16) 132 #define SUN4I_STA_SRTR (0x04 << 16) 133 #define SUN4I_STA_IDE (0x05 << 16) 134 #define SUN4I_STA_ID17_13 (0x07 << 16) 135 #define SUN4I_STA_ID12_5 (0x0f << 16) 136 #define SUN4I_STA_ID4_0 (0x0e << 16) 137 #define SUN4I_STA_RTR (0x0c << 16) 138 #define SUN4I_STA_RB1 (0x0d << 16) 139 #define SUN4I_STA_RB0 (0x09 << 16) 140 #define SUN4I_STA_DLEN (0x0b << 16) 141 #define SUN4I_STA_DATA_FIELD (0x0a << 16) 142 #define SUN4I_STA_CRC_SEQUENCE (0x08 << 16) 143 #define SUN4I_STA_CRC_DELIMITER (0x18 << 16) 144 #define SUN4I_STA_ACK (0x19 << 16) 145 #define SUN4I_STA_ACK_DELIMITER (0x1b << 16) 146 #define SUN4I_STA_END (0x1a << 16) 147 #define SUN4I_STA_INTERMISSION (0x12 << 16) 148 #define SUN4I_STA_ACTIVE_ERROR (0x11 << 16) 149 #define SUN4I_STA_PASSIVE_ERROR (0x16 << 16) 150 #define SUN4I_STA_TOLERATE_DOMINANT_BITS (0x13 << 16) 151 #define SUN4I_STA_ERROR_DELIMITER (0x17 << 16) 152 #define SUN4I_STA_OVERLOAD (0x1c << 16) 153 #define SUN4I_STA_BUS_OFF BIT(7) 154 #define SUN4I_STA_ERR_STA BIT(6) 155 #define SUN4I_STA_TRANS_BUSY BIT(5) 156 #define SUN4I_STA_RCV_BUSY BIT(4) 157 #define SUN4I_STA_TRANS_OVER BIT(3) 158 #define SUN4I_STA_TBUF_RDY BIT(2) 159 #define SUN4I_STA_DATA_ORUN BIT(1) 160 #define SUN4I_STA_RBUF_RDY BIT(0) 161 162 /* interrupt register (r) 163 * offset:0x000c default:0x0000_0000 164 */ 165 #define SUN4I_INT_BUS_ERR BIT(7) 166 #define SUN4I_INT_ARB_LOST BIT(6) 167 #define SUN4I_INT_ERR_PASSIVE BIT(5) 168 #define SUN4I_INT_WAKEUP BIT(4) 169 #define SUN4I_INT_DATA_OR BIT(3) 170 #define SUN4I_INT_ERR_WRN BIT(2) 171 #define SUN4I_INT_TBUF_VLD BIT(1) 172 #define SUN4I_INT_RBUF_VLD BIT(0) 173 174 /* interrupt enable register (r/w) 175 * offset:0x0010 default:0x0000_0000 176 */ 177 #define SUN4I_INTEN_BERR BIT(7) 178 #define SUN4I_INTEN_ARB_LOST BIT(6) 179 #define SUN4I_INTEN_ERR_PASSIVE BIT(5) 180 #define SUN4I_INTEN_WAKEUP BIT(4) 181 #define SUN4I_INTEN_OR BIT(3) 182 #define SUN4I_INTEN_ERR_WRN BIT(2) 183 #define SUN4I_INTEN_TX BIT(1) 184 #define SUN4I_INTEN_RX BIT(0) 185 186 /* error code */ 187 #define SUN4I_ERR_INRCV (0x1 << 5) 188 #define SUN4I_ERR_INTRANS (0x0 << 5) 189 190 /* filter mode */ 191 #define SUN4I_FILTER_CLOSE 0 192 #define SUN4I_SINGLE_FLTER_MODE 1 193 #define SUN4I_DUAL_FILTER_MODE 2 194 195 /* message buffer flags */ 196 #define SUN4I_MSG_EFF_FLAG BIT(7) 197 #define SUN4I_MSG_RTR_FLAG BIT(6) 198 199 /* max. number of interrupts handled in ISR */ 200 #define SUN4I_CAN_MAX_IRQ 20 201 #define SUN4I_MODE_MAX_RETRIES 100 202 203 /** 204 * struct sun4ican_quirks - Differences between SoC variants. 205 * 206 * @has_reset: SoC needs reset deasserted. 207 */ 208 struct sun4ican_quirks { 209 bool has_reset; 210 }; 211 212 struct sun4ican_priv { 213 struct can_priv can; 214 void __iomem *base; 215 struct clk *clk; 216 struct reset_control *reset; 217 spinlock_t cmdreg_lock; /* lock for concurrent cmd register writes */ 218 }; 219 220 static const struct can_bittiming_const sun4ican_bittiming_const = { 221 .name = DRV_NAME, 222 .tseg1_min = 1, 223 .tseg1_max = 16, 224 .tseg2_min = 1, 225 .tseg2_max = 8, 226 .sjw_max = 4, 227 .brp_min = 1, 228 .brp_max = 64, 229 .brp_inc = 1, 230 }; 231 232 static void sun4i_can_write_cmdreg(struct sun4ican_priv *priv, u8 val) 233 { 234 unsigned long flags; 235 236 spin_lock_irqsave(&priv->cmdreg_lock, flags); 237 writel(val, priv->base + SUN4I_REG_CMD_ADDR); 238 spin_unlock_irqrestore(&priv->cmdreg_lock, flags); 239 } 240 241 static int set_normal_mode(struct net_device *dev) 242 { 243 struct sun4ican_priv *priv = netdev_priv(dev); 244 int retry = SUN4I_MODE_MAX_RETRIES; 245 u32 mod_reg_val = 0; 246 247 do { 248 mod_reg_val = readl(priv->base + SUN4I_REG_MSEL_ADDR); 249 mod_reg_val &= ~SUN4I_MSEL_RESET_MODE; 250 writel(mod_reg_val, priv->base + SUN4I_REG_MSEL_ADDR); 251 } while (retry-- && (mod_reg_val & SUN4I_MSEL_RESET_MODE)); 252 253 if (readl(priv->base + SUN4I_REG_MSEL_ADDR) & SUN4I_MSEL_RESET_MODE) { 254 netdev_err(dev, 255 "setting controller into normal mode failed!\n"); 256 return -ETIMEDOUT; 257 } 258 259 return 0; 260 } 261 262 static int set_reset_mode(struct net_device *dev) 263 { 264 struct sun4ican_priv *priv = netdev_priv(dev); 265 int retry = SUN4I_MODE_MAX_RETRIES; 266 u32 mod_reg_val = 0; 267 268 do { 269 mod_reg_val = readl(priv->base + SUN4I_REG_MSEL_ADDR); 270 mod_reg_val |= SUN4I_MSEL_RESET_MODE; 271 writel(mod_reg_val, priv->base + SUN4I_REG_MSEL_ADDR); 272 } while (retry-- && !(mod_reg_val & SUN4I_MSEL_RESET_MODE)); 273 274 if (!(readl(priv->base + SUN4I_REG_MSEL_ADDR) & 275 SUN4I_MSEL_RESET_MODE)) { 276 netdev_err(dev, "setting controller into reset mode failed!\n"); 277 return -ETIMEDOUT; 278 } 279 280 return 0; 281 } 282 283 /* bittiming is called in reset_mode only */ 284 static int sun4ican_set_bittiming(struct net_device *dev) 285 { 286 struct sun4ican_priv *priv = netdev_priv(dev); 287 struct can_bittiming *bt = &priv->can.bittiming; 288 u32 cfg; 289 290 cfg = ((bt->brp - 1) & 0x3FF) | 291 (((bt->sjw - 1) & 0x3) << 14) | 292 (((bt->prop_seg + bt->phase_seg1 - 1) & 0xf) << 16) | 293 (((bt->phase_seg2 - 1) & 0x7) << 20); 294 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) 295 cfg |= 0x800000; 296 297 netdev_dbg(dev, "setting BITTIMING=0x%08x\n", cfg); 298 writel(cfg, priv->base + SUN4I_REG_BTIME_ADDR); 299 300 return 0; 301 } 302 303 static int sun4ican_get_berr_counter(const struct net_device *dev, 304 struct can_berr_counter *bec) 305 { 306 struct sun4ican_priv *priv = netdev_priv(dev); 307 u32 errors; 308 int err; 309 310 err = clk_prepare_enable(priv->clk); 311 if (err) { 312 netdev_err(dev, "could not enable clock\n"); 313 return err; 314 } 315 316 errors = readl(priv->base + SUN4I_REG_ERRC_ADDR); 317 318 bec->txerr = errors & 0xFF; 319 bec->rxerr = (errors >> 16) & 0xFF; 320 321 clk_disable_unprepare(priv->clk); 322 323 return 0; 324 } 325 326 static int sun4i_can_start(struct net_device *dev) 327 { 328 struct sun4ican_priv *priv = netdev_priv(dev); 329 int err; 330 u32 mod_reg_val; 331 332 /* we need to enter the reset mode */ 333 err = set_reset_mode(dev); 334 if (err) { 335 netdev_err(dev, "could not enter reset mode\n"); 336 return err; 337 } 338 339 /* set filters - we accept all */ 340 writel(0x00000000, priv->base + SUN4I_REG_ACPC_ADDR); 341 writel(0xFFFFFFFF, priv->base + SUN4I_REG_ACPM_ADDR); 342 343 /* clear error counters and error code capture */ 344 writel(0, priv->base + SUN4I_REG_ERRC_ADDR); 345 346 /* enable interrupts */ 347 if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) 348 writel(0xFF, priv->base + SUN4I_REG_INTEN_ADDR); 349 else 350 writel(0xFF & ~SUN4I_INTEN_BERR, 351 priv->base + SUN4I_REG_INTEN_ADDR); 352 353 /* enter the selected mode */ 354 mod_reg_val = readl(priv->base + SUN4I_REG_MSEL_ADDR); 355 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 356 mod_reg_val |= SUN4I_MSEL_LOOPBACK_MODE; 357 else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 358 mod_reg_val |= SUN4I_MSEL_LISTEN_ONLY_MODE; 359 writel(mod_reg_val, priv->base + SUN4I_REG_MSEL_ADDR); 360 361 err = sun4ican_set_bittiming(dev); 362 if (err) 363 return err; 364 365 /* we are ready to enter the normal mode */ 366 err = set_normal_mode(dev); 367 if (err) { 368 netdev_err(dev, "could not enter normal mode\n"); 369 return err; 370 } 371 372 priv->can.state = CAN_STATE_ERROR_ACTIVE; 373 374 return 0; 375 } 376 377 static int sun4i_can_stop(struct net_device *dev) 378 { 379 struct sun4ican_priv *priv = netdev_priv(dev); 380 int err; 381 382 priv->can.state = CAN_STATE_STOPPED; 383 /* we need to enter reset mode */ 384 err = set_reset_mode(dev); 385 if (err) { 386 netdev_err(dev, "could not enter reset mode\n"); 387 return err; 388 } 389 390 /* disable all interrupts */ 391 writel(0, priv->base + SUN4I_REG_INTEN_ADDR); 392 393 return 0; 394 } 395 396 static int sun4ican_set_mode(struct net_device *dev, enum can_mode mode) 397 { 398 int err; 399 400 switch (mode) { 401 case CAN_MODE_START: 402 err = sun4i_can_start(dev); 403 if (err) { 404 netdev_err(dev, "starting CAN controller failed!\n"); 405 return err; 406 } 407 if (netif_queue_stopped(dev)) 408 netif_wake_queue(dev); 409 break; 410 411 default: 412 return -EOPNOTSUPP; 413 } 414 return 0; 415 } 416 417 /* transmit a CAN message 418 * message layout in the sk_buff should be like this: 419 * xx xx xx xx ff ll 00 11 22 33 44 55 66 77 420 * [ can_id ] [flags] [len] [can data (up to 8 bytes] 421 */ 422 static netdev_tx_t sun4ican_start_xmit(struct sk_buff *skb, struct net_device *dev) 423 { 424 struct sun4ican_priv *priv = netdev_priv(dev); 425 struct can_frame *cf = (struct can_frame *)skb->data; 426 u8 dlc; 427 u32 dreg, msg_flag_n; 428 canid_t id; 429 int i; 430 431 if (can_dropped_invalid_skb(dev, skb)) 432 return NETDEV_TX_OK; 433 434 netif_stop_queue(dev); 435 436 id = cf->can_id; 437 dlc = cf->len; 438 msg_flag_n = dlc; 439 440 if (id & CAN_RTR_FLAG) 441 msg_flag_n |= SUN4I_MSG_RTR_FLAG; 442 443 if (id & CAN_EFF_FLAG) { 444 msg_flag_n |= SUN4I_MSG_EFF_FLAG; 445 dreg = SUN4I_REG_BUF5_ADDR; 446 writel((id >> 21) & 0xFF, priv->base + SUN4I_REG_BUF1_ADDR); 447 writel((id >> 13) & 0xFF, priv->base + SUN4I_REG_BUF2_ADDR); 448 writel((id >> 5) & 0xFF, priv->base + SUN4I_REG_BUF3_ADDR); 449 writel((id << 3) & 0xF8, priv->base + SUN4I_REG_BUF4_ADDR); 450 } else { 451 dreg = SUN4I_REG_BUF3_ADDR; 452 writel((id >> 3) & 0xFF, priv->base + SUN4I_REG_BUF1_ADDR); 453 writel((id << 5) & 0xE0, priv->base + SUN4I_REG_BUF2_ADDR); 454 } 455 456 for (i = 0; i < dlc; i++) 457 writel(cf->data[i], priv->base + (dreg + i * 4)); 458 459 writel(msg_flag_n, priv->base + SUN4I_REG_BUF0_ADDR); 460 461 can_put_echo_skb(skb, dev, 0, 0); 462 463 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 464 sun4i_can_write_cmdreg(priv, SUN4I_CMD_SELF_RCV_REQ); 465 else 466 sun4i_can_write_cmdreg(priv, SUN4I_CMD_TRANS_REQ); 467 468 return NETDEV_TX_OK; 469 } 470 471 static void sun4i_can_rx(struct net_device *dev) 472 { 473 struct sun4ican_priv *priv = netdev_priv(dev); 474 struct net_device_stats *stats = &dev->stats; 475 struct can_frame *cf; 476 struct sk_buff *skb; 477 u8 fi; 478 u32 dreg; 479 canid_t id; 480 int i; 481 482 /* create zero'ed CAN frame buffer */ 483 skb = alloc_can_skb(dev, &cf); 484 if (!skb) 485 return; 486 487 fi = readl(priv->base + SUN4I_REG_BUF0_ADDR); 488 cf->len = can_cc_dlc2len(fi & 0x0F); 489 if (fi & SUN4I_MSG_EFF_FLAG) { 490 dreg = SUN4I_REG_BUF5_ADDR; 491 id = (readl(priv->base + SUN4I_REG_BUF1_ADDR) << 21) | 492 (readl(priv->base + SUN4I_REG_BUF2_ADDR) << 13) | 493 (readl(priv->base + SUN4I_REG_BUF3_ADDR) << 5) | 494 ((readl(priv->base + SUN4I_REG_BUF4_ADDR) >> 3) & 0x1f); 495 id |= CAN_EFF_FLAG; 496 } else { 497 dreg = SUN4I_REG_BUF3_ADDR; 498 id = (readl(priv->base + SUN4I_REG_BUF1_ADDR) << 3) | 499 ((readl(priv->base + SUN4I_REG_BUF2_ADDR) >> 5) & 0x7); 500 } 501 502 /* remote frame ? */ 503 if (fi & SUN4I_MSG_RTR_FLAG) { 504 id |= CAN_RTR_FLAG; 505 } else { 506 for (i = 0; i < cf->len; i++) 507 cf->data[i] = readl(priv->base + dreg + i * 4); 508 509 stats->rx_bytes += cf->len; 510 } 511 stats->rx_packets++; 512 513 cf->can_id = id; 514 515 sun4i_can_write_cmdreg(priv, SUN4I_CMD_RELEASE_RBUF); 516 517 netif_rx(skb); 518 } 519 520 static int sun4i_can_err(struct net_device *dev, u8 isrc, u8 status) 521 { 522 struct sun4ican_priv *priv = netdev_priv(dev); 523 struct net_device_stats *stats = &dev->stats; 524 struct can_frame *cf; 525 struct sk_buff *skb; 526 enum can_state state = priv->can.state; 527 enum can_state rx_state, tx_state; 528 unsigned int rxerr, txerr, errc; 529 u32 ecc, alc; 530 531 /* we don't skip if alloc fails because we want the stats anyhow */ 532 skb = alloc_can_err_skb(dev, &cf); 533 534 errc = readl(priv->base + SUN4I_REG_ERRC_ADDR); 535 rxerr = (errc >> 16) & 0xFF; 536 txerr = errc & 0xFF; 537 538 if (skb) { 539 cf->data[6] = txerr; 540 cf->data[7] = rxerr; 541 } 542 543 if (isrc & SUN4I_INT_DATA_OR) { 544 /* data overrun interrupt */ 545 netdev_dbg(dev, "data overrun interrupt\n"); 546 if (likely(skb)) { 547 cf->can_id |= CAN_ERR_CRTL; 548 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 549 } 550 stats->rx_over_errors++; 551 stats->rx_errors++; 552 553 /* reset the CAN IP by entering reset mode 554 * ignoring timeout error 555 */ 556 set_reset_mode(dev); 557 set_normal_mode(dev); 558 559 /* clear bit */ 560 sun4i_can_write_cmdreg(priv, SUN4I_CMD_CLEAR_OR_FLAG); 561 } 562 if (isrc & SUN4I_INT_ERR_WRN) { 563 /* error warning interrupt */ 564 netdev_dbg(dev, "error warning interrupt\n"); 565 566 if (status & SUN4I_STA_BUS_OFF) 567 state = CAN_STATE_BUS_OFF; 568 else if (status & SUN4I_STA_ERR_STA) 569 state = CAN_STATE_ERROR_WARNING; 570 else 571 state = CAN_STATE_ERROR_ACTIVE; 572 } 573 if (isrc & SUN4I_INT_BUS_ERR) { 574 /* bus error interrupt */ 575 netdev_dbg(dev, "bus error interrupt\n"); 576 priv->can.can_stats.bus_error++; 577 stats->rx_errors++; 578 579 if (likely(skb)) { 580 ecc = readl(priv->base + SUN4I_REG_STA_ADDR); 581 582 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 583 584 switch (ecc & SUN4I_STA_MASK_ERR) { 585 case SUN4I_STA_BIT_ERR: 586 cf->data[2] |= CAN_ERR_PROT_BIT; 587 break; 588 case SUN4I_STA_FORM_ERR: 589 cf->data[2] |= CAN_ERR_PROT_FORM; 590 break; 591 case SUN4I_STA_STUFF_ERR: 592 cf->data[2] |= CAN_ERR_PROT_STUFF; 593 break; 594 default: 595 cf->data[3] = (ecc & SUN4I_STA_ERR_SEG_CODE) 596 >> 16; 597 break; 598 } 599 /* error occurred during transmission? */ 600 if ((ecc & SUN4I_STA_ERR_DIR) == 0) 601 cf->data[2] |= CAN_ERR_PROT_TX; 602 } 603 } 604 if (isrc & SUN4I_INT_ERR_PASSIVE) { 605 /* error passive interrupt */ 606 netdev_dbg(dev, "error passive interrupt\n"); 607 if (state == CAN_STATE_ERROR_PASSIVE) 608 state = CAN_STATE_ERROR_WARNING; 609 else 610 state = CAN_STATE_ERROR_PASSIVE; 611 } 612 if (isrc & SUN4I_INT_ARB_LOST) { 613 /* arbitration lost interrupt */ 614 netdev_dbg(dev, "arbitration lost interrupt\n"); 615 alc = readl(priv->base + SUN4I_REG_STA_ADDR); 616 priv->can.can_stats.arbitration_lost++; 617 if (likely(skb)) { 618 cf->can_id |= CAN_ERR_LOSTARB; 619 cf->data[0] = (alc >> 8) & 0x1f; 620 } 621 } 622 623 if (state != priv->can.state) { 624 tx_state = txerr >= rxerr ? state : 0; 625 rx_state = txerr <= rxerr ? state : 0; 626 627 if (likely(skb)) 628 can_change_state(dev, cf, tx_state, rx_state); 629 else 630 priv->can.state = state; 631 if (state == CAN_STATE_BUS_OFF) 632 can_bus_off(dev); 633 } 634 635 if (likely(skb)) 636 netif_rx(skb); 637 else 638 return -ENOMEM; 639 640 return 0; 641 } 642 643 static irqreturn_t sun4i_can_interrupt(int irq, void *dev_id) 644 { 645 struct net_device *dev = (struct net_device *)dev_id; 646 struct sun4ican_priv *priv = netdev_priv(dev); 647 struct net_device_stats *stats = &dev->stats; 648 u8 isrc, status; 649 int n = 0; 650 651 while ((isrc = readl(priv->base + SUN4I_REG_INT_ADDR)) && 652 (n < SUN4I_CAN_MAX_IRQ)) { 653 n++; 654 status = readl(priv->base + SUN4I_REG_STA_ADDR); 655 656 if (isrc & SUN4I_INT_WAKEUP) 657 netdev_warn(dev, "wakeup interrupt\n"); 658 659 if (isrc & SUN4I_INT_TBUF_VLD) { 660 /* transmission complete interrupt */ 661 stats->tx_bytes += can_get_echo_skb(dev, 0, NULL); 662 stats->tx_packets++; 663 netif_wake_queue(dev); 664 } 665 if ((isrc & SUN4I_INT_RBUF_VLD) && 666 !(isrc & SUN4I_INT_DATA_OR)) { 667 /* receive interrupt - don't read if overrun occurred */ 668 while (status & SUN4I_STA_RBUF_RDY) { 669 /* RX buffer is not empty */ 670 sun4i_can_rx(dev); 671 status = readl(priv->base + SUN4I_REG_STA_ADDR); 672 } 673 } 674 if (isrc & 675 (SUN4I_INT_DATA_OR | SUN4I_INT_ERR_WRN | SUN4I_INT_BUS_ERR | 676 SUN4I_INT_ERR_PASSIVE | SUN4I_INT_ARB_LOST)) { 677 /* error interrupt */ 678 if (sun4i_can_err(dev, isrc, status)) 679 netdev_err(dev, "can't allocate buffer - clearing pending interrupts\n"); 680 } 681 /* clear interrupts */ 682 writel(isrc, priv->base + SUN4I_REG_INT_ADDR); 683 readl(priv->base + SUN4I_REG_INT_ADDR); 684 } 685 if (n >= SUN4I_CAN_MAX_IRQ) 686 netdev_dbg(dev, "%d messages handled in ISR", n); 687 688 return (n) ? IRQ_HANDLED : IRQ_NONE; 689 } 690 691 static int sun4ican_open(struct net_device *dev) 692 { 693 struct sun4ican_priv *priv = netdev_priv(dev); 694 int err; 695 696 /* common open */ 697 err = open_candev(dev); 698 if (err) 699 return err; 700 701 /* register interrupt handler */ 702 err = request_irq(dev->irq, sun4i_can_interrupt, 0, dev->name, dev); 703 if (err) { 704 netdev_err(dev, "request_irq err: %d\n", err); 705 goto exit_irq; 706 } 707 708 /* software reset deassert */ 709 err = reset_control_deassert(priv->reset); 710 if (err) { 711 netdev_err(dev, "could not deassert CAN reset\n"); 712 goto exit_soft_reset; 713 } 714 715 /* turn on clocking for CAN peripheral block */ 716 err = clk_prepare_enable(priv->clk); 717 if (err) { 718 netdev_err(dev, "could not enable CAN peripheral clock\n"); 719 goto exit_clock; 720 } 721 722 err = sun4i_can_start(dev); 723 if (err) { 724 netdev_err(dev, "could not start CAN peripheral\n"); 725 goto exit_can_start; 726 } 727 728 netif_start_queue(dev); 729 730 return 0; 731 732 exit_can_start: 733 clk_disable_unprepare(priv->clk); 734 exit_clock: 735 reset_control_assert(priv->reset); 736 exit_soft_reset: 737 free_irq(dev->irq, dev); 738 exit_irq: 739 close_candev(dev); 740 return err; 741 } 742 743 static int sun4ican_close(struct net_device *dev) 744 { 745 struct sun4ican_priv *priv = netdev_priv(dev); 746 747 netif_stop_queue(dev); 748 sun4i_can_stop(dev); 749 clk_disable_unprepare(priv->clk); 750 reset_control_assert(priv->reset); 751 752 free_irq(dev->irq, dev); 753 close_candev(dev); 754 755 return 0; 756 } 757 758 static const struct net_device_ops sun4ican_netdev_ops = { 759 .ndo_open = sun4ican_open, 760 .ndo_stop = sun4ican_close, 761 .ndo_start_xmit = sun4ican_start_xmit, 762 }; 763 764 static const struct sun4ican_quirks sun4ican_quirks_a10 = { 765 .has_reset = false, 766 }; 767 768 static const struct sun4ican_quirks sun4ican_quirks_r40 = { 769 .has_reset = true, 770 }; 771 772 static const struct of_device_id sun4ican_of_match[] = { 773 { 774 .compatible = "allwinner,sun4i-a10-can", 775 .data = &sun4ican_quirks_a10 776 }, { 777 .compatible = "allwinner,sun7i-a20-can", 778 .data = &sun4ican_quirks_a10 779 }, { 780 .compatible = "allwinner,sun8i-r40-can", 781 .data = &sun4ican_quirks_r40 782 }, { 783 /* sentinel */ 784 }, 785 }; 786 787 MODULE_DEVICE_TABLE(of, sun4ican_of_match); 788 789 static int sun4ican_remove(struct platform_device *pdev) 790 { 791 struct net_device *dev = platform_get_drvdata(pdev); 792 793 unregister_netdev(dev); 794 free_candev(dev); 795 796 return 0; 797 } 798 799 static int sun4ican_probe(struct platform_device *pdev) 800 { 801 struct device_node *np = pdev->dev.of_node; 802 struct clk *clk; 803 struct reset_control *reset = NULL; 804 void __iomem *addr; 805 int err, irq; 806 struct net_device *dev; 807 struct sun4ican_priv *priv; 808 const struct sun4ican_quirks *quirks; 809 810 quirks = of_device_get_match_data(&pdev->dev); 811 if (!quirks) { 812 dev_err(&pdev->dev, "failed to determine the quirks to use\n"); 813 err = -ENODEV; 814 goto exit; 815 } 816 817 if (quirks->has_reset) { 818 reset = devm_reset_control_get_exclusive(&pdev->dev, NULL); 819 if (IS_ERR(reset)) { 820 dev_err(&pdev->dev, "unable to request reset\n"); 821 err = PTR_ERR(reset); 822 goto exit; 823 } 824 } 825 826 clk = of_clk_get(np, 0); 827 if (IS_ERR(clk)) { 828 dev_err(&pdev->dev, "unable to request clock\n"); 829 err = -ENODEV; 830 goto exit; 831 } 832 833 irq = platform_get_irq(pdev, 0); 834 if (irq < 0) { 835 err = -ENODEV; 836 goto exit; 837 } 838 839 addr = devm_platform_ioremap_resource(pdev, 0); 840 if (IS_ERR(addr)) { 841 err = PTR_ERR(addr); 842 goto exit; 843 } 844 845 dev = alloc_candev(sizeof(struct sun4ican_priv), 1); 846 if (!dev) { 847 dev_err(&pdev->dev, 848 "could not allocate memory for CAN device\n"); 849 err = -ENOMEM; 850 goto exit; 851 } 852 853 dev->netdev_ops = &sun4ican_netdev_ops; 854 dev->irq = irq; 855 dev->flags |= IFF_ECHO; 856 857 priv = netdev_priv(dev); 858 priv->can.clock.freq = clk_get_rate(clk); 859 priv->can.bittiming_const = &sun4ican_bittiming_const; 860 priv->can.do_set_mode = sun4ican_set_mode; 861 priv->can.do_get_berr_counter = sun4ican_get_berr_counter; 862 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING | 863 CAN_CTRLMODE_LISTENONLY | 864 CAN_CTRLMODE_LOOPBACK | 865 CAN_CTRLMODE_3_SAMPLES; 866 priv->base = addr; 867 priv->clk = clk; 868 priv->reset = reset; 869 spin_lock_init(&priv->cmdreg_lock); 870 871 platform_set_drvdata(pdev, dev); 872 SET_NETDEV_DEV(dev, &pdev->dev); 873 874 err = register_candev(dev); 875 if (err) { 876 dev_err(&pdev->dev, "registering %s failed (err=%d)\n", 877 DRV_NAME, err); 878 goto exit_free; 879 } 880 881 dev_info(&pdev->dev, "device registered (base=%p, irq=%d)\n", 882 priv->base, dev->irq); 883 884 return 0; 885 886 exit_free: 887 free_candev(dev); 888 exit: 889 return err; 890 } 891 892 static struct platform_driver sun4i_can_driver = { 893 .driver = { 894 .name = DRV_NAME, 895 .of_match_table = sun4ican_of_match, 896 }, 897 .probe = sun4ican_probe, 898 .remove = sun4ican_remove, 899 }; 900 901 module_platform_driver(sun4i_can_driver); 902 903 MODULE_AUTHOR("Peter Chen <xingkongcp@gmail.com>"); 904 MODULE_AUTHOR("Gerhard Bertelsmann <info@gerhard-bertelsmann.de>"); 905 MODULE_LICENSE("Dual BSD/GPL"); 906 MODULE_DESCRIPTION("CAN driver for Allwinner SoCs (A10/A20)"); 907