xref: /linux/drivers/net/can/spi/mcp251xfd/mcp251xfd.h (revision be471fe332f7f14aa6828010b220d7e6902b91a0)
1 /* SPDX-License-Identifier: GPL-2.0
2  *
3  * mcp251xfd - Microchip MCP251xFD Family CAN controller driver
4  *
5  * Copyright (c) 2019 Pengutronix,
6  *                    Marc Kleine-Budde <kernel@pengutronix.de>
7  * Copyright (c) 2019 Martin Sperl <kernel@martin.sperl.org>
8  */
9 
10 #ifndef _MCP251XFD_H
11 #define _MCP251XFD_H
12 
13 #include <linux/can/core.h>
14 #include <linux/can/dev.h>
15 #include <linux/can/rx-offload.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/kernel.h>
18 #include <linux/netdevice.h>
19 #include <linux/regmap.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/spi/spi.h>
22 #include <linux/timecounter.h>
23 #include <linux/workqueue.h>
24 
25 /* MPC251x registers */
26 
27 /* CAN FD Controller Module SFR */
28 #define MCP251XFD_REG_CON 0x00
29 #define MCP251XFD_REG_CON_TXBWS_MASK GENMASK(31, 28)
30 #define MCP251XFD_REG_CON_ABAT BIT(27)
31 #define MCP251XFD_REG_CON_REQOP_MASK GENMASK(26, 24)
32 #define MCP251XFD_REG_CON_MODE_MIXED 0
33 #define MCP251XFD_REG_CON_MODE_SLEEP 1
34 #define MCP251XFD_REG_CON_MODE_INT_LOOPBACK 2
35 #define MCP251XFD_REG_CON_MODE_LISTENONLY 3
36 #define MCP251XFD_REG_CON_MODE_CONFIG 4
37 #define MCP251XFD_REG_CON_MODE_EXT_LOOPBACK 5
38 #define MCP251XFD_REG_CON_MODE_CAN2_0 6
39 #define MCP251XFD_REG_CON_MODE_RESTRICTED 7
40 #define MCP251XFD_REG_CON_OPMOD_MASK GENMASK(23, 21)
41 #define MCP251XFD_REG_CON_TXQEN BIT(20)
42 #define MCP251XFD_REG_CON_STEF BIT(19)
43 #define MCP251XFD_REG_CON_SERR2LOM BIT(18)
44 #define MCP251XFD_REG_CON_ESIGM BIT(17)
45 #define MCP251XFD_REG_CON_RTXAT BIT(16)
46 #define MCP251XFD_REG_CON_BRSDIS BIT(12)
47 #define MCP251XFD_REG_CON_BUSY BIT(11)
48 #define MCP251XFD_REG_CON_WFT_MASK GENMASK(10, 9)
49 #define MCP251XFD_REG_CON_WFT_T00FILTER 0x0
50 #define MCP251XFD_REG_CON_WFT_T01FILTER 0x1
51 #define MCP251XFD_REG_CON_WFT_T10FILTER 0x2
52 #define MCP251XFD_REG_CON_WFT_T11FILTER 0x3
53 #define MCP251XFD_REG_CON_WAKFIL BIT(8)
54 #define MCP251XFD_REG_CON_PXEDIS BIT(6)
55 #define MCP251XFD_REG_CON_ISOCRCEN BIT(5)
56 #define MCP251XFD_REG_CON_DNCNT_MASK GENMASK(4, 0)
57 
58 #define MCP251XFD_REG_NBTCFG 0x04
59 #define MCP251XFD_REG_NBTCFG_BRP_MASK GENMASK(31, 24)
60 #define MCP251XFD_REG_NBTCFG_TSEG1_MASK GENMASK(23, 16)
61 #define MCP251XFD_REG_NBTCFG_TSEG2_MASK GENMASK(14, 8)
62 #define MCP251XFD_REG_NBTCFG_SJW_MASK GENMASK(6, 0)
63 
64 #define MCP251XFD_REG_DBTCFG 0x08
65 #define MCP251XFD_REG_DBTCFG_BRP_MASK GENMASK(31, 24)
66 #define MCP251XFD_REG_DBTCFG_TSEG1_MASK GENMASK(20, 16)
67 #define MCP251XFD_REG_DBTCFG_TSEG2_MASK GENMASK(11, 8)
68 #define MCP251XFD_REG_DBTCFG_SJW_MASK GENMASK(3, 0)
69 
70 #define MCP251XFD_REG_TDC 0x0c
71 #define MCP251XFD_REG_TDC_EDGFLTEN BIT(25)
72 #define MCP251XFD_REG_TDC_SID11EN BIT(24)
73 #define MCP251XFD_REG_TDC_TDCMOD_MASK GENMASK(17, 16)
74 #define MCP251XFD_REG_TDC_TDCMOD_AUTO 2
75 #define MCP251XFD_REG_TDC_TDCMOD_MANUAL 1
76 #define MCP251XFD_REG_TDC_TDCMOD_DISABLED 0
77 #define MCP251XFD_REG_TDC_TDCO_MASK GENMASK(14, 8)
78 #define MCP251XFD_REG_TDC_TDCV_MASK GENMASK(5, 0)
79 
80 #define MCP251XFD_REG_TBC 0x10
81 
82 #define MCP251XFD_REG_TSCON 0x14
83 #define MCP251XFD_REG_TSCON_TSRES BIT(18)
84 #define MCP251XFD_REG_TSCON_TSEOF BIT(17)
85 #define MCP251XFD_REG_TSCON_TBCEN BIT(16)
86 #define MCP251XFD_REG_TSCON_TBCPRE_MASK GENMASK(9, 0)
87 
88 #define MCP251XFD_REG_VEC 0x18
89 #define MCP251XFD_REG_VEC_RXCODE_MASK GENMASK(30, 24)
90 #define MCP251XFD_REG_VEC_TXCODE_MASK GENMASK(22, 16)
91 #define MCP251XFD_REG_VEC_FILHIT_MASK GENMASK(12, 8)
92 #define MCP251XFD_REG_VEC_ICODE_MASK GENMASK(6, 0)
93 
94 #define MCP251XFD_REG_INT 0x1c
95 #define MCP251XFD_REG_INT_IF_MASK GENMASK(15, 0)
96 #define MCP251XFD_REG_INT_IE_MASK GENMASK(31, 16)
97 #define MCP251XFD_REG_INT_IVMIE BIT(31)
98 #define MCP251XFD_REG_INT_WAKIE BIT(30)
99 #define MCP251XFD_REG_INT_CERRIE BIT(29)
100 #define MCP251XFD_REG_INT_SERRIE BIT(28)
101 #define MCP251XFD_REG_INT_RXOVIE BIT(27)
102 #define MCP251XFD_REG_INT_TXATIE BIT(26)
103 #define MCP251XFD_REG_INT_SPICRCIE BIT(25)
104 #define MCP251XFD_REG_INT_ECCIE BIT(24)
105 #define MCP251XFD_REG_INT_TEFIE BIT(20)
106 #define MCP251XFD_REG_INT_MODIE BIT(19)
107 #define MCP251XFD_REG_INT_TBCIE BIT(18)
108 #define MCP251XFD_REG_INT_RXIE BIT(17)
109 #define MCP251XFD_REG_INT_TXIE BIT(16)
110 #define MCP251XFD_REG_INT_IVMIF BIT(15)
111 #define MCP251XFD_REG_INT_WAKIF BIT(14)
112 #define MCP251XFD_REG_INT_CERRIF BIT(13)
113 #define MCP251XFD_REG_INT_SERRIF BIT(12)
114 #define MCP251XFD_REG_INT_RXOVIF BIT(11)
115 #define MCP251XFD_REG_INT_TXATIF BIT(10)
116 #define MCP251XFD_REG_INT_SPICRCIF BIT(9)
117 #define MCP251XFD_REG_INT_ECCIF BIT(8)
118 #define MCP251XFD_REG_INT_TEFIF BIT(4)
119 #define MCP251XFD_REG_INT_MODIF BIT(3)
120 #define MCP251XFD_REG_INT_TBCIF BIT(2)
121 #define MCP251XFD_REG_INT_RXIF BIT(1)
122 #define MCP251XFD_REG_INT_TXIF BIT(0)
123 /* These IRQ flags must be cleared by SW in the CAN_INT register */
124 #define MCP251XFD_REG_INT_IF_CLEARABLE_MASK \
125 	(MCP251XFD_REG_INT_IVMIF | MCP251XFD_REG_INT_WAKIF | \
126 	 MCP251XFD_REG_INT_CERRIF |  MCP251XFD_REG_INT_SERRIF | \
127 	 MCP251XFD_REG_INT_MODIF)
128 
129 #define MCP251XFD_REG_RXIF 0x20
130 #define MCP251XFD_REG_TXIF 0x24
131 #define MCP251XFD_REG_RXOVIF 0x28
132 #define MCP251XFD_REG_TXATIF 0x2c
133 #define MCP251XFD_REG_TXREQ 0x30
134 
135 #define MCP251XFD_REG_TREC 0x34
136 #define MCP251XFD_REG_TREC_TXBO BIT(21)
137 #define MCP251XFD_REG_TREC_TXBP BIT(20)
138 #define MCP251XFD_REG_TREC_RXBP BIT(19)
139 #define MCP251XFD_REG_TREC_TXWARN BIT(18)
140 #define MCP251XFD_REG_TREC_RXWARN BIT(17)
141 #define MCP251XFD_REG_TREC_EWARN BIT(16)
142 #define MCP251XFD_REG_TREC_TEC_MASK GENMASK(15, 8)
143 #define MCP251XFD_REG_TREC_REC_MASK GENMASK(7, 0)
144 
145 #define MCP251XFD_REG_BDIAG0 0x38
146 #define MCP251XFD_REG_BDIAG0_DTERRCNT_MASK GENMASK(31, 24)
147 #define MCP251XFD_REG_BDIAG0_DRERRCNT_MASK GENMASK(23, 16)
148 #define MCP251XFD_REG_BDIAG0_NTERRCNT_MASK GENMASK(15, 8)
149 #define MCP251XFD_REG_BDIAG0_NRERRCNT_MASK GENMASK(7, 0)
150 
151 #define MCP251XFD_REG_BDIAG1 0x3c
152 #define MCP251XFD_REG_BDIAG1_DLCMM BIT(31)
153 #define MCP251XFD_REG_BDIAG1_ESI BIT(30)
154 #define MCP251XFD_REG_BDIAG1_DCRCERR BIT(29)
155 #define MCP251XFD_REG_BDIAG1_DSTUFERR BIT(28)
156 #define MCP251XFD_REG_BDIAG1_DFORMERR BIT(27)
157 #define MCP251XFD_REG_BDIAG1_DBIT1ERR BIT(25)
158 #define MCP251XFD_REG_BDIAG1_DBIT0ERR BIT(24)
159 #define MCP251XFD_REG_BDIAG1_TXBOERR BIT(23)
160 #define MCP251XFD_REG_BDIAG1_NCRCERR BIT(21)
161 #define MCP251XFD_REG_BDIAG1_NSTUFERR BIT(20)
162 #define MCP251XFD_REG_BDIAG1_NFORMERR BIT(19)
163 #define MCP251XFD_REG_BDIAG1_NACKERR BIT(18)
164 #define MCP251XFD_REG_BDIAG1_NBIT1ERR BIT(17)
165 #define MCP251XFD_REG_BDIAG1_NBIT0ERR BIT(16)
166 #define MCP251XFD_REG_BDIAG1_BERR_MASK \
167 	(MCP251XFD_REG_BDIAG1_DLCMM | MCP251XFD_REG_BDIAG1_ESI | \
168 	 MCP251XFD_REG_BDIAG1_DCRCERR | MCP251XFD_REG_BDIAG1_DSTUFERR | \
169 	 MCP251XFD_REG_BDIAG1_DFORMERR | MCP251XFD_REG_BDIAG1_DBIT1ERR | \
170 	 MCP251XFD_REG_BDIAG1_DBIT0ERR | MCP251XFD_REG_BDIAG1_TXBOERR | \
171 	 MCP251XFD_REG_BDIAG1_NCRCERR | MCP251XFD_REG_BDIAG1_NSTUFERR | \
172 	 MCP251XFD_REG_BDIAG1_NFORMERR | MCP251XFD_REG_BDIAG1_NACKERR | \
173 	 MCP251XFD_REG_BDIAG1_NBIT1ERR | MCP251XFD_REG_BDIAG1_NBIT0ERR)
174 #define MCP251XFD_REG_BDIAG1_EFMSGCNT_MASK GENMASK(15, 0)
175 
176 #define MCP251XFD_REG_TEFCON 0x40
177 #define MCP251XFD_REG_TEFCON_FSIZE_MASK GENMASK(28, 24)
178 #define MCP251XFD_REG_TEFCON_FRESET BIT(10)
179 #define MCP251XFD_REG_TEFCON_UINC BIT(8)
180 #define MCP251XFD_REG_TEFCON_TEFTSEN BIT(5)
181 #define MCP251XFD_REG_TEFCON_TEFOVIE BIT(3)
182 #define MCP251XFD_REG_TEFCON_TEFFIE BIT(2)
183 #define MCP251XFD_REG_TEFCON_TEFHIE BIT(1)
184 #define MCP251XFD_REG_TEFCON_TEFNEIE BIT(0)
185 
186 #define MCP251XFD_REG_TEFSTA 0x44
187 #define MCP251XFD_REG_TEFSTA_TEFOVIF BIT(3)
188 #define MCP251XFD_REG_TEFSTA_TEFFIF BIT(2)
189 #define MCP251XFD_REG_TEFSTA_TEFHIF BIT(1)
190 #define MCP251XFD_REG_TEFSTA_TEFNEIF BIT(0)
191 
192 #define MCP251XFD_REG_TEFUA 0x48
193 
194 #define MCP251XFD_REG_TXQCON 0x50
195 #define MCP251XFD_REG_TXQCON_PLSIZE_MASK GENMASK(31, 29)
196 #define MCP251XFD_REG_TXQCON_PLSIZE_8 0
197 #define MCP251XFD_REG_TXQCON_PLSIZE_12 1
198 #define MCP251XFD_REG_TXQCON_PLSIZE_16 2
199 #define MCP251XFD_REG_TXQCON_PLSIZE_20 3
200 #define MCP251XFD_REG_TXQCON_PLSIZE_24 4
201 #define MCP251XFD_REG_TXQCON_PLSIZE_32 5
202 #define MCP251XFD_REG_TXQCON_PLSIZE_48 6
203 #define MCP251XFD_REG_TXQCON_PLSIZE_64 7
204 #define MCP251XFD_REG_TXQCON_FSIZE_MASK GENMASK(28, 24)
205 #define MCP251XFD_REG_TXQCON_TXAT_UNLIMITED 3
206 #define MCP251XFD_REG_TXQCON_TXAT_THREE_SHOT 1
207 #define MCP251XFD_REG_TXQCON_TXAT_ONE_SHOT 0
208 #define MCP251XFD_REG_TXQCON_TXAT_MASK GENMASK(22, 21)
209 #define MCP251XFD_REG_TXQCON_TXPRI_MASK GENMASK(20, 16)
210 #define MCP251XFD_REG_TXQCON_FRESET BIT(10)
211 #define MCP251XFD_REG_TXQCON_TXREQ BIT(9)
212 #define MCP251XFD_REG_TXQCON_UINC BIT(8)
213 #define MCP251XFD_REG_TXQCON_TXEN BIT(7)
214 #define MCP251XFD_REG_TXQCON_TXATIE BIT(4)
215 #define MCP251XFD_REG_TXQCON_TXQEIE BIT(2)
216 #define MCP251XFD_REG_TXQCON_TXQNIE BIT(0)
217 
218 #define MCP251XFD_REG_TXQSTA 0x54
219 #define MCP251XFD_REG_TXQSTA_TXQCI_MASK GENMASK(12, 8)
220 #define MCP251XFD_REG_TXQSTA_TXABT BIT(7)
221 #define MCP251XFD_REG_TXQSTA_TXLARB BIT(6)
222 #define MCP251XFD_REG_TXQSTA_TXERR BIT(5)
223 #define MCP251XFD_REG_TXQSTA_TXATIF BIT(4)
224 #define MCP251XFD_REG_TXQSTA_TXQEIF BIT(2)
225 #define MCP251XFD_REG_TXQSTA_TXQNIF BIT(0)
226 
227 #define MCP251XFD_REG_TXQUA 0x58
228 
229 #define MCP251XFD_REG_FIFOCON(x) (0x50 + 0xc * (x))
230 #define MCP251XFD_REG_FIFOCON_PLSIZE_MASK GENMASK(31, 29)
231 #define MCP251XFD_REG_FIFOCON_PLSIZE_8 0
232 #define MCP251XFD_REG_FIFOCON_PLSIZE_12 1
233 #define MCP251XFD_REG_FIFOCON_PLSIZE_16 2
234 #define MCP251XFD_REG_FIFOCON_PLSIZE_20 3
235 #define MCP251XFD_REG_FIFOCON_PLSIZE_24 4
236 #define MCP251XFD_REG_FIFOCON_PLSIZE_32 5
237 #define MCP251XFD_REG_FIFOCON_PLSIZE_48 6
238 #define MCP251XFD_REG_FIFOCON_PLSIZE_64 7
239 #define MCP251XFD_REG_FIFOCON_FSIZE_MASK GENMASK(28, 24)
240 #define MCP251XFD_REG_FIFOCON_TXAT_MASK GENMASK(22, 21)
241 #define MCP251XFD_REG_FIFOCON_TXAT_ONE_SHOT 0
242 #define MCP251XFD_REG_FIFOCON_TXAT_THREE_SHOT 1
243 #define MCP251XFD_REG_FIFOCON_TXAT_UNLIMITED 3
244 #define MCP251XFD_REG_FIFOCON_TXPRI_MASK GENMASK(20, 16)
245 #define MCP251XFD_REG_FIFOCON_FRESET BIT(10)
246 #define MCP251XFD_REG_FIFOCON_TXREQ BIT(9)
247 #define MCP251XFD_REG_FIFOCON_UINC BIT(8)
248 #define MCP251XFD_REG_FIFOCON_TXEN BIT(7)
249 #define MCP251XFD_REG_FIFOCON_RTREN BIT(6)
250 #define MCP251XFD_REG_FIFOCON_RXTSEN BIT(5)
251 #define MCP251XFD_REG_FIFOCON_TXATIE BIT(4)
252 #define MCP251XFD_REG_FIFOCON_RXOVIE BIT(3)
253 #define MCP251XFD_REG_FIFOCON_TFERFFIE BIT(2)
254 #define MCP251XFD_REG_FIFOCON_TFHRFHIE BIT(1)
255 #define MCP251XFD_REG_FIFOCON_TFNRFNIE BIT(0)
256 
257 #define MCP251XFD_REG_FIFOSTA(x) (0x54 + 0xc * (x))
258 #define MCP251XFD_REG_FIFOSTA_FIFOCI_MASK GENMASK(12, 8)
259 #define MCP251XFD_REG_FIFOSTA_TXABT BIT(7)
260 #define MCP251XFD_REG_FIFOSTA_TXLARB BIT(6)
261 #define MCP251XFD_REG_FIFOSTA_TXERR BIT(5)
262 #define MCP251XFD_REG_FIFOSTA_TXATIF BIT(4)
263 #define MCP251XFD_REG_FIFOSTA_RXOVIF BIT(3)
264 #define MCP251XFD_REG_FIFOSTA_TFERFFIF BIT(2)
265 #define MCP251XFD_REG_FIFOSTA_TFHRFHIF BIT(1)
266 #define MCP251XFD_REG_FIFOSTA_TFNRFNIF BIT(0)
267 
268 #define MCP251XFD_REG_FIFOUA(x) (0x58 + 0xc * (x))
269 
270 #define MCP251XFD_REG_FLTCON(x) (0x1d0 + 0x4 * (x))
271 #define MCP251XFD_REG_FLTCON_FLTEN3 BIT(31)
272 #define MCP251XFD_REG_FLTCON_F3BP_MASK GENMASK(28, 24)
273 #define MCP251XFD_REG_FLTCON_FLTEN2 BIT(23)
274 #define MCP251XFD_REG_FLTCON_F2BP_MASK GENMASK(20, 16)
275 #define MCP251XFD_REG_FLTCON_FLTEN1 BIT(15)
276 #define MCP251XFD_REG_FLTCON_F1BP_MASK GENMASK(12, 8)
277 #define MCP251XFD_REG_FLTCON_FLTEN0 BIT(7)
278 #define MCP251XFD_REG_FLTCON_F0BP_MASK GENMASK(4, 0)
279 #define MCP251XFD_REG_FLTCON_FLTEN(x) (BIT(7) << 8 * ((x) & 0x3))
280 #define MCP251XFD_REG_FLTCON_FLT_MASK(x) (GENMASK(7, 0) << (8 * ((x) & 0x3)))
281 #define MCP251XFD_REG_FLTCON_FBP(x, fifo) ((fifo) << 8 * ((x) & 0x3))
282 
283 #define MCP251XFD_REG_FLTOBJ(x) (0x1f0 + 0x8 * (x))
284 #define MCP251XFD_REG_FLTOBJ_EXIDE BIT(30)
285 #define MCP251XFD_REG_FLTOBJ_SID11 BIT(29)
286 #define MCP251XFD_REG_FLTOBJ_EID_MASK GENMASK(28, 11)
287 #define MCP251XFD_REG_FLTOBJ_SID_MASK GENMASK(10, 0)
288 
289 #define MCP251XFD_REG_FLTMASK(x) (0x1f4 + 0x8 * (x))
290 #define MCP251XFD_REG_MASK_MIDE BIT(30)
291 #define MCP251XFD_REG_MASK_MSID11 BIT(29)
292 #define MCP251XFD_REG_MASK_MEID_MASK GENMASK(28, 11)
293 #define MCP251XFD_REG_MASK_MSID_MASK GENMASK(10, 0)
294 
295 /* RAM */
296 #define MCP251XFD_RAM_START 0x400
297 #define MCP251XFD_RAM_SIZE SZ_2K
298 
299 /* Message Object */
300 #define MCP251XFD_OBJ_ID_SID11 BIT(29)
301 #define MCP251XFD_OBJ_ID_EID_MASK GENMASK(28, 11)
302 #define MCP251XFD_OBJ_ID_SID_MASK GENMASK(10, 0)
303 #define MCP251XFD_OBJ_FLAGS_SEQ_MCP2518FD_MASK GENMASK(31, 9)
304 #define MCP251XFD_OBJ_FLAGS_SEQ_MCP2517FD_MASK GENMASK(15, 9)
305 #define MCP251XFD_OBJ_FLAGS_SEQ_MASK MCP251XFD_OBJ_FLAGS_SEQ_MCP2518FD_MASK
306 #define MCP251XFD_OBJ_FLAGS_ESI BIT(8)
307 #define MCP251XFD_OBJ_FLAGS_FDF BIT(7)
308 #define MCP251XFD_OBJ_FLAGS_BRS BIT(6)
309 #define MCP251XFD_OBJ_FLAGS_RTR BIT(5)
310 #define MCP251XFD_OBJ_FLAGS_IDE BIT(4)
311 #define MCP251XFD_OBJ_FLAGS_DLC_MASK GENMASK(3, 0)
312 
313 #define MCP251XFD_REG_FRAME_EFF_SID_MASK GENMASK(28, 18)
314 #define MCP251XFD_REG_FRAME_EFF_EID_MASK GENMASK(17, 0)
315 
316 /* MCP2517/18FD SFR */
317 #define MCP251XFD_REG_OSC 0xe00
318 #define MCP251XFD_REG_OSC_SCLKRDY BIT(12)
319 #define MCP251XFD_REG_OSC_OSCRDY BIT(10)
320 #define MCP251XFD_REG_OSC_PLLRDY BIT(8)
321 #define MCP251XFD_REG_OSC_CLKODIV_10 3
322 #define MCP251XFD_REG_OSC_CLKODIV_4 2
323 #define MCP251XFD_REG_OSC_CLKODIV_2 1
324 #define MCP251XFD_REG_OSC_CLKODIV_1 0
325 #define MCP251XFD_REG_OSC_CLKODIV_MASK GENMASK(6, 5)
326 #define MCP251XFD_REG_OSC_SCLKDIV BIT(4)
327 #define MCP251XFD_REG_OSC_LPMEN BIT(3)	/* MCP2518FD only */
328 #define MCP251XFD_REG_OSC_OSCDIS BIT(2)
329 #define MCP251XFD_REG_OSC_PLLEN BIT(0)
330 
331 #define MCP251XFD_REG_IOCON 0xe04
332 #define MCP251XFD_REG_IOCON_INTOD BIT(30)
333 #define MCP251XFD_REG_IOCON_SOF BIT(29)
334 #define MCP251XFD_REG_IOCON_TXCANOD BIT(28)
335 #define MCP251XFD_REG_IOCON_PM1 BIT(25)
336 #define MCP251XFD_REG_IOCON_PM0 BIT(24)
337 #define MCP251XFD_REG_IOCON_GPIO1 BIT(17)
338 #define MCP251XFD_REG_IOCON_GPIO0 BIT(16)
339 #define MCP251XFD_REG_IOCON_LAT1 BIT(9)
340 #define MCP251XFD_REG_IOCON_LAT0 BIT(8)
341 #define MCP251XFD_REG_IOCON_XSTBYEN BIT(6)
342 #define MCP251XFD_REG_IOCON_TRIS1 BIT(1)
343 #define MCP251XFD_REG_IOCON_TRIS0 BIT(0)
344 
345 #define MCP251XFD_REG_CRC 0xe08
346 #define MCP251XFD_REG_CRC_FERRIE BIT(25)
347 #define MCP251XFD_REG_CRC_CRCERRIE BIT(24)
348 #define MCP251XFD_REG_CRC_FERRIF BIT(17)
349 #define MCP251XFD_REG_CRC_CRCERRIF BIT(16)
350 #define MCP251XFD_REG_CRC_IF_MASK GENMASK(17, 16)
351 #define MCP251XFD_REG_CRC_MASK GENMASK(15, 0)
352 
353 #define MCP251XFD_REG_ECCCON 0xe0c
354 #define MCP251XFD_REG_ECCCON_PARITY_MASK GENMASK(14, 8)
355 #define MCP251XFD_REG_ECCCON_DEDIE BIT(2)
356 #define MCP251XFD_REG_ECCCON_SECIE BIT(1)
357 #define MCP251XFD_REG_ECCCON_ECCEN BIT(0)
358 
359 #define MCP251XFD_REG_ECCSTAT 0xe10
360 #define MCP251XFD_REG_ECCSTAT_ERRADDR_MASK GENMASK(27, 16)
361 #define MCP251XFD_REG_ECCSTAT_IF_MASK GENMASK(2, 1)
362 #define MCP251XFD_REG_ECCSTAT_DEDIF BIT(2)
363 #define MCP251XFD_REG_ECCSTAT_SECIF BIT(1)
364 
365 #define MCP251XFD_REG_DEVID 0xe14	/* MCP2518FD only */
366 #define MCP251XFD_REG_DEVID_ID_MASK GENMASK(7, 4)
367 #define MCP251XFD_REG_DEVID_REV_MASK GENMASK(3, 0)
368 
369 /* number of TX FIFO objects, depending on CAN mode
370  *
371  * FIFO setup: tef: 8*12 bytes = 96 bytes, tx: 8*16 bytes = 128 bytes
372  * FIFO setup: tef: 4*12 bytes = 48 bytes, tx: 4*72 bytes = 288 bytes
373  */
374 #define MCP251XFD_RX_OBJ_NUM_MAX 32
375 #define MCP251XFD_TX_OBJ_NUM_CAN 8
376 #define MCP251XFD_TX_OBJ_NUM_CANFD 4
377 
378 #if MCP251XFD_TX_OBJ_NUM_CAN > MCP251XFD_TX_OBJ_NUM_CANFD
379 #define MCP251XFD_TX_OBJ_NUM_MAX MCP251XFD_TX_OBJ_NUM_CAN
380 #else
381 #define MCP251XFD_TX_OBJ_NUM_MAX MCP251XFD_TX_OBJ_NUM_CANFD
382 #endif
383 
384 #define MCP251XFD_NAPI_WEIGHT 32
385 #define MCP251XFD_TX_FIFO 1
386 #define MCP251XFD_RX_FIFO(x) (MCP251XFD_TX_FIFO + 1 + (x))
387 
388 /* SPI commands */
389 #define MCP251XFD_SPI_INSTRUCTION_RESET 0x0000
390 #define MCP251XFD_SPI_INSTRUCTION_WRITE 0x2000
391 #define MCP251XFD_SPI_INSTRUCTION_READ 0x3000
392 #define MCP251XFD_SPI_INSTRUCTION_WRITE_CRC 0xa000
393 #define MCP251XFD_SPI_INSTRUCTION_READ_CRC 0xb000
394 #define MCP251XFD_SPI_INSTRUCTION_WRITE_CRC_SAFE 0xc000
395 #define MCP251XFD_SPI_ADDRESS_MASK GENMASK(11, 0)
396 
397 #define MCP251XFD_SYSCLOCK_HZ_MAX 40000000
398 #define MCP251XFD_SYSCLOCK_HZ_MIN 1000000
399 #define MCP251XFD_SPICLOCK_HZ_MAX 20000000
400 #define MCP251XFD_TIMESTAMP_WORK_DELAY_SEC 45
401 static_assert(MCP251XFD_TIMESTAMP_WORK_DELAY_SEC <
402 	      CYCLECOUNTER_MASK(32) / MCP251XFD_SYSCLOCK_HZ_MAX / 2);
403 #define MCP251XFD_OSC_PLL_MULTIPLIER 10
404 #define MCP251XFD_OSC_STAB_SLEEP_US (3 * USEC_PER_MSEC)
405 #define MCP251XFD_OSC_STAB_TIMEOUT_US (10 * MCP251XFD_OSC_STAB_SLEEP_US)
406 #define MCP251XFD_POLL_SLEEP_US (10)
407 #define MCP251XFD_POLL_TIMEOUT_US (USEC_PER_MSEC)
408 #define MCP251XFD_SOFTRESET_RETRIES_MAX 3
409 #define MCP251XFD_READ_CRC_RETRIES_MAX 3
410 #define MCP251XFD_ECC_CNT_MAX 2
411 #define MCP251XFD_SANITIZE_SPI 1
412 #define MCP251XFD_SANITIZE_CAN 1
413 
414 /* Silence TX MAB overflow warnings */
415 #define MCP251XFD_QUIRK_MAB_NO_WARN BIT(0)
416 /* Use CRC to access registers */
417 #define MCP251XFD_QUIRK_CRC_REG BIT(1)
418 /* Use CRC to access RX/TEF-RAM */
419 #define MCP251XFD_QUIRK_CRC_RX BIT(2)
420 /* Use CRC to access TX-RAM */
421 #define MCP251XFD_QUIRK_CRC_TX BIT(3)
422 /* Enable ECC for RAM */
423 #define MCP251XFD_QUIRK_ECC BIT(4)
424 /* Use Half Duplex SPI transfers */
425 #define MCP251XFD_QUIRK_HALF_DUPLEX BIT(5)
426 
427 struct mcp251xfd_hw_tef_obj {
428 	u32 id;
429 	u32 flags;
430 	u32 ts;
431 };
432 
433 /* The tx_obj_raw version is used in spi async, i.e. without
434  * regmap. We have to take care of endianness ourselves.
435  */
436 struct mcp251xfd_hw_tx_obj_raw {
437 	__le32 id;
438 	__le32 flags;
439 	u8 data[sizeof_field(struct canfd_frame, data)];
440 };
441 
442 struct mcp251xfd_hw_tx_obj_can {
443 	u32 id;
444 	u32 flags;
445 	u8 data[sizeof_field(struct can_frame, data)];
446 };
447 
448 struct mcp251xfd_hw_tx_obj_canfd {
449 	u32 id;
450 	u32 flags;
451 	u8 data[sizeof_field(struct canfd_frame, data)];
452 };
453 
454 struct mcp251xfd_hw_rx_obj_can {
455 	u32 id;
456 	u32 flags;
457 	u32 ts;
458 	u8 data[sizeof_field(struct can_frame, data)];
459 };
460 
461 struct mcp251xfd_hw_rx_obj_canfd {
462 	u32 id;
463 	u32 flags;
464 	u32 ts;
465 	u8 data[sizeof_field(struct canfd_frame, data)];
466 };
467 
468 struct __packed mcp251xfd_buf_cmd {
469 	__be16 cmd;
470 };
471 
472 struct __packed mcp251xfd_buf_cmd_crc {
473 	__be16 cmd;
474 	u8 len;
475 };
476 
477 union mcp251xfd_tx_obj_load_buf {
478 	struct __packed {
479 		struct mcp251xfd_buf_cmd cmd;
480 		struct mcp251xfd_hw_tx_obj_raw hw_tx_obj;
481 	} nocrc;
482 	struct __packed {
483 		struct mcp251xfd_buf_cmd_crc cmd;
484 		struct mcp251xfd_hw_tx_obj_raw hw_tx_obj;
485 		__be16 crc;
486 	} crc;
487 } ____cacheline_aligned;
488 
489 union mcp251xfd_write_reg_buf {
490 	struct __packed {
491 		struct mcp251xfd_buf_cmd cmd;
492 		u8 data[4];
493 	} nocrc;
494 	struct __packed {
495 		struct mcp251xfd_buf_cmd_crc cmd;
496 		u8 data[4];
497 		__be16 crc;
498 	} crc;
499 } ____cacheline_aligned;
500 
501 struct mcp251xfd_tx_obj {
502 	struct spi_message msg;
503 	struct spi_transfer xfer[2];
504 	union mcp251xfd_tx_obj_load_buf buf;
505 };
506 
507 struct mcp251xfd_tef_ring {
508 	unsigned int head;
509 	unsigned int tail;
510 
511 	/* u8 obj_num equals tx_ring->obj_num */
512 	/* u8 obj_size equals sizeof(struct mcp251xfd_hw_tef_obj) */
513 
514 	union mcp251xfd_write_reg_buf uinc_buf;
515 	struct spi_transfer uinc_xfer[MCP251XFD_TX_OBJ_NUM_MAX];
516 };
517 
518 struct mcp251xfd_tx_ring {
519 	unsigned int head;
520 	unsigned int tail;
521 
522 	u16 base;
523 	u8 obj_num;
524 	u8 obj_size;
525 
526 	struct mcp251xfd_tx_obj obj[MCP251XFD_TX_OBJ_NUM_MAX];
527 	union mcp251xfd_write_reg_buf rts_buf;
528 };
529 
530 struct mcp251xfd_rx_ring {
531 	unsigned int head;
532 	unsigned int tail;
533 
534 	u16 base;
535 	u8 nr;
536 	u8 fifo_nr;
537 	u8 obj_num;
538 	u8 obj_size;
539 
540 	union mcp251xfd_write_reg_buf uinc_buf;
541 	struct spi_transfer uinc_xfer[MCP251XFD_RX_OBJ_NUM_MAX];
542 	struct mcp251xfd_hw_rx_obj_canfd obj[];
543 };
544 
545 struct __packed mcp251xfd_map_buf_nocrc {
546 	struct mcp251xfd_buf_cmd cmd;
547 	u8 data[256];
548 } ____cacheline_aligned;
549 
550 struct __packed mcp251xfd_map_buf_crc {
551 	struct mcp251xfd_buf_cmd_crc cmd;
552 	u8 data[256 - 4];
553 	__be16 crc;
554 } ____cacheline_aligned;
555 
556 struct mcp251xfd_ecc {
557 	u32 ecc_stat;
558 	int cnt;
559 };
560 
561 struct mcp251xfd_regs_status {
562 	u32 intf;
563 };
564 
565 enum mcp251xfd_model {
566 	MCP251XFD_MODEL_MCP2517FD = 0x2517,
567 	MCP251XFD_MODEL_MCP2518FD = 0x2518,
568 	MCP251XFD_MODEL_MCP251XFD = 0xffff,	/* autodetect model */
569 };
570 
571 struct mcp251xfd_devtype_data {
572 	enum mcp251xfd_model model;
573 	u32 quirks;
574 };
575 
576 struct mcp251xfd_priv {
577 	struct can_priv can;
578 	struct can_rx_offload offload;
579 	struct net_device *ndev;
580 
581 	struct regmap *map_reg;			/* register access */
582 	struct regmap *map_rx;			/* RX/TEF RAM access */
583 
584 	struct regmap *map_nocrc;
585 	struct mcp251xfd_map_buf_nocrc *map_buf_nocrc_rx;
586 	struct mcp251xfd_map_buf_nocrc *map_buf_nocrc_tx;
587 
588 	struct regmap *map_crc;
589 	struct mcp251xfd_map_buf_crc *map_buf_crc_rx;
590 	struct mcp251xfd_map_buf_crc *map_buf_crc_tx;
591 
592 	struct spi_device *spi;
593 	u32 spi_max_speed_hz_orig;
594 
595 	struct mcp251xfd_tef_ring tef[1];
596 	struct mcp251xfd_tx_ring tx[1];
597 	struct mcp251xfd_rx_ring *rx[1];
598 
599 	u8 rx_ring_num;
600 
601 	struct mcp251xfd_ecc ecc;
602 	struct mcp251xfd_regs_status regs_status;
603 
604 	struct cyclecounter cc;
605 	struct timecounter tc;
606 	struct delayed_work timestamp;
607 
608 	struct gpio_desc *rx_int;
609 	struct clk *clk;
610 	struct regulator *reg_vdd;
611 	struct regulator *reg_xceiver;
612 
613 	struct mcp251xfd_devtype_data devtype_data;
614 	struct can_berr_counter bec;
615 };
616 
617 #define MCP251XFD_IS(_model) \
618 static inline bool \
619 mcp251xfd_is_##_model(const struct mcp251xfd_priv *priv) \
620 { \
621 	return priv->devtype_data.model == MCP251XFD_MODEL_MCP##_model##FD; \
622 }
623 
624 MCP251XFD_IS(2517);
625 MCP251XFD_IS(2518);
626 MCP251XFD_IS(251X);
627 
628 static inline u8 mcp251xfd_first_byte_set(u32 mask)
629 {
630 	return (mask & 0x0000ffff) ?
631 		((mask & 0x000000ff) ? 0 : 1) :
632 		((mask & 0x00ff0000) ? 2 : 3);
633 }
634 
635 static inline u8 mcp251xfd_last_byte_set(u32 mask)
636 {
637 	return (mask & 0xffff0000) ?
638 		((mask & 0xff000000) ? 3 : 2) :
639 		((mask & 0x0000ff00) ? 1 : 0);
640 }
641 
642 static inline __be16 mcp251xfd_cmd_reset(void)
643 {
644 	return cpu_to_be16(MCP251XFD_SPI_INSTRUCTION_RESET);
645 }
646 
647 static inline void
648 mcp251xfd_spi_cmd_read_nocrc(struct mcp251xfd_buf_cmd *cmd, u16 addr)
649 {
650 	cmd->cmd = cpu_to_be16(MCP251XFD_SPI_INSTRUCTION_READ | addr);
651 }
652 
653 static inline void
654 mcp251xfd_spi_cmd_write_nocrc(struct mcp251xfd_buf_cmd *cmd, u16 addr)
655 {
656 	cmd->cmd = cpu_to_be16(MCP251XFD_SPI_INSTRUCTION_WRITE | addr);
657 }
658 
659 static inline bool mcp251xfd_reg_in_ram(unsigned int reg)
660 {
661 	static const struct regmap_range range =
662 		regmap_reg_range(MCP251XFD_RAM_START,
663 				 MCP251XFD_RAM_START + MCP251XFD_RAM_SIZE - 4);
664 
665 	return regmap_reg_in_range(reg, &range);
666 }
667 
668 static inline void
669 __mcp251xfd_spi_cmd_crc_set_len(struct mcp251xfd_buf_cmd_crc *cmd,
670 				u16 len, bool in_ram)
671 {
672 	/* Number of u32 for RAM access, number of u8 otherwise. */
673 	if (in_ram)
674 		cmd->len = len >> 2;
675 	else
676 		cmd->len = len;
677 }
678 
679 static inline void
680 mcp251xfd_spi_cmd_crc_set_len_in_ram(struct mcp251xfd_buf_cmd_crc *cmd, u16 len)
681 {
682 	__mcp251xfd_spi_cmd_crc_set_len(cmd, len, true);
683 }
684 
685 static inline void
686 mcp251xfd_spi_cmd_crc_set_len_in_reg(struct mcp251xfd_buf_cmd_crc *cmd, u16 len)
687 {
688 	__mcp251xfd_spi_cmd_crc_set_len(cmd, len, false);
689 }
690 
691 static inline void
692 mcp251xfd_spi_cmd_read_crc_set_addr(struct mcp251xfd_buf_cmd_crc *cmd, u16 addr)
693 {
694 	cmd->cmd = cpu_to_be16(MCP251XFD_SPI_INSTRUCTION_READ_CRC | addr);
695 }
696 
697 static inline void
698 mcp251xfd_spi_cmd_read_crc(struct mcp251xfd_buf_cmd_crc *cmd,
699 			   u16 addr, u16 len)
700 {
701 	mcp251xfd_spi_cmd_read_crc_set_addr(cmd, addr);
702 	__mcp251xfd_spi_cmd_crc_set_len(cmd, len, mcp251xfd_reg_in_ram(addr));
703 }
704 
705 static inline void
706 mcp251xfd_spi_cmd_write_crc_set_addr(struct mcp251xfd_buf_cmd_crc *cmd,
707 				     u16 addr)
708 {
709 	cmd->cmd = cpu_to_be16(MCP251XFD_SPI_INSTRUCTION_WRITE_CRC | addr);
710 }
711 
712 static inline void
713 mcp251xfd_spi_cmd_write_crc(struct mcp251xfd_buf_cmd_crc *cmd,
714 			    u16 addr, u16 len)
715 {
716 	mcp251xfd_spi_cmd_write_crc_set_addr(cmd, addr);
717 	__mcp251xfd_spi_cmd_crc_set_len(cmd, len, mcp251xfd_reg_in_ram(addr));
718 }
719 
720 static inline u8 *
721 mcp251xfd_spi_cmd_write(const struct mcp251xfd_priv *priv,
722 			union mcp251xfd_write_reg_buf *write_reg_buf,
723 			u16 addr)
724 {
725 	u8 *data;
726 
727 	if (priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_REG) {
728 		mcp251xfd_spi_cmd_write_crc_set_addr(&write_reg_buf->crc.cmd,
729 						     addr);
730 		data = write_reg_buf->crc.data;
731 	} else {
732 		mcp251xfd_spi_cmd_write_nocrc(&write_reg_buf->nocrc.cmd,
733 					      addr);
734 		data = write_reg_buf->nocrc.data;
735 	}
736 
737 	return data;
738 }
739 
740 static inline int mcp251xfd_get_timestamp(const struct mcp251xfd_priv *priv,
741 					  u32 *timestamp)
742 {
743 	return regmap_read(priv->map_reg, MCP251XFD_REG_TBC, timestamp);
744 }
745 
746 static inline u16 mcp251xfd_get_tef_obj_addr(u8 n)
747 {
748 	return MCP251XFD_RAM_START +
749 		sizeof(struct mcp251xfd_hw_tef_obj) * n;
750 }
751 
752 static inline u16
753 mcp251xfd_get_tx_obj_addr(const struct mcp251xfd_tx_ring *ring, u8 n)
754 {
755 	return ring->base + ring->obj_size * n;
756 }
757 
758 static inline u16
759 mcp251xfd_get_rx_obj_addr(const struct mcp251xfd_rx_ring *ring, u8 n)
760 {
761 	return ring->base + ring->obj_size * n;
762 }
763 
764 static inline u8 mcp251xfd_get_tef_head(const struct mcp251xfd_priv *priv)
765 {
766 	return priv->tef->head & (priv->tx->obj_num - 1);
767 }
768 
769 static inline u8 mcp251xfd_get_tef_tail(const struct mcp251xfd_priv *priv)
770 {
771 	return priv->tef->tail & (priv->tx->obj_num - 1);
772 }
773 
774 static inline u8 mcp251xfd_get_tef_len(const struct mcp251xfd_priv *priv)
775 {
776 	return priv->tef->head - priv->tef->tail;
777 }
778 
779 static inline u8 mcp251xfd_get_tef_linear_len(const struct mcp251xfd_priv *priv)
780 {
781 	u8 len;
782 
783 	len = mcp251xfd_get_tef_len(priv);
784 
785 	return min_t(u8, len, priv->tx->obj_num - mcp251xfd_get_tef_tail(priv));
786 }
787 
788 static inline u8 mcp251xfd_get_tx_head(const struct mcp251xfd_tx_ring *ring)
789 {
790 	return ring->head & (ring->obj_num - 1);
791 }
792 
793 static inline u8 mcp251xfd_get_tx_tail(const struct mcp251xfd_tx_ring *ring)
794 {
795 	return ring->tail & (ring->obj_num - 1);
796 }
797 
798 static inline u8 mcp251xfd_get_tx_free(const struct mcp251xfd_tx_ring *ring)
799 {
800 	return ring->obj_num - (ring->head - ring->tail);
801 }
802 
803 static inline int
804 mcp251xfd_get_tx_nr_by_addr(const struct mcp251xfd_tx_ring *tx_ring, u8 *nr,
805 			    u16 addr)
806 {
807 	if (addr < mcp251xfd_get_tx_obj_addr(tx_ring, 0) ||
808 	    addr >= mcp251xfd_get_tx_obj_addr(tx_ring, tx_ring->obj_num))
809 		return -ENOENT;
810 
811 	*nr = (addr - mcp251xfd_get_tx_obj_addr(tx_ring, 0)) /
812 		tx_ring->obj_size;
813 
814 	return 0;
815 }
816 
817 static inline u8 mcp251xfd_get_rx_head(const struct mcp251xfd_rx_ring *ring)
818 {
819 	return ring->head & (ring->obj_num - 1);
820 }
821 
822 static inline u8 mcp251xfd_get_rx_tail(const struct mcp251xfd_rx_ring *ring)
823 {
824 	return ring->tail & (ring->obj_num - 1);
825 }
826 
827 static inline u8 mcp251xfd_get_rx_len(const struct mcp251xfd_rx_ring *ring)
828 {
829 	return ring->head - ring->tail;
830 }
831 
832 static inline u8
833 mcp251xfd_get_rx_linear_len(const struct mcp251xfd_rx_ring *ring)
834 {
835 	u8 len;
836 
837 	len = mcp251xfd_get_rx_len(ring);
838 
839 	return min_t(u8, len, ring->obj_num - mcp251xfd_get_rx_tail(ring));
840 }
841 
842 #define mcp251xfd_for_each_tx_obj(ring, _obj, n) \
843 	for ((n) = 0, (_obj) = &(ring)->obj[(n)]; \
844 	     (n) < (ring)->obj_num; \
845 	     (n)++, (_obj) = &(ring)->obj[(n)])
846 
847 #define mcp251xfd_for_each_rx_ring(priv, ring, n) \
848 	for ((n) = 0, (ring) = *((priv)->rx + (n)); \
849 	     (n) < (priv)->rx_ring_num; \
850 	     (n)++, (ring) = *((priv)->rx + (n)))
851 
852 int mcp251xfd_regmap_init(struct mcp251xfd_priv *priv);
853 u16 mcp251xfd_crc16_compute2(const void *cmd, size_t cmd_size,
854 			     const void *data, size_t data_size);
855 u16 mcp251xfd_crc16_compute(const void *data, size_t data_size);
856 void mcp251xfd_skb_set_timestamp(struct mcp251xfd_priv *priv,
857 				 struct sk_buff *skb, u32 timestamp);
858 void mcp251xfd_timestamp_init(struct mcp251xfd_priv *priv);
859 void mcp251xfd_timestamp_stop(struct mcp251xfd_priv *priv);
860 
861 #if IS_ENABLED(CONFIG_DEV_COREDUMP)
862 void mcp251xfd_dump(const struct mcp251xfd_priv *priv);
863 #else
864 static inline void mcp251xfd_dump(const struct mcp251xfd_priv *priv)
865 {
866 }
867 #endif
868 
869 #endif
870