1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // mcp251xfd - Microchip MCP251xFD Family CAN controller driver 4 // 5 // Copyright (c) 2019, 2020, 2021 Pengutronix, 6 // Marc Kleine-Budde <kernel@pengutronix.de> 7 // 8 // Based on: 9 // 10 // CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface 11 // 12 // Copyright (c) 2019 Martin Sperl <kernel@martin.sperl.org> 13 // 14 15 #include <linux/bitfield.h> 16 #include <linux/clk.h> 17 #include <linux/device.h> 18 #include <linux/mod_devicetable.h> 19 #include <linux/module.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/property.h> 22 23 #include "mcp251xfd.h" 24 25 #define DEVICE_NAME "mcp251xfd" 26 27 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp2517fd = { 28 .quirks = MCP251XFD_QUIRK_MAB_NO_WARN | MCP251XFD_QUIRK_CRC_REG | 29 MCP251XFD_QUIRK_CRC_RX | MCP251XFD_QUIRK_CRC_TX | 30 MCP251XFD_QUIRK_ECC, 31 .model = MCP251XFD_MODEL_MCP2517FD, 32 }; 33 34 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp2518fd = { 35 .quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX | 36 MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC, 37 .model = MCP251XFD_MODEL_MCP2518FD, 38 }; 39 40 /* Autodetect model, start with CRC enabled. */ 41 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp251xfd = { 42 .quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX | 43 MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC, 44 .model = MCP251XFD_MODEL_MCP251XFD, 45 }; 46 47 static const struct can_bittiming_const mcp251xfd_bittiming_const = { 48 .name = DEVICE_NAME, 49 .tseg1_min = 2, 50 .tseg1_max = 256, 51 .tseg2_min = 1, 52 .tseg2_max = 128, 53 .sjw_max = 128, 54 .brp_min = 1, 55 .brp_max = 256, 56 .brp_inc = 1, 57 }; 58 59 static const struct can_bittiming_const mcp251xfd_data_bittiming_const = { 60 .name = DEVICE_NAME, 61 .tseg1_min = 1, 62 .tseg1_max = 32, 63 .tseg2_min = 1, 64 .tseg2_max = 16, 65 .sjw_max = 16, 66 .brp_min = 1, 67 .brp_max = 256, 68 .brp_inc = 1, 69 }; 70 71 static const char *__mcp251xfd_get_model_str(enum mcp251xfd_model model) 72 { 73 switch (model) { 74 case MCP251XFD_MODEL_MCP2517FD: 75 return "MCP2517FD"; 76 case MCP251XFD_MODEL_MCP2518FD: 77 return "MCP2518FD"; 78 case MCP251XFD_MODEL_MCP251XFD: 79 return "MCP251xFD"; 80 } 81 82 return "<unknown>"; 83 } 84 85 static inline const char * 86 mcp251xfd_get_model_str(const struct mcp251xfd_priv *priv) 87 { 88 return __mcp251xfd_get_model_str(priv->devtype_data.model); 89 } 90 91 static const char *mcp251xfd_get_mode_str(const u8 mode) 92 { 93 switch (mode) { 94 case MCP251XFD_REG_CON_MODE_MIXED: 95 return "Mixed (CAN FD/CAN 2.0)"; 96 case MCP251XFD_REG_CON_MODE_SLEEP: 97 return "Sleep"; 98 case MCP251XFD_REG_CON_MODE_INT_LOOPBACK: 99 return "Internal Loopback"; 100 case MCP251XFD_REG_CON_MODE_LISTENONLY: 101 return "Listen Only"; 102 case MCP251XFD_REG_CON_MODE_CONFIG: 103 return "Configuration"; 104 case MCP251XFD_REG_CON_MODE_EXT_LOOPBACK: 105 return "External Loopback"; 106 case MCP251XFD_REG_CON_MODE_CAN2_0: 107 return "CAN 2.0"; 108 case MCP251XFD_REG_CON_MODE_RESTRICTED: 109 return "Restricted Operation"; 110 } 111 112 return "<unknown>"; 113 } 114 115 static inline int mcp251xfd_vdd_enable(const struct mcp251xfd_priv *priv) 116 { 117 if (!priv->reg_vdd) 118 return 0; 119 120 return regulator_enable(priv->reg_vdd); 121 } 122 123 static inline int mcp251xfd_vdd_disable(const struct mcp251xfd_priv *priv) 124 { 125 if (!priv->reg_vdd) 126 return 0; 127 128 return regulator_disable(priv->reg_vdd); 129 } 130 131 static inline int 132 mcp251xfd_transceiver_enable(const struct mcp251xfd_priv *priv) 133 { 134 if (!priv->reg_xceiver) 135 return 0; 136 137 return regulator_enable(priv->reg_xceiver); 138 } 139 140 static inline int 141 mcp251xfd_transceiver_disable(const struct mcp251xfd_priv *priv) 142 { 143 if (!priv->reg_xceiver) 144 return 0; 145 146 return regulator_disable(priv->reg_xceiver); 147 } 148 149 static int mcp251xfd_clks_and_vdd_enable(const struct mcp251xfd_priv *priv) 150 { 151 int err; 152 153 err = clk_prepare_enable(priv->clk); 154 if (err) 155 return err; 156 157 err = mcp251xfd_vdd_enable(priv); 158 if (err) 159 clk_disable_unprepare(priv->clk); 160 161 /* Wait for oscillator stabilisation time after power up */ 162 usleep_range(MCP251XFD_OSC_STAB_SLEEP_US, 163 2 * MCP251XFD_OSC_STAB_SLEEP_US); 164 165 return err; 166 } 167 168 static int mcp251xfd_clks_and_vdd_disable(const struct mcp251xfd_priv *priv) 169 { 170 int err; 171 172 err = mcp251xfd_vdd_disable(priv); 173 if (err) 174 return err; 175 176 clk_disable_unprepare(priv->clk); 177 178 return 0; 179 } 180 181 static inline int 182 mcp251xfd_chip_get_mode(const struct mcp251xfd_priv *priv, u8 *mode) 183 { 184 u32 val; 185 int err; 186 187 err = regmap_read(priv->map_reg, MCP251XFD_REG_CON, &val); 188 if (err) 189 return err; 190 191 *mode = FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK, val); 192 193 return 0; 194 } 195 196 static int 197 __mcp251xfd_chip_set_mode(const struct mcp251xfd_priv *priv, 198 const u8 mode_req, bool nowait) 199 { 200 u32 con, con_reqop; 201 int err; 202 203 con_reqop = FIELD_PREP(MCP251XFD_REG_CON_REQOP_MASK, mode_req); 204 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_CON, 205 MCP251XFD_REG_CON_REQOP_MASK, con_reqop); 206 if (err) 207 return err; 208 209 if (mode_req == MCP251XFD_REG_CON_MODE_SLEEP || nowait) 210 return 0; 211 212 err = regmap_read_poll_timeout(priv->map_reg, MCP251XFD_REG_CON, con, 213 FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK, 214 con) == mode_req, 215 MCP251XFD_POLL_SLEEP_US, 216 MCP251XFD_POLL_TIMEOUT_US); 217 if (err) { 218 u8 mode = FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK, con); 219 220 netdev_err(priv->ndev, 221 "Controller failed to enter mode %s Mode (%u) and stays in %s Mode (%u).\n", 222 mcp251xfd_get_mode_str(mode_req), mode_req, 223 mcp251xfd_get_mode_str(mode), mode); 224 return err; 225 } 226 227 return 0; 228 } 229 230 static inline int 231 mcp251xfd_chip_set_mode(const struct mcp251xfd_priv *priv, 232 const u8 mode_req) 233 { 234 return __mcp251xfd_chip_set_mode(priv, mode_req, false); 235 } 236 237 static inline int __maybe_unused 238 mcp251xfd_chip_set_mode_nowait(const struct mcp251xfd_priv *priv, 239 const u8 mode_req) 240 { 241 return __mcp251xfd_chip_set_mode(priv, mode_req, true); 242 } 243 244 static inline bool mcp251xfd_osc_invalid(u32 reg) 245 { 246 return reg == 0x0 || reg == 0xffffffff; 247 } 248 249 static int mcp251xfd_chip_clock_enable(const struct mcp251xfd_priv *priv) 250 { 251 u32 osc, osc_reference, osc_mask; 252 int err; 253 254 /* Set Power On Defaults for "Clock Output Divisor" and remove 255 * "Oscillator Disable" bit. 256 */ 257 osc = FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK, 258 MCP251XFD_REG_OSC_CLKODIV_10); 259 osc_reference = MCP251XFD_REG_OSC_OSCRDY; 260 osc_mask = MCP251XFD_REG_OSC_OSCRDY | MCP251XFD_REG_OSC_PLLRDY; 261 262 /* Note: 263 * 264 * If the controller is in Sleep Mode the following write only 265 * removes the "Oscillator Disable" bit and powers it up. All 266 * other bits are unaffected. 267 */ 268 err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc); 269 if (err) 270 return err; 271 272 /* Wait for "Oscillator Ready" bit */ 273 err = regmap_read_poll_timeout(priv->map_reg, MCP251XFD_REG_OSC, osc, 274 (osc & osc_mask) == osc_reference, 275 MCP251XFD_OSC_STAB_SLEEP_US, 276 MCP251XFD_OSC_STAB_TIMEOUT_US); 277 if (mcp251xfd_osc_invalid(osc)) { 278 netdev_err(priv->ndev, 279 "Failed to detect %s (osc=0x%08x).\n", 280 mcp251xfd_get_model_str(priv), osc); 281 return -ENODEV; 282 } else if (err == -ETIMEDOUT) { 283 netdev_err(priv->ndev, 284 "Timeout waiting for Oscillator Ready (osc=0x%08x, osc_reference=0x%08x)\n", 285 osc, osc_reference); 286 return -ETIMEDOUT; 287 } 288 289 return err; 290 } 291 292 static int mcp251xfd_chip_softreset_do(const struct mcp251xfd_priv *priv) 293 { 294 const __be16 cmd = mcp251xfd_cmd_reset(); 295 int err; 296 297 /* The Set Mode and SPI Reset command only seems to works if 298 * the controller is not in Sleep Mode. 299 */ 300 err = mcp251xfd_chip_clock_enable(priv); 301 if (err) 302 return err; 303 304 err = mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_CONFIG); 305 if (err) 306 return err; 307 308 /* spi_write_then_read() works with non DMA-safe buffers */ 309 return spi_write_then_read(priv->spi, &cmd, sizeof(cmd), NULL, 0); 310 } 311 312 static int mcp251xfd_chip_softreset_check(const struct mcp251xfd_priv *priv) 313 { 314 u32 osc, osc_reference; 315 u8 mode; 316 int err; 317 318 err = mcp251xfd_chip_get_mode(priv, &mode); 319 if (err) 320 return err; 321 322 if (mode != MCP251XFD_REG_CON_MODE_CONFIG) { 323 netdev_info(priv->ndev, 324 "Controller not in Config Mode after reset, but in %s Mode (%u).\n", 325 mcp251xfd_get_mode_str(mode), mode); 326 return -ETIMEDOUT; 327 } 328 329 osc_reference = MCP251XFD_REG_OSC_OSCRDY | 330 FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK, 331 MCP251XFD_REG_OSC_CLKODIV_10); 332 333 /* check reset defaults of OSC reg */ 334 err = regmap_read(priv->map_reg, MCP251XFD_REG_OSC, &osc); 335 if (err) 336 return err; 337 338 if (osc != osc_reference) { 339 netdev_info(priv->ndev, 340 "Controller failed to reset. osc=0x%08x, reference value=0x%08x.\n", 341 osc, osc_reference); 342 return -ETIMEDOUT; 343 } 344 345 return 0; 346 } 347 348 static int mcp251xfd_chip_softreset(const struct mcp251xfd_priv *priv) 349 { 350 int err, i; 351 352 for (i = 0; i < MCP251XFD_SOFTRESET_RETRIES_MAX; i++) { 353 if (i) 354 netdev_info(priv->ndev, 355 "Retrying to reset controller.\n"); 356 357 err = mcp251xfd_chip_softreset_do(priv); 358 if (err == -ETIMEDOUT) 359 continue; 360 if (err) 361 return err; 362 363 err = mcp251xfd_chip_softreset_check(priv); 364 if (err == -ETIMEDOUT) 365 continue; 366 if (err) 367 return err; 368 369 return 0; 370 } 371 372 return err; 373 } 374 375 static int mcp251xfd_chip_clock_init(const struct mcp251xfd_priv *priv) 376 { 377 u32 osc; 378 int err; 379 380 /* Activate Low Power Mode on Oscillator Disable. This only 381 * works on the MCP2518FD. The MCP2517FD will go into normal 382 * Sleep Mode instead. 383 */ 384 osc = MCP251XFD_REG_OSC_LPMEN | 385 FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK, 386 MCP251XFD_REG_OSC_CLKODIV_10); 387 err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc); 388 if (err) 389 return err; 390 391 /* Set Time Base Counter Prescaler to 1. 392 * 393 * This means an overflow of the 32 bit Time Base Counter 394 * register at 40 MHz every 107 seconds. 395 */ 396 return regmap_write(priv->map_reg, MCP251XFD_REG_TSCON, 397 MCP251XFD_REG_TSCON_TBCEN); 398 } 399 400 static int mcp251xfd_set_bittiming(const struct mcp251xfd_priv *priv) 401 { 402 const struct can_bittiming *bt = &priv->can.bittiming; 403 const struct can_bittiming *dbt = &priv->can.data_bittiming; 404 u32 val = 0; 405 s8 tdco; 406 int err; 407 408 /* CAN Control Register 409 * 410 * - no transmit bandwidth sharing 411 * - config mode 412 * - disable transmit queue 413 * - store in transmit FIFO event 414 * - transition to restricted operation mode on system error 415 * - ESI is transmitted recessive when ESI of message is high or 416 * CAN controller error passive 417 * - restricted retransmission attempts, 418 * use TQXCON_TXAT and FIFOCON_TXAT 419 * - wake-up filter bits T11FILTER 420 * - use CAN bus line filter for wakeup 421 * - protocol exception is treated as a form error 422 * - Do not compare data bytes 423 */ 424 val = FIELD_PREP(MCP251XFD_REG_CON_REQOP_MASK, 425 MCP251XFD_REG_CON_MODE_CONFIG) | 426 MCP251XFD_REG_CON_STEF | 427 MCP251XFD_REG_CON_ESIGM | 428 MCP251XFD_REG_CON_RTXAT | 429 FIELD_PREP(MCP251XFD_REG_CON_WFT_MASK, 430 MCP251XFD_REG_CON_WFT_T11FILTER) | 431 MCP251XFD_REG_CON_WAKFIL | 432 MCP251XFD_REG_CON_PXEDIS; 433 434 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO)) 435 val |= MCP251XFD_REG_CON_ISOCRCEN; 436 437 err = regmap_write(priv->map_reg, MCP251XFD_REG_CON, val); 438 if (err) 439 return err; 440 441 /* Nominal Bit Time */ 442 val = FIELD_PREP(MCP251XFD_REG_NBTCFG_BRP_MASK, bt->brp - 1) | 443 FIELD_PREP(MCP251XFD_REG_NBTCFG_TSEG1_MASK, 444 bt->prop_seg + bt->phase_seg1 - 1) | 445 FIELD_PREP(MCP251XFD_REG_NBTCFG_TSEG2_MASK, 446 bt->phase_seg2 - 1) | 447 FIELD_PREP(MCP251XFD_REG_NBTCFG_SJW_MASK, bt->sjw - 1); 448 449 err = regmap_write(priv->map_reg, MCP251XFD_REG_NBTCFG, val); 450 if (err) 451 return err; 452 453 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD)) 454 return 0; 455 456 /* Data Bit Time */ 457 val = FIELD_PREP(MCP251XFD_REG_DBTCFG_BRP_MASK, dbt->brp - 1) | 458 FIELD_PREP(MCP251XFD_REG_DBTCFG_TSEG1_MASK, 459 dbt->prop_seg + dbt->phase_seg1 - 1) | 460 FIELD_PREP(MCP251XFD_REG_DBTCFG_TSEG2_MASK, 461 dbt->phase_seg2 - 1) | 462 FIELD_PREP(MCP251XFD_REG_DBTCFG_SJW_MASK, dbt->sjw - 1); 463 464 err = regmap_write(priv->map_reg, MCP251XFD_REG_DBTCFG, val); 465 if (err) 466 return err; 467 468 /* Transmitter Delay Compensation */ 469 tdco = clamp_t(int, dbt->brp * (dbt->prop_seg + dbt->phase_seg1), 470 -64, 63); 471 val = FIELD_PREP(MCP251XFD_REG_TDC_TDCMOD_MASK, 472 MCP251XFD_REG_TDC_TDCMOD_AUTO) | 473 FIELD_PREP(MCP251XFD_REG_TDC_TDCO_MASK, tdco); 474 475 return regmap_write(priv->map_reg, MCP251XFD_REG_TDC, val); 476 } 477 478 static int mcp251xfd_chip_rx_int_enable(const struct mcp251xfd_priv *priv) 479 { 480 u32 val; 481 482 if (!priv->rx_int) 483 return 0; 484 485 /* Configure GPIOs: 486 * - PIN0: GPIO Input 487 * - PIN1: GPIO Input/RX Interrupt 488 * 489 * PIN1 must be Input, otherwise there is a glitch on the 490 * rx-INT line. It happens between setting the PIN as output 491 * (in the first byte of the SPI transfer) and configuring the 492 * PIN as interrupt (in the last byte of the SPI transfer). 493 */ 494 val = MCP251XFD_REG_IOCON_PM0 | MCP251XFD_REG_IOCON_TRIS1 | 495 MCP251XFD_REG_IOCON_TRIS0; 496 return regmap_write(priv->map_reg, MCP251XFD_REG_IOCON, val); 497 } 498 499 static int mcp251xfd_chip_rx_int_disable(const struct mcp251xfd_priv *priv) 500 { 501 u32 val; 502 503 if (!priv->rx_int) 504 return 0; 505 506 /* Configure GPIOs: 507 * - PIN0: GPIO Input 508 * - PIN1: GPIO Input 509 */ 510 val = MCP251XFD_REG_IOCON_PM1 | MCP251XFD_REG_IOCON_PM0 | 511 MCP251XFD_REG_IOCON_TRIS1 | MCP251XFD_REG_IOCON_TRIS0; 512 return regmap_write(priv->map_reg, MCP251XFD_REG_IOCON, val); 513 } 514 515 static int mcp251xfd_chip_ecc_init(struct mcp251xfd_priv *priv) 516 { 517 struct mcp251xfd_ecc *ecc = &priv->ecc; 518 void *ram; 519 u32 val = 0; 520 int err; 521 522 ecc->ecc_stat = 0; 523 524 if (priv->devtype_data.quirks & MCP251XFD_QUIRK_ECC) 525 val = MCP251XFD_REG_ECCCON_ECCEN; 526 527 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON, 528 MCP251XFD_REG_ECCCON_ECCEN, val); 529 if (err) 530 return err; 531 532 ram = kzalloc(MCP251XFD_RAM_SIZE, GFP_KERNEL); 533 if (!ram) 534 return -ENOMEM; 535 536 err = regmap_raw_write(priv->map_reg, MCP251XFD_RAM_START, ram, 537 MCP251XFD_RAM_SIZE); 538 kfree(ram); 539 540 return err; 541 } 542 543 static u8 mcp251xfd_get_normal_mode(const struct mcp251xfd_priv *priv) 544 { 545 u8 mode; 546 547 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 548 mode = MCP251XFD_REG_CON_MODE_INT_LOOPBACK; 549 else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 550 mode = MCP251XFD_REG_CON_MODE_LISTENONLY; 551 else if (priv->can.ctrlmode & CAN_CTRLMODE_FD) 552 mode = MCP251XFD_REG_CON_MODE_MIXED; 553 else 554 mode = MCP251XFD_REG_CON_MODE_CAN2_0; 555 556 return mode; 557 } 558 559 static int 560 __mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv *priv, 561 bool nowait) 562 { 563 u8 mode; 564 565 mode = mcp251xfd_get_normal_mode(priv); 566 567 return __mcp251xfd_chip_set_mode(priv, mode, nowait); 568 } 569 570 static inline int 571 mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv *priv) 572 { 573 return __mcp251xfd_chip_set_normal_mode(priv, false); 574 } 575 576 static inline int 577 mcp251xfd_chip_set_normal_mode_nowait(const struct mcp251xfd_priv *priv) 578 { 579 return __mcp251xfd_chip_set_normal_mode(priv, true); 580 } 581 582 static int mcp251xfd_chip_interrupts_enable(const struct mcp251xfd_priv *priv) 583 { 584 u32 val; 585 int err; 586 587 val = MCP251XFD_REG_CRC_FERRIE | MCP251XFD_REG_CRC_CRCERRIE; 588 err = regmap_write(priv->map_reg, MCP251XFD_REG_CRC, val); 589 if (err) 590 return err; 591 592 val = MCP251XFD_REG_ECCCON_DEDIE | MCP251XFD_REG_ECCCON_SECIE; 593 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON, val, val); 594 if (err) 595 return err; 596 597 val = MCP251XFD_REG_INT_CERRIE | 598 MCP251XFD_REG_INT_SERRIE | 599 MCP251XFD_REG_INT_RXOVIE | 600 MCP251XFD_REG_INT_TXATIE | 601 MCP251XFD_REG_INT_SPICRCIE | 602 MCP251XFD_REG_INT_ECCIE | 603 MCP251XFD_REG_INT_TEFIE | 604 MCP251XFD_REG_INT_MODIE | 605 MCP251XFD_REG_INT_RXIE; 606 607 if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) 608 val |= MCP251XFD_REG_INT_IVMIE; 609 610 return regmap_write(priv->map_reg, MCP251XFD_REG_INT, val); 611 } 612 613 static int mcp251xfd_chip_interrupts_disable(const struct mcp251xfd_priv *priv) 614 { 615 int err; 616 u32 mask; 617 618 err = regmap_write(priv->map_reg, MCP251XFD_REG_INT, 0); 619 if (err) 620 return err; 621 622 mask = MCP251XFD_REG_ECCCON_DEDIE | MCP251XFD_REG_ECCCON_SECIE; 623 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON, 624 mask, 0x0); 625 if (err) 626 return err; 627 628 return regmap_write(priv->map_reg, MCP251XFD_REG_CRC, 0); 629 } 630 631 static int mcp251xfd_chip_stop(struct mcp251xfd_priv *priv, 632 const enum can_state state) 633 { 634 priv->can.state = state; 635 636 mcp251xfd_chip_interrupts_disable(priv); 637 mcp251xfd_chip_rx_int_disable(priv); 638 return mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_SLEEP); 639 } 640 641 static int mcp251xfd_chip_start(struct mcp251xfd_priv *priv) 642 { 643 int err; 644 645 err = mcp251xfd_chip_softreset(priv); 646 if (err) 647 goto out_chip_stop; 648 649 err = mcp251xfd_chip_clock_init(priv); 650 if (err) 651 goto out_chip_stop; 652 653 err = mcp251xfd_set_bittiming(priv); 654 if (err) 655 goto out_chip_stop; 656 657 err = mcp251xfd_chip_rx_int_enable(priv); 658 if (err) 659 goto out_chip_stop; 660 661 err = mcp251xfd_chip_ecc_init(priv); 662 if (err) 663 goto out_chip_stop; 664 665 mcp251xfd_ring_init(priv); 666 667 err = mcp251xfd_chip_fifo_init(priv); 668 if (err) 669 goto out_chip_stop; 670 671 priv->can.state = CAN_STATE_ERROR_ACTIVE; 672 673 err = mcp251xfd_chip_set_normal_mode(priv); 674 if (err) 675 goto out_chip_stop; 676 677 return 0; 678 679 out_chip_stop: 680 mcp251xfd_dump(priv); 681 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED); 682 683 return err; 684 } 685 686 static int mcp251xfd_set_mode(struct net_device *ndev, enum can_mode mode) 687 { 688 struct mcp251xfd_priv *priv = netdev_priv(ndev); 689 int err; 690 691 switch (mode) { 692 case CAN_MODE_START: 693 err = mcp251xfd_chip_start(priv); 694 if (err) 695 return err; 696 697 err = mcp251xfd_chip_interrupts_enable(priv); 698 if (err) { 699 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED); 700 return err; 701 } 702 703 netif_wake_queue(ndev); 704 break; 705 706 default: 707 return -EOPNOTSUPP; 708 } 709 710 return 0; 711 } 712 713 static int __mcp251xfd_get_berr_counter(const struct net_device *ndev, 714 struct can_berr_counter *bec) 715 { 716 const struct mcp251xfd_priv *priv = netdev_priv(ndev); 717 u32 trec; 718 int err; 719 720 err = regmap_read(priv->map_reg, MCP251XFD_REG_TREC, &trec); 721 if (err) 722 return err; 723 724 if (trec & MCP251XFD_REG_TREC_TXBO) 725 bec->txerr = 256; 726 else 727 bec->txerr = FIELD_GET(MCP251XFD_REG_TREC_TEC_MASK, trec); 728 bec->rxerr = FIELD_GET(MCP251XFD_REG_TREC_REC_MASK, trec); 729 730 return 0; 731 } 732 733 static int mcp251xfd_get_berr_counter(const struct net_device *ndev, 734 struct can_berr_counter *bec) 735 { 736 const struct mcp251xfd_priv *priv = netdev_priv(ndev); 737 738 /* Avoid waking up the controller if the interface is down */ 739 if (!(ndev->flags & IFF_UP)) 740 return 0; 741 742 /* The controller is powered down during Bus Off, use saved 743 * bec values. 744 */ 745 if (priv->can.state == CAN_STATE_BUS_OFF) { 746 *bec = priv->bec; 747 return 0; 748 } 749 750 return __mcp251xfd_get_berr_counter(ndev, bec); 751 } 752 753 static struct sk_buff * 754 mcp251xfd_alloc_can_err_skb(struct mcp251xfd_priv *priv, 755 struct can_frame **cf, u32 *timestamp) 756 { 757 struct sk_buff *skb; 758 int err; 759 760 err = mcp251xfd_get_timestamp(priv, timestamp); 761 if (err) 762 return NULL; 763 764 skb = alloc_can_err_skb(priv->ndev, cf); 765 if (skb) 766 mcp251xfd_skb_set_timestamp(priv, skb, *timestamp); 767 768 return skb; 769 } 770 771 static int mcp251xfd_handle_rxovif(struct mcp251xfd_priv *priv) 772 { 773 struct net_device_stats *stats = &priv->ndev->stats; 774 struct mcp251xfd_rx_ring *ring; 775 struct sk_buff *skb; 776 struct can_frame *cf; 777 u32 timestamp, rxovif; 778 int err, i; 779 780 stats->rx_over_errors++; 781 stats->rx_errors++; 782 783 err = regmap_read(priv->map_reg, MCP251XFD_REG_RXOVIF, &rxovif); 784 if (err) 785 return err; 786 787 mcp251xfd_for_each_rx_ring(priv, ring, i) { 788 if (!(rxovif & BIT(ring->fifo_nr))) 789 continue; 790 791 /* If SERRIF is active, there was a RX MAB overflow. */ 792 if (priv->regs_status.intf & MCP251XFD_REG_INT_SERRIF) { 793 if (net_ratelimit()) 794 netdev_dbg(priv->ndev, 795 "RX-%d: MAB overflow detected.\n", 796 ring->nr); 797 } else { 798 if (net_ratelimit()) 799 netdev_dbg(priv->ndev, 800 "RX-%d: FIFO overflow.\n", 801 ring->nr); 802 } 803 804 err = regmap_update_bits(priv->map_reg, 805 MCP251XFD_REG_FIFOSTA(ring->fifo_nr), 806 MCP251XFD_REG_FIFOSTA_RXOVIF, 807 0x0); 808 if (err) 809 return err; 810 } 811 812 skb = mcp251xfd_alloc_can_err_skb(priv, &cf, ×tamp); 813 if (!skb) 814 return 0; 815 816 cf->can_id |= CAN_ERR_CRTL; 817 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 818 819 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp); 820 if (err) 821 stats->rx_fifo_errors++; 822 823 return 0; 824 } 825 826 static int mcp251xfd_handle_txatif(struct mcp251xfd_priv *priv) 827 { 828 netdev_info(priv->ndev, "%s\n", __func__); 829 830 return 0; 831 } 832 833 static int mcp251xfd_handle_ivmif(struct mcp251xfd_priv *priv) 834 { 835 struct net_device_stats *stats = &priv->ndev->stats; 836 u32 bdiag1, timestamp; 837 struct sk_buff *skb; 838 struct can_frame *cf = NULL; 839 int err; 840 841 err = mcp251xfd_get_timestamp(priv, ×tamp); 842 if (err) 843 return err; 844 845 err = regmap_read(priv->map_reg, MCP251XFD_REG_BDIAG1, &bdiag1); 846 if (err) 847 return err; 848 849 /* Write 0s to clear error bits, don't write 1s to non active 850 * bits, as they will be set. 851 */ 852 err = regmap_write(priv->map_reg, MCP251XFD_REG_BDIAG1, 0x0); 853 if (err) 854 return err; 855 856 priv->can.can_stats.bus_error++; 857 858 skb = alloc_can_err_skb(priv->ndev, &cf); 859 if (cf) 860 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 861 862 /* Controller misconfiguration */ 863 if (WARN_ON(bdiag1 & MCP251XFD_REG_BDIAG1_DLCMM)) 864 netdev_err(priv->ndev, 865 "recv'd DLC is larger than PLSIZE of FIFO element."); 866 867 /* RX errors */ 868 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DCRCERR | 869 MCP251XFD_REG_BDIAG1_NCRCERR)) { 870 netdev_dbg(priv->ndev, "CRC error\n"); 871 872 stats->rx_errors++; 873 if (cf) 874 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ; 875 } 876 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DSTUFERR | 877 MCP251XFD_REG_BDIAG1_NSTUFERR)) { 878 netdev_dbg(priv->ndev, "Stuff error\n"); 879 880 stats->rx_errors++; 881 if (cf) 882 cf->data[2] |= CAN_ERR_PROT_STUFF; 883 } 884 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DFORMERR | 885 MCP251XFD_REG_BDIAG1_NFORMERR)) { 886 netdev_dbg(priv->ndev, "Format error\n"); 887 888 stats->rx_errors++; 889 if (cf) 890 cf->data[2] |= CAN_ERR_PROT_FORM; 891 } 892 893 /* TX errors */ 894 if (bdiag1 & MCP251XFD_REG_BDIAG1_NACKERR) { 895 netdev_dbg(priv->ndev, "NACK error\n"); 896 897 stats->tx_errors++; 898 if (cf) { 899 cf->can_id |= CAN_ERR_ACK; 900 cf->data[2] |= CAN_ERR_PROT_TX; 901 } 902 } 903 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DBIT1ERR | 904 MCP251XFD_REG_BDIAG1_NBIT1ERR)) { 905 netdev_dbg(priv->ndev, "Bit1 error\n"); 906 907 stats->tx_errors++; 908 if (cf) 909 cf->data[2] |= CAN_ERR_PROT_TX | CAN_ERR_PROT_BIT1; 910 } 911 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DBIT0ERR | 912 MCP251XFD_REG_BDIAG1_NBIT0ERR)) { 913 netdev_dbg(priv->ndev, "Bit0 error\n"); 914 915 stats->tx_errors++; 916 if (cf) 917 cf->data[2] |= CAN_ERR_PROT_TX | CAN_ERR_PROT_BIT0; 918 } 919 920 if (!cf) 921 return 0; 922 923 mcp251xfd_skb_set_timestamp(priv, skb, timestamp); 924 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp); 925 if (err) 926 stats->rx_fifo_errors++; 927 928 return 0; 929 } 930 931 static int mcp251xfd_handle_cerrif(struct mcp251xfd_priv *priv) 932 { 933 struct net_device_stats *stats = &priv->ndev->stats; 934 struct sk_buff *skb; 935 struct can_frame *cf = NULL; 936 enum can_state new_state, rx_state, tx_state; 937 u32 trec, timestamp; 938 int err; 939 940 err = regmap_read(priv->map_reg, MCP251XFD_REG_TREC, &trec); 941 if (err) 942 return err; 943 944 if (trec & MCP251XFD_REG_TREC_TXBO) 945 tx_state = CAN_STATE_BUS_OFF; 946 else if (trec & MCP251XFD_REG_TREC_TXBP) 947 tx_state = CAN_STATE_ERROR_PASSIVE; 948 else if (trec & MCP251XFD_REG_TREC_TXWARN) 949 tx_state = CAN_STATE_ERROR_WARNING; 950 else 951 tx_state = CAN_STATE_ERROR_ACTIVE; 952 953 if (trec & MCP251XFD_REG_TREC_RXBP) 954 rx_state = CAN_STATE_ERROR_PASSIVE; 955 else if (trec & MCP251XFD_REG_TREC_RXWARN) 956 rx_state = CAN_STATE_ERROR_WARNING; 957 else 958 rx_state = CAN_STATE_ERROR_ACTIVE; 959 960 new_state = max(tx_state, rx_state); 961 if (new_state == priv->can.state) 962 return 0; 963 964 /* The skb allocation might fail, but can_change_state() 965 * handles cf == NULL. 966 */ 967 skb = mcp251xfd_alloc_can_err_skb(priv, &cf, ×tamp); 968 can_change_state(priv->ndev, cf, tx_state, rx_state); 969 970 if (new_state == CAN_STATE_BUS_OFF) { 971 /* As we're going to switch off the chip now, let's 972 * save the error counters and return them to 973 * userspace, if do_get_berr_counter() is called while 974 * the chip is in Bus Off. 975 */ 976 err = __mcp251xfd_get_berr_counter(priv->ndev, &priv->bec); 977 if (err) 978 return err; 979 980 mcp251xfd_chip_stop(priv, CAN_STATE_BUS_OFF); 981 can_bus_off(priv->ndev); 982 } 983 984 if (!skb) 985 return 0; 986 987 if (new_state != CAN_STATE_BUS_OFF) { 988 struct can_berr_counter bec; 989 990 err = mcp251xfd_get_berr_counter(priv->ndev, &bec); 991 if (err) 992 return err; 993 cf->data[6] = bec.txerr; 994 cf->data[7] = bec.rxerr; 995 } 996 997 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp); 998 if (err) 999 stats->rx_fifo_errors++; 1000 1001 return 0; 1002 } 1003 1004 static int 1005 mcp251xfd_handle_modif(const struct mcp251xfd_priv *priv, bool *set_normal_mode) 1006 { 1007 const u8 mode_reference = mcp251xfd_get_normal_mode(priv); 1008 u8 mode; 1009 int err; 1010 1011 err = mcp251xfd_chip_get_mode(priv, &mode); 1012 if (err) 1013 return err; 1014 1015 if (mode == mode_reference) { 1016 netdev_dbg(priv->ndev, 1017 "Controller changed into %s Mode (%u).\n", 1018 mcp251xfd_get_mode_str(mode), mode); 1019 return 0; 1020 } 1021 1022 /* According to MCP2517FD errata DS80000792B 1., during a TX 1023 * MAB underflow, the controller will transition to Restricted 1024 * Operation Mode or Listen Only Mode (depending on SERR2LOM). 1025 * 1026 * However this is not always the case. If SERR2LOM is 1027 * configured for Restricted Operation Mode (SERR2LOM not set) 1028 * the MCP2517FD will sometimes transition to Listen Only Mode 1029 * first. When polling this bit we see that it will transition 1030 * to Restricted Operation Mode shortly after. 1031 */ 1032 if ((priv->devtype_data.quirks & MCP251XFD_QUIRK_MAB_NO_WARN) && 1033 (mode == MCP251XFD_REG_CON_MODE_RESTRICTED || 1034 mode == MCP251XFD_REG_CON_MODE_LISTENONLY)) 1035 netdev_dbg(priv->ndev, 1036 "Controller changed into %s Mode (%u).\n", 1037 mcp251xfd_get_mode_str(mode), mode); 1038 else 1039 netdev_err(priv->ndev, 1040 "Controller changed into %s Mode (%u).\n", 1041 mcp251xfd_get_mode_str(mode), mode); 1042 1043 /* After the application requests Normal mode, the controller 1044 * will automatically attempt to retransmit the message that 1045 * caused the TX MAB underflow. 1046 * 1047 * However, if there is an ECC error in the TX-RAM, we first 1048 * have to reload the tx-object before requesting Normal 1049 * mode. This is done later in mcp251xfd_handle_eccif(). 1050 */ 1051 if (priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF) { 1052 *set_normal_mode = true; 1053 return 0; 1054 } 1055 1056 return mcp251xfd_chip_set_normal_mode_nowait(priv); 1057 } 1058 1059 static int mcp251xfd_handle_serrif(struct mcp251xfd_priv *priv) 1060 { 1061 struct mcp251xfd_ecc *ecc = &priv->ecc; 1062 struct net_device_stats *stats = &priv->ndev->stats; 1063 bool handled = false; 1064 1065 /* TX MAB underflow 1066 * 1067 * According to MCP2517FD Errata DS80000792B 1. a TX MAB 1068 * underflow is indicated by SERRIF and MODIF. 1069 * 1070 * In addition to the effects mentioned in the Errata, there 1071 * are Bus Errors due to the aborted CAN frame, so a IVMIF 1072 * will be seen as well. 1073 * 1074 * Sometimes there is an ECC error in the TX-RAM, which leads 1075 * to a TX MAB underflow. 1076 * 1077 * However, probably due to a race condition, there is no 1078 * associated MODIF pending. 1079 * 1080 * Further, there are situations, where the SERRIF is caused 1081 * by an ECC error in the TX-RAM, but not even the ECCIF is 1082 * set. This only seems to happen _after_ the first occurrence 1083 * of a ECCIF (which is tracked in ecc->cnt). 1084 * 1085 * Treat all as a known system errors.. 1086 */ 1087 if ((priv->regs_status.intf & MCP251XFD_REG_INT_MODIF && 1088 priv->regs_status.intf & MCP251XFD_REG_INT_IVMIF) || 1089 priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF || 1090 ecc->cnt) { 1091 const char *msg; 1092 1093 if (priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF || 1094 ecc->cnt) 1095 msg = "TX MAB underflow due to ECC error detected."; 1096 else 1097 msg = "TX MAB underflow detected."; 1098 1099 if (priv->devtype_data.quirks & MCP251XFD_QUIRK_MAB_NO_WARN) 1100 netdev_dbg(priv->ndev, "%s\n", msg); 1101 else 1102 netdev_info(priv->ndev, "%s\n", msg); 1103 1104 stats->tx_aborted_errors++; 1105 stats->tx_errors++; 1106 handled = true; 1107 } 1108 1109 /* RX MAB overflow 1110 * 1111 * According to MCP2517FD Errata DS80000792B 1. a RX MAB 1112 * overflow is indicated by SERRIF. 1113 * 1114 * In addition to the effects mentioned in the Errata, (most 1115 * of the times) a RXOVIF is raised, if the FIFO that is being 1116 * received into has the RXOVIE activated (and we have enabled 1117 * RXOVIE on all FIFOs). 1118 * 1119 * Sometimes there is no RXOVIF just a RXIF is pending. 1120 * 1121 * Treat all as a known system errors.. 1122 */ 1123 if (priv->regs_status.intf & MCP251XFD_REG_INT_RXOVIF || 1124 priv->regs_status.intf & MCP251XFD_REG_INT_RXIF) { 1125 stats->rx_dropped++; 1126 handled = true; 1127 } 1128 1129 if (!handled) 1130 netdev_err(priv->ndev, 1131 "Unhandled System Error Interrupt (intf=0x%08x)!\n", 1132 priv->regs_status.intf); 1133 1134 return 0; 1135 } 1136 1137 static int 1138 mcp251xfd_handle_eccif_recover(struct mcp251xfd_priv *priv, u8 nr) 1139 { 1140 struct mcp251xfd_tx_ring *tx_ring = priv->tx; 1141 struct mcp251xfd_ecc *ecc = &priv->ecc; 1142 struct mcp251xfd_tx_obj *tx_obj; 1143 u8 chip_tx_tail, tx_tail, offset; 1144 u16 addr; 1145 int err; 1146 1147 addr = FIELD_GET(MCP251XFD_REG_ECCSTAT_ERRADDR_MASK, ecc->ecc_stat); 1148 1149 err = mcp251xfd_tx_tail_get_from_chip(priv, &chip_tx_tail); 1150 if (err) 1151 return err; 1152 1153 tx_tail = mcp251xfd_get_tx_tail(tx_ring); 1154 offset = (nr - chip_tx_tail) & (tx_ring->obj_num - 1); 1155 1156 /* Bail out if one of the following is met: 1157 * - tx_tail information is inconsistent 1158 * - for mcp2517fd: offset not 0 1159 * - for mcp2518fd: offset not 0 or 1 1160 */ 1161 if (chip_tx_tail != tx_tail || 1162 !(offset == 0 || (offset == 1 && mcp251xfd_is_2518(priv)))) { 1163 netdev_err(priv->ndev, 1164 "ECC Error information inconsistent (addr=0x%04x, nr=%d, tx_tail=0x%08x(%d), chip_tx_tail=%d, offset=%d).\n", 1165 addr, nr, tx_ring->tail, tx_tail, chip_tx_tail, 1166 offset); 1167 return -EINVAL; 1168 } 1169 1170 netdev_info(priv->ndev, 1171 "Recovering %s ECC Error at address 0x%04x (in TX-RAM, tx_obj=%d, tx_tail=0x%08x(%d), offset=%d).\n", 1172 ecc->ecc_stat & MCP251XFD_REG_ECCSTAT_SECIF ? 1173 "Single" : "Double", 1174 addr, nr, tx_ring->tail, tx_tail, offset); 1175 1176 /* reload tx_obj into controller RAM ... */ 1177 tx_obj = &tx_ring->obj[nr]; 1178 err = spi_sync_transfer(priv->spi, tx_obj->xfer, 1); 1179 if (err) 1180 return err; 1181 1182 /* ... and trigger retransmit */ 1183 return mcp251xfd_chip_set_normal_mode(priv); 1184 } 1185 1186 static int 1187 mcp251xfd_handle_eccif(struct mcp251xfd_priv *priv, bool set_normal_mode) 1188 { 1189 struct mcp251xfd_ecc *ecc = &priv->ecc; 1190 const char *msg; 1191 bool in_tx_ram; 1192 u32 ecc_stat; 1193 u16 addr; 1194 u8 nr; 1195 int err; 1196 1197 err = regmap_read(priv->map_reg, MCP251XFD_REG_ECCSTAT, &ecc_stat); 1198 if (err) 1199 return err; 1200 1201 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCSTAT, 1202 MCP251XFD_REG_ECCSTAT_IF_MASK, ~ecc_stat); 1203 if (err) 1204 return err; 1205 1206 /* Check if ECC error occurred in TX-RAM */ 1207 addr = FIELD_GET(MCP251XFD_REG_ECCSTAT_ERRADDR_MASK, ecc_stat); 1208 err = mcp251xfd_get_tx_nr_by_addr(priv->tx, &nr, addr); 1209 if (!err) 1210 in_tx_ram = true; 1211 else if (err == -ENOENT) 1212 in_tx_ram = false; 1213 else 1214 return err; 1215 1216 /* Errata Reference: 1217 * mcp2517fd: DS80000789B, mcp2518fd: DS80000792C 2. 1218 * 1219 * ECC single error correction does not work in all cases: 1220 * 1221 * Fix/Work Around: 1222 * Enable single error correction and double error detection 1223 * interrupts by setting SECIE and DEDIE. Handle SECIF as a 1224 * detection interrupt and do not rely on the error 1225 * correction. Instead, handle both interrupts as a 1226 * notification that the RAM word at ERRADDR was corrupted. 1227 */ 1228 if (ecc_stat & MCP251XFD_REG_ECCSTAT_SECIF) 1229 msg = "Single ECC Error detected at address"; 1230 else if (ecc_stat & MCP251XFD_REG_ECCSTAT_DEDIF) 1231 msg = "Double ECC Error detected at address"; 1232 else 1233 return -EINVAL; 1234 1235 if (!in_tx_ram) { 1236 ecc->ecc_stat = 0; 1237 1238 netdev_notice(priv->ndev, "%s 0x%04x.\n", msg, addr); 1239 } else { 1240 /* Re-occurring error? */ 1241 if (ecc->ecc_stat == ecc_stat) { 1242 ecc->cnt++; 1243 } else { 1244 ecc->ecc_stat = ecc_stat; 1245 ecc->cnt = 1; 1246 } 1247 1248 netdev_info(priv->ndev, 1249 "%s 0x%04x (in TX-RAM, tx_obj=%d), occurred %d time%s.\n", 1250 msg, addr, nr, ecc->cnt, ecc->cnt > 1 ? "s" : ""); 1251 1252 if (ecc->cnt >= MCP251XFD_ECC_CNT_MAX) 1253 return mcp251xfd_handle_eccif_recover(priv, nr); 1254 } 1255 1256 if (set_normal_mode) 1257 return mcp251xfd_chip_set_normal_mode_nowait(priv); 1258 1259 return 0; 1260 } 1261 1262 static int mcp251xfd_handle_spicrcif(struct mcp251xfd_priv *priv) 1263 { 1264 int err; 1265 u32 crc; 1266 1267 err = regmap_read(priv->map_reg, MCP251XFD_REG_CRC, &crc); 1268 if (err) 1269 return err; 1270 1271 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_CRC, 1272 MCP251XFD_REG_CRC_IF_MASK, 1273 ~crc); 1274 if (err) 1275 return err; 1276 1277 if (crc & MCP251XFD_REG_CRC_FERRIF) 1278 netdev_notice(priv->ndev, "CRC write command format error.\n"); 1279 else if (crc & MCP251XFD_REG_CRC_CRCERRIF) 1280 netdev_notice(priv->ndev, 1281 "CRC write error detected. CRC=0x%04lx.\n", 1282 FIELD_GET(MCP251XFD_REG_CRC_MASK, crc)); 1283 1284 return 0; 1285 } 1286 1287 #define mcp251xfd_handle(priv, irq, ...) \ 1288 ({ \ 1289 struct mcp251xfd_priv *_priv = (priv); \ 1290 int err; \ 1291 \ 1292 err = mcp251xfd_handle_##irq(_priv, ## __VA_ARGS__); \ 1293 if (err) \ 1294 netdev_err(_priv->ndev, \ 1295 "IRQ handler mcp251xfd_handle_%s() returned %d.\n", \ 1296 __stringify(irq), err); \ 1297 err; \ 1298 }) 1299 1300 static irqreturn_t mcp251xfd_irq(int irq, void *dev_id) 1301 { 1302 struct mcp251xfd_priv *priv = dev_id; 1303 const int val_bytes = regmap_get_val_bytes(priv->map_reg); 1304 irqreturn_t handled = IRQ_NONE; 1305 int err; 1306 1307 if (priv->rx_int) 1308 do { 1309 int rx_pending; 1310 1311 rx_pending = gpiod_get_value_cansleep(priv->rx_int); 1312 if (!rx_pending) 1313 break; 1314 1315 err = mcp251xfd_handle(priv, rxif); 1316 if (err) 1317 goto out_fail; 1318 1319 handled = IRQ_HANDLED; 1320 } while (1); 1321 1322 do { 1323 u32 intf_pending, intf_pending_clearable; 1324 bool set_normal_mode = false; 1325 1326 err = regmap_bulk_read(priv->map_reg, MCP251XFD_REG_INT, 1327 &priv->regs_status, 1328 sizeof(priv->regs_status) / 1329 val_bytes); 1330 if (err) 1331 goto out_fail; 1332 1333 intf_pending = FIELD_GET(MCP251XFD_REG_INT_IF_MASK, 1334 priv->regs_status.intf) & 1335 FIELD_GET(MCP251XFD_REG_INT_IE_MASK, 1336 priv->regs_status.intf); 1337 1338 if (!(intf_pending)) { 1339 can_rx_offload_threaded_irq_finish(&priv->offload); 1340 return handled; 1341 } 1342 1343 /* Some interrupts must be ACKed in the 1344 * MCP251XFD_REG_INT register. 1345 * - First ACK then handle, to avoid lost-IRQ race 1346 * condition on fast re-occurring interrupts. 1347 * - Write "0" to clear active IRQs, "1" to all other, 1348 * to avoid r/m/w race condition on the 1349 * MCP251XFD_REG_INT register. 1350 */ 1351 intf_pending_clearable = intf_pending & 1352 MCP251XFD_REG_INT_IF_CLEARABLE_MASK; 1353 if (intf_pending_clearable) { 1354 err = regmap_update_bits(priv->map_reg, 1355 MCP251XFD_REG_INT, 1356 MCP251XFD_REG_INT_IF_MASK, 1357 ~intf_pending_clearable); 1358 if (err) 1359 goto out_fail; 1360 } 1361 1362 if (intf_pending & MCP251XFD_REG_INT_MODIF) { 1363 err = mcp251xfd_handle(priv, modif, &set_normal_mode); 1364 if (err) 1365 goto out_fail; 1366 } 1367 1368 if (intf_pending & MCP251XFD_REG_INT_RXIF) { 1369 err = mcp251xfd_handle(priv, rxif); 1370 if (err) 1371 goto out_fail; 1372 } 1373 1374 if (intf_pending & MCP251XFD_REG_INT_TEFIF) { 1375 err = mcp251xfd_handle(priv, tefif); 1376 if (err) 1377 goto out_fail; 1378 } 1379 1380 if (intf_pending & MCP251XFD_REG_INT_RXOVIF) { 1381 err = mcp251xfd_handle(priv, rxovif); 1382 if (err) 1383 goto out_fail; 1384 } 1385 1386 if (intf_pending & MCP251XFD_REG_INT_TXATIF) { 1387 err = mcp251xfd_handle(priv, txatif); 1388 if (err) 1389 goto out_fail; 1390 } 1391 1392 if (intf_pending & MCP251XFD_REG_INT_IVMIF) { 1393 err = mcp251xfd_handle(priv, ivmif); 1394 if (err) 1395 goto out_fail; 1396 } 1397 1398 if (intf_pending & MCP251XFD_REG_INT_SERRIF) { 1399 err = mcp251xfd_handle(priv, serrif); 1400 if (err) 1401 goto out_fail; 1402 } 1403 1404 if (intf_pending & MCP251XFD_REG_INT_ECCIF) { 1405 err = mcp251xfd_handle(priv, eccif, set_normal_mode); 1406 if (err) 1407 goto out_fail; 1408 } 1409 1410 if (intf_pending & MCP251XFD_REG_INT_SPICRCIF) { 1411 err = mcp251xfd_handle(priv, spicrcif); 1412 if (err) 1413 goto out_fail; 1414 } 1415 1416 /* On the MCP2527FD and MCP2518FD, we don't get a 1417 * CERRIF IRQ on the transition TX ERROR_WARNING -> TX 1418 * ERROR_ACTIVE. 1419 */ 1420 if (intf_pending & MCP251XFD_REG_INT_CERRIF || 1421 priv->can.state > CAN_STATE_ERROR_ACTIVE) { 1422 err = mcp251xfd_handle(priv, cerrif); 1423 if (err) 1424 goto out_fail; 1425 1426 /* In Bus Off we completely shut down the 1427 * controller. Every subsequent register read 1428 * will read bogus data, and if 1429 * MCP251XFD_QUIRK_CRC_REG is enabled the CRC 1430 * check will fail, too. So leave IRQ handler 1431 * directly. 1432 */ 1433 if (priv->can.state == CAN_STATE_BUS_OFF) { 1434 can_rx_offload_threaded_irq_finish(&priv->offload); 1435 return IRQ_HANDLED; 1436 } 1437 } 1438 1439 handled = IRQ_HANDLED; 1440 } while (1); 1441 1442 out_fail: 1443 can_rx_offload_threaded_irq_finish(&priv->offload); 1444 1445 netdev_err(priv->ndev, "IRQ handler returned %d (intf=0x%08x).\n", 1446 err, priv->regs_status.intf); 1447 mcp251xfd_dump(priv); 1448 mcp251xfd_chip_interrupts_disable(priv); 1449 mcp251xfd_timestamp_stop(priv); 1450 1451 return handled; 1452 } 1453 1454 static int mcp251xfd_open(struct net_device *ndev) 1455 { 1456 struct mcp251xfd_priv *priv = netdev_priv(ndev); 1457 const struct spi_device *spi = priv->spi; 1458 int err; 1459 1460 err = open_candev(ndev); 1461 if (err) 1462 return err; 1463 1464 err = pm_runtime_resume_and_get(ndev->dev.parent); 1465 if (err) 1466 goto out_close_candev; 1467 1468 err = mcp251xfd_ring_alloc(priv); 1469 if (err) 1470 goto out_pm_runtime_put; 1471 1472 err = mcp251xfd_transceiver_enable(priv); 1473 if (err) 1474 goto out_mcp251xfd_ring_free; 1475 1476 err = mcp251xfd_chip_start(priv); 1477 if (err) 1478 goto out_transceiver_disable; 1479 1480 mcp251xfd_timestamp_init(priv); 1481 can_rx_offload_enable(&priv->offload); 1482 1483 err = request_threaded_irq(spi->irq, NULL, mcp251xfd_irq, 1484 IRQF_SHARED | IRQF_ONESHOT, 1485 dev_name(&spi->dev), priv); 1486 if (err) 1487 goto out_can_rx_offload_disable; 1488 1489 err = mcp251xfd_chip_interrupts_enable(priv); 1490 if (err) 1491 goto out_free_irq; 1492 1493 netif_start_queue(ndev); 1494 1495 return 0; 1496 1497 out_free_irq: 1498 free_irq(spi->irq, priv); 1499 out_can_rx_offload_disable: 1500 can_rx_offload_disable(&priv->offload); 1501 mcp251xfd_timestamp_stop(priv); 1502 out_transceiver_disable: 1503 mcp251xfd_transceiver_disable(priv); 1504 out_mcp251xfd_ring_free: 1505 mcp251xfd_ring_free(priv); 1506 out_pm_runtime_put: 1507 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED); 1508 pm_runtime_put(ndev->dev.parent); 1509 out_close_candev: 1510 close_candev(ndev); 1511 1512 return err; 1513 } 1514 1515 static int mcp251xfd_stop(struct net_device *ndev) 1516 { 1517 struct mcp251xfd_priv *priv = netdev_priv(ndev); 1518 1519 netif_stop_queue(ndev); 1520 mcp251xfd_chip_interrupts_disable(priv); 1521 free_irq(ndev->irq, priv); 1522 can_rx_offload_disable(&priv->offload); 1523 mcp251xfd_timestamp_stop(priv); 1524 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED); 1525 mcp251xfd_transceiver_disable(priv); 1526 mcp251xfd_ring_free(priv); 1527 close_candev(ndev); 1528 1529 pm_runtime_put(ndev->dev.parent); 1530 1531 return 0; 1532 } 1533 1534 static const struct net_device_ops mcp251xfd_netdev_ops = { 1535 .ndo_open = mcp251xfd_open, 1536 .ndo_stop = mcp251xfd_stop, 1537 .ndo_start_xmit = mcp251xfd_start_xmit, 1538 .ndo_change_mtu = can_change_mtu, 1539 }; 1540 1541 static void 1542 mcp251xfd_register_quirks(struct mcp251xfd_priv *priv) 1543 { 1544 const struct spi_device *spi = priv->spi; 1545 const struct spi_controller *ctlr = spi->controller; 1546 1547 if (ctlr->flags & SPI_CONTROLLER_HALF_DUPLEX) 1548 priv->devtype_data.quirks |= MCP251XFD_QUIRK_HALF_DUPLEX; 1549 } 1550 1551 static int mcp251xfd_register_chip_detect(struct mcp251xfd_priv *priv) 1552 { 1553 const struct net_device *ndev = priv->ndev; 1554 const struct mcp251xfd_devtype_data *devtype_data; 1555 u32 osc; 1556 int err; 1557 1558 /* The OSC_LPMEN is only supported on MCP2518FD, so use it to 1559 * autodetect the model. 1560 */ 1561 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_OSC, 1562 MCP251XFD_REG_OSC_LPMEN, 1563 MCP251XFD_REG_OSC_LPMEN); 1564 if (err) 1565 return err; 1566 1567 err = regmap_read(priv->map_reg, MCP251XFD_REG_OSC, &osc); 1568 if (err) 1569 return err; 1570 1571 if (osc & MCP251XFD_REG_OSC_LPMEN) 1572 devtype_data = &mcp251xfd_devtype_data_mcp2518fd; 1573 else 1574 devtype_data = &mcp251xfd_devtype_data_mcp2517fd; 1575 1576 if (!mcp251xfd_is_251X(priv) && 1577 priv->devtype_data.model != devtype_data->model) { 1578 netdev_info(ndev, 1579 "Detected %s, but firmware specifies a %s. Fixing up.\n", 1580 __mcp251xfd_get_model_str(devtype_data->model), 1581 mcp251xfd_get_model_str(priv)); 1582 } 1583 priv->devtype_data = *devtype_data; 1584 1585 /* We need to preserve the Half Duplex Quirk. */ 1586 mcp251xfd_register_quirks(priv); 1587 1588 /* Re-init regmap with quirks of detected model. */ 1589 return mcp251xfd_regmap_init(priv); 1590 } 1591 1592 static int mcp251xfd_register_check_rx_int(struct mcp251xfd_priv *priv) 1593 { 1594 int err, rx_pending; 1595 1596 if (!priv->rx_int) 1597 return 0; 1598 1599 err = mcp251xfd_chip_rx_int_enable(priv); 1600 if (err) 1601 return err; 1602 1603 /* Check if RX_INT is properly working. The RX_INT should not 1604 * be active after a softreset. 1605 */ 1606 rx_pending = gpiod_get_value_cansleep(priv->rx_int); 1607 1608 err = mcp251xfd_chip_rx_int_disable(priv); 1609 if (err) 1610 return err; 1611 1612 if (!rx_pending) 1613 return 0; 1614 1615 netdev_info(priv->ndev, 1616 "RX_INT active after softreset, disabling RX_INT support.\n"); 1617 devm_gpiod_put(&priv->spi->dev, priv->rx_int); 1618 priv->rx_int = NULL; 1619 1620 return 0; 1621 } 1622 1623 static int 1624 mcp251xfd_register_get_dev_id(const struct mcp251xfd_priv *priv, 1625 u32 *dev_id, u32 *effective_speed_hz) 1626 { 1627 struct mcp251xfd_map_buf_nocrc *buf_rx; 1628 struct mcp251xfd_map_buf_nocrc *buf_tx; 1629 struct spi_transfer xfer[2] = { }; 1630 int err; 1631 1632 buf_rx = kzalloc(sizeof(*buf_rx), GFP_KERNEL); 1633 if (!buf_rx) 1634 return -ENOMEM; 1635 1636 buf_tx = kzalloc(sizeof(*buf_tx), GFP_KERNEL); 1637 if (!buf_tx) { 1638 err = -ENOMEM; 1639 goto out_kfree_buf_rx; 1640 } 1641 1642 xfer[0].tx_buf = buf_tx; 1643 xfer[0].len = sizeof(buf_tx->cmd); 1644 xfer[1].rx_buf = buf_rx->data; 1645 xfer[1].len = sizeof(dev_id); 1646 1647 mcp251xfd_spi_cmd_read_nocrc(&buf_tx->cmd, MCP251XFD_REG_DEVID); 1648 err = spi_sync_transfer(priv->spi, xfer, ARRAY_SIZE(xfer)); 1649 if (err) 1650 goto out_kfree_buf_tx; 1651 1652 *dev_id = be32_to_cpup((__be32 *)buf_rx->data); 1653 *effective_speed_hz = xfer->effective_speed_hz; 1654 1655 out_kfree_buf_tx: 1656 kfree(buf_tx); 1657 out_kfree_buf_rx: 1658 kfree(buf_rx); 1659 1660 return 0; 1661 } 1662 1663 #define MCP251XFD_QUIRK_ACTIVE(quirk) \ 1664 (priv->devtype_data.quirks & MCP251XFD_QUIRK_##quirk ? '+' : '-') 1665 1666 static int 1667 mcp251xfd_register_done(const struct mcp251xfd_priv *priv) 1668 { 1669 u32 dev_id, effective_speed_hz; 1670 int err; 1671 1672 err = mcp251xfd_register_get_dev_id(priv, &dev_id, 1673 &effective_speed_hz); 1674 if (err) 1675 return err; 1676 1677 netdev_info(priv->ndev, 1678 "%s rev%lu.%lu (%cRX_INT %cMAB_NO_WARN %cCRC_REG %cCRC_RX %cCRC_TX %cECC %cHD c:%u.%02uMHz m:%u.%02uMHz r:%u.%02uMHz e:%u.%02uMHz) successfully initialized.\n", 1679 mcp251xfd_get_model_str(priv), 1680 FIELD_GET(MCP251XFD_REG_DEVID_ID_MASK, dev_id), 1681 FIELD_GET(MCP251XFD_REG_DEVID_REV_MASK, dev_id), 1682 priv->rx_int ? '+' : '-', 1683 MCP251XFD_QUIRK_ACTIVE(MAB_NO_WARN), 1684 MCP251XFD_QUIRK_ACTIVE(CRC_REG), 1685 MCP251XFD_QUIRK_ACTIVE(CRC_RX), 1686 MCP251XFD_QUIRK_ACTIVE(CRC_TX), 1687 MCP251XFD_QUIRK_ACTIVE(ECC), 1688 MCP251XFD_QUIRK_ACTIVE(HALF_DUPLEX), 1689 priv->can.clock.freq / 1000000, 1690 priv->can.clock.freq % 1000000 / 1000 / 10, 1691 priv->spi_max_speed_hz_orig / 1000000, 1692 priv->spi_max_speed_hz_orig % 1000000 / 1000 / 10, 1693 priv->spi->max_speed_hz / 1000000, 1694 priv->spi->max_speed_hz % 1000000 / 1000 / 10, 1695 effective_speed_hz / 1000000, 1696 effective_speed_hz % 1000000 / 1000 / 10); 1697 1698 return 0; 1699 } 1700 1701 static int mcp251xfd_register(struct mcp251xfd_priv *priv) 1702 { 1703 struct net_device *ndev = priv->ndev; 1704 int err; 1705 1706 err = mcp251xfd_clks_and_vdd_enable(priv); 1707 if (err) 1708 return err; 1709 1710 pm_runtime_get_noresume(ndev->dev.parent); 1711 err = pm_runtime_set_active(ndev->dev.parent); 1712 if (err) 1713 goto out_runtime_put_noidle; 1714 pm_runtime_enable(ndev->dev.parent); 1715 1716 mcp251xfd_register_quirks(priv); 1717 1718 err = mcp251xfd_chip_softreset(priv); 1719 if (err == -ENODEV) 1720 goto out_runtime_disable; 1721 if (err) 1722 goto out_chip_set_mode_sleep; 1723 1724 err = mcp251xfd_register_chip_detect(priv); 1725 if (err) 1726 goto out_chip_set_mode_sleep; 1727 1728 err = mcp251xfd_register_check_rx_int(priv); 1729 if (err) 1730 goto out_chip_set_mode_sleep; 1731 1732 err = register_candev(ndev); 1733 if (err) 1734 goto out_chip_set_mode_sleep; 1735 1736 err = mcp251xfd_register_done(priv); 1737 if (err) 1738 goto out_unregister_candev; 1739 1740 /* Put controller into sleep mode and let pm_runtime_put() 1741 * disable the clocks and vdd. If CONFIG_PM is not enabled, 1742 * the clocks and vdd will stay powered. 1743 */ 1744 err = mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_SLEEP); 1745 if (err) 1746 goto out_unregister_candev; 1747 1748 pm_runtime_put(ndev->dev.parent); 1749 1750 return 0; 1751 1752 out_unregister_candev: 1753 unregister_candev(ndev); 1754 out_chip_set_mode_sleep: 1755 mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_SLEEP); 1756 out_runtime_disable: 1757 pm_runtime_disable(ndev->dev.parent); 1758 out_runtime_put_noidle: 1759 pm_runtime_put_noidle(ndev->dev.parent); 1760 mcp251xfd_clks_and_vdd_disable(priv); 1761 1762 return err; 1763 } 1764 1765 static inline void mcp251xfd_unregister(struct mcp251xfd_priv *priv) 1766 { 1767 struct net_device *ndev = priv->ndev; 1768 1769 unregister_candev(ndev); 1770 1771 pm_runtime_get_sync(ndev->dev.parent); 1772 pm_runtime_put_noidle(ndev->dev.parent); 1773 mcp251xfd_clks_and_vdd_disable(priv); 1774 pm_runtime_disable(ndev->dev.parent); 1775 } 1776 1777 static const struct of_device_id mcp251xfd_of_match[] = { 1778 { 1779 .compatible = "microchip,mcp2517fd", 1780 .data = &mcp251xfd_devtype_data_mcp2517fd, 1781 }, { 1782 .compatible = "microchip,mcp2518fd", 1783 .data = &mcp251xfd_devtype_data_mcp2518fd, 1784 }, { 1785 .compatible = "microchip,mcp251xfd", 1786 .data = &mcp251xfd_devtype_data_mcp251xfd, 1787 }, { 1788 /* sentinel */ 1789 }, 1790 }; 1791 MODULE_DEVICE_TABLE(of, mcp251xfd_of_match); 1792 1793 static const struct spi_device_id mcp251xfd_id_table[] = { 1794 { 1795 .name = "mcp2517fd", 1796 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp2517fd, 1797 }, { 1798 .name = "mcp2518fd", 1799 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp2518fd, 1800 }, { 1801 .name = "mcp251xfd", 1802 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp251xfd, 1803 }, { 1804 /* sentinel */ 1805 }, 1806 }; 1807 MODULE_DEVICE_TABLE(spi, mcp251xfd_id_table); 1808 1809 static int mcp251xfd_probe(struct spi_device *spi) 1810 { 1811 const void *match; 1812 struct net_device *ndev; 1813 struct mcp251xfd_priv *priv; 1814 struct gpio_desc *rx_int; 1815 struct regulator *reg_vdd, *reg_xceiver; 1816 struct clk *clk; 1817 u32 freq = 0; 1818 int err; 1819 1820 if (!spi->irq) 1821 return dev_err_probe(&spi->dev, -ENXIO, 1822 "No IRQ specified (maybe node \"interrupts-extended\" in DT missing)!\n"); 1823 1824 rx_int = devm_gpiod_get_optional(&spi->dev, "microchip,rx-int", 1825 GPIOD_IN); 1826 if (IS_ERR(rx_int)) 1827 return dev_err_probe(&spi->dev, PTR_ERR(rx_int), 1828 "Failed to get RX-INT!\n"); 1829 1830 reg_vdd = devm_regulator_get_optional(&spi->dev, "vdd"); 1831 if (PTR_ERR(reg_vdd) == -ENODEV) 1832 reg_vdd = NULL; 1833 else if (IS_ERR(reg_vdd)) 1834 return dev_err_probe(&spi->dev, PTR_ERR(reg_vdd), 1835 "Failed to get VDD regulator!\n"); 1836 1837 reg_xceiver = devm_regulator_get_optional(&spi->dev, "xceiver"); 1838 if (PTR_ERR(reg_xceiver) == -ENODEV) 1839 reg_xceiver = NULL; 1840 else if (IS_ERR(reg_xceiver)) 1841 return dev_err_probe(&spi->dev, PTR_ERR(reg_xceiver), 1842 "Failed to get Transceiver regulator!\n"); 1843 1844 clk = devm_clk_get_optional(&spi->dev, NULL); 1845 if (IS_ERR(clk)) 1846 return dev_err_probe(&spi->dev, PTR_ERR(clk), 1847 "Failed to get Oscillator (clock)!\n"); 1848 if (clk) { 1849 freq = clk_get_rate(clk); 1850 } else { 1851 err = device_property_read_u32(&spi->dev, "clock-frequency", 1852 &freq); 1853 if (err) 1854 return dev_err_probe(&spi->dev, err, 1855 "Failed to get clock-frequency!\n"); 1856 } 1857 1858 /* Sanity check */ 1859 if (freq < MCP251XFD_SYSCLOCK_HZ_MIN || 1860 freq > MCP251XFD_SYSCLOCK_HZ_MAX) { 1861 dev_err(&spi->dev, 1862 "Oscillator frequency (%u Hz) is too low or high.\n", 1863 freq); 1864 return -ERANGE; 1865 } 1866 1867 if (freq <= MCP251XFD_SYSCLOCK_HZ_MAX / MCP251XFD_OSC_PLL_MULTIPLIER) { 1868 dev_err(&spi->dev, 1869 "Oscillator frequency (%u Hz) is too low and PLL is not supported.\n", 1870 freq); 1871 return -ERANGE; 1872 } 1873 1874 ndev = alloc_candev(sizeof(struct mcp251xfd_priv), 1875 MCP251XFD_TX_OBJ_NUM_MAX); 1876 if (!ndev) 1877 return -ENOMEM; 1878 1879 SET_NETDEV_DEV(ndev, &spi->dev); 1880 1881 ndev->netdev_ops = &mcp251xfd_netdev_ops; 1882 ndev->irq = spi->irq; 1883 ndev->flags |= IFF_ECHO; 1884 1885 priv = netdev_priv(ndev); 1886 spi_set_drvdata(spi, priv); 1887 priv->can.clock.freq = freq; 1888 priv->can.do_set_mode = mcp251xfd_set_mode; 1889 priv->can.do_get_berr_counter = mcp251xfd_get_berr_counter; 1890 priv->can.bittiming_const = &mcp251xfd_bittiming_const; 1891 priv->can.data_bittiming_const = &mcp251xfd_data_bittiming_const; 1892 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1893 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_BERR_REPORTING | 1894 CAN_CTRLMODE_FD | CAN_CTRLMODE_FD_NON_ISO | 1895 CAN_CTRLMODE_CC_LEN8_DLC; 1896 priv->ndev = ndev; 1897 priv->spi = spi; 1898 priv->rx_int = rx_int; 1899 priv->clk = clk; 1900 priv->reg_vdd = reg_vdd; 1901 priv->reg_xceiver = reg_xceiver; 1902 1903 match = device_get_match_data(&spi->dev); 1904 if (match) 1905 priv->devtype_data = *(struct mcp251xfd_devtype_data *)match; 1906 else 1907 priv->devtype_data = *(struct mcp251xfd_devtype_data *) 1908 spi_get_device_id(spi)->driver_data; 1909 1910 /* Errata Reference: 1911 * mcp2517fd: DS80000792C 5., mcp2518fd: DS80000789C 4. 1912 * 1913 * The SPI can write corrupted data to the RAM at fast SPI 1914 * speeds: 1915 * 1916 * Simultaneous activity on the CAN bus while writing data to 1917 * RAM via the SPI interface, with high SCK frequency, can 1918 * lead to corrupted data being written to RAM. 1919 * 1920 * Fix/Work Around: 1921 * Ensure that FSCK is less than or equal to 0.85 * 1922 * (FSYSCLK/2). 1923 * 1924 * Known good combinations are: 1925 * 1926 * MCP ext-clk SoC SPI SPI-clk max-clk parent-clk config 1927 * 1928 * 2518 20 MHz allwinner,sun8i-h3 allwinner,sun8i-h3-spi 8333333 Hz 83.33% 600000000 Hz assigned-clocks = <&ccu CLK_SPIx> 1929 * 2518 40 MHz allwinner,sun8i-h3 allwinner,sun8i-h3-spi 16666667 Hz 83.33% 600000000 Hz assigned-clocks = <&ccu CLK_SPIx> 1930 * 2517 40 MHz atmel,sama5d27 atmel,at91rm9200-spi 16400000 Hz 82.00% 82000000 Hz default 1931 * 2518 40 MHz atmel,sama5d27 atmel,at91rm9200-spi 16400000 Hz 82.00% 82000000 Hz default 1932 * 2518 40 MHz fsl,imx6dl fsl,imx51-ecspi 15000000 Hz 75.00% 30000000 Hz default 1933 * 2517 20 MHz fsl,imx8mm fsl,imx51-ecspi 8333333 Hz 83.33% 16666667 Hz assigned-clocks = <&clk IMX8MM_CLK_ECSPIx_ROOT> 1934 * 1935 */ 1936 priv->spi_max_speed_hz_orig = spi->max_speed_hz; 1937 spi->max_speed_hz = min(spi->max_speed_hz, freq / 2 / 1000 * 850); 1938 spi->bits_per_word = 8; 1939 spi->rt = true; 1940 err = spi_setup(spi); 1941 if (err) 1942 goto out_free_candev; 1943 1944 err = mcp251xfd_regmap_init(priv); 1945 if (err) 1946 goto out_free_candev; 1947 1948 err = can_rx_offload_add_manual(ndev, &priv->offload, 1949 MCP251XFD_NAPI_WEIGHT); 1950 if (err) 1951 goto out_free_candev; 1952 1953 err = mcp251xfd_register(priv); 1954 if (err) 1955 goto out_can_rx_offload_del; 1956 1957 return 0; 1958 1959 out_can_rx_offload_del: 1960 can_rx_offload_del(&priv->offload); 1961 out_free_candev: 1962 spi->max_speed_hz = priv->spi_max_speed_hz_orig; 1963 1964 free_candev(ndev); 1965 1966 return err; 1967 } 1968 1969 static int mcp251xfd_remove(struct spi_device *spi) 1970 { 1971 struct mcp251xfd_priv *priv = spi_get_drvdata(spi); 1972 struct net_device *ndev = priv->ndev; 1973 1974 can_rx_offload_del(&priv->offload); 1975 mcp251xfd_unregister(priv); 1976 spi->max_speed_hz = priv->spi_max_speed_hz_orig; 1977 free_candev(ndev); 1978 1979 return 0; 1980 } 1981 1982 static int __maybe_unused mcp251xfd_runtime_suspend(struct device *device) 1983 { 1984 const struct mcp251xfd_priv *priv = dev_get_drvdata(device); 1985 1986 return mcp251xfd_clks_and_vdd_disable(priv); 1987 } 1988 1989 static int __maybe_unused mcp251xfd_runtime_resume(struct device *device) 1990 { 1991 const struct mcp251xfd_priv *priv = dev_get_drvdata(device); 1992 1993 return mcp251xfd_clks_and_vdd_enable(priv); 1994 } 1995 1996 static const struct dev_pm_ops mcp251xfd_pm_ops = { 1997 SET_RUNTIME_PM_OPS(mcp251xfd_runtime_suspend, 1998 mcp251xfd_runtime_resume, NULL) 1999 }; 2000 2001 static struct spi_driver mcp251xfd_driver = { 2002 .driver = { 2003 .name = DEVICE_NAME, 2004 .pm = &mcp251xfd_pm_ops, 2005 .of_match_table = mcp251xfd_of_match, 2006 }, 2007 .probe = mcp251xfd_probe, 2008 .remove = mcp251xfd_remove, 2009 .id_table = mcp251xfd_id_table, 2010 }; 2011 module_spi_driver(mcp251xfd_driver); 2012 2013 MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>"); 2014 MODULE_DESCRIPTION("Microchip MCP251xFD Family CAN controller driver"); 2015 MODULE_LICENSE("GPL v2"); 2016