1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * CAN bus driver for Microchip 251x/25625 CAN Controller with SPI Interface 4 * 5 * MCP2510 support and bug fixes by Christian Pellegrin 6 * <chripell@evolware.org> 7 * 8 * Copyright 2009 Christian Pellegrin EVOL S.r.l. 9 * 10 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved. 11 * Written under contract by: 12 * Chris Elston, Katalix Systems, Ltd. 13 * 14 * Based on Microchip MCP251x CAN controller driver written by 15 * David Vrabel, Copyright 2006 Arcom Control Systems Ltd. 16 * 17 * Based on CAN bus driver for the CCAN controller written by 18 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix 19 * - Simon Kallweit, intefo AG 20 * Copyright 2007 21 * 22 * Your platform definition file should specify something like: 23 * 24 * static struct mcp251x_platform_data mcp251x_info = { 25 * .oscillator_frequency = 8000000, 26 * }; 27 * 28 * static struct spi_board_info spi_board_info[] = { 29 * { 30 * .modalias = "mcp2510", 31 * // "mcp2515" or "mcp25625" depending on your controller 32 * .platform_data = &mcp251x_info, 33 * .irq = IRQ_EINT13, 34 * .max_speed_hz = 2*1000*1000, 35 * .chip_select = 2, 36 * }, 37 * }; 38 * 39 * Please see mcp251x.h for a description of the fields in 40 * struct mcp251x_platform_data. 41 */ 42 43 #include <linux/can/core.h> 44 #include <linux/can/dev.h> 45 #include <linux/can/led.h> 46 #include <linux/can/platform/mcp251x.h> 47 #include <linux/clk.h> 48 #include <linux/completion.h> 49 #include <linux/delay.h> 50 #include <linux/device.h> 51 #include <linux/dma-mapping.h> 52 #include <linux/freezer.h> 53 #include <linux/interrupt.h> 54 #include <linux/io.h> 55 #include <linux/kernel.h> 56 #include <linux/module.h> 57 #include <linux/netdevice.h> 58 #include <linux/of.h> 59 #include <linux/of_device.h> 60 #include <linux/platform_device.h> 61 #include <linux/slab.h> 62 #include <linux/spi/spi.h> 63 #include <linux/uaccess.h> 64 #include <linux/regulator/consumer.h> 65 66 /* SPI interface instruction set */ 67 #define INSTRUCTION_WRITE 0x02 68 #define INSTRUCTION_READ 0x03 69 #define INSTRUCTION_BIT_MODIFY 0x05 70 #define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n)) 71 #define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94) 72 #define INSTRUCTION_RESET 0xC0 73 #define RTS_TXB0 0x01 74 #define RTS_TXB1 0x02 75 #define RTS_TXB2 0x04 76 #define INSTRUCTION_RTS(n) (0x80 | ((n) & 0x07)) 77 78 79 /* MPC251x registers */ 80 #define CANSTAT 0x0e 81 #define CANCTRL 0x0f 82 # define CANCTRL_REQOP_MASK 0xe0 83 # define CANCTRL_REQOP_CONF 0x80 84 # define CANCTRL_REQOP_LISTEN_ONLY 0x60 85 # define CANCTRL_REQOP_LOOPBACK 0x40 86 # define CANCTRL_REQOP_SLEEP 0x20 87 # define CANCTRL_REQOP_NORMAL 0x00 88 # define CANCTRL_OSM 0x08 89 # define CANCTRL_ABAT 0x10 90 #define TEC 0x1c 91 #define REC 0x1d 92 #define CNF1 0x2a 93 # define CNF1_SJW_SHIFT 6 94 #define CNF2 0x29 95 # define CNF2_BTLMODE 0x80 96 # define CNF2_SAM 0x40 97 # define CNF2_PS1_SHIFT 3 98 #define CNF3 0x28 99 # define CNF3_SOF 0x08 100 # define CNF3_WAKFIL 0x04 101 # define CNF3_PHSEG2_MASK 0x07 102 #define CANINTE 0x2b 103 # define CANINTE_MERRE 0x80 104 # define CANINTE_WAKIE 0x40 105 # define CANINTE_ERRIE 0x20 106 # define CANINTE_TX2IE 0x10 107 # define CANINTE_TX1IE 0x08 108 # define CANINTE_TX0IE 0x04 109 # define CANINTE_RX1IE 0x02 110 # define CANINTE_RX0IE 0x01 111 #define CANINTF 0x2c 112 # define CANINTF_MERRF 0x80 113 # define CANINTF_WAKIF 0x40 114 # define CANINTF_ERRIF 0x20 115 # define CANINTF_TX2IF 0x10 116 # define CANINTF_TX1IF 0x08 117 # define CANINTF_TX0IF 0x04 118 # define CANINTF_RX1IF 0x02 119 # define CANINTF_RX0IF 0x01 120 # define CANINTF_RX (CANINTF_RX0IF | CANINTF_RX1IF) 121 # define CANINTF_TX (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF) 122 # define CANINTF_ERR (CANINTF_ERRIF) 123 #define EFLG 0x2d 124 # define EFLG_EWARN 0x01 125 # define EFLG_RXWAR 0x02 126 # define EFLG_TXWAR 0x04 127 # define EFLG_RXEP 0x08 128 # define EFLG_TXEP 0x10 129 # define EFLG_TXBO 0x20 130 # define EFLG_RX0OVR 0x40 131 # define EFLG_RX1OVR 0x80 132 #define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF) 133 # define TXBCTRL_ABTF 0x40 134 # define TXBCTRL_MLOA 0x20 135 # define TXBCTRL_TXERR 0x10 136 # define TXBCTRL_TXREQ 0x08 137 #define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF) 138 # define SIDH_SHIFT 3 139 #define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF) 140 # define SIDL_SID_MASK 7 141 # define SIDL_SID_SHIFT 5 142 # define SIDL_EXIDE_SHIFT 3 143 # define SIDL_EID_SHIFT 16 144 # define SIDL_EID_MASK 3 145 #define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF) 146 #define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF) 147 #define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF) 148 # define DLC_RTR_SHIFT 6 149 #define TXBCTRL_OFF 0 150 #define TXBSIDH_OFF 1 151 #define TXBSIDL_OFF 2 152 #define TXBEID8_OFF 3 153 #define TXBEID0_OFF 4 154 #define TXBDLC_OFF 5 155 #define TXBDAT_OFF 6 156 #define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF) 157 # define RXBCTRL_BUKT 0x04 158 # define RXBCTRL_RXM0 0x20 159 # define RXBCTRL_RXM1 0x40 160 #define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF) 161 # define RXBSIDH_SHIFT 3 162 #define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF) 163 # define RXBSIDL_IDE 0x08 164 # define RXBSIDL_SRR 0x10 165 # define RXBSIDL_EID 3 166 # define RXBSIDL_SHIFT 5 167 #define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF) 168 #define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF) 169 #define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF) 170 # define RXBDLC_LEN_MASK 0x0f 171 # define RXBDLC_RTR 0x40 172 #define RXBCTRL_OFF 0 173 #define RXBSIDH_OFF 1 174 #define RXBSIDL_OFF 2 175 #define RXBEID8_OFF 3 176 #define RXBEID0_OFF 4 177 #define RXBDLC_OFF 5 178 #define RXBDAT_OFF 6 179 #define RXFSID(n) ((n < 3) ? 0 : 4) 180 #define RXFSIDH(n) ((n) * 4 + RXFSID(n)) 181 #define RXFSIDL(n) ((n) * 4 + 1 + RXFSID(n)) 182 #define RXFEID8(n) ((n) * 4 + 2 + RXFSID(n)) 183 #define RXFEID0(n) ((n) * 4 + 3 + RXFSID(n)) 184 #define RXMSIDH(n) ((n) * 4 + 0x20) 185 #define RXMSIDL(n) ((n) * 4 + 0x21) 186 #define RXMEID8(n) ((n) * 4 + 0x22) 187 #define RXMEID0(n) ((n) * 4 + 0x23) 188 189 #define GET_BYTE(val, byte) \ 190 (((val) >> ((byte) * 8)) & 0xff) 191 #define SET_BYTE(val, byte) \ 192 (((val) & 0xff) << ((byte) * 8)) 193 194 /* 195 * Buffer size required for the largest SPI transfer (i.e., reading a 196 * frame) 197 */ 198 #define CAN_FRAME_MAX_DATA_LEN 8 199 #define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN) 200 #define CAN_FRAME_MAX_BITS 128 201 202 #define TX_ECHO_SKB_MAX 1 203 204 #define MCP251X_OST_DELAY_MS (5) 205 206 #define DEVICE_NAME "mcp251x" 207 208 static int mcp251x_enable_dma; /* Enable SPI DMA. Default: 0 (Off) */ 209 module_param(mcp251x_enable_dma, int, 0444); 210 MODULE_PARM_DESC(mcp251x_enable_dma, "Enable SPI DMA. Default: 0 (Off)"); 211 212 static const struct can_bittiming_const mcp251x_bittiming_const = { 213 .name = DEVICE_NAME, 214 .tseg1_min = 3, 215 .tseg1_max = 16, 216 .tseg2_min = 2, 217 .tseg2_max = 8, 218 .sjw_max = 4, 219 .brp_min = 1, 220 .brp_max = 64, 221 .brp_inc = 1, 222 }; 223 224 enum mcp251x_model { 225 CAN_MCP251X_MCP2510 = 0x2510, 226 CAN_MCP251X_MCP2515 = 0x2515, 227 CAN_MCP251X_MCP25625 = 0x25625, 228 }; 229 230 struct mcp251x_priv { 231 struct can_priv can; 232 struct net_device *net; 233 struct spi_device *spi; 234 enum mcp251x_model model; 235 236 struct mutex mcp_lock; /* SPI device lock */ 237 238 u8 *spi_tx_buf; 239 u8 *spi_rx_buf; 240 dma_addr_t spi_tx_dma; 241 dma_addr_t spi_rx_dma; 242 243 struct sk_buff *tx_skb; 244 int tx_len; 245 246 struct workqueue_struct *wq; 247 struct work_struct tx_work; 248 struct work_struct restart_work; 249 250 int force_quit; 251 int after_suspend; 252 #define AFTER_SUSPEND_UP 1 253 #define AFTER_SUSPEND_DOWN 2 254 #define AFTER_SUSPEND_POWER 4 255 #define AFTER_SUSPEND_RESTART 8 256 int restart_tx; 257 struct regulator *power; 258 struct regulator *transceiver; 259 struct clk *clk; 260 }; 261 262 #define MCP251X_IS(_model) \ 263 static inline int mcp251x_is_##_model(struct spi_device *spi) \ 264 { \ 265 struct mcp251x_priv *priv = spi_get_drvdata(spi); \ 266 return priv->model == CAN_MCP251X_MCP##_model; \ 267 } 268 269 MCP251X_IS(2510); 270 271 static void mcp251x_clean(struct net_device *net) 272 { 273 struct mcp251x_priv *priv = netdev_priv(net); 274 275 if (priv->tx_skb || priv->tx_len) 276 net->stats.tx_errors++; 277 if (priv->tx_skb) 278 dev_kfree_skb(priv->tx_skb); 279 if (priv->tx_len) 280 can_free_echo_skb(priv->net, 0); 281 priv->tx_skb = NULL; 282 priv->tx_len = 0; 283 } 284 285 /* 286 * Note about handling of error return of mcp251x_spi_trans: accessing 287 * registers via SPI is not really different conceptually than using 288 * normal I/O assembler instructions, although it's much more 289 * complicated from a practical POV. So it's not advisable to always 290 * check the return value of this function. Imagine that every 291 * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0) 292 * error();", it would be a great mess (well there are some situation 293 * when exception handling C++ like could be useful after all). So we 294 * just check that transfers are OK at the beginning of our 295 * conversation with the chip and to avoid doing really nasty things 296 * (like injecting bogus packets in the network stack). 297 */ 298 static int mcp251x_spi_trans(struct spi_device *spi, int len) 299 { 300 struct mcp251x_priv *priv = spi_get_drvdata(spi); 301 struct spi_transfer t = { 302 .tx_buf = priv->spi_tx_buf, 303 .rx_buf = priv->spi_rx_buf, 304 .len = len, 305 .cs_change = 0, 306 }; 307 struct spi_message m; 308 int ret; 309 310 spi_message_init(&m); 311 312 if (mcp251x_enable_dma) { 313 t.tx_dma = priv->spi_tx_dma; 314 t.rx_dma = priv->spi_rx_dma; 315 m.is_dma_mapped = 1; 316 } 317 318 spi_message_add_tail(&t, &m); 319 320 ret = spi_sync(spi, &m); 321 if (ret) 322 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret); 323 return ret; 324 } 325 326 static u8 mcp251x_read_reg(struct spi_device *spi, uint8_t reg) 327 { 328 struct mcp251x_priv *priv = spi_get_drvdata(spi); 329 u8 val = 0; 330 331 priv->spi_tx_buf[0] = INSTRUCTION_READ; 332 priv->spi_tx_buf[1] = reg; 333 334 mcp251x_spi_trans(spi, 3); 335 val = priv->spi_rx_buf[2]; 336 337 return val; 338 } 339 340 static void mcp251x_read_2regs(struct spi_device *spi, uint8_t reg, 341 uint8_t *v1, uint8_t *v2) 342 { 343 struct mcp251x_priv *priv = spi_get_drvdata(spi); 344 345 priv->spi_tx_buf[0] = INSTRUCTION_READ; 346 priv->spi_tx_buf[1] = reg; 347 348 mcp251x_spi_trans(spi, 4); 349 350 *v1 = priv->spi_rx_buf[2]; 351 *v2 = priv->spi_rx_buf[3]; 352 } 353 354 static void mcp251x_write_reg(struct spi_device *spi, u8 reg, uint8_t val) 355 { 356 struct mcp251x_priv *priv = spi_get_drvdata(spi); 357 358 priv->spi_tx_buf[0] = INSTRUCTION_WRITE; 359 priv->spi_tx_buf[1] = reg; 360 priv->spi_tx_buf[2] = val; 361 362 mcp251x_spi_trans(spi, 3); 363 } 364 365 static void mcp251x_write_bits(struct spi_device *spi, u8 reg, 366 u8 mask, uint8_t val) 367 { 368 struct mcp251x_priv *priv = spi_get_drvdata(spi); 369 370 priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY; 371 priv->spi_tx_buf[1] = reg; 372 priv->spi_tx_buf[2] = mask; 373 priv->spi_tx_buf[3] = val; 374 375 mcp251x_spi_trans(spi, 4); 376 } 377 378 static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf, 379 int len, int tx_buf_idx) 380 { 381 struct mcp251x_priv *priv = spi_get_drvdata(spi); 382 383 if (mcp251x_is_2510(spi)) { 384 int i; 385 386 for (i = 1; i < TXBDAT_OFF + len; i++) 387 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + i, 388 buf[i]); 389 } else { 390 memcpy(priv->spi_tx_buf, buf, TXBDAT_OFF + len); 391 mcp251x_spi_trans(spi, TXBDAT_OFF + len); 392 } 393 } 394 395 static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame, 396 int tx_buf_idx) 397 { 398 struct mcp251x_priv *priv = spi_get_drvdata(spi); 399 u32 sid, eid, exide, rtr; 400 u8 buf[SPI_TRANSFER_BUF_LEN]; 401 402 exide = (frame->can_id & CAN_EFF_FLAG) ? 1 : 0; /* Extended ID Enable */ 403 if (exide) 404 sid = (frame->can_id & CAN_EFF_MASK) >> 18; 405 else 406 sid = frame->can_id & CAN_SFF_MASK; /* Standard ID */ 407 eid = frame->can_id & CAN_EFF_MASK; /* Extended ID */ 408 rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0; /* Remote transmission */ 409 410 buf[TXBCTRL_OFF] = INSTRUCTION_LOAD_TXB(tx_buf_idx); 411 buf[TXBSIDH_OFF] = sid >> SIDH_SHIFT; 412 buf[TXBSIDL_OFF] = ((sid & SIDL_SID_MASK) << SIDL_SID_SHIFT) | 413 (exide << SIDL_EXIDE_SHIFT) | 414 ((eid >> SIDL_EID_SHIFT) & SIDL_EID_MASK); 415 buf[TXBEID8_OFF] = GET_BYTE(eid, 1); 416 buf[TXBEID0_OFF] = GET_BYTE(eid, 0); 417 buf[TXBDLC_OFF] = (rtr << DLC_RTR_SHIFT) | frame->can_dlc; 418 memcpy(buf + TXBDAT_OFF, frame->data, frame->can_dlc); 419 mcp251x_hw_tx_frame(spi, buf, frame->can_dlc, tx_buf_idx); 420 421 /* use INSTRUCTION_RTS, to avoid "repeated frame problem" */ 422 priv->spi_tx_buf[0] = INSTRUCTION_RTS(1 << tx_buf_idx); 423 mcp251x_spi_trans(priv->spi, 1); 424 } 425 426 static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf, 427 int buf_idx) 428 { 429 struct mcp251x_priv *priv = spi_get_drvdata(spi); 430 431 if (mcp251x_is_2510(spi)) { 432 int i, len; 433 434 for (i = 1; i < RXBDAT_OFF; i++) 435 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i); 436 437 len = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK); 438 for (; i < (RXBDAT_OFF + len); i++) 439 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i); 440 } else { 441 priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx); 442 mcp251x_spi_trans(spi, SPI_TRANSFER_BUF_LEN); 443 memcpy(buf, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN); 444 } 445 } 446 447 static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx) 448 { 449 struct mcp251x_priv *priv = spi_get_drvdata(spi); 450 struct sk_buff *skb; 451 struct can_frame *frame; 452 u8 buf[SPI_TRANSFER_BUF_LEN]; 453 454 skb = alloc_can_skb(priv->net, &frame); 455 if (!skb) { 456 dev_err(&spi->dev, "cannot allocate RX skb\n"); 457 priv->net->stats.rx_dropped++; 458 return; 459 } 460 461 mcp251x_hw_rx_frame(spi, buf, buf_idx); 462 if (buf[RXBSIDL_OFF] & RXBSIDL_IDE) { 463 /* Extended ID format */ 464 frame->can_id = CAN_EFF_FLAG; 465 frame->can_id |= 466 /* Extended ID part */ 467 SET_BYTE(buf[RXBSIDL_OFF] & RXBSIDL_EID, 2) | 468 SET_BYTE(buf[RXBEID8_OFF], 1) | 469 SET_BYTE(buf[RXBEID0_OFF], 0) | 470 /* Standard ID part */ 471 (((buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) | 472 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT)) << 18); 473 /* Remote transmission request */ 474 if (buf[RXBDLC_OFF] & RXBDLC_RTR) 475 frame->can_id |= CAN_RTR_FLAG; 476 } else { 477 /* Standard ID format */ 478 frame->can_id = 479 (buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) | 480 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT); 481 if (buf[RXBSIDL_OFF] & RXBSIDL_SRR) 482 frame->can_id |= CAN_RTR_FLAG; 483 } 484 /* Data length */ 485 frame->can_dlc = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK); 486 memcpy(frame->data, buf + RXBDAT_OFF, frame->can_dlc); 487 488 priv->net->stats.rx_packets++; 489 priv->net->stats.rx_bytes += frame->can_dlc; 490 491 can_led_event(priv->net, CAN_LED_EVENT_RX); 492 493 netif_rx_ni(skb); 494 } 495 496 static void mcp251x_hw_sleep(struct spi_device *spi) 497 { 498 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP); 499 } 500 501 static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb, 502 struct net_device *net) 503 { 504 struct mcp251x_priv *priv = netdev_priv(net); 505 struct spi_device *spi = priv->spi; 506 507 if (priv->tx_skb || priv->tx_len) { 508 dev_warn(&spi->dev, "hard_xmit called while tx busy\n"); 509 return NETDEV_TX_BUSY; 510 } 511 512 if (can_dropped_invalid_skb(net, skb)) 513 return NETDEV_TX_OK; 514 515 netif_stop_queue(net); 516 priv->tx_skb = skb; 517 queue_work(priv->wq, &priv->tx_work); 518 519 return NETDEV_TX_OK; 520 } 521 522 static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode) 523 { 524 struct mcp251x_priv *priv = netdev_priv(net); 525 526 switch (mode) { 527 case CAN_MODE_START: 528 mcp251x_clean(net); 529 /* We have to delay work since SPI I/O may sleep */ 530 priv->can.state = CAN_STATE_ERROR_ACTIVE; 531 priv->restart_tx = 1; 532 if (priv->can.restart_ms == 0) 533 priv->after_suspend = AFTER_SUSPEND_RESTART; 534 queue_work(priv->wq, &priv->restart_work); 535 break; 536 default: 537 return -EOPNOTSUPP; 538 } 539 540 return 0; 541 } 542 543 static int mcp251x_set_normal_mode(struct spi_device *spi) 544 { 545 struct mcp251x_priv *priv = spi_get_drvdata(spi); 546 unsigned long timeout; 547 548 /* Enable interrupts */ 549 mcp251x_write_reg(spi, CANINTE, 550 CANINTE_ERRIE | CANINTE_TX2IE | CANINTE_TX1IE | 551 CANINTE_TX0IE | CANINTE_RX1IE | CANINTE_RX0IE); 552 553 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 554 /* Put device into loopback mode */ 555 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK); 556 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) { 557 /* Put device into listen-only mode */ 558 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LISTEN_ONLY); 559 } else { 560 /* Put device into normal mode */ 561 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL); 562 563 /* Wait for the device to enter normal mode */ 564 timeout = jiffies + HZ; 565 while (mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) { 566 schedule(); 567 if (time_after(jiffies, timeout)) { 568 dev_err(&spi->dev, "MCP251x didn't" 569 " enter in normal mode\n"); 570 return -EBUSY; 571 } 572 } 573 } 574 priv->can.state = CAN_STATE_ERROR_ACTIVE; 575 return 0; 576 } 577 578 static int mcp251x_do_set_bittiming(struct net_device *net) 579 { 580 struct mcp251x_priv *priv = netdev_priv(net); 581 struct can_bittiming *bt = &priv->can.bittiming; 582 struct spi_device *spi = priv->spi; 583 584 mcp251x_write_reg(spi, CNF1, ((bt->sjw - 1) << CNF1_SJW_SHIFT) | 585 (bt->brp - 1)); 586 mcp251x_write_reg(spi, CNF2, CNF2_BTLMODE | 587 (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ? 588 CNF2_SAM : 0) | 589 ((bt->phase_seg1 - 1) << CNF2_PS1_SHIFT) | 590 (bt->prop_seg - 1)); 591 mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK, 592 (bt->phase_seg2 - 1)); 593 dev_dbg(&spi->dev, "CNF: 0x%02x 0x%02x 0x%02x\n", 594 mcp251x_read_reg(spi, CNF1), 595 mcp251x_read_reg(spi, CNF2), 596 mcp251x_read_reg(spi, CNF3)); 597 598 return 0; 599 } 600 601 static int mcp251x_setup(struct net_device *net, struct spi_device *spi) 602 { 603 mcp251x_do_set_bittiming(net); 604 605 mcp251x_write_reg(spi, RXBCTRL(0), 606 RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1); 607 mcp251x_write_reg(spi, RXBCTRL(1), 608 RXBCTRL_RXM0 | RXBCTRL_RXM1); 609 return 0; 610 } 611 612 static int mcp251x_hw_reset(struct spi_device *spi) 613 { 614 struct mcp251x_priv *priv = spi_get_drvdata(spi); 615 u8 reg; 616 int ret; 617 618 /* Wait for oscillator startup timer after power up */ 619 mdelay(MCP251X_OST_DELAY_MS); 620 621 priv->spi_tx_buf[0] = INSTRUCTION_RESET; 622 ret = mcp251x_spi_trans(spi, 1); 623 if (ret) 624 return ret; 625 626 /* Wait for oscillator startup timer after reset */ 627 mdelay(MCP251X_OST_DELAY_MS); 628 629 reg = mcp251x_read_reg(spi, CANSTAT); 630 if ((reg & CANCTRL_REQOP_MASK) != CANCTRL_REQOP_CONF) 631 return -ENODEV; 632 633 return 0; 634 } 635 636 static int mcp251x_hw_probe(struct spi_device *spi) 637 { 638 u8 ctrl; 639 int ret; 640 641 ret = mcp251x_hw_reset(spi); 642 if (ret) 643 return ret; 644 645 ctrl = mcp251x_read_reg(spi, CANCTRL); 646 647 dev_dbg(&spi->dev, "CANCTRL 0x%02x\n", ctrl); 648 649 /* Check for power up default value */ 650 if ((ctrl & 0x17) != 0x07) 651 return -ENODEV; 652 653 return 0; 654 } 655 656 static int mcp251x_power_enable(struct regulator *reg, int enable) 657 { 658 if (IS_ERR_OR_NULL(reg)) 659 return 0; 660 661 if (enable) 662 return regulator_enable(reg); 663 else 664 return regulator_disable(reg); 665 } 666 667 static int mcp251x_stop(struct net_device *net) 668 { 669 struct mcp251x_priv *priv = netdev_priv(net); 670 struct spi_device *spi = priv->spi; 671 672 close_candev(net); 673 674 priv->force_quit = 1; 675 free_irq(spi->irq, priv); 676 destroy_workqueue(priv->wq); 677 priv->wq = NULL; 678 679 mutex_lock(&priv->mcp_lock); 680 681 /* Disable and clear pending interrupts */ 682 mcp251x_write_reg(spi, CANINTE, 0x00); 683 mcp251x_write_reg(spi, CANINTF, 0x00); 684 685 mcp251x_write_reg(spi, TXBCTRL(0), 0); 686 mcp251x_clean(net); 687 688 mcp251x_hw_sleep(spi); 689 690 mcp251x_power_enable(priv->transceiver, 0); 691 692 priv->can.state = CAN_STATE_STOPPED; 693 694 mutex_unlock(&priv->mcp_lock); 695 696 can_led_event(net, CAN_LED_EVENT_STOP); 697 698 return 0; 699 } 700 701 static void mcp251x_error_skb(struct net_device *net, int can_id, int data1) 702 { 703 struct sk_buff *skb; 704 struct can_frame *frame; 705 706 skb = alloc_can_err_skb(net, &frame); 707 if (skb) { 708 frame->can_id |= can_id; 709 frame->data[1] = data1; 710 netif_rx_ni(skb); 711 } else { 712 netdev_err(net, "cannot allocate error skb\n"); 713 } 714 } 715 716 static void mcp251x_tx_work_handler(struct work_struct *ws) 717 { 718 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv, 719 tx_work); 720 struct spi_device *spi = priv->spi; 721 struct net_device *net = priv->net; 722 struct can_frame *frame; 723 724 mutex_lock(&priv->mcp_lock); 725 if (priv->tx_skb) { 726 if (priv->can.state == CAN_STATE_BUS_OFF) { 727 mcp251x_clean(net); 728 } else { 729 frame = (struct can_frame *)priv->tx_skb->data; 730 731 if (frame->can_dlc > CAN_FRAME_MAX_DATA_LEN) 732 frame->can_dlc = CAN_FRAME_MAX_DATA_LEN; 733 mcp251x_hw_tx(spi, frame, 0); 734 priv->tx_len = 1 + frame->can_dlc; 735 can_put_echo_skb(priv->tx_skb, net, 0); 736 priv->tx_skb = NULL; 737 } 738 } 739 mutex_unlock(&priv->mcp_lock); 740 } 741 742 static void mcp251x_restart_work_handler(struct work_struct *ws) 743 { 744 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv, 745 restart_work); 746 struct spi_device *spi = priv->spi; 747 struct net_device *net = priv->net; 748 749 mutex_lock(&priv->mcp_lock); 750 if (priv->after_suspend) { 751 mcp251x_hw_reset(spi); 752 mcp251x_setup(net, spi); 753 if (priv->after_suspend & AFTER_SUSPEND_RESTART) { 754 mcp251x_set_normal_mode(spi); 755 } else if (priv->after_suspend & AFTER_SUSPEND_UP) { 756 netif_device_attach(net); 757 mcp251x_clean(net); 758 mcp251x_set_normal_mode(spi); 759 netif_wake_queue(net); 760 } else { 761 mcp251x_hw_sleep(spi); 762 } 763 priv->after_suspend = 0; 764 priv->force_quit = 0; 765 } 766 767 if (priv->restart_tx) { 768 priv->restart_tx = 0; 769 mcp251x_write_reg(spi, TXBCTRL(0), 0); 770 mcp251x_clean(net); 771 netif_wake_queue(net); 772 mcp251x_error_skb(net, CAN_ERR_RESTARTED, 0); 773 } 774 mutex_unlock(&priv->mcp_lock); 775 } 776 777 static irqreturn_t mcp251x_can_ist(int irq, void *dev_id) 778 { 779 struct mcp251x_priv *priv = dev_id; 780 struct spi_device *spi = priv->spi; 781 struct net_device *net = priv->net; 782 783 mutex_lock(&priv->mcp_lock); 784 while (!priv->force_quit) { 785 enum can_state new_state; 786 u8 intf, eflag; 787 u8 clear_intf = 0; 788 int can_id = 0, data1 = 0; 789 790 mcp251x_read_2regs(spi, CANINTF, &intf, &eflag); 791 792 /* mask out flags we don't care about */ 793 intf &= CANINTF_RX | CANINTF_TX | CANINTF_ERR; 794 795 /* receive buffer 0 */ 796 if (intf & CANINTF_RX0IF) { 797 mcp251x_hw_rx(spi, 0); 798 /* Free one buffer ASAP 799 * (The MCP2515/25625 does this automatically.) 800 */ 801 if (mcp251x_is_2510(spi)) 802 mcp251x_write_bits(spi, CANINTF, CANINTF_RX0IF, 0x00); 803 } 804 805 /* receive buffer 1 */ 806 if (intf & CANINTF_RX1IF) { 807 mcp251x_hw_rx(spi, 1); 808 /* The MCP2515/25625 does this automatically. */ 809 if (mcp251x_is_2510(spi)) 810 clear_intf |= CANINTF_RX1IF; 811 } 812 813 /* any error or tx interrupt we need to clear? */ 814 if (intf & (CANINTF_ERR | CANINTF_TX)) 815 clear_intf |= intf & (CANINTF_ERR | CANINTF_TX); 816 if (clear_intf) 817 mcp251x_write_bits(spi, CANINTF, clear_intf, 0x00); 818 819 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) 820 mcp251x_write_bits(spi, EFLG, eflag, 0x00); 821 822 /* Update can state */ 823 if (eflag & EFLG_TXBO) { 824 new_state = CAN_STATE_BUS_OFF; 825 can_id |= CAN_ERR_BUSOFF; 826 } else if (eflag & EFLG_TXEP) { 827 new_state = CAN_STATE_ERROR_PASSIVE; 828 can_id |= CAN_ERR_CRTL; 829 data1 |= CAN_ERR_CRTL_TX_PASSIVE; 830 } else if (eflag & EFLG_RXEP) { 831 new_state = CAN_STATE_ERROR_PASSIVE; 832 can_id |= CAN_ERR_CRTL; 833 data1 |= CAN_ERR_CRTL_RX_PASSIVE; 834 } else if (eflag & EFLG_TXWAR) { 835 new_state = CAN_STATE_ERROR_WARNING; 836 can_id |= CAN_ERR_CRTL; 837 data1 |= CAN_ERR_CRTL_TX_WARNING; 838 } else if (eflag & EFLG_RXWAR) { 839 new_state = CAN_STATE_ERROR_WARNING; 840 can_id |= CAN_ERR_CRTL; 841 data1 |= CAN_ERR_CRTL_RX_WARNING; 842 } else { 843 new_state = CAN_STATE_ERROR_ACTIVE; 844 } 845 846 /* Update can state statistics */ 847 switch (priv->can.state) { 848 case CAN_STATE_ERROR_ACTIVE: 849 if (new_state >= CAN_STATE_ERROR_WARNING && 850 new_state <= CAN_STATE_BUS_OFF) 851 priv->can.can_stats.error_warning++; 852 /* fall through */ 853 case CAN_STATE_ERROR_WARNING: 854 if (new_state >= CAN_STATE_ERROR_PASSIVE && 855 new_state <= CAN_STATE_BUS_OFF) 856 priv->can.can_stats.error_passive++; 857 break; 858 default: 859 break; 860 } 861 priv->can.state = new_state; 862 863 if (intf & CANINTF_ERRIF) { 864 /* Handle overflow counters */ 865 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) { 866 if (eflag & EFLG_RX0OVR) { 867 net->stats.rx_over_errors++; 868 net->stats.rx_errors++; 869 } 870 if (eflag & EFLG_RX1OVR) { 871 net->stats.rx_over_errors++; 872 net->stats.rx_errors++; 873 } 874 can_id |= CAN_ERR_CRTL; 875 data1 |= CAN_ERR_CRTL_RX_OVERFLOW; 876 } 877 mcp251x_error_skb(net, can_id, data1); 878 } 879 880 if (priv->can.state == CAN_STATE_BUS_OFF) { 881 if (priv->can.restart_ms == 0) { 882 priv->force_quit = 1; 883 priv->can.can_stats.bus_off++; 884 can_bus_off(net); 885 mcp251x_hw_sleep(spi); 886 break; 887 } 888 } 889 890 if (intf == 0) 891 break; 892 893 if (intf & CANINTF_TX) { 894 net->stats.tx_packets++; 895 net->stats.tx_bytes += priv->tx_len - 1; 896 can_led_event(net, CAN_LED_EVENT_TX); 897 if (priv->tx_len) { 898 can_get_echo_skb(net, 0); 899 priv->tx_len = 0; 900 } 901 netif_wake_queue(net); 902 } 903 904 } 905 mutex_unlock(&priv->mcp_lock); 906 return IRQ_HANDLED; 907 } 908 909 static int mcp251x_open(struct net_device *net) 910 { 911 struct mcp251x_priv *priv = netdev_priv(net); 912 struct spi_device *spi = priv->spi; 913 unsigned long flags = IRQF_ONESHOT | IRQF_TRIGGER_FALLING; 914 int ret; 915 916 ret = open_candev(net); 917 if (ret) { 918 dev_err(&spi->dev, "unable to set initial baudrate!\n"); 919 return ret; 920 } 921 922 mutex_lock(&priv->mcp_lock); 923 mcp251x_power_enable(priv->transceiver, 1); 924 925 priv->force_quit = 0; 926 priv->tx_skb = NULL; 927 priv->tx_len = 0; 928 929 ret = request_threaded_irq(spi->irq, NULL, mcp251x_can_ist, 930 flags | IRQF_ONESHOT, DEVICE_NAME, priv); 931 if (ret) { 932 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq); 933 goto out_close; 934 } 935 936 priv->wq = alloc_workqueue("mcp251x_wq", WQ_FREEZABLE | WQ_MEM_RECLAIM, 937 0); 938 if (!priv->wq) { 939 ret = -ENOMEM; 940 goto out_clean; 941 } 942 INIT_WORK(&priv->tx_work, mcp251x_tx_work_handler); 943 INIT_WORK(&priv->restart_work, mcp251x_restart_work_handler); 944 945 ret = mcp251x_hw_reset(spi); 946 if (ret) 947 goto out_free_wq; 948 ret = mcp251x_setup(net, spi); 949 if (ret) 950 goto out_free_wq; 951 ret = mcp251x_set_normal_mode(spi); 952 if (ret) 953 goto out_free_wq; 954 955 can_led_event(net, CAN_LED_EVENT_OPEN); 956 957 netif_wake_queue(net); 958 mutex_unlock(&priv->mcp_lock); 959 960 return 0; 961 962 out_free_wq: 963 destroy_workqueue(priv->wq); 964 out_clean: 965 free_irq(spi->irq, priv); 966 mcp251x_hw_sleep(spi); 967 out_close: 968 mcp251x_power_enable(priv->transceiver, 0); 969 close_candev(net); 970 mutex_unlock(&priv->mcp_lock); 971 return ret; 972 } 973 974 static const struct net_device_ops mcp251x_netdev_ops = { 975 .ndo_open = mcp251x_open, 976 .ndo_stop = mcp251x_stop, 977 .ndo_start_xmit = mcp251x_hard_start_xmit, 978 .ndo_change_mtu = can_change_mtu, 979 }; 980 981 static const struct of_device_id mcp251x_of_match[] = { 982 { 983 .compatible = "microchip,mcp2510", 984 .data = (void *)CAN_MCP251X_MCP2510, 985 }, 986 { 987 .compatible = "microchip,mcp2515", 988 .data = (void *)CAN_MCP251X_MCP2515, 989 }, 990 { 991 .compatible = "microchip,mcp25625", 992 .data = (void *)CAN_MCP251X_MCP25625, 993 }, 994 { } 995 }; 996 MODULE_DEVICE_TABLE(of, mcp251x_of_match); 997 998 static const struct spi_device_id mcp251x_id_table[] = { 999 { 1000 .name = "mcp2510", 1001 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2510, 1002 }, 1003 { 1004 .name = "mcp2515", 1005 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2515, 1006 }, 1007 { 1008 .name = "mcp25625", 1009 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP25625, 1010 }, 1011 { } 1012 }; 1013 MODULE_DEVICE_TABLE(spi, mcp251x_id_table); 1014 1015 static int mcp251x_can_probe(struct spi_device *spi) 1016 { 1017 const struct of_device_id *of_id = of_match_device(mcp251x_of_match, 1018 &spi->dev); 1019 struct mcp251x_platform_data *pdata = dev_get_platdata(&spi->dev); 1020 struct net_device *net; 1021 struct mcp251x_priv *priv; 1022 struct clk *clk; 1023 int freq, ret; 1024 1025 clk = devm_clk_get(&spi->dev, NULL); 1026 if (IS_ERR(clk)) { 1027 if (pdata) 1028 freq = pdata->oscillator_frequency; 1029 else 1030 return PTR_ERR(clk); 1031 } else { 1032 freq = clk_get_rate(clk); 1033 } 1034 1035 /* Sanity check */ 1036 if (freq < 1000000 || freq > 25000000) 1037 return -ERANGE; 1038 1039 /* Allocate can/net device */ 1040 net = alloc_candev(sizeof(struct mcp251x_priv), TX_ECHO_SKB_MAX); 1041 if (!net) 1042 return -ENOMEM; 1043 1044 if (!IS_ERR(clk)) { 1045 ret = clk_prepare_enable(clk); 1046 if (ret) 1047 goto out_free; 1048 } 1049 1050 net->netdev_ops = &mcp251x_netdev_ops; 1051 net->flags |= IFF_ECHO; 1052 1053 priv = netdev_priv(net); 1054 priv->can.bittiming_const = &mcp251x_bittiming_const; 1055 priv->can.do_set_mode = mcp251x_do_set_mode; 1056 priv->can.clock.freq = freq / 2; 1057 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES | 1058 CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY; 1059 if (of_id) 1060 priv->model = (enum mcp251x_model)of_id->data; 1061 else 1062 priv->model = spi_get_device_id(spi)->driver_data; 1063 priv->net = net; 1064 priv->clk = clk; 1065 1066 spi_set_drvdata(spi, priv); 1067 1068 /* Configure the SPI bus */ 1069 spi->bits_per_word = 8; 1070 if (mcp251x_is_2510(spi)) 1071 spi->max_speed_hz = spi->max_speed_hz ? : 5 * 1000 * 1000; 1072 else 1073 spi->max_speed_hz = spi->max_speed_hz ? : 10 * 1000 * 1000; 1074 ret = spi_setup(spi); 1075 if (ret) 1076 goto out_clk; 1077 1078 priv->power = devm_regulator_get_optional(&spi->dev, "vdd"); 1079 priv->transceiver = devm_regulator_get_optional(&spi->dev, "xceiver"); 1080 if ((PTR_ERR(priv->power) == -EPROBE_DEFER) || 1081 (PTR_ERR(priv->transceiver) == -EPROBE_DEFER)) { 1082 ret = -EPROBE_DEFER; 1083 goto out_clk; 1084 } 1085 1086 ret = mcp251x_power_enable(priv->power, 1); 1087 if (ret) 1088 goto out_clk; 1089 1090 priv->spi = spi; 1091 mutex_init(&priv->mcp_lock); 1092 1093 /* If requested, allocate DMA buffers */ 1094 if (mcp251x_enable_dma) { 1095 spi->dev.coherent_dma_mask = ~0; 1096 1097 /* 1098 * Minimum coherent DMA allocation is PAGE_SIZE, so allocate 1099 * that much and share it between Tx and Rx DMA buffers. 1100 */ 1101 priv->spi_tx_buf = dmam_alloc_coherent(&spi->dev, 1102 PAGE_SIZE, 1103 &priv->spi_tx_dma, 1104 GFP_DMA); 1105 1106 if (priv->spi_tx_buf) { 1107 priv->spi_rx_buf = (priv->spi_tx_buf + (PAGE_SIZE / 2)); 1108 priv->spi_rx_dma = (dma_addr_t)(priv->spi_tx_dma + 1109 (PAGE_SIZE / 2)); 1110 } else { 1111 /* Fall back to non-DMA */ 1112 mcp251x_enable_dma = 0; 1113 } 1114 } 1115 1116 /* Allocate non-DMA buffers */ 1117 if (!mcp251x_enable_dma) { 1118 priv->spi_tx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN, 1119 GFP_KERNEL); 1120 if (!priv->spi_tx_buf) { 1121 ret = -ENOMEM; 1122 goto error_probe; 1123 } 1124 priv->spi_rx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN, 1125 GFP_KERNEL); 1126 if (!priv->spi_rx_buf) { 1127 ret = -ENOMEM; 1128 goto error_probe; 1129 } 1130 } 1131 1132 SET_NETDEV_DEV(net, &spi->dev); 1133 1134 /* Here is OK to not lock the MCP, no one knows about it yet */ 1135 ret = mcp251x_hw_probe(spi); 1136 if (ret) { 1137 if (ret == -ENODEV) 1138 dev_err(&spi->dev, "Cannot initialize MCP%x. Wrong wiring?\n", priv->model); 1139 goto error_probe; 1140 } 1141 1142 mcp251x_hw_sleep(spi); 1143 1144 ret = register_candev(net); 1145 if (ret) 1146 goto error_probe; 1147 1148 devm_can_led_init(net); 1149 1150 netdev_info(net, "MCP%x successfully initialized.\n", priv->model); 1151 return 0; 1152 1153 error_probe: 1154 mcp251x_power_enable(priv->power, 0); 1155 1156 out_clk: 1157 if (!IS_ERR(clk)) 1158 clk_disable_unprepare(clk); 1159 1160 out_free: 1161 free_candev(net); 1162 1163 dev_err(&spi->dev, "Probe failed, err=%d\n", -ret); 1164 return ret; 1165 } 1166 1167 static int mcp251x_can_remove(struct spi_device *spi) 1168 { 1169 struct mcp251x_priv *priv = spi_get_drvdata(spi); 1170 struct net_device *net = priv->net; 1171 1172 unregister_candev(net); 1173 1174 mcp251x_power_enable(priv->power, 0); 1175 1176 if (!IS_ERR(priv->clk)) 1177 clk_disable_unprepare(priv->clk); 1178 1179 free_candev(net); 1180 1181 return 0; 1182 } 1183 1184 static int __maybe_unused mcp251x_can_suspend(struct device *dev) 1185 { 1186 struct spi_device *spi = to_spi_device(dev); 1187 struct mcp251x_priv *priv = spi_get_drvdata(spi); 1188 struct net_device *net = priv->net; 1189 1190 priv->force_quit = 1; 1191 disable_irq(spi->irq); 1192 /* 1193 * Note: at this point neither IST nor workqueues are running. 1194 * open/stop cannot be called anyway so locking is not needed 1195 */ 1196 if (netif_running(net)) { 1197 netif_device_detach(net); 1198 1199 mcp251x_hw_sleep(spi); 1200 mcp251x_power_enable(priv->transceiver, 0); 1201 priv->after_suspend = AFTER_SUSPEND_UP; 1202 } else { 1203 priv->after_suspend = AFTER_SUSPEND_DOWN; 1204 } 1205 1206 if (!IS_ERR_OR_NULL(priv->power)) { 1207 regulator_disable(priv->power); 1208 priv->after_suspend |= AFTER_SUSPEND_POWER; 1209 } 1210 1211 return 0; 1212 } 1213 1214 static int __maybe_unused mcp251x_can_resume(struct device *dev) 1215 { 1216 struct spi_device *spi = to_spi_device(dev); 1217 struct mcp251x_priv *priv = spi_get_drvdata(spi); 1218 1219 if (priv->after_suspend & AFTER_SUSPEND_POWER) 1220 mcp251x_power_enable(priv->power, 1); 1221 1222 if (priv->after_suspend & AFTER_SUSPEND_UP) { 1223 mcp251x_power_enable(priv->transceiver, 1); 1224 queue_work(priv->wq, &priv->restart_work); 1225 } else { 1226 priv->after_suspend = 0; 1227 } 1228 1229 priv->force_quit = 0; 1230 enable_irq(spi->irq); 1231 return 0; 1232 } 1233 1234 static SIMPLE_DEV_PM_OPS(mcp251x_can_pm_ops, mcp251x_can_suspend, 1235 mcp251x_can_resume); 1236 1237 static struct spi_driver mcp251x_can_driver = { 1238 .driver = { 1239 .name = DEVICE_NAME, 1240 .of_match_table = mcp251x_of_match, 1241 .pm = &mcp251x_can_pm_ops, 1242 }, 1243 .id_table = mcp251x_id_table, 1244 .probe = mcp251x_can_probe, 1245 .remove = mcp251x_can_remove, 1246 }; 1247 module_spi_driver(mcp251x_can_driver); 1248 1249 MODULE_AUTHOR("Chris Elston <celston@katalix.com>, " 1250 "Christian Pellegrin <chripell@evolware.org>"); 1251 MODULE_DESCRIPTION("Microchip 251x/25625 CAN driver"); 1252 MODULE_LICENSE("GPL v2"); 1253