1 // SPDX-License-Identifier: GPL-2.0-only 2 /* CAN bus driver for Microchip 251x/25625 CAN Controller with SPI Interface 3 * 4 * MCP2510 support and bug fixes by Christian Pellegrin 5 * <chripell@evolware.org> 6 * 7 * Copyright 2009 Christian Pellegrin EVOL S.r.l. 8 * 9 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved. 10 * Written under contract by: 11 * Chris Elston, Katalix Systems, Ltd. 12 * 13 * Based on Microchip MCP251x CAN controller driver written by 14 * David Vrabel, Copyright 2006 Arcom Control Systems Ltd. 15 * 16 * Based on CAN bus driver for the CCAN controller written by 17 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix 18 * - Simon Kallweit, intefo AG 19 * Copyright 2007 20 */ 21 22 #include <linux/can/core.h> 23 #include <linux/can/dev.h> 24 #include <linux/can/led.h> 25 #include <linux/clk.h> 26 #include <linux/completion.h> 27 #include <linux/delay.h> 28 #include <linux/device.h> 29 #include <linux/freezer.h> 30 #include <linux/interrupt.h> 31 #include <linux/io.h> 32 #include <linux/kernel.h> 33 #include <linux/module.h> 34 #include <linux/netdevice.h> 35 #include <linux/property.h> 36 #include <linux/platform_device.h> 37 #include <linux/slab.h> 38 #include <linux/spi/spi.h> 39 #include <linux/uaccess.h> 40 #include <linux/regulator/consumer.h> 41 42 /* SPI interface instruction set */ 43 #define INSTRUCTION_WRITE 0x02 44 #define INSTRUCTION_READ 0x03 45 #define INSTRUCTION_BIT_MODIFY 0x05 46 #define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n)) 47 #define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94) 48 #define INSTRUCTION_RESET 0xC0 49 #define RTS_TXB0 0x01 50 #define RTS_TXB1 0x02 51 #define RTS_TXB2 0x04 52 #define INSTRUCTION_RTS(n) (0x80 | ((n) & 0x07)) 53 54 /* MPC251x registers */ 55 #define CANSTAT 0x0e 56 #define CANCTRL 0x0f 57 # define CANCTRL_REQOP_MASK 0xe0 58 # define CANCTRL_REQOP_CONF 0x80 59 # define CANCTRL_REQOP_LISTEN_ONLY 0x60 60 # define CANCTRL_REQOP_LOOPBACK 0x40 61 # define CANCTRL_REQOP_SLEEP 0x20 62 # define CANCTRL_REQOP_NORMAL 0x00 63 # define CANCTRL_OSM 0x08 64 # define CANCTRL_ABAT 0x10 65 #define TEC 0x1c 66 #define REC 0x1d 67 #define CNF1 0x2a 68 # define CNF1_SJW_SHIFT 6 69 #define CNF2 0x29 70 # define CNF2_BTLMODE 0x80 71 # define CNF2_SAM 0x40 72 # define CNF2_PS1_SHIFT 3 73 #define CNF3 0x28 74 # define CNF3_SOF 0x08 75 # define CNF3_WAKFIL 0x04 76 # define CNF3_PHSEG2_MASK 0x07 77 #define CANINTE 0x2b 78 # define CANINTE_MERRE 0x80 79 # define CANINTE_WAKIE 0x40 80 # define CANINTE_ERRIE 0x20 81 # define CANINTE_TX2IE 0x10 82 # define CANINTE_TX1IE 0x08 83 # define CANINTE_TX0IE 0x04 84 # define CANINTE_RX1IE 0x02 85 # define CANINTE_RX0IE 0x01 86 #define CANINTF 0x2c 87 # define CANINTF_MERRF 0x80 88 # define CANINTF_WAKIF 0x40 89 # define CANINTF_ERRIF 0x20 90 # define CANINTF_TX2IF 0x10 91 # define CANINTF_TX1IF 0x08 92 # define CANINTF_TX0IF 0x04 93 # define CANINTF_RX1IF 0x02 94 # define CANINTF_RX0IF 0x01 95 # define CANINTF_RX (CANINTF_RX0IF | CANINTF_RX1IF) 96 # define CANINTF_TX (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF) 97 # define CANINTF_ERR (CANINTF_ERRIF) 98 #define EFLG 0x2d 99 # define EFLG_EWARN 0x01 100 # define EFLG_RXWAR 0x02 101 # define EFLG_TXWAR 0x04 102 # define EFLG_RXEP 0x08 103 # define EFLG_TXEP 0x10 104 # define EFLG_TXBO 0x20 105 # define EFLG_RX0OVR 0x40 106 # define EFLG_RX1OVR 0x80 107 #define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF) 108 # define TXBCTRL_ABTF 0x40 109 # define TXBCTRL_MLOA 0x20 110 # define TXBCTRL_TXERR 0x10 111 # define TXBCTRL_TXREQ 0x08 112 #define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF) 113 # define SIDH_SHIFT 3 114 #define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF) 115 # define SIDL_SID_MASK 7 116 # define SIDL_SID_SHIFT 5 117 # define SIDL_EXIDE_SHIFT 3 118 # define SIDL_EID_SHIFT 16 119 # define SIDL_EID_MASK 3 120 #define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF) 121 #define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF) 122 #define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF) 123 # define DLC_RTR_SHIFT 6 124 #define TXBCTRL_OFF 0 125 #define TXBSIDH_OFF 1 126 #define TXBSIDL_OFF 2 127 #define TXBEID8_OFF 3 128 #define TXBEID0_OFF 4 129 #define TXBDLC_OFF 5 130 #define TXBDAT_OFF 6 131 #define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF) 132 # define RXBCTRL_BUKT 0x04 133 # define RXBCTRL_RXM0 0x20 134 # define RXBCTRL_RXM1 0x40 135 #define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF) 136 # define RXBSIDH_SHIFT 3 137 #define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF) 138 # define RXBSIDL_IDE 0x08 139 # define RXBSIDL_SRR 0x10 140 # define RXBSIDL_EID 3 141 # define RXBSIDL_SHIFT 5 142 #define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF) 143 #define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF) 144 #define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF) 145 # define RXBDLC_LEN_MASK 0x0f 146 # define RXBDLC_RTR 0x40 147 #define RXBCTRL_OFF 0 148 #define RXBSIDH_OFF 1 149 #define RXBSIDL_OFF 2 150 #define RXBEID8_OFF 3 151 #define RXBEID0_OFF 4 152 #define RXBDLC_OFF 5 153 #define RXBDAT_OFF 6 154 #define RXFSID(n) ((n < 3) ? 0 : 4) 155 #define RXFSIDH(n) ((n) * 4 + RXFSID(n)) 156 #define RXFSIDL(n) ((n) * 4 + 1 + RXFSID(n)) 157 #define RXFEID8(n) ((n) * 4 + 2 + RXFSID(n)) 158 #define RXFEID0(n) ((n) * 4 + 3 + RXFSID(n)) 159 #define RXMSIDH(n) ((n) * 4 + 0x20) 160 #define RXMSIDL(n) ((n) * 4 + 0x21) 161 #define RXMEID8(n) ((n) * 4 + 0x22) 162 #define RXMEID0(n) ((n) * 4 + 0x23) 163 164 #define GET_BYTE(val, byte) \ 165 (((val) >> ((byte) * 8)) & 0xff) 166 #define SET_BYTE(val, byte) \ 167 (((val) & 0xff) << ((byte) * 8)) 168 169 /* Buffer size required for the largest SPI transfer (i.e., reading a 170 * frame) 171 */ 172 #define CAN_FRAME_MAX_DATA_LEN 8 173 #define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN) 174 #define CAN_FRAME_MAX_BITS 128 175 176 #define TX_ECHO_SKB_MAX 1 177 178 #define MCP251X_OST_DELAY_MS (5) 179 180 #define DEVICE_NAME "mcp251x" 181 182 static const struct can_bittiming_const mcp251x_bittiming_const = { 183 .name = DEVICE_NAME, 184 .tseg1_min = 3, 185 .tseg1_max = 16, 186 .tseg2_min = 2, 187 .tseg2_max = 8, 188 .sjw_max = 4, 189 .brp_min = 1, 190 .brp_max = 64, 191 .brp_inc = 1, 192 }; 193 194 enum mcp251x_model { 195 CAN_MCP251X_MCP2510 = 0x2510, 196 CAN_MCP251X_MCP2515 = 0x2515, 197 CAN_MCP251X_MCP25625 = 0x25625, 198 }; 199 200 struct mcp251x_priv { 201 struct can_priv can; 202 struct net_device *net; 203 struct spi_device *spi; 204 enum mcp251x_model model; 205 206 struct mutex mcp_lock; /* SPI device lock */ 207 208 u8 *spi_tx_buf; 209 u8 *spi_rx_buf; 210 211 struct sk_buff *tx_skb; 212 int tx_len; 213 214 struct workqueue_struct *wq; 215 struct work_struct tx_work; 216 struct work_struct restart_work; 217 218 int force_quit; 219 int after_suspend; 220 #define AFTER_SUSPEND_UP 1 221 #define AFTER_SUSPEND_DOWN 2 222 #define AFTER_SUSPEND_POWER 4 223 #define AFTER_SUSPEND_RESTART 8 224 int restart_tx; 225 struct regulator *power; 226 struct regulator *transceiver; 227 struct clk *clk; 228 }; 229 230 #define MCP251X_IS(_model) \ 231 static inline int mcp251x_is_##_model(struct spi_device *spi) \ 232 { \ 233 struct mcp251x_priv *priv = spi_get_drvdata(spi); \ 234 return priv->model == CAN_MCP251X_MCP##_model; \ 235 } 236 237 MCP251X_IS(2510); 238 239 static void mcp251x_clean(struct net_device *net) 240 { 241 struct mcp251x_priv *priv = netdev_priv(net); 242 243 if (priv->tx_skb || priv->tx_len) 244 net->stats.tx_errors++; 245 dev_kfree_skb(priv->tx_skb); 246 if (priv->tx_len) 247 can_free_echo_skb(priv->net, 0); 248 priv->tx_skb = NULL; 249 priv->tx_len = 0; 250 } 251 252 /* Note about handling of error return of mcp251x_spi_trans: accessing 253 * registers via SPI is not really different conceptually than using 254 * normal I/O assembler instructions, although it's much more 255 * complicated from a practical POV. So it's not advisable to always 256 * check the return value of this function. Imagine that every 257 * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0) 258 * error();", it would be a great mess (well there are some situation 259 * when exception handling C++ like could be useful after all). So we 260 * just check that transfers are OK at the beginning of our 261 * conversation with the chip and to avoid doing really nasty things 262 * (like injecting bogus packets in the network stack). 263 */ 264 static int mcp251x_spi_trans(struct spi_device *spi, int len) 265 { 266 struct mcp251x_priv *priv = spi_get_drvdata(spi); 267 struct spi_transfer t = { 268 .tx_buf = priv->spi_tx_buf, 269 .rx_buf = priv->spi_rx_buf, 270 .len = len, 271 .cs_change = 0, 272 }; 273 struct spi_message m; 274 int ret; 275 276 spi_message_init(&m); 277 spi_message_add_tail(&t, &m); 278 279 ret = spi_sync(spi, &m); 280 if (ret) 281 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret); 282 return ret; 283 } 284 285 static u8 mcp251x_read_reg(struct spi_device *spi, u8 reg) 286 { 287 struct mcp251x_priv *priv = spi_get_drvdata(spi); 288 u8 val = 0; 289 290 priv->spi_tx_buf[0] = INSTRUCTION_READ; 291 priv->spi_tx_buf[1] = reg; 292 293 mcp251x_spi_trans(spi, 3); 294 val = priv->spi_rx_buf[2]; 295 296 return val; 297 } 298 299 static void mcp251x_read_2regs(struct spi_device *spi, u8 reg, u8 *v1, u8 *v2) 300 { 301 struct mcp251x_priv *priv = spi_get_drvdata(spi); 302 303 priv->spi_tx_buf[0] = INSTRUCTION_READ; 304 priv->spi_tx_buf[1] = reg; 305 306 mcp251x_spi_trans(spi, 4); 307 308 *v1 = priv->spi_rx_buf[2]; 309 *v2 = priv->spi_rx_buf[3]; 310 } 311 312 static void mcp251x_write_reg(struct spi_device *spi, u8 reg, u8 val) 313 { 314 struct mcp251x_priv *priv = spi_get_drvdata(spi); 315 316 priv->spi_tx_buf[0] = INSTRUCTION_WRITE; 317 priv->spi_tx_buf[1] = reg; 318 priv->spi_tx_buf[2] = val; 319 320 mcp251x_spi_trans(spi, 3); 321 } 322 323 static void mcp251x_write_2regs(struct spi_device *spi, u8 reg, u8 v1, u8 v2) 324 { 325 struct mcp251x_priv *priv = spi_get_drvdata(spi); 326 327 priv->spi_tx_buf[0] = INSTRUCTION_WRITE; 328 priv->spi_tx_buf[1] = reg; 329 priv->spi_tx_buf[2] = v1; 330 priv->spi_tx_buf[3] = v2; 331 332 mcp251x_spi_trans(spi, 4); 333 } 334 335 static void mcp251x_write_bits(struct spi_device *spi, u8 reg, 336 u8 mask, u8 val) 337 { 338 struct mcp251x_priv *priv = spi_get_drvdata(spi); 339 340 priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY; 341 priv->spi_tx_buf[1] = reg; 342 priv->spi_tx_buf[2] = mask; 343 priv->spi_tx_buf[3] = val; 344 345 mcp251x_spi_trans(spi, 4); 346 } 347 348 static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf, 349 int len, int tx_buf_idx) 350 { 351 struct mcp251x_priv *priv = spi_get_drvdata(spi); 352 353 if (mcp251x_is_2510(spi)) { 354 int i; 355 356 for (i = 1; i < TXBDAT_OFF + len; i++) 357 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + i, 358 buf[i]); 359 } else { 360 memcpy(priv->spi_tx_buf, buf, TXBDAT_OFF + len); 361 mcp251x_spi_trans(spi, TXBDAT_OFF + len); 362 } 363 } 364 365 static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame, 366 int tx_buf_idx) 367 { 368 struct mcp251x_priv *priv = spi_get_drvdata(spi); 369 u32 sid, eid, exide, rtr; 370 u8 buf[SPI_TRANSFER_BUF_LEN]; 371 372 exide = (frame->can_id & CAN_EFF_FLAG) ? 1 : 0; /* Extended ID Enable */ 373 if (exide) 374 sid = (frame->can_id & CAN_EFF_MASK) >> 18; 375 else 376 sid = frame->can_id & CAN_SFF_MASK; /* Standard ID */ 377 eid = frame->can_id & CAN_EFF_MASK; /* Extended ID */ 378 rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0; /* Remote transmission */ 379 380 buf[TXBCTRL_OFF] = INSTRUCTION_LOAD_TXB(tx_buf_idx); 381 buf[TXBSIDH_OFF] = sid >> SIDH_SHIFT; 382 buf[TXBSIDL_OFF] = ((sid & SIDL_SID_MASK) << SIDL_SID_SHIFT) | 383 (exide << SIDL_EXIDE_SHIFT) | 384 ((eid >> SIDL_EID_SHIFT) & SIDL_EID_MASK); 385 buf[TXBEID8_OFF] = GET_BYTE(eid, 1); 386 buf[TXBEID0_OFF] = GET_BYTE(eid, 0); 387 buf[TXBDLC_OFF] = (rtr << DLC_RTR_SHIFT) | frame->can_dlc; 388 memcpy(buf + TXBDAT_OFF, frame->data, frame->can_dlc); 389 mcp251x_hw_tx_frame(spi, buf, frame->can_dlc, tx_buf_idx); 390 391 /* use INSTRUCTION_RTS, to avoid "repeated frame problem" */ 392 priv->spi_tx_buf[0] = INSTRUCTION_RTS(1 << tx_buf_idx); 393 mcp251x_spi_trans(priv->spi, 1); 394 } 395 396 static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf, 397 int buf_idx) 398 { 399 struct mcp251x_priv *priv = spi_get_drvdata(spi); 400 401 if (mcp251x_is_2510(spi)) { 402 int i, len; 403 404 for (i = 1; i < RXBDAT_OFF; i++) 405 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i); 406 407 len = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK); 408 for (; i < (RXBDAT_OFF + len); i++) 409 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i); 410 } else { 411 priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx); 412 mcp251x_spi_trans(spi, SPI_TRANSFER_BUF_LEN); 413 memcpy(buf, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN); 414 } 415 } 416 417 static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx) 418 { 419 struct mcp251x_priv *priv = spi_get_drvdata(spi); 420 struct sk_buff *skb; 421 struct can_frame *frame; 422 u8 buf[SPI_TRANSFER_BUF_LEN]; 423 424 skb = alloc_can_skb(priv->net, &frame); 425 if (!skb) { 426 dev_err(&spi->dev, "cannot allocate RX skb\n"); 427 priv->net->stats.rx_dropped++; 428 return; 429 } 430 431 mcp251x_hw_rx_frame(spi, buf, buf_idx); 432 if (buf[RXBSIDL_OFF] & RXBSIDL_IDE) { 433 /* Extended ID format */ 434 frame->can_id = CAN_EFF_FLAG; 435 frame->can_id |= 436 /* Extended ID part */ 437 SET_BYTE(buf[RXBSIDL_OFF] & RXBSIDL_EID, 2) | 438 SET_BYTE(buf[RXBEID8_OFF], 1) | 439 SET_BYTE(buf[RXBEID0_OFF], 0) | 440 /* Standard ID part */ 441 (((buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) | 442 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT)) << 18); 443 /* Remote transmission request */ 444 if (buf[RXBDLC_OFF] & RXBDLC_RTR) 445 frame->can_id |= CAN_RTR_FLAG; 446 } else { 447 /* Standard ID format */ 448 frame->can_id = 449 (buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) | 450 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT); 451 if (buf[RXBSIDL_OFF] & RXBSIDL_SRR) 452 frame->can_id |= CAN_RTR_FLAG; 453 } 454 /* Data length */ 455 frame->can_dlc = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK); 456 memcpy(frame->data, buf + RXBDAT_OFF, frame->can_dlc); 457 458 priv->net->stats.rx_packets++; 459 priv->net->stats.rx_bytes += frame->can_dlc; 460 461 can_led_event(priv->net, CAN_LED_EVENT_RX); 462 463 netif_rx_ni(skb); 464 } 465 466 static void mcp251x_hw_sleep(struct spi_device *spi) 467 { 468 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP); 469 } 470 471 /* May only be called when device is sleeping! */ 472 static int mcp251x_hw_wake(struct spi_device *spi) 473 { 474 unsigned long timeout; 475 476 /* Force wakeup interrupt to wake device, but don't execute IST */ 477 disable_irq(spi->irq); 478 mcp251x_write_2regs(spi, CANINTE, CANINTE_WAKIE, CANINTF_WAKIF); 479 480 /* Wait for oscillator startup timer after wake up */ 481 mdelay(MCP251X_OST_DELAY_MS); 482 483 /* Put device into config mode */ 484 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_CONF); 485 486 /* Wait for the device to enter config mode */ 487 timeout = jiffies + HZ; 488 while ((mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) != 489 CANCTRL_REQOP_CONF) { 490 schedule(); 491 if (time_after(jiffies, timeout)) { 492 dev_err(&spi->dev, "MCP251x didn't enter in config mode\n"); 493 return -EBUSY; 494 } 495 } 496 497 /* Disable and clear pending interrupts */ 498 mcp251x_write_2regs(spi, CANINTE, 0x00, 0x00); 499 enable_irq(spi->irq); 500 501 return 0; 502 } 503 504 static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb, 505 struct net_device *net) 506 { 507 struct mcp251x_priv *priv = netdev_priv(net); 508 struct spi_device *spi = priv->spi; 509 510 if (priv->tx_skb || priv->tx_len) { 511 dev_warn(&spi->dev, "hard_xmit called while tx busy\n"); 512 return NETDEV_TX_BUSY; 513 } 514 515 if (can_dropped_invalid_skb(net, skb)) 516 return NETDEV_TX_OK; 517 518 netif_stop_queue(net); 519 priv->tx_skb = skb; 520 queue_work(priv->wq, &priv->tx_work); 521 522 return NETDEV_TX_OK; 523 } 524 525 static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode) 526 { 527 struct mcp251x_priv *priv = netdev_priv(net); 528 529 switch (mode) { 530 case CAN_MODE_START: 531 mcp251x_clean(net); 532 /* We have to delay work since SPI I/O may sleep */ 533 priv->can.state = CAN_STATE_ERROR_ACTIVE; 534 priv->restart_tx = 1; 535 if (priv->can.restart_ms == 0) 536 priv->after_suspend = AFTER_SUSPEND_RESTART; 537 queue_work(priv->wq, &priv->restart_work); 538 break; 539 default: 540 return -EOPNOTSUPP; 541 } 542 543 return 0; 544 } 545 546 static int mcp251x_set_normal_mode(struct spi_device *spi) 547 { 548 struct mcp251x_priv *priv = spi_get_drvdata(spi); 549 unsigned long timeout; 550 551 /* Enable interrupts */ 552 mcp251x_write_reg(spi, CANINTE, 553 CANINTE_ERRIE | CANINTE_TX2IE | CANINTE_TX1IE | 554 CANINTE_TX0IE | CANINTE_RX1IE | CANINTE_RX0IE); 555 556 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 557 /* Put device into loopback mode */ 558 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK); 559 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) { 560 /* Put device into listen-only mode */ 561 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LISTEN_ONLY); 562 } else { 563 /* Put device into normal mode */ 564 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL); 565 566 /* Wait for the device to enter normal mode */ 567 timeout = jiffies + HZ; 568 while (mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) { 569 schedule(); 570 if (time_after(jiffies, timeout)) { 571 dev_err(&spi->dev, "MCP251x didn't enter in normal mode\n"); 572 return -EBUSY; 573 } 574 } 575 } 576 priv->can.state = CAN_STATE_ERROR_ACTIVE; 577 return 0; 578 } 579 580 static int mcp251x_do_set_bittiming(struct net_device *net) 581 { 582 struct mcp251x_priv *priv = netdev_priv(net); 583 struct can_bittiming *bt = &priv->can.bittiming; 584 struct spi_device *spi = priv->spi; 585 586 mcp251x_write_reg(spi, CNF1, ((bt->sjw - 1) << CNF1_SJW_SHIFT) | 587 (bt->brp - 1)); 588 mcp251x_write_reg(spi, CNF2, CNF2_BTLMODE | 589 (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ? 590 CNF2_SAM : 0) | 591 ((bt->phase_seg1 - 1) << CNF2_PS1_SHIFT) | 592 (bt->prop_seg - 1)); 593 mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK, 594 (bt->phase_seg2 - 1)); 595 dev_dbg(&spi->dev, "CNF: 0x%02x 0x%02x 0x%02x\n", 596 mcp251x_read_reg(spi, CNF1), 597 mcp251x_read_reg(spi, CNF2), 598 mcp251x_read_reg(spi, CNF3)); 599 600 return 0; 601 } 602 603 static int mcp251x_setup(struct net_device *net, struct spi_device *spi) 604 { 605 mcp251x_do_set_bittiming(net); 606 607 mcp251x_write_reg(spi, RXBCTRL(0), 608 RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1); 609 mcp251x_write_reg(spi, RXBCTRL(1), 610 RXBCTRL_RXM0 | RXBCTRL_RXM1); 611 return 0; 612 } 613 614 static int mcp251x_hw_reset(struct spi_device *spi) 615 { 616 struct mcp251x_priv *priv = spi_get_drvdata(spi); 617 unsigned long timeout; 618 int ret; 619 620 /* Wait for oscillator startup timer after power up */ 621 mdelay(MCP251X_OST_DELAY_MS); 622 623 priv->spi_tx_buf[0] = INSTRUCTION_RESET; 624 ret = mcp251x_spi_trans(spi, 1); 625 if (ret) 626 return ret; 627 628 /* Wait for oscillator startup timer after reset */ 629 mdelay(MCP251X_OST_DELAY_MS); 630 631 /* Wait for reset to finish */ 632 timeout = jiffies + HZ; 633 while ((mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) != 634 CANCTRL_REQOP_CONF) { 635 usleep_range(MCP251X_OST_DELAY_MS * 1000, 636 MCP251X_OST_DELAY_MS * 1000 * 2); 637 638 if (time_after(jiffies, timeout)) { 639 dev_err(&spi->dev, 640 "MCP251x didn't enter in conf mode after reset\n"); 641 return -EBUSY; 642 } 643 } 644 return 0; 645 } 646 647 static int mcp251x_hw_probe(struct spi_device *spi) 648 { 649 u8 ctrl; 650 int ret; 651 652 ret = mcp251x_hw_reset(spi); 653 if (ret) 654 return ret; 655 656 ctrl = mcp251x_read_reg(spi, CANCTRL); 657 658 dev_dbg(&spi->dev, "CANCTRL 0x%02x\n", ctrl); 659 660 /* Check for power up default value */ 661 if ((ctrl & 0x17) != 0x07) 662 return -ENODEV; 663 664 return 0; 665 } 666 667 static int mcp251x_power_enable(struct regulator *reg, int enable) 668 { 669 if (IS_ERR_OR_NULL(reg)) 670 return 0; 671 672 if (enable) 673 return regulator_enable(reg); 674 else 675 return regulator_disable(reg); 676 } 677 678 static int mcp251x_stop(struct net_device *net) 679 { 680 struct mcp251x_priv *priv = netdev_priv(net); 681 struct spi_device *spi = priv->spi; 682 683 close_candev(net); 684 685 priv->force_quit = 1; 686 free_irq(spi->irq, priv); 687 destroy_workqueue(priv->wq); 688 priv->wq = NULL; 689 690 mutex_lock(&priv->mcp_lock); 691 692 /* Disable and clear pending interrupts */ 693 mcp251x_write_2regs(spi, CANINTE, 0x00, 0x00); 694 695 mcp251x_write_reg(spi, TXBCTRL(0), 0); 696 mcp251x_clean(net); 697 698 mcp251x_hw_sleep(spi); 699 700 mcp251x_power_enable(priv->transceiver, 0); 701 702 priv->can.state = CAN_STATE_STOPPED; 703 704 mutex_unlock(&priv->mcp_lock); 705 706 can_led_event(net, CAN_LED_EVENT_STOP); 707 708 return 0; 709 } 710 711 static void mcp251x_error_skb(struct net_device *net, int can_id, int data1) 712 { 713 struct sk_buff *skb; 714 struct can_frame *frame; 715 716 skb = alloc_can_err_skb(net, &frame); 717 if (skb) { 718 frame->can_id |= can_id; 719 frame->data[1] = data1; 720 netif_rx_ni(skb); 721 } else { 722 netdev_err(net, "cannot allocate error skb\n"); 723 } 724 } 725 726 static void mcp251x_tx_work_handler(struct work_struct *ws) 727 { 728 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv, 729 tx_work); 730 struct spi_device *spi = priv->spi; 731 struct net_device *net = priv->net; 732 struct can_frame *frame; 733 734 mutex_lock(&priv->mcp_lock); 735 if (priv->tx_skb) { 736 if (priv->can.state == CAN_STATE_BUS_OFF) { 737 mcp251x_clean(net); 738 } else { 739 frame = (struct can_frame *)priv->tx_skb->data; 740 741 if (frame->can_dlc > CAN_FRAME_MAX_DATA_LEN) 742 frame->can_dlc = CAN_FRAME_MAX_DATA_LEN; 743 mcp251x_hw_tx(spi, frame, 0); 744 priv->tx_len = 1 + frame->can_dlc; 745 can_put_echo_skb(priv->tx_skb, net, 0); 746 priv->tx_skb = NULL; 747 } 748 } 749 mutex_unlock(&priv->mcp_lock); 750 } 751 752 static void mcp251x_restart_work_handler(struct work_struct *ws) 753 { 754 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv, 755 restart_work); 756 struct spi_device *spi = priv->spi; 757 struct net_device *net = priv->net; 758 759 mutex_lock(&priv->mcp_lock); 760 if (priv->after_suspend) { 761 if (priv->after_suspend & AFTER_SUSPEND_POWER) { 762 mcp251x_hw_reset(spi); 763 mcp251x_setup(net, spi); 764 } else { 765 mcp251x_hw_wake(spi); 766 } 767 priv->force_quit = 0; 768 if (priv->after_suspend & AFTER_SUSPEND_RESTART) { 769 mcp251x_set_normal_mode(spi); 770 } else if (priv->after_suspend & AFTER_SUSPEND_UP) { 771 netif_device_attach(net); 772 mcp251x_clean(net); 773 mcp251x_set_normal_mode(spi); 774 netif_wake_queue(net); 775 } else { 776 mcp251x_hw_sleep(spi); 777 } 778 priv->after_suspend = 0; 779 } 780 781 if (priv->restart_tx) { 782 priv->restart_tx = 0; 783 mcp251x_write_reg(spi, TXBCTRL(0), 0); 784 mcp251x_clean(net); 785 netif_wake_queue(net); 786 mcp251x_error_skb(net, CAN_ERR_RESTARTED, 0); 787 } 788 mutex_unlock(&priv->mcp_lock); 789 } 790 791 static irqreturn_t mcp251x_can_ist(int irq, void *dev_id) 792 { 793 struct mcp251x_priv *priv = dev_id; 794 struct spi_device *spi = priv->spi; 795 struct net_device *net = priv->net; 796 797 mutex_lock(&priv->mcp_lock); 798 while (!priv->force_quit) { 799 enum can_state new_state; 800 u8 intf, eflag; 801 u8 clear_intf = 0; 802 int can_id = 0, data1 = 0; 803 804 mcp251x_read_2regs(spi, CANINTF, &intf, &eflag); 805 806 /* mask out flags we don't care about */ 807 intf &= CANINTF_RX | CANINTF_TX | CANINTF_ERR; 808 809 /* receive buffer 0 */ 810 if (intf & CANINTF_RX0IF) { 811 mcp251x_hw_rx(spi, 0); 812 /* Free one buffer ASAP 813 * (The MCP2515/25625 does this automatically.) 814 */ 815 if (mcp251x_is_2510(spi)) 816 mcp251x_write_bits(spi, CANINTF, 817 CANINTF_RX0IF, 0x00); 818 } 819 820 /* receive buffer 1 */ 821 if (intf & CANINTF_RX1IF) { 822 mcp251x_hw_rx(spi, 1); 823 /* The MCP2515/25625 does this automatically. */ 824 if (mcp251x_is_2510(spi)) 825 clear_intf |= CANINTF_RX1IF; 826 } 827 828 /* any error or tx interrupt we need to clear? */ 829 if (intf & (CANINTF_ERR | CANINTF_TX)) 830 clear_intf |= intf & (CANINTF_ERR | CANINTF_TX); 831 if (clear_intf) 832 mcp251x_write_bits(spi, CANINTF, clear_intf, 0x00); 833 834 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) 835 mcp251x_write_bits(spi, EFLG, eflag, 0x00); 836 837 /* Update can state */ 838 if (eflag & EFLG_TXBO) { 839 new_state = CAN_STATE_BUS_OFF; 840 can_id |= CAN_ERR_BUSOFF; 841 } else if (eflag & EFLG_TXEP) { 842 new_state = CAN_STATE_ERROR_PASSIVE; 843 can_id |= CAN_ERR_CRTL; 844 data1 |= CAN_ERR_CRTL_TX_PASSIVE; 845 } else if (eflag & EFLG_RXEP) { 846 new_state = CAN_STATE_ERROR_PASSIVE; 847 can_id |= CAN_ERR_CRTL; 848 data1 |= CAN_ERR_CRTL_RX_PASSIVE; 849 } else if (eflag & EFLG_TXWAR) { 850 new_state = CAN_STATE_ERROR_WARNING; 851 can_id |= CAN_ERR_CRTL; 852 data1 |= CAN_ERR_CRTL_TX_WARNING; 853 } else if (eflag & EFLG_RXWAR) { 854 new_state = CAN_STATE_ERROR_WARNING; 855 can_id |= CAN_ERR_CRTL; 856 data1 |= CAN_ERR_CRTL_RX_WARNING; 857 } else { 858 new_state = CAN_STATE_ERROR_ACTIVE; 859 } 860 861 /* Update can state statistics */ 862 switch (priv->can.state) { 863 case CAN_STATE_ERROR_ACTIVE: 864 if (new_state >= CAN_STATE_ERROR_WARNING && 865 new_state <= CAN_STATE_BUS_OFF) 866 priv->can.can_stats.error_warning++; 867 /* fall through */ 868 case CAN_STATE_ERROR_WARNING: 869 if (new_state >= CAN_STATE_ERROR_PASSIVE && 870 new_state <= CAN_STATE_BUS_OFF) 871 priv->can.can_stats.error_passive++; 872 break; 873 default: 874 break; 875 } 876 priv->can.state = new_state; 877 878 if (intf & CANINTF_ERRIF) { 879 /* Handle overflow counters */ 880 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) { 881 if (eflag & EFLG_RX0OVR) { 882 net->stats.rx_over_errors++; 883 net->stats.rx_errors++; 884 } 885 if (eflag & EFLG_RX1OVR) { 886 net->stats.rx_over_errors++; 887 net->stats.rx_errors++; 888 } 889 can_id |= CAN_ERR_CRTL; 890 data1 |= CAN_ERR_CRTL_RX_OVERFLOW; 891 } 892 mcp251x_error_skb(net, can_id, data1); 893 } 894 895 if (priv->can.state == CAN_STATE_BUS_OFF) { 896 if (priv->can.restart_ms == 0) { 897 priv->force_quit = 1; 898 priv->can.can_stats.bus_off++; 899 can_bus_off(net); 900 mcp251x_hw_sleep(spi); 901 break; 902 } 903 } 904 905 if (intf == 0) 906 break; 907 908 if (intf & CANINTF_TX) { 909 net->stats.tx_packets++; 910 net->stats.tx_bytes += priv->tx_len - 1; 911 can_led_event(net, CAN_LED_EVENT_TX); 912 if (priv->tx_len) { 913 can_get_echo_skb(net, 0); 914 priv->tx_len = 0; 915 } 916 netif_wake_queue(net); 917 } 918 } 919 mutex_unlock(&priv->mcp_lock); 920 return IRQ_HANDLED; 921 } 922 923 static int mcp251x_open(struct net_device *net) 924 { 925 struct mcp251x_priv *priv = netdev_priv(net); 926 struct spi_device *spi = priv->spi; 927 unsigned long flags = 0; 928 int ret; 929 930 ret = open_candev(net); 931 if (ret) { 932 dev_err(&spi->dev, "unable to set initial baudrate!\n"); 933 return ret; 934 } 935 936 mutex_lock(&priv->mcp_lock); 937 mcp251x_power_enable(priv->transceiver, 1); 938 939 priv->force_quit = 0; 940 priv->tx_skb = NULL; 941 priv->tx_len = 0; 942 943 if (!dev_fwnode(&spi->dev)) 944 flags = IRQF_TRIGGER_FALLING; 945 946 ret = request_threaded_irq(spi->irq, NULL, mcp251x_can_ist, 947 flags | IRQF_ONESHOT, dev_name(&spi->dev), 948 priv); 949 if (ret) { 950 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq); 951 goto out_close; 952 } 953 954 priv->wq = alloc_workqueue("mcp251x_wq", WQ_FREEZABLE | WQ_MEM_RECLAIM, 955 0); 956 if (!priv->wq) { 957 ret = -ENOMEM; 958 goto out_clean; 959 } 960 INIT_WORK(&priv->tx_work, mcp251x_tx_work_handler); 961 INIT_WORK(&priv->restart_work, mcp251x_restart_work_handler); 962 963 ret = mcp251x_hw_wake(spi); 964 if (ret) 965 goto out_free_wq; 966 ret = mcp251x_setup(net, spi); 967 if (ret) 968 goto out_free_wq; 969 ret = mcp251x_set_normal_mode(spi); 970 if (ret) 971 goto out_free_wq; 972 973 can_led_event(net, CAN_LED_EVENT_OPEN); 974 975 netif_wake_queue(net); 976 mutex_unlock(&priv->mcp_lock); 977 978 return 0; 979 980 out_free_wq: 981 destroy_workqueue(priv->wq); 982 out_clean: 983 free_irq(spi->irq, priv); 984 mcp251x_hw_sleep(spi); 985 out_close: 986 mcp251x_power_enable(priv->transceiver, 0); 987 close_candev(net); 988 mutex_unlock(&priv->mcp_lock); 989 return ret; 990 } 991 992 static const struct net_device_ops mcp251x_netdev_ops = { 993 .ndo_open = mcp251x_open, 994 .ndo_stop = mcp251x_stop, 995 .ndo_start_xmit = mcp251x_hard_start_xmit, 996 .ndo_change_mtu = can_change_mtu, 997 }; 998 999 static const struct of_device_id mcp251x_of_match[] = { 1000 { 1001 .compatible = "microchip,mcp2510", 1002 .data = (void *)CAN_MCP251X_MCP2510, 1003 }, 1004 { 1005 .compatible = "microchip,mcp2515", 1006 .data = (void *)CAN_MCP251X_MCP2515, 1007 }, 1008 { 1009 .compatible = "microchip,mcp25625", 1010 .data = (void *)CAN_MCP251X_MCP25625, 1011 }, 1012 { } 1013 }; 1014 MODULE_DEVICE_TABLE(of, mcp251x_of_match); 1015 1016 static const struct spi_device_id mcp251x_id_table[] = { 1017 { 1018 .name = "mcp2510", 1019 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2510, 1020 }, 1021 { 1022 .name = "mcp2515", 1023 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2515, 1024 }, 1025 { 1026 .name = "mcp25625", 1027 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP25625, 1028 }, 1029 { } 1030 }; 1031 MODULE_DEVICE_TABLE(spi, mcp251x_id_table); 1032 1033 static int mcp251x_can_probe(struct spi_device *spi) 1034 { 1035 const void *match = device_get_match_data(&spi->dev); 1036 struct net_device *net; 1037 struct mcp251x_priv *priv; 1038 struct clk *clk; 1039 u32 freq; 1040 int ret; 1041 1042 clk = devm_clk_get_optional(&spi->dev, NULL); 1043 if (IS_ERR(clk)) 1044 return PTR_ERR(clk); 1045 1046 freq = clk_get_rate(clk); 1047 if (freq == 0) 1048 device_property_read_u32(&spi->dev, "clock-frequency", &freq); 1049 1050 /* Sanity check */ 1051 if (freq < 1000000 || freq > 25000000) 1052 return -ERANGE; 1053 1054 /* Allocate can/net device */ 1055 net = alloc_candev(sizeof(struct mcp251x_priv), TX_ECHO_SKB_MAX); 1056 if (!net) 1057 return -ENOMEM; 1058 1059 ret = clk_prepare_enable(clk); 1060 if (ret) 1061 goto out_free; 1062 1063 net->netdev_ops = &mcp251x_netdev_ops; 1064 net->flags |= IFF_ECHO; 1065 1066 priv = netdev_priv(net); 1067 priv->can.bittiming_const = &mcp251x_bittiming_const; 1068 priv->can.do_set_mode = mcp251x_do_set_mode; 1069 priv->can.clock.freq = freq / 2; 1070 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES | 1071 CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY; 1072 if (match) 1073 priv->model = (enum mcp251x_model)match; 1074 else 1075 priv->model = spi_get_device_id(spi)->driver_data; 1076 priv->net = net; 1077 priv->clk = clk; 1078 1079 spi_set_drvdata(spi, priv); 1080 1081 /* Configure the SPI bus */ 1082 spi->bits_per_word = 8; 1083 if (mcp251x_is_2510(spi)) 1084 spi->max_speed_hz = spi->max_speed_hz ? : 5 * 1000 * 1000; 1085 else 1086 spi->max_speed_hz = spi->max_speed_hz ? : 10 * 1000 * 1000; 1087 ret = spi_setup(spi); 1088 if (ret) 1089 goto out_clk; 1090 1091 priv->power = devm_regulator_get_optional(&spi->dev, "vdd"); 1092 priv->transceiver = devm_regulator_get_optional(&spi->dev, "xceiver"); 1093 if ((PTR_ERR(priv->power) == -EPROBE_DEFER) || 1094 (PTR_ERR(priv->transceiver) == -EPROBE_DEFER)) { 1095 ret = -EPROBE_DEFER; 1096 goto out_clk; 1097 } 1098 1099 ret = mcp251x_power_enable(priv->power, 1); 1100 if (ret) 1101 goto out_clk; 1102 1103 priv->spi = spi; 1104 mutex_init(&priv->mcp_lock); 1105 1106 priv->spi_tx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN, 1107 GFP_KERNEL); 1108 if (!priv->spi_tx_buf) { 1109 ret = -ENOMEM; 1110 goto error_probe; 1111 } 1112 1113 priv->spi_rx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN, 1114 GFP_KERNEL); 1115 if (!priv->spi_rx_buf) { 1116 ret = -ENOMEM; 1117 goto error_probe; 1118 } 1119 1120 SET_NETDEV_DEV(net, &spi->dev); 1121 1122 /* Here is OK to not lock the MCP, no one knows about it yet */ 1123 ret = mcp251x_hw_probe(spi); 1124 if (ret) { 1125 if (ret == -ENODEV) 1126 dev_err(&spi->dev, "Cannot initialize MCP%x. Wrong wiring?\n", 1127 priv->model); 1128 goto error_probe; 1129 } 1130 1131 mcp251x_hw_sleep(spi); 1132 1133 ret = register_candev(net); 1134 if (ret) 1135 goto error_probe; 1136 1137 devm_can_led_init(net); 1138 1139 netdev_info(net, "MCP%x successfully initialized.\n", priv->model); 1140 return 0; 1141 1142 error_probe: 1143 mcp251x_power_enable(priv->power, 0); 1144 1145 out_clk: 1146 clk_disable_unprepare(clk); 1147 1148 out_free: 1149 free_candev(net); 1150 1151 dev_err(&spi->dev, "Probe failed, err=%d\n", -ret); 1152 return ret; 1153 } 1154 1155 static int mcp251x_can_remove(struct spi_device *spi) 1156 { 1157 struct mcp251x_priv *priv = spi_get_drvdata(spi); 1158 struct net_device *net = priv->net; 1159 1160 unregister_candev(net); 1161 1162 mcp251x_power_enable(priv->power, 0); 1163 1164 clk_disable_unprepare(priv->clk); 1165 1166 free_candev(net); 1167 1168 return 0; 1169 } 1170 1171 static int __maybe_unused mcp251x_can_suspend(struct device *dev) 1172 { 1173 struct spi_device *spi = to_spi_device(dev); 1174 struct mcp251x_priv *priv = spi_get_drvdata(spi); 1175 struct net_device *net = priv->net; 1176 1177 priv->force_quit = 1; 1178 disable_irq(spi->irq); 1179 /* Note: at this point neither IST nor workqueues are running. 1180 * open/stop cannot be called anyway so locking is not needed 1181 */ 1182 if (netif_running(net)) { 1183 netif_device_detach(net); 1184 1185 mcp251x_hw_sleep(spi); 1186 mcp251x_power_enable(priv->transceiver, 0); 1187 priv->after_suspend = AFTER_SUSPEND_UP; 1188 } else { 1189 priv->after_suspend = AFTER_SUSPEND_DOWN; 1190 } 1191 1192 mcp251x_power_enable(priv->power, 0); 1193 priv->after_suspend |= AFTER_SUSPEND_POWER; 1194 1195 return 0; 1196 } 1197 1198 static int __maybe_unused mcp251x_can_resume(struct device *dev) 1199 { 1200 struct spi_device *spi = to_spi_device(dev); 1201 struct mcp251x_priv *priv = spi_get_drvdata(spi); 1202 1203 if (priv->after_suspend & AFTER_SUSPEND_POWER) 1204 mcp251x_power_enable(priv->power, 1); 1205 if (priv->after_suspend & AFTER_SUSPEND_UP) 1206 mcp251x_power_enable(priv->transceiver, 1); 1207 1208 if (priv->after_suspend & (AFTER_SUSPEND_POWER | AFTER_SUSPEND_UP)) 1209 queue_work(priv->wq, &priv->restart_work); 1210 else 1211 priv->after_suspend = 0; 1212 1213 priv->force_quit = 0; 1214 enable_irq(spi->irq); 1215 return 0; 1216 } 1217 1218 static SIMPLE_DEV_PM_OPS(mcp251x_can_pm_ops, mcp251x_can_suspend, 1219 mcp251x_can_resume); 1220 1221 static struct spi_driver mcp251x_can_driver = { 1222 .driver = { 1223 .name = DEVICE_NAME, 1224 .of_match_table = mcp251x_of_match, 1225 .pm = &mcp251x_can_pm_ops, 1226 }, 1227 .id_table = mcp251x_id_table, 1228 .probe = mcp251x_can_probe, 1229 .remove = mcp251x_can_remove, 1230 }; 1231 module_spi_driver(mcp251x_can_driver); 1232 1233 MODULE_AUTHOR("Chris Elston <celston@katalix.com>, " 1234 "Christian Pellegrin <chripell@evolware.org>"); 1235 MODULE_DESCRIPTION("Microchip 251x/25625 CAN driver"); 1236 MODULE_LICENSE("GPL v2"); 1237