1 /* 2 * Copyright (C) 2008-2010 Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su> 3 * 4 * Derived from the ems_pci.c driver: 5 * Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com> 6 * Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com> 7 * Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the version 2 of the GNU General Public License 11 * as published by the Free Software Foundation 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/interrupt.h> 25 #include <linux/netdevice.h> 26 #include <linux/delay.h> 27 #include <linux/slab.h> 28 #include <linux/pci.h> 29 #include <linux/can/dev.h> 30 #include <linux/io.h> 31 32 #include "sja1000.h" 33 34 #define DRV_NAME "sja1000_plx_pci" 35 36 MODULE_AUTHOR("Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>"); 37 MODULE_DESCRIPTION("Socket-CAN driver for PLX90xx PCI-bridge cards with " 38 "the SJA1000 chips"); 39 MODULE_SUPPORTED_DEVICE("Adlink PCI-7841/cPCI-7841, " 40 "Adlink PCI-7841/cPCI-7841 SE, " 41 "Marathon CAN-bus-PCI, " 42 "Marathon CAN-bus-PCIe, " 43 "TEWS TECHNOLOGIES TPMC810, " 44 "esd CAN-PCI/CPCI/PCI104/200, " 45 "esd CAN-PCI/PMC/266, " 46 "esd CAN-PCIe/2000, " 47 "Connect Tech Inc. CANpro/104-Plus Opto (CRG001), " 48 "IXXAT PC-I 04/PCI, " 49 "ELCUS CAN-200-PCI") 50 MODULE_LICENSE("GPL v2"); 51 52 #define PLX_PCI_MAX_CHAN 2 53 54 struct plx_pci_card { 55 int channels; /* detected channels count */ 56 struct net_device *net_dev[PLX_PCI_MAX_CHAN]; 57 void __iomem *conf_addr; 58 59 /* Pointer to device-dependent reset function */ 60 void (*reset_func)(struct pci_dev *pdev); 61 }; 62 63 #define PLX_PCI_CAN_CLOCK (16000000 / 2) 64 65 /* PLX9030/9050/9052 registers */ 66 #define PLX_INTCSR 0x4c /* Interrupt Control/Status */ 67 #define PLX_CNTRL 0x50 /* User I/O, Direct Slave Response, 68 * Serial EEPROM, and Initialization 69 * Control register 70 */ 71 72 #define PLX_LINT1_EN 0x1 /* Local interrupt 1 enable */ 73 #define PLX_LINT2_EN (1 << 3) /* Local interrupt 2 enable */ 74 #define PLX_PCI_INT_EN (1 << 6) /* PCI Interrupt Enable */ 75 #define PLX_PCI_RESET (1 << 30) /* PCI Adapter Software Reset */ 76 77 /* PLX9056 registers */ 78 #define PLX9056_INTCSR 0x68 /* Interrupt Control/Status */ 79 #define PLX9056_CNTRL 0x6c /* Control / Software Reset */ 80 81 #define PLX9056_LINTI (1 << 11) 82 #define PLX9056_PCI_INT_EN (1 << 8) 83 #define PLX9056_PCI_RCR (1 << 29) /* Read Configuration Registers */ 84 85 /* 86 * The board configuration is probably following: 87 * RX1 is connected to ground. 88 * TX1 is not connected. 89 * CLKO is not connected. 90 * Setting the OCR register to 0xDA is a good idea. 91 * This means normal output mode, push-pull and the correct polarity. 92 */ 93 #define PLX_PCI_OCR (OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL) 94 95 /* 96 * In the CDR register, you should set CBP to 1. 97 * You will probably also want to set the clock divider value to 7 98 * (meaning direct oscillator output) because the second SJA1000 chip 99 * is driven by the first one CLKOUT output. 100 */ 101 #define PLX_PCI_CDR (CDR_CBP | CDR_CLKOUT_MASK) 102 103 /* SJA1000 Control Register in the BasicCAN Mode */ 104 #define REG_CR 0x00 105 106 /* States of some SJA1000 registers after hardware reset in the BasicCAN mode*/ 107 #define REG_CR_BASICCAN_INITIAL 0x21 108 #define REG_CR_BASICCAN_INITIAL_MASK 0xa1 109 #define REG_SR_BASICCAN_INITIAL 0x0c 110 #define REG_IR_BASICCAN_INITIAL 0xe0 111 112 /* States of some SJA1000 registers after hardware reset in the PeliCAN mode*/ 113 #define REG_MOD_PELICAN_INITIAL 0x01 114 #define REG_SR_PELICAN_INITIAL 0x3c 115 #define REG_IR_PELICAN_INITIAL 0x00 116 117 #define ADLINK_PCI_VENDOR_ID 0x144A 118 #define ADLINK_PCI_DEVICE_ID 0x7841 119 120 #define ESD_PCI_SUB_SYS_ID_PCI200 0x0004 121 #define ESD_PCI_SUB_SYS_ID_PCI266 0x0009 122 #define ESD_PCI_SUB_SYS_ID_PMC266 0x000e 123 #define ESD_PCI_SUB_SYS_ID_CPCI200 0x010b 124 #define ESD_PCI_SUB_SYS_ID_PCIE2000 0x0200 125 #define ESD_PCI_SUB_SYS_ID_PCI104200 0x0501 126 127 #define CAN200PCI_DEVICE_ID 0x9030 128 #define CAN200PCI_VENDOR_ID 0x10b5 129 #define CAN200PCI_SUB_DEVICE_ID 0x0301 130 #define CAN200PCI_SUB_VENDOR_ID 0xe1c5 131 132 #define IXXAT_PCI_VENDOR_ID 0x10b5 133 #define IXXAT_PCI_DEVICE_ID 0x9050 134 #define IXXAT_PCI_SUB_SYS_ID 0x2540 135 136 #define MARATHON_PCI_DEVICE_ID 0x2715 137 #define MARATHON_PCIE_DEVICE_ID 0x3432 138 139 #define TEWS_PCI_VENDOR_ID 0x1498 140 #define TEWS_PCI_DEVICE_ID_TMPC810 0x032A 141 142 #define CTI_PCI_VENDOR_ID 0x12c4 143 #define CTI_PCI_DEVICE_ID_CRG001 0x0900 144 145 static void plx_pci_reset_common(struct pci_dev *pdev); 146 static void plx9056_pci_reset_common(struct pci_dev *pdev); 147 static void plx_pci_reset_marathon_pci(struct pci_dev *pdev); 148 static void plx_pci_reset_marathon_pcie(struct pci_dev *pdev); 149 150 struct plx_pci_channel_map { 151 u32 bar; 152 u32 offset; 153 u32 size; /* 0x00 - auto, e.g. length of entire bar */ 154 }; 155 156 struct plx_pci_card_info { 157 const char *name; 158 int channel_count; 159 u32 can_clock; 160 u8 ocr; /* output control register */ 161 u8 cdr; /* clock divider register */ 162 163 /* Parameters for mapping local configuration space */ 164 struct plx_pci_channel_map conf_map; 165 166 /* Parameters for mapping the SJA1000 chips */ 167 struct plx_pci_channel_map chan_map_tbl[PLX_PCI_MAX_CHAN]; 168 169 /* Pointer to device-dependent reset function */ 170 void (*reset_func)(struct pci_dev *pdev); 171 }; 172 173 static struct plx_pci_card_info plx_pci_card_info_adlink = { 174 "Adlink PCI-7841/cPCI-7841", 2, 175 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 176 {1, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} }, 177 &plx_pci_reset_common 178 /* based on PLX9052 */ 179 }; 180 181 static struct plx_pci_card_info plx_pci_card_info_adlink_se = { 182 "Adlink PCI-7841/cPCI-7841 SE", 2, 183 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 184 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} }, 185 &plx_pci_reset_common 186 /* based on PLX9052 */ 187 }; 188 189 static struct plx_pci_card_info plx_pci_card_info_esd200 = { 190 "esd CAN-PCI/CPCI/PCI104/200", 2, 191 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 192 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} }, 193 &plx_pci_reset_common 194 /* based on PLX9030/9050 */ 195 }; 196 197 static struct plx_pci_card_info plx_pci_card_info_esd266 = { 198 "esd CAN-PCI/PMC/266", 2, 199 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 200 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} }, 201 &plx9056_pci_reset_common 202 /* based on PLX9056 */ 203 }; 204 205 static struct plx_pci_card_info plx_pci_card_info_esd2000 = { 206 "esd CAN-PCIe/2000", 2, 207 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 208 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} }, 209 &plx9056_pci_reset_common 210 /* based on PEX8311 */ 211 }; 212 213 static struct plx_pci_card_info plx_pci_card_info_ixxat = { 214 "IXXAT PC-I 04/PCI", 2, 215 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 216 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x200, 0x80} }, 217 &plx_pci_reset_common 218 /* based on PLX9050 */ 219 }; 220 221 static struct plx_pci_card_info plx_pci_card_info_marathon_pci = { 222 "Marathon CAN-bus-PCI", 2, 223 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 224 {0, 0x00, 0x00}, { {2, 0x00, 0x00}, {4, 0x00, 0x00} }, 225 &plx_pci_reset_marathon_pci 226 /* based on PLX9052 */ 227 }; 228 229 static struct plx_pci_card_info plx_pci_card_info_marathon_pcie = { 230 "Marathon CAN-bus-PCIe", 2, 231 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 232 {0, 0x00, 0x00}, { {2, 0x00, 0x00}, {3, 0x80, 0x00} }, 233 &plx_pci_reset_marathon_pcie 234 /* based on PEX8311 */ 235 }; 236 237 static struct plx_pci_card_info plx_pci_card_info_tews = { 238 "TEWS TECHNOLOGIES TPMC810", 2, 239 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 240 {0, 0x00, 0x00}, { {2, 0x000, 0x80}, {2, 0x100, 0x80} }, 241 &plx_pci_reset_common 242 /* based on PLX9030 */ 243 }; 244 245 static struct plx_pci_card_info plx_pci_card_info_cti = { 246 "Connect Tech Inc. CANpro/104-Plus Opto (CRG001)", 2, 247 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 248 {0, 0x00, 0x00}, { {2, 0x000, 0x80}, {2, 0x100, 0x80} }, 249 &plx_pci_reset_common 250 /* based on PLX9030 */ 251 }; 252 253 static struct plx_pci_card_info plx_pci_card_info_elcus = { 254 "Eclus CAN-200-PCI", 2, 255 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 256 {1, 0x00, 0x00}, { {2, 0x00, 0x80}, {3, 0x00, 0x80} }, 257 &plx_pci_reset_common 258 /* based on PLX9030 */ 259 }; 260 261 static const struct pci_device_id plx_pci_tbl[] = { 262 { 263 /* Adlink PCI-7841/cPCI-7841 */ 264 ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID, 265 PCI_ANY_ID, PCI_ANY_ID, 266 PCI_CLASS_NETWORK_OTHER << 8, ~0, 267 (kernel_ulong_t)&plx_pci_card_info_adlink 268 }, 269 { 270 /* Adlink PCI-7841/cPCI-7841 SE */ 271 ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID, 272 PCI_ANY_ID, PCI_ANY_ID, 273 PCI_CLASS_COMMUNICATION_OTHER << 8, ~0, 274 (kernel_ulong_t)&plx_pci_card_info_adlink_se 275 }, 276 { 277 /* esd CAN-PCI/200 */ 278 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 279 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI200, 280 0, 0, 281 (kernel_ulong_t)&plx_pci_card_info_esd200 282 }, 283 { 284 /* esd CAN-CPCI/200 */ 285 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 286 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_CPCI200, 287 0, 0, 288 (kernel_ulong_t)&plx_pci_card_info_esd200 289 }, 290 { 291 /* esd CAN-PCI104/200 */ 292 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 293 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI104200, 294 0, 0, 295 (kernel_ulong_t)&plx_pci_card_info_esd200 296 }, 297 { 298 /* esd CAN-PCI/266 */ 299 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056, 300 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI266, 301 0, 0, 302 (kernel_ulong_t)&plx_pci_card_info_esd266 303 }, 304 { 305 /* esd CAN-PMC/266 */ 306 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056, 307 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PMC266, 308 0, 0, 309 (kernel_ulong_t)&plx_pci_card_info_esd266 310 }, 311 { 312 /* esd CAN-PCIE/2000 */ 313 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056, 314 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCIE2000, 315 0, 0, 316 (kernel_ulong_t)&plx_pci_card_info_esd2000 317 }, 318 { 319 /* IXXAT PC-I 04/PCI card */ 320 IXXAT_PCI_VENDOR_ID, IXXAT_PCI_DEVICE_ID, 321 PCI_ANY_ID, IXXAT_PCI_SUB_SYS_ID, 322 0, 0, 323 (kernel_ulong_t)&plx_pci_card_info_ixxat 324 }, 325 { 326 /* Marathon CAN-bus-PCI card */ 327 PCI_VENDOR_ID_PLX, MARATHON_PCI_DEVICE_ID, 328 PCI_ANY_ID, PCI_ANY_ID, 329 0, 0, 330 (kernel_ulong_t)&plx_pci_card_info_marathon_pci 331 }, 332 { 333 /* Marathon CAN-bus-PCIe card */ 334 PCI_VENDOR_ID_PLX, MARATHON_PCIE_DEVICE_ID, 335 PCI_ANY_ID, PCI_ANY_ID, 336 0, 0, 337 (kernel_ulong_t)&plx_pci_card_info_marathon_pcie 338 }, 339 { 340 /* TEWS TECHNOLOGIES TPMC810 card */ 341 TEWS_PCI_VENDOR_ID, TEWS_PCI_DEVICE_ID_TMPC810, 342 PCI_ANY_ID, PCI_ANY_ID, 343 0, 0, 344 (kernel_ulong_t)&plx_pci_card_info_tews 345 }, 346 { 347 /* Connect Tech Inc. CANpro/104-Plus Opto (CRG001) card */ 348 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 349 CTI_PCI_VENDOR_ID, CTI_PCI_DEVICE_ID_CRG001, 350 0, 0, 351 (kernel_ulong_t)&plx_pci_card_info_cti 352 }, 353 { 354 /* Elcus CAN-200-PCI */ 355 CAN200PCI_VENDOR_ID, CAN200PCI_DEVICE_ID, 356 CAN200PCI_SUB_VENDOR_ID, CAN200PCI_SUB_DEVICE_ID, 357 0, 0, 358 (kernel_ulong_t)&plx_pci_card_info_elcus 359 }, 360 { 0,} 361 }; 362 MODULE_DEVICE_TABLE(pci, plx_pci_tbl); 363 364 static u8 plx_pci_read_reg(const struct sja1000_priv *priv, int port) 365 { 366 return ioread8(priv->reg_base + port); 367 } 368 369 static void plx_pci_write_reg(const struct sja1000_priv *priv, int port, u8 val) 370 { 371 iowrite8(val, priv->reg_base + port); 372 } 373 374 /* 375 * Check if a CAN controller is present at the specified location 376 * by trying to switch 'em from the Basic mode into the PeliCAN mode. 377 * Also check states of some registers in reset mode. 378 */ 379 static inline int plx_pci_check_sja1000(const struct sja1000_priv *priv) 380 { 381 int flag = 0; 382 383 /* 384 * Check registers after hardware reset (the Basic mode) 385 * See states on p. 10 of the Datasheet. 386 */ 387 if ((priv->read_reg(priv, REG_CR) & REG_CR_BASICCAN_INITIAL_MASK) == 388 REG_CR_BASICCAN_INITIAL && 389 (priv->read_reg(priv, SJA1000_SR) == REG_SR_BASICCAN_INITIAL) && 390 (priv->read_reg(priv, SJA1000_IR) == REG_IR_BASICCAN_INITIAL)) 391 flag = 1; 392 393 /* Bring the SJA1000 into the PeliCAN mode*/ 394 priv->write_reg(priv, SJA1000_CDR, CDR_PELICAN); 395 396 /* 397 * Check registers after reset in the PeliCAN mode. 398 * See states on p. 23 of the Datasheet. 399 */ 400 if (priv->read_reg(priv, SJA1000_MOD) == REG_MOD_PELICAN_INITIAL && 401 priv->read_reg(priv, SJA1000_SR) == REG_SR_PELICAN_INITIAL && 402 priv->read_reg(priv, SJA1000_IR) == REG_IR_PELICAN_INITIAL) 403 return flag; 404 405 return 0; 406 } 407 408 /* 409 * PLX9030/50/52 software reset 410 * Also LRESET# asserts and brings to reset device on the Local Bus (if wired). 411 * For most cards it's enough for reset the SJA1000 chips. 412 */ 413 static void plx_pci_reset_common(struct pci_dev *pdev) 414 { 415 struct plx_pci_card *card = pci_get_drvdata(pdev); 416 u32 cntrl; 417 418 cntrl = ioread32(card->conf_addr + PLX_CNTRL); 419 cntrl |= PLX_PCI_RESET; 420 iowrite32(cntrl, card->conf_addr + PLX_CNTRL); 421 udelay(100); 422 cntrl ^= PLX_PCI_RESET; 423 iowrite32(cntrl, card->conf_addr + PLX_CNTRL); 424 }; 425 426 /* 427 * PLX9056 software reset 428 * Assert LRESET# and reset device(s) on the Local Bus (if wired). 429 */ 430 static void plx9056_pci_reset_common(struct pci_dev *pdev) 431 { 432 struct plx_pci_card *card = pci_get_drvdata(pdev); 433 u32 cntrl; 434 435 /* issue a local bus reset */ 436 cntrl = ioread32(card->conf_addr + PLX9056_CNTRL); 437 cntrl |= PLX_PCI_RESET; 438 iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); 439 udelay(100); 440 cntrl ^= PLX_PCI_RESET; 441 iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); 442 443 /* reload local configuration from EEPROM */ 444 cntrl |= PLX9056_PCI_RCR; 445 iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); 446 447 /* 448 * There is no safe way to poll for the end 449 * of reconfiguration process. Waiting for 10ms 450 * is safe. 451 */ 452 mdelay(10); 453 454 cntrl ^= PLX9056_PCI_RCR; 455 iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); 456 }; 457 458 /* Special reset function for Marathon CAN-bus-PCI card */ 459 static void plx_pci_reset_marathon_pci(struct pci_dev *pdev) 460 { 461 void __iomem *reset_addr; 462 int i; 463 static const int reset_bar[2] = {3, 5}; 464 465 plx_pci_reset_common(pdev); 466 467 for (i = 0; i < 2; i++) { 468 reset_addr = pci_iomap(pdev, reset_bar[i], 0); 469 if (!reset_addr) { 470 dev_err(&pdev->dev, "Failed to remap reset " 471 "space %d (BAR%d)\n", i, reset_bar[i]); 472 } else { 473 /* reset the SJA1000 chip */ 474 iowrite8(0x1, reset_addr); 475 udelay(100); 476 pci_iounmap(pdev, reset_addr); 477 } 478 } 479 } 480 481 /* Special reset function for Marathon CAN-bus-PCIe card */ 482 static void plx_pci_reset_marathon_pcie(struct pci_dev *pdev) 483 { 484 void __iomem *addr; 485 void __iomem *reset_addr; 486 int i; 487 488 plx9056_pci_reset_common(pdev); 489 490 for (i = 0; i < 2; i++) { 491 struct plx_pci_channel_map *chan_map = 492 &plx_pci_card_info_marathon_pcie.chan_map_tbl[i]; 493 addr = pci_iomap(pdev, chan_map->bar, chan_map->size); 494 if (!addr) { 495 dev_err(&pdev->dev, "Failed to remap reset " 496 "space %d (BAR%d)\n", i, chan_map->bar); 497 } else { 498 /* reset the SJA1000 chip */ 499 #define MARATHON_PCIE_RESET_OFFSET 32 500 reset_addr = addr + chan_map->offset + 501 MARATHON_PCIE_RESET_OFFSET; 502 iowrite8(0x1, reset_addr); 503 udelay(100); 504 pci_iounmap(pdev, addr); 505 } 506 } 507 } 508 509 static void plx_pci_del_card(struct pci_dev *pdev) 510 { 511 struct plx_pci_card *card = pci_get_drvdata(pdev); 512 struct net_device *dev; 513 struct sja1000_priv *priv; 514 int i = 0; 515 516 for (i = 0; i < PLX_PCI_MAX_CHAN; i++) { 517 dev = card->net_dev[i]; 518 if (!dev) 519 continue; 520 521 dev_info(&pdev->dev, "Removing %s\n", dev->name); 522 unregister_sja1000dev(dev); 523 priv = netdev_priv(dev); 524 if (priv->reg_base) 525 pci_iounmap(pdev, priv->reg_base); 526 free_sja1000dev(dev); 527 } 528 529 card->reset_func(pdev); 530 531 /* 532 * Disable interrupts from PCI-card and disable local 533 * interrupts 534 */ 535 if (pdev->device != PCI_DEVICE_ID_PLX_9056 && 536 pdev->device != MARATHON_PCIE_DEVICE_ID) 537 iowrite32(0x0, card->conf_addr + PLX_INTCSR); 538 else 539 iowrite32(0x0, card->conf_addr + PLX9056_INTCSR); 540 541 if (card->conf_addr) 542 pci_iounmap(pdev, card->conf_addr); 543 544 kfree(card); 545 546 pci_disable_device(pdev); 547 } 548 549 /* 550 * Probe PLX90xx based device for the SJA1000 chips and register each 551 * available CAN channel to SJA1000 Socket-CAN subsystem. 552 */ 553 static int plx_pci_add_card(struct pci_dev *pdev, 554 const struct pci_device_id *ent) 555 { 556 struct sja1000_priv *priv; 557 struct net_device *dev; 558 struct plx_pci_card *card; 559 struct plx_pci_card_info *ci; 560 int err, i; 561 u32 val; 562 void __iomem *addr; 563 564 ci = (struct plx_pci_card_info *)ent->driver_data; 565 566 if (pci_enable_device(pdev) < 0) { 567 dev_err(&pdev->dev, "Failed to enable PCI device\n"); 568 return -ENODEV; 569 } 570 571 dev_info(&pdev->dev, "Detected \"%s\" card at slot #%i\n", 572 ci->name, PCI_SLOT(pdev->devfn)); 573 574 /* Allocate card structures to hold addresses, ... */ 575 card = kzalloc(sizeof(*card), GFP_KERNEL); 576 if (!card) { 577 pci_disable_device(pdev); 578 return -ENOMEM; 579 } 580 581 pci_set_drvdata(pdev, card); 582 583 card->channels = 0; 584 585 /* Remap PLX90xx configuration space */ 586 addr = pci_iomap(pdev, ci->conf_map.bar, ci->conf_map.size); 587 if (!addr) { 588 err = -ENOMEM; 589 dev_err(&pdev->dev, "Failed to remap configuration space " 590 "(BAR%d)\n", ci->conf_map.bar); 591 goto failure_cleanup; 592 } 593 card->conf_addr = addr + ci->conf_map.offset; 594 595 ci->reset_func(pdev); 596 card->reset_func = ci->reset_func; 597 598 /* Detect available channels */ 599 for (i = 0; i < ci->channel_count; i++) { 600 struct plx_pci_channel_map *cm = &ci->chan_map_tbl[i]; 601 602 dev = alloc_sja1000dev(0); 603 if (!dev) { 604 err = -ENOMEM; 605 goto failure_cleanup; 606 } 607 608 card->net_dev[i] = dev; 609 priv = netdev_priv(dev); 610 priv->priv = card; 611 priv->irq_flags = IRQF_SHARED; 612 613 dev->irq = pdev->irq; 614 615 /* 616 * Remap IO space of the SJA1000 chips 617 * This is device-dependent mapping 618 */ 619 addr = pci_iomap(pdev, cm->bar, cm->size); 620 if (!addr) { 621 err = -ENOMEM; 622 dev_err(&pdev->dev, "Failed to remap BAR%d\n", cm->bar); 623 goto failure_cleanup; 624 } 625 626 priv->reg_base = addr + cm->offset; 627 priv->read_reg = plx_pci_read_reg; 628 priv->write_reg = plx_pci_write_reg; 629 630 /* Check if channel is present */ 631 if (plx_pci_check_sja1000(priv)) { 632 priv->can.clock.freq = ci->can_clock; 633 priv->ocr = ci->ocr; 634 priv->cdr = ci->cdr; 635 636 SET_NETDEV_DEV(dev, &pdev->dev); 637 dev->dev_id = i; 638 639 /* Register SJA1000 device */ 640 err = register_sja1000dev(dev); 641 if (err) { 642 dev_err(&pdev->dev, "Registering device failed " 643 "(err=%d)\n", err); 644 goto failure_cleanup; 645 } 646 647 card->channels++; 648 649 dev_info(&pdev->dev, "Channel #%d at 0x%p, irq %d " 650 "registered as %s\n", i + 1, priv->reg_base, 651 dev->irq, dev->name); 652 } else { 653 dev_err(&pdev->dev, "Channel #%d not detected\n", 654 i + 1); 655 free_sja1000dev(dev); 656 card->net_dev[i] = NULL; 657 } 658 } 659 660 if (!card->channels) { 661 err = -ENODEV; 662 goto failure_cleanup; 663 } 664 665 /* 666 * Enable interrupts from PCI-card (PLX90xx) and enable Local_1, 667 * Local_2 interrupts from the SJA1000 chips 668 */ 669 if (pdev->device != PCI_DEVICE_ID_PLX_9056 && 670 pdev->device != MARATHON_PCIE_DEVICE_ID) { 671 val = ioread32(card->conf_addr + PLX_INTCSR); 672 if (pdev->subsystem_vendor == PCI_VENDOR_ID_ESDGMBH) 673 val |= PLX_LINT1_EN | PLX_PCI_INT_EN; 674 else 675 val |= PLX_LINT1_EN | PLX_LINT2_EN | PLX_PCI_INT_EN; 676 iowrite32(val, card->conf_addr + PLX_INTCSR); 677 } else { 678 iowrite32(PLX9056_LINTI | PLX9056_PCI_INT_EN, 679 card->conf_addr + PLX9056_INTCSR); 680 } 681 return 0; 682 683 failure_cleanup: 684 dev_err(&pdev->dev, "Error: %d. Cleaning Up.\n", err); 685 686 plx_pci_del_card(pdev); 687 688 return err; 689 } 690 691 static struct pci_driver plx_pci_driver = { 692 .name = DRV_NAME, 693 .id_table = plx_pci_tbl, 694 .probe = plx_pci_add_card, 695 .remove = plx_pci_del_card, 696 }; 697 698 module_pci_driver(plx_pci_driver); 699