1 /* 2 * Copyright (C) 2007, 2011 Wolfgang Grandegger <wg@grandegger.com> 3 * 4 * Derived from the PCAN project file driver/src/pcan_pci.c: 5 * 6 * Copyright (C) 2001-2006 PEAK System-Technik GmbH 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the version 2 of the GNU General Public License 10 * as published by the Free Software Foundation 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software Foundation, 19 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 20 */ 21 22 #include <linux/kernel.h> 23 #include <linux/version.h> 24 #include <linux/module.h> 25 #include <linux/interrupt.h> 26 #include <linux/netdevice.h> 27 #include <linux/delay.h> 28 #include <linux/pci.h> 29 #include <linux/io.h> 30 #include <linux/can.h> 31 #include <linux/can/dev.h> 32 33 #include "sja1000.h" 34 35 MODULE_AUTHOR("Wolfgang Grandegger <wg@grandegger.com>"); 36 MODULE_DESCRIPTION("Socket-CAN driver for PEAK PCAN PCI/PCIe cards"); 37 MODULE_SUPPORTED_DEVICE("PEAK PCAN PCI/PCIe CAN card"); 38 MODULE_LICENSE("GPL v2"); 39 40 #define DRV_NAME "peak_pci" 41 42 struct peak_pci_chan { 43 void __iomem *cfg_base; /* Common for all channels */ 44 struct net_device *next_dev; /* Chain of network devices */ 45 u16 icr_mask; /* Interrupt mask for fast ack */ 46 }; 47 48 #define PEAK_PCI_CAN_CLOCK (16000000 / 2) 49 50 #define PEAK_PCI_CDR (CDR_CBP | CDR_CLKOUT_MASK) 51 #define PEAK_PCI_OCR OCR_TX0_PUSHPULL 52 53 /* 54 * Important PITA registers 55 */ 56 #define PITA_ICR 0x00 /* Interrupt control register */ 57 #define PITA_GPIOICR 0x18 /* GPIO interface control register */ 58 #define PITA_MISC 0x1C /* Miscellaneous register */ 59 60 #define PEAK_PCI_CFG_SIZE 0x1000 /* Size of the config PCI bar */ 61 #define PEAK_PCI_CHAN_SIZE 0x0400 /* Size used by the channel */ 62 63 #define PEAK_PCI_VENDOR_ID 0x001C /* The PCI device and vendor IDs */ 64 #define PEAK_PCI_DEVICE_ID 0x0001 /* for PCI/PCIe slot cards */ 65 66 static const u16 peak_pci_icr_masks[] = {0x02, 0x01, 0x40, 0x80}; 67 68 static DEFINE_PCI_DEVICE_TABLE(peak_pci_tbl) = { 69 {PEAK_PCI_VENDOR_ID, PEAK_PCI_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, 70 {0,} 71 }; 72 73 MODULE_DEVICE_TABLE(pci, peak_pci_tbl); 74 75 static u8 peak_pci_read_reg(const struct sja1000_priv *priv, int port) 76 { 77 return readb(priv->reg_base + (port << 2)); 78 } 79 80 static void peak_pci_write_reg(const struct sja1000_priv *priv, 81 int port, u8 val) 82 { 83 writeb(val, priv->reg_base + (port << 2)); 84 } 85 86 static void peak_pci_post_irq(const struct sja1000_priv *priv) 87 { 88 struct peak_pci_chan *chan = priv->priv; 89 u16 icr; 90 91 /* Select and clear in PITA stored interrupt */ 92 icr = readw(chan->cfg_base + PITA_ICR); 93 if (icr & chan->icr_mask) 94 writew(chan->icr_mask, chan->cfg_base + PITA_ICR); 95 } 96 97 static int __devinit peak_pci_probe(struct pci_dev *pdev, 98 const struct pci_device_id *ent) 99 { 100 struct sja1000_priv *priv; 101 struct peak_pci_chan *chan; 102 struct net_device *dev, *dev0 = NULL; 103 void __iomem *cfg_base, *reg_base; 104 u16 sub_sys_id, icr; 105 int i, err, channels; 106 107 err = pci_enable_device(pdev); 108 if (err) 109 return err; 110 111 err = pci_request_regions(pdev, DRV_NAME); 112 if (err) 113 goto failure_disable_pci; 114 115 err = pci_read_config_word(pdev, 0x2e, &sub_sys_id); 116 if (err) 117 goto failure_release_regions; 118 119 dev_dbg(&pdev->dev, "probing device %04x:%04x:%04x\n", 120 pdev->vendor, pdev->device, sub_sys_id); 121 122 err = pci_write_config_word(pdev, 0x44, 0); 123 if (err) 124 goto failure_release_regions; 125 126 if (sub_sys_id >= 12) 127 channels = 4; 128 else if (sub_sys_id >= 10) 129 channels = 3; 130 else if (sub_sys_id >= 4) 131 channels = 2; 132 else 133 channels = 1; 134 135 cfg_base = pci_iomap(pdev, 0, PEAK_PCI_CFG_SIZE); 136 if (!cfg_base) { 137 dev_err(&pdev->dev, "failed to map PCI resource #0\n"); 138 goto failure_release_regions; 139 } 140 141 reg_base = pci_iomap(pdev, 1, PEAK_PCI_CHAN_SIZE * channels); 142 if (!reg_base) { 143 dev_err(&pdev->dev, "failed to map PCI resource #1\n"); 144 goto failure_unmap_cfg_base; 145 } 146 147 /* Set GPIO control register */ 148 writew(0x0005, cfg_base + PITA_GPIOICR + 2); 149 /* Enable all channels of this card */ 150 writeb(0x00, cfg_base + PITA_GPIOICR); 151 /* Toggle reset */ 152 writeb(0x05, cfg_base + PITA_MISC + 3); 153 mdelay(5); 154 /* Leave parport mux mode */ 155 writeb(0x04, cfg_base + PITA_MISC + 3); 156 157 icr = readw(cfg_base + PITA_ICR + 2); 158 159 for (i = 0; i < channels; i++) { 160 dev = alloc_sja1000dev(sizeof(struct peak_pci_chan)); 161 if (!dev) { 162 err = -ENOMEM; 163 goto failure_remove_channels; 164 } 165 166 priv = netdev_priv(dev); 167 chan = priv->priv; 168 169 chan->cfg_base = cfg_base; 170 priv->reg_base = reg_base + i * PEAK_PCI_CHAN_SIZE; 171 172 priv->read_reg = peak_pci_read_reg; 173 priv->write_reg = peak_pci_write_reg; 174 priv->post_irq = peak_pci_post_irq; 175 176 priv->can.clock.freq = PEAK_PCI_CAN_CLOCK; 177 priv->ocr = PEAK_PCI_OCR; 178 priv->cdr = PEAK_PCI_CDR; 179 /* Neither a slave nor a single device distributes the clock */ 180 if (channels == 1 || i > 0) 181 priv->cdr |= CDR_CLK_OFF; 182 183 /* Setup interrupt handling */ 184 priv->irq_flags = IRQF_SHARED; 185 dev->irq = pdev->irq; 186 187 chan->icr_mask = peak_pci_icr_masks[i]; 188 icr |= chan->icr_mask; 189 190 SET_NETDEV_DEV(dev, &pdev->dev); 191 192 err = register_sja1000dev(dev); 193 if (err) { 194 dev_err(&pdev->dev, "failed to register device\n"); 195 free_sja1000dev(dev); 196 goto failure_remove_channels; 197 } 198 199 /* Create chain of SJA1000 devices */ 200 if (i == 0) 201 dev0 = dev; 202 else 203 chan->next_dev = dev; 204 205 dev_info(&pdev->dev, 206 "%s at reg_base=0x%p cfg_base=0x%p irq=%d\n", 207 dev->name, priv->reg_base, chan->cfg_base, dev->irq); 208 } 209 210 pci_set_drvdata(pdev, dev0); 211 212 /* Enable interrupts */ 213 writew(icr, cfg_base + PITA_ICR + 2); 214 215 return 0; 216 217 failure_remove_channels: 218 /* Disable interrupts */ 219 writew(0x0, cfg_base + PITA_ICR + 2); 220 221 for (dev = dev0; dev; dev = chan->next_dev) { 222 unregister_sja1000dev(dev); 223 free_sja1000dev(dev); 224 priv = netdev_priv(dev); 225 chan = priv->priv; 226 dev = chan->next_dev; 227 } 228 229 pci_iounmap(pdev, reg_base); 230 231 failure_unmap_cfg_base: 232 pci_iounmap(pdev, cfg_base); 233 234 failure_release_regions: 235 pci_release_regions(pdev); 236 237 failure_disable_pci: 238 pci_disable_device(pdev); 239 240 return err; 241 } 242 243 static void __devexit peak_pci_remove(struct pci_dev *pdev) 244 { 245 struct net_device *dev = pci_get_drvdata(pdev); /* First device */ 246 struct sja1000_priv *priv = netdev_priv(dev); 247 struct peak_pci_chan *chan = priv->priv; 248 void __iomem *cfg_base = chan->cfg_base; 249 void __iomem *reg_base = priv->reg_base; 250 251 /* Disable interrupts */ 252 writew(0x0, cfg_base + PITA_ICR + 2); 253 254 /* Loop over all registered devices */ 255 while (1) { 256 dev_info(&pdev->dev, "removing device %s\n", dev->name); 257 unregister_sja1000dev(dev); 258 free_sja1000dev(dev); 259 dev = chan->next_dev; 260 if (!dev) 261 break; 262 priv = netdev_priv(dev); 263 chan = priv->priv; 264 } 265 266 pci_iounmap(pdev, reg_base); 267 pci_iounmap(pdev, cfg_base); 268 pci_release_regions(pdev); 269 pci_disable_device(pdev); 270 271 pci_set_drvdata(pdev, NULL); 272 } 273 274 static struct pci_driver peak_pci_driver = { 275 .name = DRV_NAME, 276 .id_table = peak_pci_tbl, 277 .probe = peak_pci_probe, 278 .remove = __devexit_p(peak_pci_remove), 279 }; 280 281 static int __init peak_pci_init(void) 282 { 283 return pci_register_driver(&peak_pci_driver); 284 } 285 module_init(peak_pci_init); 286 287 static void __exit peak_pci_exit(void) 288 { 289 pci_unregister_driver(&peak_pci_driver); 290 } 291 module_exit(peak_pci_exit); 292