1 /* 2 * Copyright (C) 2007, 2011 Wolfgang Grandegger <wg@grandegger.com> 3 * 4 * Derived from the PCAN project file driver/src/pcan_pci.c: 5 * 6 * Copyright (C) 2001-2006 PEAK System-Technik GmbH 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the version 2 of the GNU General Public License 10 * as published by the Free Software Foundation 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software Foundation, 19 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 20 */ 21 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/interrupt.h> 25 #include <linux/netdevice.h> 26 #include <linux/delay.h> 27 #include <linux/pci.h> 28 #include <linux/io.h> 29 #include <linux/can.h> 30 #include <linux/can/dev.h> 31 32 #include "sja1000.h" 33 34 MODULE_AUTHOR("Wolfgang Grandegger <wg@grandegger.com>"); 35 MODULE_DESCRIPTION("Socket-CAN driver for PEAK PCAN PCI/PCIe cards"); 36 MODULE_SUPPORTED_DEVICE("PEAK PCAN PCI/PCIe CAN card"); 37 MODULE_LICENSE("GPL v2"); 38 39 #define DRV_NAME "peak_pci" 40 41 struct peak_pci_chan { 42 void __iomem *cfg_base; /* Common for all channels */ 43 struct net_device *next_dev; /* Chain of network devices */ 44 u16 icr_mask; /* Interrupt mask for fast ack */ 45 }; 46 47 #define PEAK_PCI_CAN_CLOCK (16000000 / 2) 48 49 #define PEAK_PCI_CDR (CDR_CBP | CDR_CLKOUT_MASK) 50 #define PEAK_PCI_OCR OCR_TX0_PUSHPULL 51 52 /* 53 * Important PITA registers 54 */ 55 #define PITA_ICR 0x00 /* Interrupt control register */ 56 #define PITA_GPIOICR 0x18 /* GPIO interface control register */ 57 #define PITA_MISC 0x1C /* Miscellaneous register */ 58 59 #define PEAK_PCI_CFG_SIZE 0x1000 /* Size of the config PCI bar */ 60 #define PEAK_PCI_CHAN_SIZE 0x0400 /* Size used by the channel */ 61 62 #define PEAK_PCI_VENDOR_ID 0x001C /* The PCI device and vendor IDs */ 63 #define PEAK_PCI_DEVICE_ID 0x0001 /* for PCI/PCIe slot cards */ 64 65 static const u16 peak_pci_icr_masks[] = {0x02, 0x01, 0x40, 0x80}; 66 67 static DEFINE_PCI_DEVICE_TABLE(peak_pci_tbl) = { 68 {PEAK_PCI_VENDOR_ID, PEAK_PCI_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, 69 {0,} 70 }; 71 72 MODULE_DEVICE_TABLE(pci, peak_pci_tbl); 73 74 static u8 peak_pci_read_reg(const struct sja1000_priv *priv, int port) 75 { 76 return readb(priv->reg_base + (port << 2)); 77 } 78 79 static void peak_pci_write_reg(const struct sja1000_priv *priv, 80 int port, u8 val) 81 { 82 writeb(val, priv->reg_base + (port << 2)); 83 } 84 85 static void peak_pci_post_irq(const struct sja1000_priv *priv) 86 { 87 struct peak_pci_chan *chan = priv->priv; 88 u16 icr; 89 90 /* Select and clear in PITA stored interrupt */ 91 icr = readw(chan->cfg_base + PITA_ICR); 92 if (icr & chan->icr_mask) 93 writew(chan->icr_mask, chan->cfg_base + PITA_ICR); 94 } 95 96 static int __devinit peak_pci_probe(struct pci_dev *pdev, 97 const struct pci_device_id *ent) 98 { 99 struct sja1000_priv *priv; 100 struct peak_pci_chan *chan; 101 struct net_device *dev, *dev0 = NULL; 102 void __iomem *cfg_base, *reg_base; 103 u16 sub_sys_id, icr; 104 int i, err, channels; 105 106 err = pci_enable_device(pdev); 107 if (err) 108 return err; 109 110 err = pci_request_regions(pdev, DRV_NAME); 111 if (err) 112 goto failure_disable_pci; 113 114 err = pci_read_config_word(pdev, 0x2e, &sub_sys_id); 115 if (err) 116 goto failure_release_regions; 117 118 dev_dbg(&pdev->dev, "probing device %04x:%04x:%04x\n", 119 pdev->vendor, pdev->device, sub_sys_id); 120 121 err = pci_write_config_word(pdev, 0x44, 0); 122 if (err) 123 goto failure_release_regions; 124 125 if (sub_sys_id >= 12) 126 channels = 4; 127 else if (sub_sys_id >= 10) 128 channels = 3; 129 else if (sub_sys_id >= 4) 130 channels = 2; 131 else 132 channels = 1; 133 134 cfg_base = pci_iomap(pdev, 0, PEAK_PCI_CFG_SIZE); 135 if (!cfg_base) { 136 dev_err(&pdev->dev, "failed to map PCI resource #0\n"); 137 goto failure_release_regions; 138 } 139 140 reg_base = pci_iomap(pdev, 1, PEAK_PCI_CHAN_SIZE * channels); 141 if (!reg_base) { 142 dev_err(&pdev->dev, "failed to map PCI resource #1\n"); 143 goto failure_unmap_cfg_base; 144 } 145 146 /* Set GPIO control register */ 147 writew(0x0005, cfg_base + PITA_GPIOICR + 2); 148 /* Enable all channels of this card */ 149 writeb(0x00, cfg_base + PITA_GPIOICR); 150 /* Toggle reset */ 151 writeb(0x05, cfg_base + PITA_MISC + 3); 152 mdelay(5); 153 /* Leave parport mux mode */ 154 writeb(0x04, cfg_base + PITA_MISC + 3); 155 156 icr = readw(cfg_base + PITA_ICR + 2); 157 158 for (i = 0; i < channels; i++) { 159 dev = alloc_sja1000dev(sizeof(struct peak_pci_chan)); 160 if (!dev) { 161 err = -ENOMEM; 162 goto failure_remove_channels; 163 } 164 165 priv = netdev_priv(dev); 166 chan = priv->priv; 167 168 chan->cfg_base = cfg_base; 169 priv->reg_base = reg_base + i * PEAK_PCI_CHAN_SIZE; 170 171 priv->read_reg = peak_pci_read_reg; 172 priv->write_reg = peak_pci_write_reg; 173 priv->post_irq = peak_pci_post_irq; 174 175 priv->can.clock.freq = PEAK_PCI_CAN_CLOCK; 176 priv->ocr = PEAK_PCI_OCR; 177 priv->cdr = PEAK_PCI_CDR; 178 /* Neither a slave nor a single device distributes the clock */ 179 if (channels == 1 || i > 0) 180 priv->cdr |= CDR_CLK_OFF; 181 182 /* Setup interrupt handling */ 183 priv->irq_flags = IRQF_SHARED; 184 dev->irq = pdev->irq; 185 186 chan->icr_mask = peak_pci_icr_masks[i]; 187 icr |= chan->icr_mask; 188 189 SET_NETDEV_DEV(dev, &pdev->dev); 190 191 err = register_sja1000dev(dev); 192 if (err) { 193 dev_err(&pdev->dev, "failed to register device\n"); 194 free_sja1000dev(dev); 195 goto failure_remove_channels; 196 } 197 198 /* Create chain of SJA1000 devices */ 199 if (i == 0) 200 dev0 = dev; 201 else 202 chan->next_dev = dev; 203 204 dev_info(&pdev->dev, 205 "%s at reg_base=0x%p cfg_base=0x%p irq=%d\n", 206 dev->name, priv->reg_base, chan->cfg_base, dev->irq); 207 } 208 209 pci_set_drvdata(pdev, dev0); 210 211 /* Enable interrupts */ 212 writew(icr, cfg_base + PITA_ICR + 2); 213 214 return 0; 215 216 failure_remove_channels: 217 /* Disable interrupts */ 218 writew(0x0, cfg_base + PITA_ICR + 2); 219 220 for (dev = dev0; dev; dev = chan->next_dev) { 221 unregister_sja1000dev(dev); 222 free_sja1000dev(dev); 223 priv = netdev_priv(dev); 224 chan = priv->priv; 225 dev = chan->next_dev; 226 } 227 228 pci_iounmap(pdev, reg_base); 229 230 failure_unmap_cfg_base: 231 pci_iounmap(pdev, cfg_base); 232 233 failure_release_regions: 234 pci_release_regions(pdev); 235 236 failure_disable_pci: 237 pci_disable_device(pdev); 238 239 return err; 240 } 241 242 static void __devexit peak_pci_remove(struct pci_dev *pdev) 243 { 244 struct net_device *dev = pci_get_drvdata(pdev); /* First device */ 245 struct sja1000_priv *priv = netdev_priv(dev); 246 struct peak_pci_chan *chan = priv->priv; 247 void __iomem *cfg_base = chan->cfg_base; 248 void __iomem *reg_base = priv->reg_base; 249 250 /* Disable interrupts */ 251 writew(0x0, cfg_base + PITA_ICR + 2); 252 253 /* Loop over all registered devices */ 254 while (1) { 255 dev_info(&pdev->dev, "removing device %s\n", dev->name); 256 unregister_sja1000dev(dev); 257 free_sja1000dev(dev); 258 dev = chan->next_dev; 259 if (!dev) 260 break; 261 priv = netdev_priv(dev); 262 chan = priv->priv; 263 } 264 265 pci_iounmap(pdev, reg_base); 266 pci_iounmap(pdev, cfg_base); 267 pci_release_regions(pdev); 268 pci_disable_device(pdev); 269 270 pci_set_drvdata(pdev, NULL); 271 } 272 273 static struct pci_driver peak_pci_driver = { 274 .name = DRV_NAME, 275 .id_table = peak_pci_tbl, 276 .probe = peak_pci_probe, 277 .remove = __devexit_p(peak_pci_remove), 278 }; 279 280 static int __init peak_pci_init(void) 281 { 282 return pci_register_driver(&peak_pci_driver); 283 } 284 module_init(peak_pci_init); 285 286 static void __exit peak_pci_exit(void) 287 { 288 pci_unregister_driver(&peak_pci_driver); 289 } 290 module_exit(peak_pci_exit); 291