1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com> 4 * Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com> 5 * Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com> 6 * Copyright (C) 2023 EMS Dr. Thomas Wuensche 7 */ 8 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/interrupt.h> 12 #include <linux/netdevice.h> 13 #include <linux/delay.h> 14 #include <linux/slab.h> 15 #include <linux/pci.h> 16 #include <linux/can/dev.h> 17 #include <linux/io.h> 18 19 #include "sja1000.h" 20 21 #define DRV_NAME "ems_pci" 22 23 MODULE_AUTHOR("Sebastian Haas <support@ems-wuensche.com>"); 24 MODULE_AUTHOR("Gerhard Uttenthaler <uttenthaler@ems-wuensche.com>"); 25 MODULE_DESCRIPTION("Socket-CAN driver for EMS CPC-PCI/PCIe/104P CAN cards"); 26 MODULE_LICENSE("GPL v2"); 27 28 #define EMS_PCI_V1_MAX_CHAN 2 29 #define EMS_PCI_V2_MAX_CHAN 4 30 #define EMS_PCI_V3_MAX_CHAN 4 31 #define EMS_PCI_MAX_CHAN EMS_PCI_V2_MAX_CHAN 32 33 struct ems_pci_card { 34 int version; 35 int channels; 36 37 struct pci_dev *pci_dev; 38 struct net_device *net_dev[EMS_PCI_MAX_CHAN]; 39 40 void __iomem *conf_addr; 41 void __iomem *base_addr; 42 }; 43 44 #define EMS_PCI_CAN_CLOCK (16000000 / 2) 45 46 /* Register definitions and descriptions are from LinCAN 0.3.3. 47 * 48 * PSB4610 PITA-2 bridge control registers 49 */ 50 #define PITA2_ICR 0x00 /* Interrupt Control Register */ 51 #define PITA2_ICR_INT0 0x00000002 /* [RC] INT0 Active/Clear */ 52 #define PITA2_ICR_INT0_EN 0x00020000 /* [RW] Enable INT0 */ 53 54 #define PITA2_MISC 0x1c /* Miscellaneous Register */ 55 #define PITA2_MISC_CONFIG 0x04000000 /* Multiplexed parallel interface */ 56 57 /* Register definitions for the PLX 9030 58 */ 59 #define PLX_ICSR 0x4c /* Interrupt Control/Status register */ 60 #define PLX_ICSR_LINTI1_ENA 0x0001 /* LINTi1 Enable */ 61 #define PLX_ICSR_PCIINT_ENA 0x0040 /* PCI Interrupt Enable */ 62 #define PLX_ICSR_LINTI1_CLR 0x0400 /* Local Edge Triggerable Interrupt Clear */ 63 #define PLX_ICSR_ENA_CLR (PLX_ICSR_LINTI1_ENA | PLX_ICSR_PCIINT_ENA | \ 64 PLX_ICSR_LINTI1_CLR) 65 66 /* Register definitions for the ASIX99100 67 */ 68 #define ASIX_LINTSR 0x28 /* Interrupt Control/Status register */ 69 #define ASIX_LINTSR_INT0AC BIT(0) /* Writing 1 enables or clears interrupt */ 70 71 #define ASIX_LIEMR 0x24 /* Local Interrupt Enable / Miscellaneous Register */ 72 #define ASIX_LIEMR_L0EINTEN BIT(16) /* Local INT0 input assertion enable */ 73 #define ASIX_LIEMR_LRST BIT(14) /* Local Reset assert */ 74 75 /* The board configuration is probably following: 76 * RX1 is connected to ground. 77 * TX1 is not connected. 78 * CLKO is not connected. 79 * Setting the OCR register to 0xDA is a good idea. 80 * This means normal output mode, push-pull and the correct polarity. 81 */ 82 #define EMS_PCI_OCR (OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL) 83 84 /* In the CDR register, you should set CBP to 1. 85 * You will probably also want to set the clock divider value to 7 86 * (meaning direct oscillator output) because the second SJA1000 chip 87 * is driven by the first one CLKOUT output. 88 */ 89 #define EMS_PCI_CDR (CDR_CBP | CDR_CLKOUT_MASK) 90 91 #define EMS_PCI_V1_BASE_BAR 1 92 #define EMS_PCI_V1_CONF_BAR 0 93 #define EMS_PCI_V1_CONF_SIZE 4096 /* size of PITA control area */ 94 #define EMS_PCI_V1_CAN_BASE_OFFSET 0x400 /* offset where the controllers start */ 95 #define EMS_PCI_V1_CAN_CTRL_SIZE 0x200 /* memory size for each controller */ 96 97 #define EMS_PCI_V2_BASE_BAR 2 98 #define EMS_PCI_V2_CONF_BAR 0 99 #define EMS_PCI_V2_CONF_SIZE 128 /* size of PLX control area */ 100 #define EMS_PCI_V2_CAN_BASE_OFFSET 0x400 /* offset where the controllers start */ 101 #define EMS_PCI_V2_CAN_CTRL_SIZE 0x200 /* memory size for each controller */ 102 103 #define EMS_PCI_V3_BASE_BAR 0 104 #define EMS_PCI_V3_CONF_BAR 5 105 #define EMS_PCI_V3_CONF_SIZE 128 /* size of ASIX control area */ 106 #define EMS_PCI_V3_CAN_BASE_OFFSET 0x00 /* offset where the controllers starts */ 107 #define EMS_PCI_V3_CAN_CTRL_SIZE 0x100 /* memory size for each controller */ 108 109 #define EMS_PCI_BASE_SIZE 4096 /* size of controller area */ 110 111 #define PCI_SUBDEVICE_ID_EMS 0x4010 112 113 static const struct pci_device_id ems_pci_tbl[] = { 114 /* CPC-PCI v1 */ 115 {PCI_VENDOR_ID_SIEMENS, 0x2104, PCI_ANY_ID, PCI_ANY_ID,}, 116 /* CPC-PCI v2 */ 117 {PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_PLX, 0x4000}, 118 /* CPC-104P v2 */ 119 {PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_PLX, 0x4002}, 120 /* CPC-PCIe v3 */ 121 {PCI_VENDOR_ID_ASIX, PCI_DEVICE_ID_ASIX_AX99100_LB, 0xa000, PCI_SUBDEVICE_ID_EMS}, 122 {0,} 123 }; 124 MODULE_DEVICE_TABLE(pci, ems_pci_tbl); 125 126 /* Helper to read internal registers from card logic (not CAN) 127 */ 128 static u8 ems_pci_v1_readb(struct ems_pci_card *card, unsigned int port) 129 { 130 return readb(card->base_addr + (port * 4)); 131 } 132 133 static u8 ems_pci_v1_read_reg(const struct sja1000_priv *priv, int port) 134 { 135 return readb(priv->reg_base + (port * 4)); 136 } 137 138 static void ems_pci_v1_write_reg(const struct sja1000_priv *priv, 139 int port, u8 val) 140 { 141 writeb(val, priv->reg_base + (port * 4)); 142 } 143 144 static void ems_pci_v1_post_irq(const struct sja1000_priv *priv) 145 { 146 struct ems_pci_card *card = priv->priv; 147 148 /* reset int flag of pita */ 149 writel(PITA2_ICR_INT0_EN | PITA2_ICR_INT0, 150 card->conf_addr + PITA2_ICR); 151 } 152 153 static u8 ems_pci_v2_read_reg(const struct sja1000_priv *priv, int port) 154 { 155 return readb(priv->reg_base + port); 156 } 157 158 static void ems_pci_v2_write_reg(const struct sja1000_priv *priv, 159 int port, u8 val) 160 { 161 writeb(val, priv->reg_base + port); 162 } 163 164 static void ems_pci_v2_post_irq(const struct sja1000_priv *priv) 165 { 166 struct ems_pci_card *card = priv->priv; 167 168 writel(PLX_ICSR_ENA_CLR, card->conf_addr + PLX_ICSR); 169 } 170 171 static u8 ems_pci_v3_read_reg(const struct sja1000_priv *priv, int port) 172 { 173 return readb(priv->reg_base + port); 174 } 175 176 static void ems_pci_v3_write_reg(const struct sja1000_priv *priv, 177 int port, u8 val) 178 { 179 writeb(val, priv->reg_base + port); 180 } 181 182 static void ems_pci_v3_post_irq(const struct sja1000_priv *priv) 183 { 184 struct ems_pci_card *card = priv->priv; 185 186 writel(ASIX_LINTSR_INT0AC, card->conf_addr + ASIX_LINTSR); 187 } 188 189 /* Check if a CAN controller is present at the specified location 190 * by trying to set 'em into the PeliCAN mode 191 */ 192 static inline int ems_pci_check_chan(const struct sja1000_priv *priv) 193 { 194 unsigned char res; 195 196 /* Make sure SJA1000 is in reset mode */ 197 priv->write_reg(priv, SJA1000_MOD, 1); 198 199 priv->write_reg(priv, SJA1000_CDR, CDR_PELICAN); 200 201 /* read reset-values */ 202 res = priv->read_reg(priv, SJA1000_CDR); 203 204 if (res == CDR_PELICAN) 205 return 1; 206 207 return 0; 208 } 209 210 static void ems_pci_del_card(struct pci_dev *pdev) 211 { 212 struct ems_pci_card *card = pci_get_drvdata(pdev); 213 struct net_device *dev; 214 int i = 0; 215 216 for (i = 0; i < card->channels; i++) { 217 dev = card->net_dev[i]; 218 219 if (!dev) 220 continue; 221 222 dev_info(&pdev->dev, "Removing %s.\n", dev->name); 223 unregister_sja1000dev(dev); 224 free_sja1000dev(dev); 225 } 226 227 if (card->base_addr) 228 pci_iounmap(card->pci_dev, card->base_addr); 229 230 if (card->conf_addr) 231 pci_iounmap(card->pci_dev, card->conf_addr); 232 233 kfree(card); 234 235 pci_disable_device(pdev); 236 } 237 238 static void ems_pci_card_reset(struct ems_pci_card *card) 239 { 240 /* Request board reset */ 241 writeb(0, card->base_addr); 242 } 243 244 /* Probe PCI device for EMS CAN signature and register each available 245 * CAN channel to SJA1000 Socket-CAN subsystem. 246 */ 247 static int ems_pci_add_card(struct pci_dev *pdev, 248 const struct pci_device_id *ent) 249 { 250 struct sja1000_priv *priv; 251 struct net_device *dev; 252 struct ems_pci_card *card; 253 int max_chan, conf_size, base_bar, conf_bar; 254 int err, i; 255 256 /* Enabling PCI device */ 257 if (pci_enable_device(pdev) < 0) { 258 dev_err(&pdev->dev, "Enabling PCI device failed\n"); 259 return -ENODEV; 260 } 261 262 /* Allocating card structures to hold addresses, ... */ 263 card = kzalloc(sizeof(*card), GFP_KERNEL); 264 if (!card) { 265 pci_disable_device(pdev); 266 return -ENOMEM; 267 } 268 269 pci_set_drvdata(pdev, card); 270 271 card->pci_dev = pdev; 272 273 card->channels = 0; 274 275 if (pdev->vendor == PCI_VENDOR_ID_ASIX) { 276 card->version = 3; /* CPC-PCI v3 */ 277 max_chan = EMS_PCI_V3_MAX_CHAN; 278 base_bar = EMS_PCI_V3_BASE_BAR; 279 conf_bar = EMS_PCI_V3_CONF_BAR; 280 conf_size = EMS_PCI_V3_CONF_SIZE; 281 } else if (pdev->vendor == PCI_VENDOR_ID_PLX) { 282 card->version = 2; /* CPC-PCI v2 */ 283 max_chan = EMS_PCI_V2_MAX_CHAN; 284 base_bar = EMS_PCI_V2_BASE_BAR; 285 conf_bar = EMS_PCI_V2_CONF_BAR; 286 conf_size = EMS_PCI_V2_CONF_SIZE; 287 } else { 288 card->version = 1; /* CPC-PCI v1 */ 289 max_chan = EMS_PCI_V1_MAX_CHAN; 290 base_bar = EMS_PCI_V1_BASE_BAR; 291 conf_bar = EMS_PCI_V1_CONF_BAR; 292 conf_size = EMS_PCI_V1_CONF_SIZE; 293 } 294 295 /* Remap configuration space and controller memory area */ 296 card->conf_addr = pci_iomap(pdev, conf_bar, conf_size); 297 if (!card->conf_addr) { 298 err = -ENOMEM; 299 goto failure_cleanup; 300 } 301 302 card->base_addr = pci_iomap(pdev, base_bar, EMS_PCI_BASE_SIZE); 303 if (!card->base_addr) { 304 err = -ENOMEM; 305 goto failure_cleanup; 306 } 307 308 if (card->version == 1) { 309 /* Configure PITA-2 parallel interface (enable MUX) */ 310 writel(PITA2_MISC_CONFIG, card->conf_addr + PITA2_MISC); 311 312 /* Check for unique EMS CAN signature */ 313 if (ems_pci_v1_readb(card, 0) != 0x55 || 314 ems_pci_v1_readb(card, 1) != 0xAA || 315 ems_pci_v1_readb(card, 2) != 0x01 || 316 ems_pci_v1_readb(card, 3) != 0xCB || 317 ems_pci_v1_readb(card, 4) != 0x11) { 318 dev_err(&pdev->dev, 319 "Not EMS Dr. Thomas Wuensche interface\n"); 320 err = -ENODEV; 321 goto failure_cleanup; 322 } 323 } 324 325 if (card->version == 3) { 326 /* ASIX chip asserts local reset to CAN controllers 327 * after bootup until it is deasserted 328 */ 329 writel(readl(card->conf_addr + ASIX_LIEMR) & ~ASIX_LIEMR_LRST, 330 card->conf_addr + ASIX_LIEMR); 331 } 332 333 ems_pci_card_reset(card); 334 335 /* Detect available channels */ 336 for (i = 0; i < max_chan; i++) { 337 dev = alloc_sja1000dev(0); 338 if (!dev) { 339 err = -ENOMEM; 340 goto failure_cleanup; 341 } 342 343 card->net_dev[i] = dev; 344 priv = netdev_priv(dev); 345 priv->priv = card; 346 priv->irq_flags = IRQF_SHARED; 347 348 dev->irq = pdev->irq; 349 350 if (card->version == 1) { 351 priv->read_reg = ems_pci_v1_read_reg; 352 priv->write_reg = ems_pci_v1_write_reg; 353 priv->post_irq = ems_pci_v1_post_irq; 354 priv->reg_base = card->base_addr + EMS_PCI_V1_CAN_BASE_OFFSET 355 + (i * EMS_PCI_V1_CAN_CTRL_SIZE); 356 } else if (card->version == 2) { 357 priv->read_reg = ems_pci_v2_read_reg; 358 priv->write_reg = ems_pci_v2_write_reg; 359 priv->post_irq = ems_pci_v2_post_irq; 360 priv->reg_base = card->base_addr + EMS_PCI_V2_CAN_BASE_OFFSET 361 + (i * EMS_PCI_V2_CAN_CTRL_SIZE); 362 } else { 363 priv->read_reg = ems_pci_v3_read_reg; 364 priv->write_reg = ems_pci_v3_write_reg; 365 priv->post_irq = ems_pci_v3_post_irq; 366 priv->reg_base = card->base_addr + EMS_PCI_V3_CAN_BASE_OFFSET 367 + (i * EMS_PCI_V3_CAN_CTRL_SIZE); 368 } 369 370 /* Check if channel is present */ 371 if (ems_pci_check_chan(priv)) { 372 priv->can.clock.freq = EMS_PCI_CAN_CLOCK; 373 priv->ocr = EMS_PCI_OCR; 374 priv->cdr = EMS_PCI_CDR; 375 376 SET_NETDEV_DEV(dev, &pdev->dev); 377 dev->dev_id = i; 378 379 if (card->version == 1) { 380 /* reset int flag of pita */ 381 writel(PITA2_ICR_INT0_EN | PITA2_ICR_INT0, 382 card->conf_addr + PITA2_ICR); 383 } else if (card->version == 2) { 384 /* enable IRQ in PLX 9030 */ 385 writel(PLX_ICSR_ENA_CLR, 386 card->conf_addr + PLX_ICSR); 387 } else { 388 /* Enable IRQ in AX99100 */ 389 writel(ASIX_LINTSR_INT0AC, card->conf_addr + ASIX_LINTSR); 390 /* Enable local INT0 input enable */ 391 writel(readl(card->conf_addr + ASIX_LIEMR) | ASIX_LIEMR_L0EINTEN, 392 card->conf_addr + ASIX_LIEMR); 393 } 394 395 /* Register SJA1000 device */ 396 err = register_sja1000dev(dev); 397 if (err) { 398 dev_err(&pdev->dev, 399 "Registering device failed: %pe\n", 400 ERR_PTR(err)); 401 free_sja1000dev(dev); 402 goto failure_cleanup; 403 } 404 405 card->channels++; 406 407 dev_info(&pdev->dev, "Channel #%d at 0x%p, irq %d\n", 408 i + 1, priv->reg_base, dev->irq); 409 } else { 410 free_sja1000dev(dev); 411 } 412 } 413 414 return 0; 415 416 failure_cleanup: 417 dev_err(&pdev->dev, "Error: %d. Cleaning Up.\n", err); 418 419 ems_pci_del_card(pdev); 420 421 return err; 422 } 423 424 static struct pci_driver ems_pci_driver = { 425 .name = DRV_NAME, 426 .id_table = ems_pci_tbl, 427 .probe = ems_pci_add_card, 428 .remove = ems_pci_del_card, 429 }; 430 431 module_pci_driver(ems_pci_driver); 432