1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Renesas R-Car CAN FD device driver 3 * 4 * Copyright (C) 2015 Renesas Electronics Corp. 5 */ 6 7 /* The R-Car CAN FD controller can operate in either one of the below two modes 8 * - CAN FD only mode 9 * - Classical CAN (CAN 2.0) only mode 10 * 11 * This driver puts the controller in CAN FD only mode by default. In this 12 * mode, the controller acts as a CAN FD node that can also interoperate with 13 * CAN 2.0 nodes. 14 * 15 * To switch the controller to Classical CAN (CAN 2.0) only mode, add 16 * "renesas,no-can-fd" optional property to the device tree node. A h/w reset is 17 * also required to switch modes. 18 * 19 * Note: The h/w manual register naming convention is clumsy and not acceptable 20 * to use as it is in the driver. However, those names are added as comments 21 * wherever it is modified to a readable name. 22 */ 23 24 #include <linux/bitfield.h> 25 #include <linux/bitmap.h> 26 #include <linux/bitops.h> 27 #include <linux/can/dev.h> 28 #include <linux/clk.h> 29 #include <linux/errno.h> 30 #include <linux/ethtool.h> 31 #include <linux/interrupt.h> 32 #include <linux/iopoll.h> 33 #include <linux/kernel.h> 34 #include <linux/module.h> 35 #include <linux/moduleparam.h> 36 #include <linux/netdevice.h> 37 #include <linux/of.h> 38 #include <linux/phy/phy.h> 39 #include <linux/platform_device.h> 40 #include <linux/reset.h> 41 #include <linux/types.h> 42 43 #define RCANFD_DRV_NAME "rcar_canfd" 44 45 /* Global register bits */ 46 47 /* RSCFDnCFDGRMCFG */ 48 #define RCANFD_GRMCFG_RCMC BIT(0) 49 50 /* RSCFDnCFDGCFG / RSCFDnGCFG */ 51 #define RCANFD_GCFG_EEFE BIT(6) 52 #define RCANFD_GCFG_CMPOC BIT(5) /* CAN FD only */ 53 #define RCANFD_GCFG_DCS BIT(4) 54 #define RCANFD_GCFG_DCE BIT(1) 55 #define RCANFD_GCFG_TPRI BIT(0) 56 57 /* RSCFDnCFDGCTR / RSCFDnGCTR */ 58 #define RCANFD_GCTR_TSRST BIT(16) 59 #define RCANFD_GCTR_CFMPOFIE BIT(11) /* CAN FD only */ 60 #define RCANFD_GCTR_THLEIE BIT(10) 61 #define RCANFD_GCTR_MEIE BIT(9) 62 #define RCANFD_GCTR_DEIE BIT(8) 63 #define RCANFD_GCTR_GSLPR BIT(2) 64 #define RCANFD_GCTR_GMDC_MASK (0x3) 65 #define RCANFD_GCTR_GMDC_GOPM (0x0) 66 #define RCANFD_GCTR_GMDC_GRESET (0x1) 67 #define RCANFD_GCTR_GMDC_GTEST (0x2) 68 69 /* RSCFDnCFDGSTS / RSCFDnGSTS */ 70 #define RCANFD_GSTS_GRAMINIT BIT(3) 71 #define RCANFD_GSTS_GSLPSTS BIT(2) 72 #define RCANFD_GSTS_GHLTSTS BIT(1) 73 #define RCANFD_GSTS_GRSTSTS BIT(0) 74 /* Non-operational status */ 75 #define RCANFD_GSTS_GNOPM (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 76 77 /* RSCFDnCFDGERFL / RSCFDnGERFL */ 78 #define RCANFD_GERFL_EEF GENMASK(23, 16) 79 #define RCANFD_GERFL_CMPOF BIT(3) /* CAN FD only */ 80 #define RCANFD_GERFL_THLES BIT(2) 81 #define RCANFD_GERFL_MES BIT(1) 82 #define RCANFD_GERFL_DEF BIT(0) 83 84 #define RCANFD_GERFL_ERR(gpriv, x) \ 85 ({\ 86 typeof(gpriv) (_gpriv) = (gpriv); \ 87 ((x) & ((FIELD_PREP(RCANFD_GERFL_EEF, (_gpriv)->channels_mask)) | \ 88 RCANFD_GERFL_MES | ((_gpriv)->fdmode ? RCANFD_GERFL_CMPOF : 0))); \ 89 }) 90 91 /* AFL Rx rules registers */ 92 93 /* RSCFDnCFDGAFLECTR / RSCFDnGAFLECTR */ 94 #define RCANFD_GAFLECTR_AFLDAE BIT(8) 95 #define RCANFD_GAFLECTR_AFLPN(gpriv, page_num) ((page_num) & (gpriv)->info->max_aflpn) 96 97 /* RSCFDnCFDGAFLIDj / RSCFDnGAFLIDj */ 98 #define RCANFD_GAFLID_GAFLLB BIT(29) 99 100 /* RSCFDnCFDGAFLP1_j / RSCFDnGAFLP1_j */ 101 #define RCANFD_GAFLP1_GAFLFDP(x) (1 << (x)) 102 103 /* Channel register bits */ 104 105 /* RSCFDnCmCFG - Classical CAN only */ 106 #define RCANFD_CFG_SJW(x) (((x) & 0x3) << 24) 107 #define RCANFD_CFG_TSEG2(x) (((x) & 0x7) << 20) 108 #define RCANFD_CFG_TSEG1(x) (((x) & 0xf) << 16) 109 #define RCANFD_CFG_BRP(x) (((x) & 0x3ff) << 0) 110 111 /* RSCFDnCFDCmNCFG - CAN FD only */ 112 #define RCANFD_NCFG_NTSEG2(gpriv, x) \ 113 (((x) & ((gpriv)->info->nom_bittiming->tseg2_max - 1)) << (gpriv)->info->sh->ntseg2) 114 115 #define RCANFD_NCFG_NTSEG1(gpriv, x) \ 116 (((x) & ((gpriv)->info->nom_bittiming->tseg1_max - 1)) << (gpriv)->info->sh->ntseg1) 117 118 #define RCANFD_NCFG_NSJW(gpriv, x) \ 119 (((x) & ((gpriv)->info->nom_bittiming->sjw_max - 1)) << (gpriv)->info->sh->nsjw) 120 121 #define RCANFD_NCFG_NBRP(x) (((x) & 0x3ff) << 0) 122 123 /* RSCFDnCFDCmCTR / RSCFDnCmCTR */ 124 #define RCANFD_CCTR_CTME BIT(24) 125 #define RCANFD_CCTR_ERRD BIT(23) 126 #define RCANFD_CCTR_BOM_MASK (0x3 << 21) 127 #define RCANFD_CCTR_BOM_ISO (0x0 << 21) 128 #define RCANFD_CCTR_BOM_BENTRY (0x1 << 21) 129 #define RCANFD_CCTR_BOM_BEND (0x2 << 21) 130 #define RCANFD_CCTR_TDCVFIE BIT(19) 131 #define RCANFD_CCTR_SOCOIE BIT(18) 132 #define RCANFD_CCTR_EOCOIE BIT(17) 133 #define RCANFD_CCTR_TAIE BIT(16) 134 #define RCANFD_CCTR_ALIE BIT(15) 135 #define RCANFD_CCTR_BLIE BIT(14) 136 #define RCANFD_CCTR_OLIE BIT(13) 137 #define RCANFD_CCTR_BORIE BIT(12) 138 #define RCANFD_CCTR_BOEIE BIT(11) 139 #define RCANFD_CCTR_EPIE BIT(10) 140 #define RCANFD_CCTR_EWIE BIT(9) 141 #define RCANFD_CCTR_BEIE BIT(8) 142 #define RCANFD_CCTR_CSLPR BIT(2) 143 #define RCANFD_CCTR_CHMDC_MASK (0x3) 144 #define RCANFD_CCTR_CHDMC_COPM (0x0) 145 #define RCANFD_CCTR_CHDMC_CRESET (0x1) 146 #define RCANFD_CCTR_CHDMC_CHLT (0x2) 147 148 /* RSCFDnCFDCmSTS / RSCFDnCmSTS */ 149 #define RCANFD_CSTS_COMSTS BIT(7) 150 #define RCANFD_CSTS_RECSTS BIT(6) 151 #define RCANFD_CSTS_TRMSTS BIT(5) 152 #define RCANFD_CSTS_BOSTS BIT(4) 153 #define RCANFD_CSTS_EPSTS BIT(3) 154 #define RCANFD_CSTS_SLPSTS BIT(2) 155 #define RCANFD_CSTS_HLTSTS BIT(1) 156 #define RCANFD_CSTS_CRSTSTS BIT(0) 157 158 #define RCANFD_CSTS_TECCNT(x) (((x) >> 24) & 0xff) 159 #define RCANFD_CSTS_RECCNT(x) (((x) >> 16) & 0xff) 160 161 /* RSCFDnCFDCmERFL / RSCFDnCmERFL */ 162 #define RCANFD_CERFL_ADERR BIT(14) 163 #define RCANFD_CERFL_B0ERR BIT(13) 164 #define RCANFD_CERFL_B1ERR BIT(12) 165 #define RCANFD_CERFL_CERR BIT(11) 166 #define RCANFD_CERFL_AERR BIT(10) 167 #define RCANFD_CERFL_FERR BIT(9) 168 #define RCANFD_CERFL_SERR BIT(8) 169 #define RCANFD_CERFL_ALF BIT(7) 170 #define RCANFD_CERFL_BLF BIT(6) 171 #define RCANFD_CERFL_OVLF BIT(5) 172 #define RCANFD_CERFL_BORF BIT(4) 173 #define RCANFD_CERFL_BOEF BIT(3) 174 #define RCANFD_CERFL_EPF BIT(2) 175 #define RCANFD_CERFL_EWF BIT(1) 176 #define RCANFD_CERFL_BEF BIT(0) 177 178 #define RCANFD_CERFL_ERR(x) ((x) & (0x7fff)) /* above bits 14:0 */ 179 180 /* RSCFDnCFDCmDCFG */ 181 #define RCANFD_DCFG_DSJW(gpriv, x) (((x) & ((gpriv)->info->data_bittiming->sjw_max - 1)) << 24) 182 183 #define RCANFD_DCFG_DTSEG2(gpriv, x) \ 184 (((x) & ((gpriv)->info->data_bittiming->tseg2_max - 1)) << (gpriv)->info->sh->dtseg2) 185 186 #define RCANFD_DCFG_DTSEG1(gpriv, x) \ 187 (((x) & ((gpriv)->info->data_bittiming->tseg1_max - 1)) << (gpriv)->info->sh->dtseg1) 188 189 #define RCANFD_DCFG_DBRP(x) (((x) & 0xff) << 0) 190 191 /* RSCFDnCFDCmFDCFG */ 192 #define RCANFD_GEN4_FDCFG_CLOE BIT(30) 193 #define RCANFD_GEN4_FDCFG_FDOE BIT(28) 194 #define RCANFD_FDCFG_TDCE BIT(9) 195 #define RCANFD_FDCFG_TDCOC BIT(8) 196 #define RCANFD_FDCFG_TDCO(x) (((x) & 0x7f) >> 16) 197 198 /* RSCFDnCFDRFCCx */ 199 #define RCANFD_RFCC_RFIM BIT(12) 200 #define RCANFD_RFCC_RFDC(x) (((x) & 0x7) << 8) 201 #define RCANFD_RFCC_RFPLS(x) (((x) & 0x7) << 4) 202 #define RCANFD_RFCC_RFIE BIT(1) 203 #define RCANFD_RFCC_RFE BIT(0) 204 205 /* RSCFDnCFDRFSTSx */ 206 #define RCANFD_RFSTS_RFIF BIT(3) 207 #define RCANFD_RFSTS_RFMLT BIT(2) 208 #define RCANFD_RFSTS_RFFLL BIT(1) 209 #define RCANFD_RFSTS_RFEMP BIT(0) 210 211 /* RSCFDnCFDRFIDx */ 212 #define RCANFD_RFID_RFIDE BIT(31) 213 #define RCANFD_RFID_RFRTR BIT(30) 214 215 /* RSCFDnCFDRFPTRx */ 216 #define RCANFD_RFPTR_RFDLC(x) (((x) >> 28) & 0xf) 217 #define RCANFD_RFPTR_RFPTR(x) (((x) >> 16) & 0xfff) 218 #define RCANFD_RFPTR_RFTS(x) (((x) >> 0) & 0xffff) 219 220 /* RSCFDnCFDRFFDSTSx */ 221 #define RCANFD_RFFDSTS_RFFDF BIT(2) 222 #define RCANFD_RFFDSTS_RFBRS BIT(1) 223 #define RCANFD_RFFDSTS_RFESI BIT(0) 224 225 /* Common FIFO bits */ 226 227 /* RSCFDnCFDCFCCk */ 228 #define RCANFD_CFCC_CFTML(gpriv, cftml) \ 229 ({\ 230 typeof(gpriv) (_gpriv) = (gpriv); \ 231 (((cftml) & (_gpriv)->info->max_cftml) << (_gpriv)->info->sh->cftml); \ 232 }) 233 #define RCANFD_CFCC_CFM(gpriv, x) (((x) & 0x3) << (gpriv)->info->sh->cfm) 234 #define RCANFD_CFCC_CFIM BIT(12) 235 #define RCANFD_CFCC_CFDC(gpriv, x) (((x) & 0x7) << (gpriv)->info->sh->cfdc) 236 #define RCANFD_CFCC_CFPLS(x) (((x) & 0x7) << 4) 237 #define RCANFD_CFCC_CFTXIE BIT(2) 238 #define RCANFD_CFCC_CFE BIT(0) 239 240 /* RSCFDnCFDCFSTSk */ 241 #define RCANFD_CFSTS_CFMC(x) (((x) >> 8) & 0xff) 242 #define RCANFD_CFSTS_CFTXIF BIT(4) 243 #define RCANFD_CFSTS_CFMLT BIT(2) 244 #define RCANFD_CFSTS_CFFLL BIT(1) 245 #define RCANFD_CFSTS_CFEMP BIT(0) 246 247 /* RSCFDnCFDCFIDk */ 248 #define RCANFD_CFID_CFIDE BIT(31) 249 #define RCANFD_CFID_CFRTR BIT(30) 250 #define RCANFD_CFID_CFID_MASK(x) ((x) & 0x1fffffff) 251 252 /* RSCFDnCFDCFPTRk */ 253 #define RCANFD_CFPTR_CFDLC(x) (((x) & 0xf) << 28) 254 #define RCANFD_CFPTR_CFPTR(x) (((x) & 0xfff) << 16) 255 #define RCANFD_CFPTR_CFTS(x) (((x) & 0xff) << 0) 256 257 /* RSCFDnCFDCFFDCSTSk */ 258 #define RCANFD_CFFDCSTS_CFFDF BIT(2) 259 #define RCANFD_CFFDCSTS_CFBRS BIT(1) 260 #define RCANFD_CFFDCSTS_CFESI BIT(0) 261 262 /* This controller supports either Classical CAN only mode or CAN FD only mode. 263 * These modes are supported in two separate set of register maps & names. 264 * However, some of the register offsets are common for both modes. Those 265 * offsets are listed below as Common registers. 266 * 267 * The CAN FD only mode specific registers & Classical CAN only mode specific 268 * registers are listed separately. Their register names starts with 269 * RCANFD_F_xxx & RCANFD_C_xxx respectively. 270 */ 271 272 /* Common registers */ 273 274 /* RSCFDnCFDCmNCFG / RSCFDnCmCFG */ 275 #define RCANFD_CCFG(m) (0x0000 + (0x10 * (m))) 276 /* RSCFDnCFDCmCTR / RSCFDnCmCTR */ 277 #define RCANFD_CCTR(m) (0x0004 + (0x10 * (m))) 278 /* RSCFDnCFDCmSTS / RSCFDnCmSTS */ 279 #define RCANFD_CSTS(m) (0x0008 + (0x10 * (m))) 280 /* RSCFDnCFDCmERFL / RSCFDnCmERFL */ 281 #define RCANFD_CERFL(m) (0x000C + (0x10 * (m))) 282 283 /* RSCFDnCFDGCFG / RSCFDnGCFG */ 284 #define RCANFD_GCFG (0x0084) 285 /* RSCFDnCFDGCTR / RSCFDnGCTR */ 286 #define RCANFD_GCTR (0x0088) 287 /* RSCFDnCFDGCTS / RSCFDnGCTS */ 288 #define RCANFD_GSTS (0x008c) 289 /* RSCFDnCFDGERFL / RSCFDnGERFL */ 290 #define RCANFD_GERFL (0x0090) 291 /* RSCFDnCFDGTSC / RSCFDnGTSC */ 292 #define RCANFD_GTSC (0x0094) 293 /* RSCFDnCFDGAFLECTR / RSCFDnGAFLECTR */ 294 #define RCANFD_GAFLECTR (0x0098) 295 /* RSCFDnCFDGAFLCFG / RSCFDnGAFLCFG */ 296 #define RCANFD_GAFLCFG(w) (0x009c + (0x04 * (w))) 297 /* RSCFDnCFDRMNB / RSCFDnRMNB */ 298 #define RCANFD_RMNB (0x00a4) 299 /* RSCFDnCFDRMND / RSCFDnRMND */ 300 #define RCANFD_RMND(y) (0x00a8 + (0x04 * (y))) 301 302 /* RSCFDnCFDRFCCx / RSCFDnRFCCx */ 303 #define RCANFD_RFCC(gpriv, x) ((gpriv)->info->regs->rfcc + (0x04 * (x))) 304 /* RSCFDnCFDRFSTSx / RSCFDnRFSTSx */ 305 #define RCANFD_RFSTS(gpriv, x) (RCANFD_RFCC(gpriv, x) + 0x20) 306 /* RSCFDnCFDRFPCTRx / RSCFDnRFPCTRx */ 307 #define RCANFD_RFPCTR(gpriv, x) (RCANFD_RFCC(gpriv, x) + 0x40) 308 309 /* Common FIFO Control registers */ 310 311 /* RSCFDnCFDCFCCx / RSCFDnCFCCx */ 312 #define RCANFD_CFCC(gpriv, ch, idx) \ 313 ((gpriv)->info->regs->cfcc + (0x0c * (ch)) + (0x04 * (idx))) 314 /* RSCFDnCFDCFSTSx / RSCFDnCFSTSx */ 315 #define RCANFD_CFSTS(gpriv, ch, idx) \ 316 ((gpriv)->info->regs->cfsts + (0x0c * (ch)) + (0x04 * (idx))) 317 /* RSCFDnCFDCFPCTRx / RSCFDnCFPCTRx */ 318 #define RCANFD_CFPCTR(gpriv, ch, idx) \ 319 ((gpriv)->info->regs->cfpctr + (0x0c * (ch)) + (0x04 * (idx))) 320 321 /* RSCFDnCFDFESTS / RSCFDnFESTS */ 322 #define RCANFD_FESTS (0x0238) 323 /* RSCFDnCFDFFSTS / RSCFDnFFSTS */ 324 #define RCANFD_FFSTS (0x023c) 325 /* RSCFDnCFDFMSTS / RSCFDnFMSTS */ 326 #define RCANFD_FMSTS (0x0240) 327 /* RSCFDnCFDRFISTS / RSCFDnRFISTS */ 328 #define RCANFD_RFISTS (0x0244) 329 /* RSCFDnCFDCFRISTS / RSCFDnCFRISTS */ 330 #define RCANFD_CFRISTS (0x0248) 331 /* RSCFDnCFDCFTISTS / RSCFDnCFTISTS */ 332 #define RCANFD_CFTISTS (0x024c) 333 334 /* RSCFDnCFDTMCp / RSCFDnTMCp */ 335 #define RCANFD_TMC(p) (0x0250 + (0x01 * (p))) 336 /* RSCFDnCFDTMSTSp / RSCFDnTMSTSp */ 337 #define RCANFD_TMSTS(p) (0x02d0 + (0x01 * (p))) 338 339 /* RSCFDnCFDTMTRSTSp / RSCFDnTMTRSTSp */ 340 #define RCANFD_TMTRSTS(y) (0x0350 + (0x04 * (y))) 341 /* RSCFDnCFDTMTARSTSp / RSCFDnTMTARSTSp */ 342 #define RCANFD_TMTARSTS(y) (0x0360 + (0x04 * (y))) 343 /* RSCFDnCFDTMTCSTSp / RSCFDnTMTCSTSp */ 344 #define RCANFD_TMTCSTS(y) (0x0370 + (0x04 * (y))) 345 /* RSCFDnCFDTMTASTSp / RSCFDnTMTASTSp */ 346 #define RCANFD_TMTASTS(y) (0x0380 + (0x04 * (y))) 347 /* RSCFDnCFDTMIECy / RSCFDnTMIECy */ 348 #define RCANFD_TMIEC(y) (0x0390 + (0x04 * (y))) 349 350 /* RSCFDnCFDTXQCCm / RSCFDnTXQCCm */ 351 #define RCANFD_TXQCC(m) (0x03a0 + (0x04 * (m))) 352 /* RSCFDnCFDTXQSTSm / RSCFDnTXQSTSm */ 353 #define RCANFD_TXQSTS(m) (0x03c0 + (0x04 * (m))) 354 /* RSCFDnCFDTXQPCTRm / RSCFDnTXQPCTRm */ 355 #define RCANFD_TXQPCTR(m) (0x03e0 + (0x04 * (m))) 356 357 /* RSCFDnCFDTHLCCm / RSCFDnTHLCCm */ 358 #define RCANFD_THLCC(m) (0x0400 + (0x04 * (m))) 359 /* RSCFDnCFDTHLSTSm / RSCFDnTHLSTSm */ 360 #define RCANFD_THLSTS(m) (0x0420 + (0x04 * (m))) 361 /* RSCFDnCFDTHLPCTRm / RSCFDnTHLPCTRm */ 362 #define RCANFD_THLPCTR(m) (0x0440 + (0x04 * (m))) 363 364 /* RSCFDnCFDGTINTSTS0 / RSCFDnGTINTSTS0 */ 365 #define RCANFD_GTINTSTS0 (0x0460) 366 /* RSCFDnCFDGTINTSTS1 / RSCFDnGTINTSTS1 */ 367 #define RCANFD_GTINTSTS1 (0x0464) 368 /* RSCFDnCFDGTSTCFG / RSCFDnGTSTCFG */ 369 #define RCANFD_GTSTCFG (0x0468) 370 /* RSCFDnCFDGTSTCTR / RSCFDnGTSTCTR */ 371 #define RCANFD_GTSTCTR (0x046c) 372 /* RSCFDnCFDGLOCKK / RSCFDnGLOCKK */ 373 #define RCANFD_GLOCKK (0x047c) 374 /* RSCFDnCFDGRMCFG */ 375 #define RCANFD_GRMCFG (0x04fc) 376 377 /* RSCFDnCFDGAFLIDj / RSCFDnGAFLIDj */ 378 #define RCANFD_GAFLID(offset, j) ((offset) + (0x10 * (j))) 379 /* RSCFDnCFDGAFLMj / RSCFDnGAFLMj */ 380 #define RCANFD_GAFLM(offset, j) ((offset) + 0x04 + (0x10 * (j))) 381 /* RSCFDnCFDGAFLP0j / RSCFDnGAFLP0j */ 382 #define RCANFD_GAFLP0(offset, j) ((offset) + 0x08 + (0x10 * (j))) 383 /* RSCFDnCFDGAFLP1j / RSCFDnGAFLP1j */ 384 #define RCANFD_GAFLP1(offset, j) ((offset) + 0x0c + (0x10 * (j))) 385 386 /* Classical CAN only mode register map */ 387 388 /* RSCFDnGAFLXXXj offset */ 389 #define RCANFD_C_GAFL_OFFSET (0x0500) 390 391 /* RSCFDnRMXXXq -> RCANFD_C_RMXXX(q) */ 392 #define RCANFD_C_RMID(q) (0x0600 + (0x10 * (q))) 393 #define RCANFD_C_RMPTR(q) (0x0604 + (0x10 * (q))) 394 #define RCANFD_C_RMDF0(q) (0x0608 + (0x10 * (q))) 395 #define RCANFD_C_RMDF1(q) (0x060c + (0x10 * (q))) 396 397 /* RSCFDnRFXXx -> RCANFD_C_RFXX(x) */ 398 #define RCANFD_C_RFOFFSET (0x0e00) 399 #define RCANFD_C_RFID(x) (RCANFD_C_RFOFFSET + (0x10 * (x))) 400 #define RCANFD_C_RFPTR(x) (RCANFD_C_RFOFFSET + 0x04 + (0x10 * (x))) 401 #define RCANFD_C_RFDF(x, df) \ 402 (RCANFD_C_RFOFFSET + 0x08 + (0x10 * (x)) + (0x04 * (df))) 403 404 /* RSCFDnCFXXk -> RCANFD_C_CFXX(ch, k) */ 405 #define RCANFD_C_CFOFFSET (0x0e80) 406 407 #define RCANFD_C_CFID(ch, idx) \ 408 (RCANFD_C_CFOFFSET + (0x30 * (ch)) + (0x10 * (idx))) 409 410 #define RCANFD_C_CFPTR(ch, idx) \ 411 (RCANFD_C_CFOFFSET + 0x04 + (0x30 * (ch)) + (0x10 * (idx))) 412 413 #define RCANFD_C_CFDF(ch, idx, df) \ 414 (RCANFD_C_CFOFFSET + 0x08 + (0x30 * (ch)) + (0x10 * (idx)) + (0x04 * (df))) 415 416 /* RSCFDnTMXXp -> RCANFD_C_TMXX(p) */ 417 #define RCANFD_C_TMID(p) (0x1000 + (0x10 * (p))) 418 #define RCANFD_C_TMPTR(p) (0x1004 + (0x10 * (p))) 419 #define RCANFD_C_TMDF0(p) (0x1008 + (0x10 * (p))) 420 #define RCANFD_C_TMDF1(p) (0x100c + (0x10 * (p))) 421 422 /* RSCFDnTHLACCm */ 423 #define RCANFD_C_THLACC(m) (0x1800 + (0x04 * (m))) 424 /* RSCFDnRPGACCr */ 425 #define RCANFD_C_RPGACC(r) (0x1900 + (0x04 * (r))) 426 427 /* R-Car Gen4 Classical and CAN FD mode specific register map */ 428 #define RCANFD_GEN4_FDCFG(m) (0x1404 + (0x20 * (m))) 429 430 #define RCANFD_GEN4_GAFL_OFFSET (0x1800) 431 432 /* CAN FD mode specific register map */ 433 434 /* RSCFDnCFDCmXXX -> RCANFD_F_XXX(m) */ 435 #define RCANFD_F_DCFG(gpriv, m) ((gpriv)->info->regs->f_dcfg + (0x20 * (m))) 436 #define RCANFD_F_CFDCFG(m) (0x0504 + (0x20 * (m))) 437 #define RCANFD_F_CFDCTR(m) (0x0508 + (0x20 * (m))) 438 #define RCANFD_F_CFDSTS(m) (0x050c + (0x20 * (m))) 439 #define RCANFD_F_CFDCRC(m) (0x0510 + (0x20 * (m))) 440 441 /* RSCFDnCFDGAFLXXXj offset */ 442 #define RCANFD_F_GAFL_OFFSET (0x1000) 443 444 /* RSCFDnCFDRMXXXq -> RCANFD_F_RMXXX(q) */ 445 #define RCANFD_F_RMID(q) (0x2000 + (0x20 * (q))) 446 #define RCANFD_F_RMPTR(q) (0x2004 + (0x20 * (q))) 447 #define RCANFD_F_RMFDSTS(q) (0x2008 + (0x20 * (q))) 448 #define RCANFD_F_RMDF(q, b) (0x200c + (0x04 * (b)) + (0x20 * (q))) 449 450 /* RSCFDnCFDRFXXx -> RCANFD_F_RFXX(x) */ 451 #define RCANFD_F_RFOFFSET(gpriv) ((gpriv)->info->regs->rfoffset) 452 #define RCANFD_F_RFID(gpriv, x) (RCANFD_F_RFOFFSET(gpriv) + (0x80 * (x))) 453 #define RCANFD_F_RFPTR(gpriv, x) (RCANFD_F_RFOFFSET(gpriv) + 0x04 + (0x80 * (x))) 454 #define RCANFD_F_RFFDSTS(gpriv, x) (RCANFD_F_RFOFFSET(gpriv) + 0x08 + (0x80 * (x))) 455 #define RCANFD_F_RFDF(gpriv, x, df) \ 456 (RCANFD_F_RFOFFSET(gpriv) + 0x0c + (0x80 * (x)) + (0x04 * (df))) 457 458 /* RSCFDnCFDCFXXk -> RCANFD_F_CFXX(ch, k) */ 459 #define RCANFD_F_CFOFFSET(gpriv) ((gpriv)->info->regs->cfoffset) 460 461 #define RCANFD_F_CFID(gpriv, ch, idx) \ 462 (RCANFD_F_CFOFFSET(gpriv) + (0x180 * (ch)) + (0x80 * (idx))) 463 464 #define RCANFD_F_CFPTR(gpriv, ch, idx) \ 465 (RCANFD_F_CFOFFSET(gpriv) + 0x04 + (0x180 * (ch)) + (0x80 * (idx))) 466 467 #define RCANFD_F_CFFDCSTS(gpriv, ch, idx) \ 468 (RCANFD_F_CFOFFSET(gpriv) + 0x08 + (0x180 * (ch)) + (0x80 * (idx))) 469 470 #define RCANFD_F_CFDF(gpriv, ch, idx, df) \ 471 (RCANFD_F_CFOFFSET(gpriv) + 0x0c + (0x180 * (ch)) + (0x80 * (idx)) + \ 472 (0x04 * (df))) 473 474 /* RSCFDnCFDTMXXp -> RCANFD_F_TMXX(p) */ 475 #define RCANFD_F_TMID(p) (0x4000 + (0x20 * (p))) 476 #define RCANFD_F_TMPTR(p) (0x4004 + (0x20 * (p))) 477 #define RCANFD_F_TMFDCTR(p) (0x4008 + (0x20 * (p))) 478 #define RCANFD_F_TMDF(p, b) (0x400c + (0x20 * (p)) + (0x04 * (b))) 479 480 /* RSCFDnCFDTHLACCm */ 481 #define RCANFD_F_THLACC(m) (0x6000 + (0x04 * (m))) 482 /* RSCFDnCFDRPGACCr */ 483 #define RCANFD_F_RPGACC(r) (0x6400 + (0x04 * (r))) 484 485 /* Constants */ 486 #define RCANFD_FIFO_DEPTH 8 /* Tx FIFO depth */ 487 #define RCANFD_NAPI_WEIGHT 8 /* Rx poll quota */ 488 489 #define RCANFD_NUM_CHANNELS 8 /* Eight channels max */ 490 #define RCANFD_CHANNELS_MASK BIT((RCANFD_NUM_CHANNELS) - 1) 491 492 #define RCANFD_GAFL_PAGENUM(entry) ((entry) / 16) 493 #define RCANFD_CHANNEL_NUMRULES 1 /* only one rule per channel */ 494 495 /* Rx FIFO is a global resource of the controller. There are 8 such FIFOs 496 * available. Each channel gets a dedicated Rx FIFO (i.e.) the channel 497 * number is added to RFFIFO index. 498 */ 499 #define RCANFD_RFFIFO_IDX 0 500 501 /* Tx/Rx or Common FIFO is a per channel resource. Each channel has 3 Common 502 * FIFOs dedicated to them. Use the first (index 0) FIFO out of the 3 for Tx. 503 */ 504 #define RCANFD_CFFIFO_IDX 0 505 506 struct rcar_canfd_global; 507 508 struct rcar_canfd_regs { 509 u16 rfcc; /* RX FIFO Configuration/Control Register */ 510 u16 cfcc; /* Common FIFO Configuration/Control Register */ 511 u16 cfsts; /* Common FIFO Status Register */ 512 u16 cfpctr; /* Common FIFO Pointer Control Register */ 513 u16 f_dcfg; /* Global FD Configuration Register */ 514 u16 rfoffset; /* Receive FIFO buffer access ID register */ 515 u16 cfoffset; /* Transmit/receive FIFO buffer access ID register */ 516 }; 517 518 struct rcar_canfd_shift_data { 519 u8 ntseg2; /* Nominal Bit Rate Time Segment 2 Control */ 520 u8 ntseg1; /* Nominal Bit Rate Time Segment 1 Control */ 521 u8 nsjw; /* Nominal Bit Rate Resynchronization Jump Width Control */ 522 u8 dtseg2; /* Data Bit Rate Time Segment 2 Control */ 523 u8 dtseg1; /* Data Bit Rate Time Segment 1 Control */ 524 u8 cftml; /* Common FIFO TX Message Buffer Link */ 525 u8 cfm; /* Common FIFO Mode */ 526 u8 cfdc; /* Common FIFO Depth Configuration */ 527 }; 528 529 struct rcar_canfd_hw_info { 530 const struct can_bittiming_const *nom_bittiming; 531 const struct can_bittiming_const *data_bittiming; 532 const struct rcar_canfd_regs *regs; 533 const struct rcar_canfd_shift_data *sh; 534 u8 rnc_field_width; 535 u8 max_aflpn; 536 u8 max_cftml; 537 u8 max_channels; 538 u8 postdiv; 539 /* hardware features */ 540 unsigned shared_global_irqs:1; /* Has shared global irqs */ 541 unsigned multi_channel_irqs:1; /* Has multiple channel irqs */ 542 unsigned ch_interface_mode:1; /* Has channel interface mode */ 543 unsigned shared_can_regs:1; /* Has shared classical can registers */ 544 unsigned external_clk:1; /* Has external clock */ 545 }; 546 547 /* Channel priv data */ 548 struct rcar_canfd_channel { 549 struct can_priv can; /* Must be the first member */ 550 struct net_device *ndev; 551 struct rcar_canfd_global *gpriv; /* Controller reference */ 552 void __iomem *base; /* Register base address */ 553 struct phy *transceiver; /* Optional transceiver */ 554 struct napi_struct napi; 555 u32 tx_head; /* Incremented on xmit */ 556 u32 tx_tail; /* Incremented on xmit done */ 557 u32 channel; /* Channel number */ 558 spinlock_t tx_lock; /* To protect tx path */ 559 }; 560 561 /* Global priv data */ 562 struct rcar_canfd_global { 563 struct rcar_canfd_channel *ch[RCANFD_NUM_CHANNELS]; 564 void __iomem *base; /* Register base address */ 565 struct platform_device *pdev; /* Respective platform device */ 566 struct clk *clkp; /* Peripheral clock */ 567 struct clk *can_clk; /* fCAN clock */ 568 unsigned long channels_mask; /* Enabled channels mask */ 569 bool extclk; /* CANFD or Ext clock */ 570 bool fdmode; /* CAN FD or Classical CAN only mode */ 571 struct reset_control *rstc1; 572 struct reset_control *rstc2; 573 const struct rcar_canfd_hw_info *info; 574 }; 575 576 /* CAN FD mode nominal rate constants */ 577 static const struct can_bittiming_const rcar_canfd_gen3_nom_bittiming_const = { 578 .name = RCANFD_DRV_NAME, 579 .tseg1_min = 2, 580 .tseg1_max = 128, 581 .tseg2_min = 2, 582 .tseg2_max = 32, 583 .sjw_max = 32, 584 .brp_min = 1, 585 .brp_max = 1024, 586 .brp_inc = 1, 587 }; 588 589 static const struct can_bittiming_const rcar_canfd_gen4_nom_bittiming_const = { 590 .name = RCANFD_DRV_NAME, 591 .tseg1_min = 2, 592 .tseg1_max = 256, 593 .tseg2_min = 2, 594 .tseg2_max = 128, 595 .sjw_max = 128, 596 .brp_min = 1, 597 .brp_max = 1024, 598 .brp_inc = 1, 599 }; 600 601 /* CAN FD mode data rate constants */ 602 static const struct can_bittiming_const rcar_canfd_gen3_data_bittiming_const = { 603 .name = RCANFD_DRV_NAME, 604 .tseg1_min = 2, 605 .tseg1_max = 16, 606 .tseg2_min = 2, 607 .tseg2_max = 8, 608 .sjw_max = 8, 609 .brp_min = 1, 610 .brp_max = 256, 611 .brp_inc = 1, 612 }; 613 614 static const struct can_bittiming_const rcar_canfd_gen4_data_bittiming_const = { 615 .name = RCANFD_DRV_NAME, 616 .tseg1_min = 2, 617 .tseg1_max = 32, 618 .tseg2_min = 2, 619 .tseg2_max = 16, 620 .sjw_max = 16, 621 .brp_min = 1, 622 .brp_max = 256, 623 .brp_inc = 1, 624 }; 625 626 /* Classical CAN mode bitrate constants */ 627 static const struct can_bittiming_const rcar_canfd_bittiming_const = { 628 .name = RCANFD_DRV_NAME, 629 .tseg1_min = 4, 630 .tseg1_max = 16, 631 .tseg2_min = 2, 632 .tseg2_max = 8, 633 .sjw_max = 4, 634 .brp_min = 1, 635 .brp_max = 1024, 636 .brp_inc = 1, 637 }; 638 639 static const struct rcar_canfd_regs rcar_gen3_regs = { 640 .rfcc = 0x00b8, 641 .cfcc = 0x0118, 642 .cfsts = 0x0178, 643 .cfpctr = 0x01d8, 644 .f_dcfg = 0x0500, 645 .rfoffset = 0x3000, 646 .cfoffset = 0x3400, 647 }; 648 649 static const struct rcar_canfd_regs rcar_gen4_regs = { 650 .rfcc = 0x00c0, 651 .cfcc = 0x0120, 652 .cfsts = 0x01e0, 653 .cfpctr = 0x0240, 654 .f_dcfg = 0x1400, 655 .rfoffset = 0x6000, 656 .cfoffset = 0x6400, 657 }; 658 659 static const struct rcar_canfd_shift_data rcar_gen3_shift_data = { 660 .ntseg2 = 24, 661 .ntseg1 = 16, 662 .nsjw = 11, 663 .dtseg2 = 20, 664 .dtseg1 = 16, 665 .cftml = 20, 666 .cfm = 16, 667 .cfdc = 8, 668 }; 669 670 static const struct rcar_canfd_shift_data rcar_gen4_shift_data = { 671 .ntseg2 = 25, 672 .ntseg1 = 17, 673 .nsjw = 10, 674 .dtseg2 = 16, 675 .dtseg1 = 8, 676 .cftml = 16, 677 .cfm = 8, 678 .cfdc = 21, 679 }; 680 681 static const struct rcar_canfd_hw_info rcar_gen3_hw_info = { 682 .nom_bittiming = &rcar_canfd_gen3_nom_bittiming_const, 683 .data_bittiming = &rcar_canfd_gen3_data_bittiming_const, 684 .regs = &rcar_gen3_regs, 685 .sh = &rcar_gen3_shift_data, 686 .rnc_field_width = 8, 687 .max_aflpn = 31, 688 .max_cftml = 15, 689 .max_channels = 2, 690 .postdiv = 2, 691 .shared_global_irqs = 1, 692 .ch_interface_mode = 0, 693 .shared_can_regs = 0, 694 .external_clk = 1, 695 }; 696 697 static const struct rcar_canfd_hw_info rcar_gen4_hw_info = { 698 .nom_bittiming = &rcar_canfd_gen4_nom_bittiming_const, 699 .data_bittiming = &rcar_canfd_gen4_data_bittiming_const, 700 .regs = &rcar_gen4_regs, 701 .sh = &rcar_gen4_shift_data, 702 .rnc_field_width = 16, 703 .max_aflpn = 127, 704 .max_cftml = 31, 705 .max_channels = 8, 706 .postdiv = 2, 707 .shared_global_irqs = 1, 708 .ch_interface_mode = 1, 709 .shared_can_regs = 1, 710 .external_clk = 1, 711 }; 712 713 static const struct rcar_canfd_hw_info rzg2l_hw_info = { 714 .nom_bittiming = &rcar_canfd_gen3_nom_bittiming_const, 715 .data_bittiming = &rcar_canfd_gen3_data_bittiming_const, 716 .regs = &rcar_gen3_regs, 717 .sh = &rcar_gen3_shift_data, 718 .rnc_field_width = 8, 719 .max_aflpn = 31, 720 .max_cftml = 15, 721 .max_channels = 2, 722 .postdiv = 1, 723 .multi_channel_irqs = 1, 724 .ch_interface_mode = 0, 725 .shared_can_regs = 0, 726 .external_clk = 1, 727 }; 728 729 static const struct rcar_canfd_hw_info r9a09g047_hw_info = { 730 .nom_bittiming = &rcar_canfd_gen4_nom_bittiming_const, 731 .data_bittiming = &rcar_canfd_gen4_data_bittiming_const, 732 .regs = &rcar_gen4_regs, 733 .sh = &rcar_gen4_shift_data, 734 .rnc_field_width = 16, 735 .max_aflpn = 63, 736 .max_cftml = 31, 737 .max_channels = 6, 738 .postdiv = 1, 739 .multi_channel_irqs = 1, 740 .ch_interface_mode = 1, 741 .shared_can_regs = 1, 742 .external_clk = 0, 743 }; 744 745 /* Helper functions */ 746 static inline void rcar_canfd_update(u32 mask, u32 val, u32 __iomem *reg) 747 { 748 u32 data = readl(reg); 749 750 data &= ~mask; 751 data |= (val & mask); 752 writel(data, reg); 753 } 754 755 static inline u32 rcar_canfd_read(void __iomem *base, u32 offset) 756 { 757 return readl(base + offset); 758 } 759 760 static inline void rcar_canfd_write(void __iomem *base, u32 offset, u32 val) 761 { 762 writel(val, base + offset); 763 } 764 765 static void rcar_canfd_set_bit(void __iomem *base, u32 reg, u32 val) 766 { 767 rcar_canfd_update(val, val, base + reg); 768 } 769 770 static void rcar_canfd_clear_bit(void __iomem *base, u32 reg, u32 val) 771 { 772 rcar_canfd_update(val, 0, base + reg); 773 } 774 775 static void rcar_canfd_update_bit(void __iomem *base, u32 reg, 776 u32 mask, u32 val) 777 { 778 rcar_canfd_update(mask, val, base + reg); 779 } 780 781 static void rcar_canfd_get_data(struct rcar_canfd_channel *priv, 782 struct canfd_frame *cf, u32 off) 783 { 784 u32 i, lwords; 785 786 lwords = DIV_ROUND_UP(cf->len, sizeof(u32)); 787 for (i = 0; i < lwords; i++) 788 *((u32 *)cf->data + i) = 789 rcar_canfd_read(priv->base, off + i * sizeof(u32)); 790 } 791 792 static void rcar_canfd_put_data(struct rcar_canfd_channel *priv, 793 struct canfd_frame *cf, u32 off) 794 { 795 u32 i, lwords; 796 797 lwords = DIV_ROUND_UP(cf->len, sizeof(u32)); 798 for (i = 0; i < lwords; i++) 799 rcar_canfd_write(priv->base, off + i * sizeof(u32), 800 *((u32 *)cf->data + i)); 801 } 802 803 static void rcar_canfd_tx_failure_cleanup(struct net_device *ndev) 804 { 805 u32 i; 806 807 for (i = 0; i < RCANFD_FIFO_DEPTH; i++) 808 can_free_echo_skb(ndev, i, NULL); 809 } 810 811 static void rcar_canfd_setrnc(struct rcar_canfd_global *gpriv, unsigned int ch, 812 unsigned int num_rules) 813 { 814 unsigned int rnc_stride = 32 / gpriv->info->rnc_field_width; 815 unsigned int shift = 32 - (ch % rnc_stride + 1) * gpriv->info->rnc_field_width; 816 unsigned int w = ch / rnc_stride; 817 u32 rnc = num_rules << shift; 818 819 rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLCFG(w), rnc); 820 } 821 822 static void rcar_canfd_set_mode(struct rcar_canfd_global *gpriv) 823 { 824 if (gpriv->info->ch_interface_mode) { 825 u32 ch, val = gpriv->fdmode ? RCANFD_GEN4_FDCFG_FDOE 826 : RCANFD_GEN4_FDCFG_CLOE; 827 828 for_each_set_bit(ch, &gpriv->channels_mask, 829 gpriv->info->max_channels) 830 rcar_canfd_set_bit(gpriv->base, RCANFD_GEN4_FDCFG(ch), 831 val); 832 } else { 833 if (gpriv->fdmode) 834 rcar_canfd_set_bit(gpriv->base, RCANFD_GRMCFG, 835 RCANFD_GRMCFG_RCMC); 836 else 837 rcar_canfd_clear_bit(gpriv->base, RCANFD_GRMCFG, 838 RCANFD_GRMCFG_RCMC); 839 } 840 } 841 842 static int rcar_canfd_reset_controller(struct rcar_canfd_global *gpriv) 843 { 844 u32 sts, ch; 845 int err; 846 847 /* Check RAMINIT flag as CAN RAM initialization takes place 848 * after the MCU reset 849 */ 850 err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts, 851 !(sts & RCANFD_GSTS_GRAMINIT), 2, 500000); 852 if (err) { 853 dev_dbg(&gpriv->pdev->dev, "global raminit failed\n"); 854 return err; 855 } 856 857 /* Transition to Global Reset mode */ 858 rcar_canfd_clear_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR); 859 rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR, 860 RCANFD_GCTR_GMDC_MASK, RCANFD_GCTR_GMDC_GRESET); 861 862 /* Ensure Global reset mode */ 863 err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts, 864 (sts & RCANFD_GSTS_GRSTSTS), 2, 500000); 865 if (err) { 866 dev_dbg(&gpriv->pdev->dev, "global reset failed\n"); 867 return err; 868 } 869 870 /* Reset Global error flags */ 871 rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0x0); 872 873 /* Set the controller into appropriate mode */ 874 rcar_canfd_set_mode(gpriv); 875 876 /* Transition all Channels to reset mode */ 877 for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) { 878 rcar_canfd_clear_bit(gpriv->base, 879 RCANFD_CCTR(ch), RCANFD_CCTR_CSLPR); 880 881 rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch), 882 RCANFD_CCTR_CHMDC_MASK, 883 RCANFD_CCTR_CHDMC_CRESET); 884 885 /* Ensure Channel reset mode */ 886 err = readl_poll_timeout((gpriv->base + RCANFD_CSTS(ch)), sts, 887 (sts & RCANFD_CSTS_CRSTSTS), 888 2, 500000); 889 if (err) { 890 dev_dbg(&gpriv->pdev->dev, 891 "channel %u reset failed\n", ch); 892 return err; 893 } 894 } 895 return 0; 896 } 897 898 static void rcar_canfd_configure_controller(struct rcar_canfd_global *gpriv) 899 { 900 u32 cfg, ch; 901 902 /* Global configuration settings */ 903 904 /* ECC Error flag Enable */ 905 cfg = RCANFD_GCFG_EEFE; 906 907 if (gpriv->fdmode) 908 /* Truncate payload to configured message size RFPLS */ 909 cfg |= RCANFD_GCFG_CMPOC; 910 911 /* Set External Clock if selected */ 912 if (gpriv->extclk) 913 cfg |= RCANFD_GCFG_DCS; 914 915 rcar_canfd_set_bit(gpriv->base, RCANFD_GCFG, cfg); 916 917 /* Channel configuration settings */ 918 for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) { 919 rcar_canfd_set_bit(gpriv->base, RCANFD_CCTR(ch), 920 RCANFD_CCTR_ERRD); 921 rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch), 922 RCANFD_CCTR_BOM_MASK, 923 RCANFD_CCTR_BOM_BENTRY); 924 } 925 } 926 927 static void rcar_canfd_configure_afl_rules(struct rcar_canfd_global *gpriv, 928 u32 ch, u32 rule_entry) 929 { 930 unsigned int offset, page, num_rules = RCANFD_CHANNEL_NUMRULES; 931 u32 rule_entry_index = rule_entry % 16; 932 u32 ridx = ch + RCANFD_RFFIFO_IDX; 933 934 /* Enable write access to entry */ 935 page = RCANFD_GAFL_PAGENUM(rule_entry); 936 rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLECTR, 937 (RCANFD_GAFLECTR_AFLPN(gpriv, page) | 938 RCANFD_GAFLECTR_AFLDAE)); 939 940 /* Write number of rules for channel */ 941 rcar_canfd_setrnc(gpriv, ch, num_rules); 942 if (gpriv->info->shared_can_regs) 943 offset = RCANFD_GEN4_GAFL_OFFSET; 944 else if (gpriv->fdmode) 945 offset = RCANFD_F_GAFL_OFFSET; 946 else 947 offset = RCANFD_C_GAFL_OFFSET; 948 949 /* Accept all IDs */ 950 rcar_canfd_write(gpriv->base, RCANFD_GAFLID(offset, rule_entry_index), 0); 951 /* IDE or RTR is not considered for matching */ 952 rcar_canfd_write(gpriv->base, RCANFD_GAFLM(offset, rule_entry_index), 0); 953 /* Any data length accepted */ 954 rcar_canfd_write(gpriv->base, RCANFD_GAFLP0(offset, rule_entry_index), 0); 955 /* Place the msg in corresponding Rx FIFO entry */ 956 rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLP1(offset, rule_entry_index), 957 RCANFD_GAFLP1_GAFLFDP(ridx)); 958 959 /* Disable write access to page */ 960 rcar_canfd_clear_bit(gpriv->base, 961 RCANFD_GAFLECTR, RCANFD_GAFLECTR_AFLDAE); 962 } 963 964 static void rcar_canfd_configure_rx(struct rcar_canfd_global *gpriv, u32 ch) 965 { 966 /* Rx FIFO is used for reception */ 967 u32 cfg; 968 u16 rfdc, rfpls; 969 970 /* Select Rx FIFO based on channel */ 971 u32 ridx = ch + RCANFD_RFFIFO_IDX; 972 973 rfdc = 2; /* b010 - 8 messages Rx FIFO depth */ 974 if (gpriv->fdmode) 975 rfpls = 7; /* b111 - Max 64 bytes payload */ 976 else 977 rfpls = 0; /* b000 - Max 8 bytes payload */ 978 979 cfg = (RCANFD_RFCC_RFIM | RCANFD_RFCC_RFDC(rfdc) | 980 RCANFD_RFCC_RFPLS(rfpls) | RCANFD_RFCC_RFIE); 981 rcar_canfd_write(gpriv->base, RCANFD_RFCC(gpriv, ridx), cfg); 982 } 983 984 static void rcar_canfd_configure_tx(struct rcar_canfd_global *gpriv, u32 ch) 985 { 986 /* Tx/Rx(Common) FIFO configured in Tx mode is 987 * used for transmission 988 * 989 * Each channel has 3 Common FIFO dedicated to them. 990 * Use the 1st (index 0) out of 3 991 */ 992 u32 cfg; 993 u16 cftml, cfm, cfdc, cfpls; 994 995 cftml = 0; /* 0th buffer */ 996 cfm = 1; /* b01 - Transmit mode */ 997 cfdc = 2; /* b010 - 8 messages Tx FIFO depth */ 998 if (gpriv->fdmode) 999 cfpls = 7; /* b111 - Max 64 bytes payload */ 1000 else 1001 cfpls = 0; /* b000 - Max 8 bytes payload */ 1002 1003 cfg = (RCANFD_CFCC_CFTML(gpriv, cftml) | RCANFD_CFCC_CFM(gpriv, cfm) | 1004 RCANFD_CFCC_CFIM | RCANFD_CFCC_CFDC(gpriv, cfdc) | 1005 RCANFD_CFCC_CFPLS(cfpls) | RCANFD_CFCC_CFTXIE); 1006 rcar_canfd_write(gpriv->base, RCANFD_CFCC(gpriv, ch, RCANFD_CFFIFO_IDX), cfg); 1007 1008 if (gpriv->fdmode) 1009 /* Clear FD mode specific control/status register */ 1010 rcar_canfd_write(gpriv->base, 1011 RCANFD_F_CFFDCSTS(gpriv, ch, RCANFD_CFFIFO_IDX), 0); 1012 } 1013 1014 static void rcar_canfd_enable_global_interrupts(struct rcar_canfd_global *gpriv) 1015 { 1016 u32 ctr; 1017 1018 /* Clear any stray error interrupt flags */ 1019 rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0); 1020 1021 /* Global interrupts setup */ 1022 ctr = RCANFD_GCTR_MEIE; 1023 if (gpriv->fdmode) 1024 ctr |= RCANFD_GCTR_CFMPOFIE; 1025 1026 rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, ctr); 1027 } 1028 1029 static void rcar_canfd_disable_global_interrupts(struct rcar_canfd_global 1030 *gpriv) 1031 { 1032 /* Disable all interrupts */ 1033 rcar_canfd_write(gpriv->base, RCANFD_GCTR, 0); 1034 1035 /* Clear any stray error interrupt flags */ 1036 rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0); 1037 } 1038 1039 static void rcar_canfd_enable_channel_interrupts(struct rcar_canfd_channel 1040 *priv) 1041 { 1042 u32 ctr, ch = priv->channel; 1043 1044 /* Clear any stray error flags */ 1045 rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0); 1046 1047 /* Channel interrupts setup */ 1048 ctr = (RCANFD_CCTR_TAIE | 1049 RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE | 1050 RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE | 1051 RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE | 1052 RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE); 1053 rcar_canfd_set_bit(priv->base, RCANFD_CCTR(ch), ctr); 1054 } 1055 1056 static void rcar_canfd_disable_channel_interrupts(struct rcar_canfd_channel 1057 *priv) 1058 { 1059 u32 ctr, ch = priv->channel; 1060 1061 ctr = (RCANFD_CCTR_TAIE | 1062 RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE | 1063 RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE | 1064 RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE | 1065 RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE); 1066 rcar_canfd_clear_bit(priv->base, RCANFD_CCTR(ch), ctr); 1067 1068 /* Clear any stray error flags */ 1069 rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0); 1070 } 1071 1072 static void rcar_canfd_global_error(struct net_device *ndev) 1073 { 1074 struct rcar_canfd_channel *priv = netdev_priv(ndev); 1075 struct rcar_canfd_global *gpriv = priv->gpriv; 1076 struct net_device_stats *stats = &ndev->stats; 1077 u32 ch = priv->channel; 1078 u32 gerfl, sts; 1079 u32 ridx = ch + RCANFD_RFFIFO_IDX; 1080 1081 gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL); 1082 if (gerfl & FIELD_PREP(RCANFD_GERFL_EEF, BIT(ch))) { 1083 netdev_dbg(ndev, "Ch%u: ECC Error flag\n", ch); 1084 stats->tx_dropped++; 1085 } 1086 if (gerfl & RCANFD_GERFL_MES) { 1087 sts = rcar_canfd_read(priv->base, 1088 RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX)); 1089 if (sts & RCANFD_CFSTS_CFMLT) { 1090 netdev_dbg(ndev, "Tx Message Lost flag\n"); 1091 stats->tx_dropped++; 1092 rcar_canfd_write(priv->base, 1093 RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX), 1094 sts & ~RCANFD_CFSTS_CFMLT); 1095 } 1096 1097 sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(gpriv, ridx)); 1098 if (sts & RCANFD_RFSTS_RFMLT) { 1099 netdev_dbg(ndev, "Rx Message Lost flag\n"); 1100 stats->rx_dropped++; 1101 rcar_canfd_write(priv->base, RCANFD_RFSTS(gpriv, ridx), 1102 sts & ~RCANFD_RFSTS_RFMLT); 1103 } 1104 } 1105 if (gpriv->fdmode && gerfl & RCANFD_GERFL_CMPOF) { 1106 /* Message Lost flag will be set for respective channel 1107 * when this condition happens with counters and flags 1108 * already updated. 1109 */ 1110 netdev_dbg(ndev, "global payload overflow interrupt\n"); 1111 } 1112 1113 /* Clear all global error interrupts. Only affected channels bits 1114 * get cleared 1115 */ 1116 rcar_canfd_write(priv->base, RCANFD_GERFL, 0); 1117 } 1118 1119 static void rcar_canfd_error(struct net_device *ndev, u32 cerfl, 1120 u16 txerr, u16 rxerr) 1121 { 1122 struct rcar_canfd_channel *priv = netdev_priv(ndev); 1123 struct net_device_stats *stats = &ndev->stats; 1124 struct can_frame *cf; 1125 struct sk_buff *skb; 1126 u32 ch = priv->channel; 1127 1128 netdev_dbg(ndev, "ch erfl %x txerr %u rxerr %u\n", cerfl, txerr, rxerr); 1129 1130 /* Propagate the error condition to the CAN stack */ 1131 skb = alloc_can_err_skb(ndev, &cf); 1132 if (!skb) { 1133 stats->rx_dropped++; 1134 return; 1135 } 1136 1137 /* Channel error interrupts */ 1138 if (cerfl & RCANFD_CERFL_BEF) { 1139 netdev_dbg(ndev, "Bus error\n"); 1140 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT; 1141 cf->data[2] = CAN_ERR_PROT_UNSPEC; 1142 priv->can.can_stats.bus_error++; 1143 } 1144 if (cerfl & RCANFD_CERFL_ADERR) { 1145 netdev_dbg(ndev, "ACK Delimiter Error\n"); 1146 stats->tx_errors++; 1147 cf->data[3] |= CAN_ERR_PROT_LOC_ACK_DEL; 1148 } 1149 if (cerfl & RCANFD_CERFL_B0ERR) { 1150 netdev_dbg(ndev, "Bit Error (dominant)\n"); 1151 stats->tx_errors++; 1152 cf->data[2] |= CAN_ERR_PROT_BIT0; 1153 } 1154 if (cerfl & RCANFD_CERFL_B1ERR) { 1155 netdev_dbg(ndev, "Bit Error (recessive)\n"); 1156 stats->tx_errors++; 1157 cf->data[2] |= CAN_ERR_PROT_BIT1; 1158 } 1159 if (cerfl & RCANFD_CERFL_CERR) { 1160 netdev_dbg(ndev, "CRC Error\n"); 1161 stats->rx_errors++; 1162 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ; 1163 } 1164 if (cerfl & RCANFD_CERFL_AERR) { 1165 netdev_dbg(ndev, "ACK Error\n"); 1166 stats->tx_errors++; 1167 cf->can_id |= CAN_ERR_ACK; 1168 cf->data[3] |= CAN_ERR_PROT_LOC_ACK; 1169 } 1170 if (cerfl & RCANFD_CERFL_FERR) { 1171 netdev_dbg(ndev, "Form Error\n"); 1172 stats->rx_errors++; 1173 cf->data[2] |= CAN_ERR_PROT_FORM; 1174 } 1175 if (cerfl & RCANFD_CERFL_SERR) { 1176 netdev_dbg(ndev, "Stuff Error\n"); 1177 stats->rx_errors++; 1178 cf->data[2] |= CAN_ERR_PROT_STUFF; 1179 } 1180 if (cerfl & RCANFD_CERFL_ALF) { 1181 netdev_dbg(ndev, "Arbitration lost Error\n"); 1182 priv->can.can_stats.arbitration_lost++; 1183 cf->can_id |= CAN_ERR_LOSTARB; 1184 cf->data[0] |= CAN_ERR_LOSTARB_UNSPEC; 1185 } 1186 if (cerfl & RCANFD_CERFL_BLF) { 1187 netdev_dbg(ndev, "Bus Lock Error\n"); 1188 stats->rx_errors++; 1189 cf->can_id |= CAN_ERR_BUSERROR; 1190 } 1191 if (cerfl & RCANFD_CERFL_EWF) { 1192 netdev_dbg(ndev, "Error warning interrupt\n"); 1193 priv->can.state = CAN_STATE_ERROR_WARNING; 1194 priv->can.can_stats.error_warning++; 1195 cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT; 1196 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING : 1197 CAN_ERR_CRTL_RX_WARNING; 1198 cf->data[6] = txerr; 1199 cf->data[7] = rxerr; 1200 } 1201 if (cerfl & RCANFD_CERFL_EPF) { 1202 netdev_dbg(ndev, "Error passive interrupt\n"); 1203 priv->can.state = CAN_STATE_ERROR_PASSIVE; 1204 priv->can.can_stats.error_passive++; 1205 cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT; 1206 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE : 1207 CAN_ERR_CRTL_RX_PASSIVE; 1208 cf->data[6] = txerr; 1209 cf->data[7] = rxerr; 1210 } 1211 if (cerfl & RCANFD_CERFL_BOEF) { 1212 netdev_dbg(ndev, "Bus-off entry interrupt\n"); 1213 rcar_canfd_tx_failure_cleanup(ndev); 1214 priv->can.state = CAN_STATE_BUS_OFF; 1215 priv->can.can_stats.bus_off++; 1216 can_bus_off(ndev); 1217 cf->can_id |= CAN_ERR_BUSOFF; 1218 } 1219 if (cerfl & RCANFD_CERFL_OVLF) { 1220 netdev_dbg(ndev, 1221 "Overload Frame Transmission error interrupt\n"); 1222 stats->tx_errors++; 1223 cf->can_id |= CAN_ERR_PROT; 1224 cf->data[2] |= CAN_ERR_PROT_OVERLOAD; 1225 } 1226 1227 /* Clear channel error interrupts that are handled */ 1228 rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 1229 RCANFD_CERFL_ERR(~cerfl)); 1230 netif_rx(skb); 1231 } 1232 1233 static void rcar_canfd_tx_done(struct net_device *ndev) 1234 { 1235 struct rcar_canfd_channel *priv = netdev_priv(ndev); 1236 struct rcar_canfd_global *gpriv = priv->gpriv; 1237 struct net_device_stats *stats = &ndev->stats; 1238 u32 sts; 1239 unsigned long flags; 1240 u32 ch = priv->channel; 1241 1242 do { 1243 u8 unsent, sent; 1244 1245 sent = priv->tx_tail % RCANFD_FIFO_DEPTH; 1246 stats->tx_packets++; 1247 stats->tx_bytes += can_get_echo_skb(ndev, sent, NULL); 1248 1249 spin_lock_irqsave(&priv->tx_lock, flags); 1250 priv->tx_tail++; 1251 sts = rcar_canfd_read(priv->base, 1252 RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX)); 1253 unsent = RCANFD_CFSTS_CFMC(sts); 1254 1255 /* Wake producer only when there is room */ 1256 if (unsent != RCANFD_FIFO_DEPTH) 1257 netif_wake_queue(ndev); 1258 1259 if (priv->tx_head - priv->tx_tail <= unsent) { 1260 spin_unlock_irqrestore(&priv->tx_lock, flags); 1261 break; 1262 } 1263 spin_unlock_irqrestore(&priv->tx_lock, flags); 1264 1265 } while (1); 1266 1267 /* Clear interrupt */ 1268 rcar_canfd_write(priv->base, RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX), 1269 sts & ~RCANFD_CFSTS_CFTXIF); 1270 } 1271 1272 static void rcar_canfd_handle_global_err(struct rcar_canfd_global *gpriv, u32 ch) 1273 { 1274 struct rcar_canfd_channel *priv = gpriv->ch[ch]; 1275 struct net_device *ndev = priv->ndev; 1276 u32 gerfl; 1277 1278 /* Handle global error interrupts */ 1279 gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL); 1280 if (unlikely(RCANFD_GERFL_ERR(gpriv, gerfl))) 1281 rcar_canfd_global_error(ndev); 1282 } 1283 1284 static irqreturn_t rcar_canfd_global_err_interrupt(int irq, void *dev_id) 1285 { 1286 struct rcar_canfd_global *gpriv = dev_id; 1287 u32 ch; 1288 1289 for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) 1290 rcar_canfd_handle_global_err(gpriv, ch); 1291 1292 return IRQ_HANDLED; 1293 } 1294 1295 static void rcar_canfd_handle_global_receive(struct rcar_canfd_global *gpriv, u32 ch) 1296 { 1297 struct rcar_canfd_channel *priv = gpriv->ch[ch]; 1298 u32 ridx = ch + RCANFD_RFFIFO_IDX; 1299 u32 sts, cc; 1300 1301 /* Handle Rx interrupts */ 1302 sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(gpriv, ridx)); 1303 cc = rcar_canfd_read(priv->base, RCANFD_RFCC(gpriv, ridx)); 1304 if (likely(sts & RCANFD_RFSTS_RFIF && 1305 cc & RCANFD_RFCC_RFIE)) { 1306 if (napi_schedule_prep(&priv->napi)) { 1307 /* Disable Rx FIFO interrupts */ 1308 rcar_canfd_clear_bit(priv->base, 1309 RCANFD_RFCC(gpriv, ridx), 1310 RCANFD_RFCC_RFIE); 1311 __napi_schedule(&priv->napi); 1312 } 1313 } 1314 } 1315 1316 static irqreturn_t rcar_canfd_global_receive_fifo_interrupt(int irq, void *dev_id) 1317 { 1318 struct rcar_canfd_global *gpriv = dev_id; 1319 u32 ch; 1320 1321 for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) 1322 rcar_canfd_handle_global_receive(gpriv, ch); 1323 1324 return IRQ_HANDLED; 1325 } 1326 1327 static irqreturn_t rcar_canfd_global_interrupt(int irq, void *dev_id) 1328 { 1329 struct rcar_canfd_global *gpriv = dev_id; 1330 u32 ch; 1331 1332 /* Global error interrupts still indicate a condition specific 1333 * to a channel. RxFIFO interrupt is a global interrupt. 1334 */ 1335 for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) { 1336 rcar_canfd_handle_global_err(gpriv, ch); 1337 rcar_canfd_handle_global_receive(gpriv, ch); 1338 } 1339 return IRQ_HANDLED; 1340 } 1341 1342 static void rcar_canfd_state_change(struct net_device *ndev, 1343 u16 txerr, u16 rxerr) 1344 { 1345 struct rcar_canfd_channel *priv = netdev_priv(ndev); 1346 struct net_device_stats *stats = &ndev->stats; 1347 enum can_state rx_state, tx_state, state = priv->can.state; 1348 struct can_frame *cf; 1349 struct sk_buff *skb; 1350 1351 /* Handle transition from error to normal states */ 1352 if (txerr < 96 && rxerr < 96) 1353 state = CAN_STATE_ERROR_ACTIVE; 1354 else if (txerr < 128 && rxerr < 128) 1355 state = CAN_STATE_ERROR_WARNING; 1356 1357 if (state != priv->can.state) { 1358 netdev_dbg(ndev, "state: new %d, old %d: txerr %u, rxerr %u\n", 1359 state, priv->can.state, txerr, rxerr); 1360 skb = alloc_can_err_skb(ndev, &cf); 1361 if (!skb) { 1362 stats->rx_dropped++; 1363 return; 1364 } 1365 tx_state = txerr >= rxerr ? state : 0; 1366 rx_state = txerr <= rxerr ? state : 0; 1367 1368 can_change_state(ndev, cf, tx_state, rx_state); 1369 netif_rx(skb); 1370 } 1371 } 1372 1373 static void rcar_canfd_handle_channel_tx(struct rcar_canfd_global *gpriv, u32 ch) 1374 { 1375 struct rcar_canfd_channel *priv = gpriv->ch[ch]; 1376 struct net_device *ndev = priv->ndev; 1377 u32 sts; 1378 1379 /* Handle Tx interrupts */ 1380 sts = rcar_canfd_read(priv->base, 1381 RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX)); 1382 if (likely(sts & RCANFD_CFSTS_CFTXIF)) 1383 rcar_canfd_tx_done(ndev); 1384 } 1385 1386 static irqreturn_t rcar_canfd_channel_tx_interrupt(int irq, void *dev_id) 1387 { 1388 struct rcar_canfd_channel *priv = dev_id; 1389 1390 rcar_canfd_handle_channel_tx(priv->gpriv, priv->channel); 1391 1392 return IRQ_HANDLED; 1393 } 1394 1395 static void rcar_canfd_handle_channel_err(struct rcar_canfd_global *gpriv, u32 ch) 1396 { 1397 struct rcar_canfd_channel *priv = gpriv->ch[ch]; 1398 struct net_device *ndev = priv->ndev; 1399 u16 txerr, rxerr; 1400 u32 sts, cerfl; 1401 1402 /* Handle channel error interrupts */ 1403 cerfl = rcar_canfd_read(priv->base, RCANFD_CERFL(ch)); 1404 sts = rcar_canfd_read(priv->base, RCANFD_CSTS(ch)); 1405 txerr = RCANFD_CSTS_TECCNT(sts); 1406 rxerr = RCANFD_CSTS_RECCNT(sts); 1407 if (unlikely(RCANFD_CERFL_ERR(cerfl))) 1408 rcar_canfd_error(ndev, cerfl, txerr, rxerr); 1409 1410 /* Handle state change to lower states */ 1411 if (unlikely(priv->can.state != CAN_STATE_ERROR_ACTIVE && 1412 priv->can.state != CAN_STATE_BUS_OFF)) 1413 rcar_canfd_state_change(ndev, txerr, rxerr); 1414 } 1415 1416 static irqreturn_t rcar_canfd_channel_err_interrupt(int irq, void *dev_id) 1417 { 1418 struct rcar_canfd_channel *priv = dev_id; 1419 1420 rcar_canfd_handle_channel_err(priv->gpriv, priv->channel); 1421 1422 return IRQ_HANDLED; 1423 } 1424 1425 static irqreturn_t rcar_canfd_channel_interrupt(int irq, void *dev_id) 1426 { 1427 struct rcar_canfd_global *gpriv = dev_id; 1428 u32 ch; 1429 1430 /* Common FIFO is a per channel resource */ 1431 for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) { 1432 rcar_canfd_handle_channel_err(gpriv, ch); 1433 rcar_canfd_handle_channel_tx(gpriv, ch); 1434 } 1435 1436 return IRQ_HANDLED; 1437 } 1438 1439 static void rcar_canfd_set_bittiming(struct net_device *dev) 1440 { 1441 struct rcar_canfd_channel *priv = netdev_priv(dev); 1442 struct rcar_canfd_global *gpriv = priv->gpriv; 1443 const struct can_bittiming *bt = &priv->can.bittiming; 1444 const struct can_bittiming *dbt = &priv->can.fd.data_bittiming; 1445 u16 brp, sjw, tseg1, tseg2; 1446 u32 cfg; 1447 u32 ch = priv->channel; 1448 1449 /* Nominal bit timing settings */ 1450 brp = bt->brp - 1; 1451 sjw = bt->sjw - 1; 1452 tseg1 = bt->prop_seg + bt->phase_seg1 - 1; 1453 tseg2 = bt->phase_seg2 - 1; 1454 1455 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) { 1456 /* CAN FD only mode */ 1457 cfg = (RCANFD_NCFG_NTSEG1(gpriv, tseg1) | RCANFD_NCFG_NBRP(brp) | 1458 RCANFD_NCFG_NSJW(gpriv, sjw) | RCANFD_NCFG_NTSEG2(gpriv, tseg2)); 1459 1460 rcar_canfd_write(priv->base, RCANFD_CCFG(ch), cfg); 1461 netdev_dbg(priv->ndev, "nrate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n", 1462 brp, sjw, tseg1, tseg2); 1463 1464 /* Data bit timing settings */ 1465 brp = dbt->brp - 1; 1466 sjw = dbt->sjw - 1; 1467 tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1; 1468 tseg2 = dbt->phase_seg2 - 1; 1469 1470 cfg = (RCANFD_DCFG_DTSEG1(gpriv, tseg1) | RCANFD_DCFG_DBRP(brp) | 1471 RCANFD_DCFG_DSJW(gpriv, sjw) | RCANFD_DCFG_DTSEG2(gpriv, tseg2)); 1472 1473 rcar_canfd_write(priv->base, RCANFD_F_DCFG(gpriv, ch), cfg); 1474 netdev_dbg(priv->ndev, "drate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n", 1475 brp, sjw, tseg1, tseg2); 1476 } else { 1477 /* Classical CAN only mode */ 1478 if (gpriv->info->shared_can_regs) { 1479 cfg = (RCANFD_NCFG_NTSEG1(gpriv, tseg1) | 1480 RCANFD_NCFG_NBRP(brp) | 1481 RCANFD_NCFG_NSJW(gpriv, sjw) | 1482 RCANFD_NCFG_NTSEG2(gpriv, tseg2)); 1483 } else { 1484 cfg = (RCANFD_CFG_TSEG1(tseg1) | 1485 RCANFD_CFG_BRP(brp) | 1486 RCANFD_CFG_SJW(sjw) | 1487 RCANFD_CFG_TSEG2(tseg2)); 1488 } 1489 1490 rcar_canfd_write(priv->base, RCANFD_CCFG(ch), cfg); 1491 netdev_dbg(priv->ndev, 1492 "rate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n", 1493 brp, sjw, tseg1, tseg2); 1494 } 1495 } 1496 1497 static int rcar_canfd_start(struct net_device *ndev) 1498 { 1499 struct rcar_canfd_channel *priv = netdev_priv(ndev); 1500 struct rcar_canfd_global *gpriv = priv->gpriv; 1501 int err = -EOPNOTSUPP; 1502 u32 sts, ch = priv->channel; 1503 u32 ridx = ch + RCANFD_RFFIFO_IDX; 1504 1505 rcar_canfd_set_bittiming(ndev); 1506 1507 rcar_canfd_enable_channel_interrupts(priv); 1508 1509 /* Set channel to Operational mode */ 1510 rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch), 1511 RCANFD_CCTR_CHMDC_MASK, RCANFD_CCTR_CHDMC_COPM); 1512 1513 /* Verify channel mode change */ 1514 err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts, 1515 (sts & RCANFD_CSTS_COMSTS), 2, 500000); 1516 if (err) { 1517 netdev_err(ndev, "channel %u communication state failed\n", ch); 1518 goto fail_mode_change; 1519 } 1520 1521 /* Enable Common & Rx FIFO */ 1522 rcar_canfd_set_bit(priv->base, RCANFD_CFCC(gpriv, ch, RCANFD_CFFIFO_IDX), 1523 RCANFD_CFCC_CFE); 1524 rcar_canfd_set_bit(priv->base, RCANFD_RFCC(gpriv, ridx), RCANFD_RFCC_RFE); 1525 1526 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1527 return 0; 1528 1529 fail_mode_change: 1530 rcar_canfd_disable_channel_interrupts(priv); 1531 return err; 1532 } 1533 1534 static int rcar_canfd_open(struct net_device *ndev) 1535 { 1536 struct rcar_canfd_channel *priv = netdev_priv(ndev); 1537 struct rcar_canfd_global *gpriv = priv->gpriv; 1538 int err; 1539 1540 err = phy_power_on(priv->transceiver); 1541 if (err) { 1542 netdev_err(ndev, "failed to power on PHY: %pe\n", ERR_PTR(err)); 1543 return err; 1544 } 1545 1546 /* Peripheral clock is already enabled in probe */ 1547 err = clk_prepare_enable(gpriv->can_clk); 1548 if (err) { 1549 netdev_err(ndev, "failed to enable CAN clock: %pe\n", ERR_PTR(err)); 1550 goto out_phy; 1551 } 1552 1553 err = open_candev(ndev); 1554 if (err) { 1555 netdev_err(ndev, "open_candev() failed: %pe\n", ERR_PTR(err)); 1556 goto out_can_clock; 1557 } 1558 1559 napi_enable(&priv->napi); 1560 err = rcar_canfd_start(ndev); 1561 if (err) 1562 goto out_close; 1563 netif_start_queue(ndev); 1564 return 0; 1565 out_close: 1566 napi_disable(&priv->napi); 1567 close_candev(ndev); 1568 out_can_clock: 1569 clk_disable_unprepare(gpriv->can_clk); 1570 out_phy: 1571 phy_power_off(priv->transceiver); 1572 return err; 1573 } 1574 1575 static void rcar_canfd_stop(struct net_device *ndev) 1576 { 1577 struct rcar_canfd_channel *priv = netdev_priv(ndev); 1578 struct rcar_canfd_global *gpriv = priv->gpriv; 1579 int err; 1580 u32 sts, ch = priv->channel; 1581 u32 ridx = ch + RCANFD_RFFIFO_IDX; 1582 1583 /* Transition to channel reset mode */ 1584 rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch), 1585 RCANFD_CCTR_CHMDC_MASK, RCANFD_CCTR_CHDMC_CRESET); 1586 1587 /* Check Channel reset mode */ 1588 err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts, 1589 (sts & RCANFD_CSTS_CRSTSTS), 2, 500000); 1590 if (err) 1591 netdev_err(ndev, "channel %u reset failed\n", ch); 1592 1593 rcar_canfd_disable_channel_interrupts(priv); 1594 1595 /* Disable Common & Rx FIFO */ 1596 rcar_canfd_clear_bit(priv->base, RCANFD_CFCC(gpriv, ch, RCANFD_CFFIFO_IDX), 1597 RCANFD_CFCC_CFE); 1598 rcar_canfd_clear_bit(priv->base, RCANFD_RFCC(gpriv, ridx), RCANFD_RFCC_RFE); 1599 1600 /* Set the state as STOPPED */ 1601 priv->can.state = CAN_STATE_STOPPED; 1602 } 1603 1604 static int rcar_canfd_close(struct net_device *ndev) 1605 { 1606 struct rcar_canfd_channel *priv = netdev_priv(ndev); 1607 struct rcar_canfd_global *gpriv = priv->gpriv; 1608 1609 netif_stop_queue(ndev); 1610 rcar_canfd_stop(ndev); 1611 napi_disable(&priv->napi); 1612 clk_disable_unprepare(gpriv->can_clk); 1613 close_candev(ndev); 1614 phy_power_off(priv->transceiver); 1615 return 0; 1616 } 1617 1618 static netdev_tx_t rcar_canfd_start_xmit(struct sk_buff *skb, 1619 struct net_device *ndev) 1620 { 1621 struct rcar_canfd_channel *priv = netdev_priv(ndev); 1622 struct rcar_canfd_global *gpriv = priv->gpriv; 1623 struct canfd_frame *cf = (struct canfd_frame *)skb->data; 1624 u32 sts = 0, id, dlc; 1625 unsigned long flags; 1626 u32 ch = priv->channel; 1627 1628 if (can_dev_dropped_skb(ndev, skb)) 1629 return NETDEV_TX_OK; 1630 1631 if (cf->can_id & CAN_EFF_FLAG) { 1632 id = cf->can_id & CAN_EFF_MASK; 1633 id |= RCANFD_CFID_CFIDE; 1634 } else { 1635 id = cf->can_id & CAN_SFF_MASK; 1636 } 1637 1638 if (cf->can_id & CAN_RTR_FLAG) 1639 id |= RCANFD_CFID_CFRTR; 1640 1641 dlc = RCANFD_CFPTR_CFDLC(can_fd_len2dlc(cf->len)); 1642 1643 if ((priv->can.ctrlmode & CAN_CTRLMODE_FD) || gpriv->info->shared_can_regs) { 1644 rcar_canfd_write(priv->base, 1645 RCANFD_F_CFID(gpriv, ch, RCANFD_CFFIFO_IDX), id); 1646 rcar_canfd_write(priv->base, 1647 RCANFD_F_CFPTR(gpriv, ch, RCANFD_CFFIFO_IDX), dlc); 1648 1649 if (can_is_canfd_skb(skb)) { 1650 /* CAN FD frame format */ 1651 sts |= RCANFD_CFFDCSTS_CFFDF; 1652 if (cf->flags & CANFD_BRS) 1653 sts |= RCANFD_CFFDCSTS_CFBRS; 1654 1655 if (priv->can.state == CAN_STATE_ERROR_PASSIVE) 1656 sts |= RCANFD_CFFDCSTS_CFESI; 1657 } 1658 1659 rcar_canfd_write(priv->base, 1660 RCANFD_F_CFFDCSTS(gpriv, ch, RCANFD_CFFIFO_IDX), sts); 1661 1662 rcar_canfd_put_data(priv, cf, 1663 RCANFD_F_CFDF(gpriv, ch, RCANFD_CFFIFO_IDX, 0)); 1664 } else { 1665 rcar_canfd_write(priv->base, 1666 RCANFD_C_CFID(ch, RCANFD_CFFIFO_IDX), id); 1667 rcar_canfd_write(priv->base, 1668 RCANFD_C_CFPTR(ch, RCANFD_CFFIFO_IDX), dlc); 1669 rcar_canfd_put_data(priv, cf, 1670 RCANFD_C_CFDF(ch, RCANFD_CFFIFO_IDX, 0)); 1671 } 1672 1673 can_put_echo_skb(skb, ndev, priv->tx_head % RCANFD_FIFO_DEPTH, 0); 1674 1675 spin_lock_irqsave(&priv->tx_lock, flags); 1676 priv->tx_head++; 1677 1678 /* Stop the queue if we've filled all FIFO entries */ 1679 if (priv->tx_head - priv->tx_tail >= RCANFD_FIFO_DEPTH) 1680 netif_stop_queue(ndev); 1681 1682 /* Start Tx: Write 0xff to CFPC to increment the CPU-side 1683 * pointer for the Common FIFO 1684 */ 1685 rcar_canfd_write(priv->base, 1686 RCANFD_CFPCTR(gpriv, ch, RCANFD_CFFIFO_IDX), 0xff); 1687 1688 spin_unlock_irqrestore(&priv->tx_lock, flags); 1689 return NETDEV_TX_OK; 1690 } 1691 1692 static void rcar_canfd_rx_pkt(struct rcar_canfd_channel *priv) 1693 { 1694 struct net_device_stats *stats = &priv->ndev->stats; 1695 struct rcar_canfd_global *gpriv = priv->gpriv; 1696 struct canfd_frame *cf; 1697 struct sk_buff *skb; 1698 u32 sts = 0, id, dlc; 1699 u32 ch = priv->channel; 1700 u32 ridx = ch + RCANFD_RFFIFO_IDX; 1701 1702 if ((priv->can.ctrlmode & CAN_CTRLMODE_FD) || gpriv->info->shared_can_regs) { 1703 id = rcar_canfd_read(priv->base, RCANFD_F_RFID(gpriv, ridx)); 1704 dlc = rcar_canfd_read(priv->base, RCANFD_F_RFPTR(gpriv, ridx)); 1705 1706 sts = rcar_canfd_read(priv->base, RCANFD_F_RFFDSTS(gpriv, ridx)); 1707 1708 if ((priv->can.ctrlmode & CAN_CTRLMODE_FD) && 1709 sts & RCANFD_RFFDSTS_RFFDF) 1710 skb = alloc_canfd_skb(priv->ndev, &cf); 1711 else 1712 skb = alloc_can_skb(priv->ndev, 1713 (struct can_frame **)&cf); 1714 } else { 1715 id = rcar_canfd_read(priv->base, RCANFD_C_RFID(ridx)); 1716 dlc = rcar_canfd_read(priv->base, RCANFD_C_RFPTR(ridx)); 1717 skb = alloc_can_skb(priv->ndev, (struct can_frame **)&cf); 1718 } 1719 1720 if (!skb) { 1721 stats->rx_dropped++; 1722 return; 1723 } 1724 1725 if (id & RCANFD_RFID_RFIDE) 1726 cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG; 1727 else 1728 cf->can_id = id & CAN_SFF_MASK; 1729 1730 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) { 1731 if (sts & RCANFD_RFFDSTS_RFFDF) 1732 cf->len = can_fd_dlc2len(RCANFD_RFPTR_RFDLC(dlc)); 1733 else 1734 cf->len = can_cc_dlc2len(RCANFD_RFPTR_RFDLC(dlc)); 1735 1736 if (sts & RCANFD_RFFDSTS_RFESI) { 1737 cf->flags |= CANFD_ESI; 1738 netdev_dbg(priv->ndev, "ESI Error\n"); 1739 } 1740 1741 if (!(sts & RCANFD_RFFDSTS_RFFDF) && (id & RCANFD_RFID_RFRTR)) { 1742 cf->can_id |= CAN_RTR_FLAG; 1743 } else { 1744 if (sts & RCANFD_RFFDSTS_RFBRS) 1745 cf->flags |= CANFD_BRS; 1746 1747 rcar_canfd_get_data(priv, cf, RCANFD_F_RFDF(gpriv, ridx, 0)); 1748 } 1749 } else { 1750 cf->len = can_cc_dlc2len(RCANFD_RFPTR_RFDLC(dlc)); 1751 if (id & RCANFD_RFID_RFRTR) 1752 cf->can_id |= CAN_RTR_FLAG; 1753 else if (gpriv->info->shared_can_regs) 1754 rcar_canfd_get_data(priv, cf, RCANFD_F_RFDF(gpriv, ridx, 0)); 1755 else 1756 rcar_canfd_get_data(priv, cf, RCANFD_C_RFDF(ridx, 0)); 1757 } 1758 1759 /* Write 0xff to RFPC to increment the CPU-side 1760 * pointer of the Rx FIFO 1761 */ 1762 rcar_canfd_write(priv->base, RCANFD_RFPCTR(gpriv, ridx), 0xff); 1763 1764 if (!(cf->can_id & CAN_RTR_FLAG)) 1765 stats->rx_bytes += cf->len; 1766 stats->rx_packets++; 1767 netif_receive_skb(skb); 1768 } 1769 1770 static int rcar_canfd_rx_poll(struct napi_struct *napi, int quota) 1771 { 1772 struct rcar_canfd_channel *priv = 1773 container_of(napi, struct rcar_canfd_channel, napi); 1774 struct rcar_canfd_global *gpriv = priv->gpriv; 1775 int num_pkts; 1776 u32 sts; 1777 u32 ch = priv->channel; 1778 u32 ridx = ch + RCANFD_RFFIFO_IDX; 1779 1780 for (num_pkts = 0; num_pkts < quota; num_pkts++) { 1781 sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(gpriv, ridx)); 1782 /* Check FIFO empty condition */ 1783 if (sts & RCANFD_RFSTS_RFEMP) 1784 break; 1785 1786 rcar_canfd_rx_pkt(priv); 1787 1788 /* Clear interrupt bit */ 1789 if (sts & RCANFD_RFSTS_RFIF) 1790 rcar_canfd_write(priv->base, RCANFD_RFSTS(gpriv, ridx), 1791 sts & ~RCANFD_RFSTS_RFIF); 1792 } 1793 1794 /* All packets processed */ 1795 if (num_pkts < quota) { 1796 if (napi_complete_done(napi, num_pkts)) { 1797 /* Enable Rx FIFO interrupts */ 1798 rcar_canfd_set_bit(priv->base, RCANFD_RFCC(gpriv, ridx), 1799 RCANFD_RFCC_RFIE); 1800 } 1801 } 1802 return num_pkts; 1803 } 1804 1805 static int rcar_canfd_do_set_mode(struct net_device *ndev, enum can_mode mode) 1806 { 1807 int err; 1808 1809 switch (mode) { 1810 case CAN_MODE_START: 1811 err = rcar_canfd_start(ndev); 1812 if (err) 1813 return err; 1814 netif_wake_queue(ndev); 1815 return 0; 1816 default: 1817 return -EOPNOTSUPP; 1818 } 1819 } 1820 1821 static int rcar_canfd_get_berr_counter(const struct net_device *dev, 1822 struct can_berr_counter *bec) 1823 { 1824 struct rcar_canfd_channel *priv = netdev_priv(dev); 1825 u32 val, ch = priv->channel; 1826 1827 /* Peripheral clock is already enabled in probe */ 1828 val = rcar_canfd_read(priv->base, RCANFD_CSTS(ch)); 1829 bec->txerr = RCANFD_CSTS_TECCNT(val); 1830 bec->rxerr = RCANFD_CSTS_RECCNT(val); 1831 return 0; 1832 } 1833 1834 static const struct net_device_ops rcar_canfd_netdev_ops = { 1835 .ndo_open = rcar_canfd_open, 1836 .ndo_stop = rcar_canfd_close, 1837 .ndo_start_xmit = rcar_canfd_start_xmit, 1838 .ndo_change_mtu = can_change_mtu, 1839 }; 1840 1841 static const struct ethtool_ops rcar_canfd_ethtool_ops = { 1842 .get_ts_info = ethtool_op_get_ts_info, 1843 }; 1844 1845 static int rcar_canfd_channel_probe(struct rcar_canfd_global *gpriv, u32 ch, 1846 u32 fcan_freq, struct phy *transceiver) 1847 { 1848 const struct rcar_canfd_hw_info *info = gpriv->info; 1849 struct platform_device *pdev = gpriv->pdev; 1850 struct device *dev = &pdev->dev; 1851 struct rcar_canfd_channel *priv; 1852 struct net_device *ndev; 1853 int err = -ENODEV; 1854 1855 ndev = alloc_candev(sizeof(*priv), RCANFD_FIFO_DEPTH); 1856 if (!ndev) 1857 return -ENOMEM; 1858 1859 priv = netdev_priv(ndev); 1860 1861 ndev->netdev_ops = &rcar_canfd_netdev_ops; 1862 ndev->ethtool_ops = &rcar_canfd_ethtool_ops; 1863 ndev->flags |= IFF_ECHO; 1864 priv->ndev = ndev; 1865 priv->base = gpriv->base; 1866 priv->transceiver = transceiver; 1867 priv->channel = ch; 1868 priv->gpriv = gpriv; 1869 if (transceiver) 1870 priv->can.bitrate_max = transceiver->attrs.max_link_rate; 1871 priv->can.clock.freq = fcan_freq; 1872 dev_info(dev, "can_clk rate is %u\n", priv->can.clock.freq); 1873 1874 if (info->multi_channel_irqs) { 1875 char *irq_name; 1876 char name[10]; 1877 int err_irq; 1878 int tx_irq; 1879 1880 scnprintf(name, sizeof(name), "ch%u_err", ch); 1881 err_irq = platform_get_irq_byname(pdev, name); 1882 if (err_irq < 0) { 1883 err = err_irq; 1884 goto fail; 1885 } 1886 1887 scnprintf(name, sizeof(name), "ch%u_trx", ch); 1888 tx_irq = platform_get_irq_byname(pdev, name); 1889 if (tx_irq < 0) { 1890 err = tx_irq; 1891 goto fail; 1892 } 1893 1894 irq_name = devm_kasprintf(dev, GFP_KERNEL, "canfd.ch%d_err", 1895 ch); 1896 if (!irq_name) { 1897 err = -ENOMEM; 1898 goto fail; 1899 } 1900 err = devm_request_irq(dev, err_irq, 1901 rcar_canfd_channel_err_interrupt, 0, 1902 irq_name, priv); 1903 if (err) { 1904 dev_err(dev, "devm_request_irq CH Err %d failed: %pe\n", 1905 err_irq, ERR_PTR(err)); 1906 goto fail; 1907 } 1908 irq_name = devm_kasprintf(dev, GFP_KERNEL, "canfd.ch%d_trx", 1909 ch); 1910 if (!irq_name) { 1911 err = -ENOMEM; 1912 goto fail; 1913 } 1914 err = devm_request_irq(dev, tx_irq, 1915 rcar_canfd_channel_tx_interrupt, 0, 1916 irq_name, priv); 1917 if (err) { 1918 dev_err(dev, "devm_request_irq Tx %d failed: %pe\n", 1919 tx_irq, ERR_PTR(err)); 1920 goto fail; 1921 } 1922 } 1923 1924 if (gpriv->fdmode) { 1925 priv->can.bittiming_const = gpriv->info->nom_bittiming; 1926 priv->can.fd.data_bittiming_const = gpriv->info->data_bittiming; 1927 1928 /* Controller starts in CAN FD only mode */ 1929 err = can_set_static_ctrlmode(ndev, CAN_CTRLMODE_FD); 1930 if (err) 1931 goto fail; 1932 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING; 1933 } else { 1934 /* Controller starts in Classical CAN only mode */ 1935 priv->can.bittiming_const = &rcar_canfd_bittiming_const; 1936 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING; 1937 } 1938 1939 priv->can.do_set_mode = rcar_canfd_do_set_mode; 1940 priv->can.do_get_berr_counter = rcar_canfd_get_berr_counter; 1941 SET_NETDEV_DEV(ndev, dev); 1942 1943 netif_napi_add_weight(ndev, &priv->napi, rcar_canfd_rx_poll, 1944 RCANFD_NAPI_WEIGHT); 1945 spin_lock_init(&priv->tx_lock); 1946 gpriv->ch[priv->channel] = priv; 1947 err = register_candev(ndev); 1948 if (err) { 1949 dev_err(dev, "register_candev() failed: %pe\n", ERR_PTR(err)); 1950 goto fail_candev; 1951 } 1952 dev_info(dev, "device registered (channel %u)\n", priv->channel); 1953 return 0; 1954 1955 fail_candev: 1956 netif_napi_del(&priv->napi); 1957 fail: 1958 free_candev(ndev); 1959 return err; 1960 } 1961 1962 static void rcar_canfd_channel_remove(struct rcar_canfd_global *gpriv, u32 ch) 1963 { 1964 struct rcar_canfd_channel *priv = gpriv->ch[ch]; 1965 1966 if (priv) { 1967 unregister_candev(priv->ndev); 1968 netif_napi_del(&priv->napi); 1969 free_candev(priv->ndev); 1970 } 1971 } 1972 1973 static int rcar_canfd_probe(struct platform_device *pdev) 1974 { 1975 struct phy *transceivers[RCANFD_NUM_CHANNELS] = { NULL, }; 1976 const struct rcar_canfd_hw_info *info; 1977 struct device *dev = &pdev->dev; 1978 void __iomem *addr; 1979 u32 sts, ch, fcan_freq; 1980 struct rcar_canfd_global *gpriv; 1981 struct device_node *of_child; 1982 unsigned long channels_mask = 0; 1983 int err, ch_irq, g_irq; 1984 int g_err_irq, g_recc_irq; 1985 u32 rule_entry = 0; 1986 bool fdmode = true; /* CAN FD only mode - default */ 1987 char name[9] = "channelX"; 1988 struct clk *clk_ram; 1989 int i; 1990 1991 info = of_device_get_match_data(dev); 1992 1993 if (of_property_read_bool(dev->of_node, "renesas,no-can-fd")) 1994 fdmode = false; /* Classical CAN only mode */ 1995 1996 for (i = 0; i < info->max_channels; ++i) { 1997 name[7] = '0' + i; 1998 of_child = of_get_available_child_by_name(dev->of_node, name); 1999 if (of_child) { 2000 channels_mask |= BIT(i); 2001 transceivers[i] = devm_of_phy_optional_get(dev, 2002 of_child, NULL); 2003 of_node_put(of_child); 2004 } 2005 if (IS_ERR(transceivers[i])) 2006 return PTR_ERR(transceivers[i]); 2007 } 2008 2009 if (info->shared_global_irqs) { 2010 ch_irq = platform_get_irq_byname_optional(pdev, "ch_int"); 2011 if (ch_irq < 0) { 2012 /* For backward compatibility get irq by index */ 2013 ch_irq = platform_get_irq(pdev, 0); 2014 if (ch_irq < 0) 2015 return ch_irq; 2016 } 2017 2018 g_irq = platform_get_irq_byname_optional(pdev, "g_int"); 2019 if (g_irq < 0) { 2020 /* For backward compatibility get irq by index */ 2021 g_irq = platform_get_irq(pdev, 1); 2022 if (g_irq < 0) 2023 return g_irq; 2024 } 2025 } else { 2026 g_err_irq = platform_get_irq_byname(pdev, "g_err"); 2027 if (g_err_irq < 0) 2028 return g_err_irq; 2029 2030 g_recc_irq = platform_get_irq_byname(pdev, "g_recc"); 2031 if (g_recc_irq < 0) 2032 return g_recc_irq; 2033 } 2034 2035 /* Global controller context */ 2036 gpriv = devm_kzalloc(dev, sizeof(*gpriv), GFP_KERNEL); 2037 if (!gpriv) 2038 return -ENOMEM; 2039 2040 gpriv->pdev = pdev; 2041 gpriv->channels_mask = channels_mask; 2042 gpriv->fdmode = fdmode; 2043 gpriv->info = info; 2044 2045 gpriv->rstc1 = devm_reset_control_get_optional_exclusive(dev, "rstp_n"); 2046 if (IS_ERR(gpriv->rstc1)) 2047 return dev_err_probe(dev, PTR_ERR(gpriv->rstc1), 2048 "failed to get rstp_n\n"); 2049 2050 gpriv->rstc2 = devm_reset_control_get_optional_exclusive(dev, "rstc_n"); 2051 if (IS_ERR(gpriv->rstc2)) 2052 return dev_err_probe(dev, PTR_ERR(gpriv->rstc2), 2053 "failed to get rstc_n\n"); 2054 2055 /* Peripheral clock */ 2056 gpriv->clkp = devm_clk_get(dev, "fck"); 2057 if (IS_ERR(gpriv->clkp)) 2058 return dev_err_probe(dev, PTR_ERR(gpriv->clkp), 2059 "cannot get peripheral clock\n"); 2060 2061 /* fCAN clock: Pick External clock. If not available fallback to 2062 * CANFD clock 2063 */ 2064 gpriv->can_clk = devm_clk_get(dev, "can_clk"); 2065 if (IS_ERR(gpriv->can_clk) || (clk_get_rate(gpriv->can_clk) == 0)) { 2066 gpriv->can_clk = devm_clk_get(dev, "canfd"); 2067 if (IS_ERR(gpriv->can_clk)) 2068 return dev_err_probe(dev, PTR_ERR(gpriv->can_clk), 2069 "cannot get canfd clock\n"); 2070 2071 /* CANFD clock may be further divided within the IP */ 2072 fcan_freq = clk_get_rate(gpriv->can_clk) / info->postdiv; 2073 } else { 2074 fcan_freq = clk_get_rate(gpriv->can_clk); 2075 gpriv->extclk = gpriv->info->external_clk; 2076 } 2077 2078 clk_ram = devm_clk_get_optional_enabled(dev, "ram_clk"); 2079 if (IS_ERR(clk_ram)) 2080 return dev_err_probe(dev, PTR_ERR(clk_ram), 2081 "cannot get enabled ram clock\n"); 2082 2083 addr = devm_platform_ioremap_resource(pdev, 0); 2084 if (IS_ERR(addr)) { 2085 err = PTR_ERR(addr); 2086 goto fail_dev; 2087 } 2088 gpriv->base = addr; 2089 2090 /* Request IRQ that's common for both channels */ 2091 if (info->shared_global_irqs) { 2092 err = devm_request_irq(dev, ch_irq, 2093 rcar_canfd_channel_interrupt, 0, 2094 "canfd.ch_int", gpriv); 2095 if (err) { 2096 dev_err(dev, "devm_request_irq %d failed: %pe\n", 2097 ch_irq, ERR_PTR(err)); 2098 goto fail_dev; 2099 } 2100 2101 err = devm_request_irq(dev, g_irq, rcar_canfd_global_interrupt, 2102 0, "canfd.g_int", gpriv); 2103 if (err) { 2104 dev_err(dev, "devm_request_irq %d failed: %pe\n", 2105 g_irq, ERR_PTR(err)); 2106 goto fail_dev; 2107 } 2108 } else { 2109 err = devm_request_irq(dev, g_recc_irq, 2110 rcar_canfd_global_receive_fifo_interrupt, 0, 2111 "canfd.g_recc", gpriv); 2112 2113 if (err) { 2114 dev_err(dev, "devm_request_irq %d failed: %pe\n", 2115 g_recc_irq, ERR_PTR(err)); 2116 goto fail_dev; 2117 } 2118 2119 err = devm_request_irq(dev, g_err_irq, 2120 rcar_canfd_global_err_interrupt, 0, 2121 "canfd.g_err", gpriv); 2122 if (err) { 2123 dev_err(dev, "devm_request_irq %d failed: %pe\n", 2124 g_err_irq, ERR_PTR(err)); 2125 goto fail_dev; 2126 } 2127 } 2128 2129 err = reset_control_reset(gpriv->rstc1); 2130 if (err) 2131 goto fail_dev; 2132 err = reset_control_reset(gpriv->rstc2); 2133 if (err) { 2134 reset_control_assert(gpriv->rstc1); 2135 goto fail_dev; 2136 } 2137 2138 /* Enable peripheral clock for register access */ 2139 err = clk_prepare_enable(gpriv->clkp); 2140 if (err) { 2141 dev_err(dev, "failed to enable peripheral clock: %pe\n", 2142 ERR_PTR(err)); 2143 goto fail_reset; 2144 } 2145 2146 err = rcar_canfd_reset_controller(gpriv); 2147 if (err) { 2148 dev_err(dev, "reset controller failed: %pe\n", ERR_PTR(err)); 2149 goto fail_clk; 2150 } 2151 2152 /* Controller in Global reset & Channel reset mode */ 2153 rcar_canfd_configure_controller(gpriv); 2154 2155 /* Configure per channel attributes */ 2156 for_each_set_bit(ch, &gpriv->channels_mask, info->max_channels) { 2157 /* Configure Channel's Rx fifo */ 2158 rcar_canfd_configure_rx(gpriv, ch); 2159 2160 /* Configure Channel's Tx (Common) fifo */ 2161 rcar_canfd_configure_tx(gpriv, ch); 2162 2163 /* Configure receive rules */ 2164 rcar_canfd_configure_afl_rules(gpriv, ch, rule_entry); 2165 rule_entry += RCANFD_CHANNEL_NUMRULES; 2166 } 2167 2168 /* Configure common interrupts */ 2169 rcar_canfd_enable_global_interrupts(gpriv); 2170 2171 /* Start Global operation mode */ 2172 rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GMDC_MASK, 2173 RCANFD_GCTR_GMDC_GOPM); 2174 2175 /* Verify mode change */ 2176 err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts, 2177 !(sts & RCANFD_GSTS_GNOPM), 2, 500000); 2178 if (err) { 2179 dev_err(dev, "global operational mode failed\n"); 2180 goto fail_mode; 2181 } 2182 2183 for_each_set_bit(ch, &gpriv->channels_mask, info->max_channels) { 2184 err = rcar_canfd_channel_probe(gpriv, ch, fcan_freq, 2185 transceivers[ch]); 2186 if (err) 2187 goto fail_channel; 2188 } 2189 2190 platform_set_drvdata(pdev, gpriv); 2191 dev_info(dev, "global operational state (%s clk, %s mode)\n", 2192 gpriv->extclk ? "ext" : "canfd", 2193 gpriv->fdmode ? "fd" : "classical"); 2194 return 0; 2195 2196 fail_channel: 2197 for_each_set_bit(ch, &gpriv->channels_mask, info->max_channels) 2198 rcar_canfd_channel_remove(gpriv, ch); 2199 fail_mode: 2200 rcar_canfd_disable_global_interrupts(gpriv); 2201 fail_clk: 2202 clk_disable_unprepare(gpriv->clkp); 2203 fail_reset: 2204 reset_control_assert(gpriv->rstc1); 2205 reset_control_assert(gpriv->rstc2); 2206 fail_dev: 2207 return err; 2208 } 2209 2210 static void rcar_canfd_remove(struct platform_device *pdev) 2211 { 2212 struct rcar_canfd_global *gpriv = platform_get_drvdata(pdev); 2213 u32 ch; 2214 2215 rcar_canfd_reset_controller(gpriv); 2216 rcar_canfd_disable_global_interrupts(gpriv); 2217 2218 for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) { 2219 rcar_canfd_disable_channel_interrupts(gpriv->ch[ch]); 2220 rcar_canfd_channel_remove(gpriv, ch); 2221 } 2222 2223 /* Enter global sleep mode */ 2224 rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR); 2225 clk_disable_unprepare(gpriv->clkp); 2226 reset_control_assert(gpriv->rstc1); 2227 reset_control_assert(gpriv->rstc2); 2228 } 2229 2230 static int __maybe_unused rcar_canfd_suspend(struct device *dev) 2231 { 2232 return 0; 2233 } 2234 2235 static int __maybe_unused rcar_canfd_resume(struct device *dev) 2236 { 2237 return 0; 2238 } 2239 2240 static SIMPLE_DEV_PM_OPS(rcar_canfd_pm_ops, rcar_canfd_suspend, 2241 rcar_canfd_resume); 2242 2243 static const __maybe_unused struct of_device_id rcar_canfd_of_table[] = { 2244 { .compatible = "renesas,r8a779a0-canfd", .data = &rcar_gen4_hw_info }, 2245 { .compatible = "renesas,r9a09g047-canfd", .data = &r9a09g047_hw_info }, 2246 { .compatible = "renesas,rcar-gen3-canfd", .data = &rcar_gen3_hw_info }, 2247 { .compatible = "renesas,rcar-gen4-canfd", .data = &rcar_gen4_hw_info }, 2248 { .compatible = "renesas,rzg2l-canfd", .data = &rzg2l_hw_info }, 2249 { } 2250 }; 2251 2252 MODULE_DEVICE_TABLE(of, rcar_canfd_of_table); 2253 2254 static struct platform_driver rcar_canfd_driver = { 2255 .driver = { 2256 .name = RCANFD_DRV_NAME, 2257 .of_match_table = of_match_ptr(rcar_canfd_of_table), 2258 .pm = &rcar_canfd_pm_ops, 2259 }, 2260 .probe = rcar_canfd_probe, 2261 .remove = rcar_canfd_remove, 2262 }; 2263 2264 module_platform_driver(rcar_canfd_driver); 2265 2266 MODULE_AUTHOR("Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>"); 2267 MODULE_LICENSE("GPL"); 2268 MODULE_DESCRIPTION("CAN FD driver for Renesas R-Car SoC"); 2269 MODULE_ALIAS("platform:" RCANFD_DRV_NAME); 2270