1 /* 2 * Copyright (C) 2007, 2011 Wolfgang Grandegger <wg@grandegger.com> 3 * Copyright (C) 2012 Stephane Grosjean <s.grosjean@peak-system.com> 4 * 5 * Derived from the PCAN project file driver/src/pcan_pci.c: 6 * 7 * Copyright (C) 2001-2006 PEAK System-Technik GmbH 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the version 2 of the GNU General Public License 11 * as published by the Free Software Foundation 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/interrupt.h> 22 #include <linux/netdevice.h> 23 #include <linux/delay.h> 24 #include <linux/pci.h> 25 #include <linux/io.h> 26 #include <linux/can.h> 27 #include <linux/can/dev.h> 28 29 #include "peak_canfd_user.h" 30 31 MODULE_AUTHOR("Stephane Grosjean <s.grosjean@peak-system.com>"); 32 MODULE_DESCRIPTION("Socket-CAN driver for PEAK PCAN PCIe/M.2 FD family cards"); 33 MODULE_SUPPORTED_DEVICE("PEAK PCAN PCIe/M.2 FD CAN cards"); 34 MODULE_LICENSE("GPL v2"); 35 36 #define PCIEFD_DRV_NAME "peak_pciefd" 37 38 #define PEAK_PCI_VENDOR_ID 0x001c /* The PCI device and vendor IDs */ 39 #define PEAK_PCIEFD_ID 0x0013 /* for PCIe slot cards */ 40 #define PCAN_CPCIEFD_ID 0x0014 /* for Compact-PCI Serial slot cards */ 41 #define PCAN_PCIE104FD_ID 0x0017 /* for PCIe-104 Express slot cards */ 42 #define PCAN_MINIPCIEFD_ID 0x0018 /* for mini-PCIe slot cards */ 43 #define PCAN_PCIEFD_OEM_ID 0x0019 /* for PCIe slot OEM cards */ 44 #define PCAN_M2_ID 0x001a /* for M2 slot cards */ 45 46 /* PEAK PCIe board access description */ 47 #define PCIEFD_BAR0_SIZE (64 * 1024) 48 #define PCIEFD_RX_DMA_SIZE (4 * 1024) 49 #define PCIEFD_TX_DMA_SIZE (4 * 1024) 50 51 #define PCIEFD_TX_PAGE_SIZE (2 * 1024) 52 53 /* System Control Registers */ 54 #define PCIEFD_REG_SYS_CTL_SET 0x0000 /* set bits */ 55 #define PCIEFD_REG_SYS_CTL_CLR 0x0004 /* clear bits */ 56 57 /* Version info registers */ 58 #define PCIEFD_REG_SYS_VER1 0x0040 /* version reg #1 */ 59 #define PCIEFD_REG_SYS_VER2 0x0044 /* version reg #2 */ 60 61 #define PCIEFD_FW_VERSION(x, y, z) (((u32)(x) << 24) | \ 62 ((u32)(y) << 16) | \ 63 ((u32)(z) << 8)) 64 65 /* System Control Registers Bits */ 66 #define PCIEFD_SYS_CTL_TS_RST 0x00000001 /* timestamp clock */ 67 #define PCIEFD_SYS_CTL_CLK_EN 0x00000002 /* system clock */ 68 69 /* CAN-FD channel addresses */ 70 #define PCIEFD_CANX_OFF(c) (((c) + 1) * 0x1000) 71 72 #define PCIEFD_ECHO_SKB_MAX PCANFD_ECHO_SKB_DEF 73 74 /* CAN-FD channel registers */ 75 #define PCIEFD_REG_CAN_MISC 0x0000 /* Misc. control */ 76 #define PCIEFD_REG_CAN_CLK_SEL 0x0008 /* Clock selector */ 77 #define PCIEFD_REG_CAN_CMD_PORT_L 0x0010 /* 64-bits command port */ 78 #define PCIEFD_REG_CAN_CMD_PORT_H 0x0014 79 #define PCIEFD_REG_CAN_TX_REQ_ACC 0x0020 /* Tx request accumulator */ 80 #define PCIEFD_REG_CAN_TX_CTL_SET 0x0030 /* Tx control set register */ 81 #define PCIEFD_REG_CAN_TX_CTL_CLR 0x0038 /* Tx control clear register */ 82 #define PCIEFD_REG_CAN_TX_DMA_ADDR_L 0x0040 /* 64-bits addr for Tx DMA */ 83 #define PCIEFD_REG_CAN_TX_DMA_ADDR_H 0x0044 84 #define PCIEFD_REG_CAN_RX_CTL_SET 0x0050 /* Rx control set register */ 85 #define PCIEFD_REG_CAN_RX_CTL_CLR 0x0058 /* Rx control clear register */ 86 #define PCIEFD_REG_CAN_RX_CTL_WRT 0x0060 /* Rx control write register */ 87 #define PCIEFD_REG_CAN_RX_CTL_ACK 0x0068 /* Rx control ACK register */ 88 #define PCIEFD_REG_CAN_RX_DMA_ADDR_L 0x0070 /* 64-bits addr for Rx DMA */ 89 #define PCIEFD_REG_CAN_RX_DMA_ADDR_H 0x0074 90 91 /* CAN-FD channel misc register bits */ 92 #define CANFD_MISC_TS_RST 0x00000001 /* timestamp cnt rst */ 93 94 /* CAN-FD channel Clock SELector Source & DIVider */ 95 #define CANFD_CLK_SEL_DIV_MASK 0x00000007 96 #define CANFD_CLK_SEL_DIV_60MHZ 0x00000000 /* SRC=240MHz only */ 97 #define CANFD_CLK_SEL_DIV_40MHZ 0x00000001 /* SRC=240MHz only */ 98 #define CANFD_CLK_SEL_DIV_30MHZ 0x00000002 /* SRC=240MHz only */ 99 #define CANFD_CLK_SEL_DIV_24MHZ 0x00000003 /* SRC=240MHz only */ 100 #define CANFD_CLK_SEL_DIV_20MHZ 0x00000004 /* SRC=240MHz only */ 101 102 #define CANFD_CLK_SEL_SRC_MASK 0x00000008 /* 0=80MHz, 1=240MHz */ 103 #define CANFD_CLK_SEL_SRC_240MHZ 0x00000008 104 #define CANFD_CLK_SEL_SRC_80MHZ (~CANFD_CLK_SEL_SRC_240MHZ & \ 105 CANFD_CLK_SEL_SRC_MASK) 106 107 #define CANFD_CLK_SEL_20MHZ (CANFD_CLK_SEL_SRC_240MHZ |\ 108 CANFD_CLK_SEL_DIV_20MHZ) 109 #define CANFD_CLK_SEL_24MHZ (CANFD_CLK_SEL_SRC_240MHZ |\ 110 CANFD_CLK_SEL_DIV_24MHZ) 111 #define CANFD_CLK_SEL_30MHZ (CANFD_CLK_SEL_SRC_240MHZ |\ 112 CANFD_CLK_SEL_DIV_30MHZ) 113 #define CANFD_CLK_SEL_40MHZ (CANFD_CLK_SEL_SRC_240MHZ |\ 114 CANFD_CLK_SEL_DIV_40MHZ) 115 #define CANFD_CLK_SEL_60MHZ (CANFD_CLK_SEL_SRC_240MHZ |\ 116 CANFD_CLK_SEL_DIV_60MHZ) 117 #define CANFD_CLK_SEL_80MHZ (CANFD_CLK_SEL_SRC_80MHZ) 118 119 /* CAN-FD channel Rx/Tx control register bits */ 120 #define CANFD_CTL_UNC_BIT 0x00010000 /* Uncached DMA mem */ 121 #define CANFD_CTL_RST_BIT 0x00020000 /* reset DMA action */ 122 #define CANFD_CTL_IEN_BIT 0x00040000 /* IRQ enable */ 123 124 /* Rx IRQ Count and Time Limits */ 125 #define CANFD_CTL_IRQ_CL_DEF 16 /* Rx msg max nb per IRQ in Rx DMA */ 126 #define CANFD_CTL_IRQ_TL_DEF 10 /* Time before IRQ if < CL (x100 µs) */ 127 128 #define CANFD_OPTIONS_SET (CANFD_OPTION_ERROR | CANFD_OPTION_BUSLOAD) 129 130 /* Tx anticipation window (link logical address should be aligned on 2K 131 * boundary) 132 */ 133 #define PCIEFD_TX_PAGE_COUNT (PCIEFD_TX_DMA_SIZE / PCIEFD_TX_PAGE_SIZE) 134 135 #define CANFD_MSG_LNK_TX 0x1001 /* Tx msgs link */ 136 137 /* 32-bits IRQ status fields, heading Rx DMA area */ 138 static inline int pciefd_irq_tag(u32 irq_status) 139 { 140 return irq_status & 0x0000000f; 141 } 142 143 static inline int pciefd_irq_rx_cnt(u32 irq_status) 144 { 145 return (irq_status & 0x000007f0) >> 4; 146 } 147 148 static inline int pciefd_irq_is_lnk(u32 irq_status) 149 { 150 return irq_status & 0x00010000; 151 } 152 153 /* Rx record */ 154 struct pciefd_rx_dma { 155 __le32 irq_status; 156 __le32 sys_time_low; 157 __le32 sys_time_high; 158 struct pucan_rx_msg msg[0]; 159 } __packed __aligned(4); 160 161 /* Tx Link record */ 162 struct pciefd_tx_link { 163 __le16 size; 164 __le16 type; 165 __le32 laddr_lo; 166 __le32 laddr_hi; 167 } __packed __aligned(4); 168 169 /* Tx page descriptor */ 170 struct pciefd_page { 171 void *vbase; /* page virtual address */ 172 dma_addr_t lbase; /* page logical address */ 173 u32 offset; 174 u32 size; 175 }; 176 177 #define CANFD_IRQ_SET 0x00000001 178 #define CANFD_TX_PATH_SET 0x00000002 179 180 /* CAN-FD channel object */ 181 struct pciefd_board; 182 struct pciefd_can { 183 struct peak_canfd_priv ucan; /* must be the first member */ 184 void __iomem *reg_base; /* channel config base addr */ 185 struct pciefd_board *board; /* reverse link */ 186 187 struct pucan_command pucan_cmd; /* command buffer */ 188 189 dma_addr_t rx_dma_laddr; /* DMA virtual and logical addr */ 190 void *rx_dma_vaddr; /* for Rx and Tx areas */ 191 dma_addr_t tx_dma_laddr; 192 void *tx_dma_vaddr; 193 194 struct pciefd_page tx_pages[PCIEFD_TX_PAGE_COUNT]; 195 u16 tx_pages_free; /* free Tx pages counter */ 196 u16 tx_page_index; /* current page used for Tx */ 197 spinlock_t tx_lock; 198 199 u32 irq_status; 200 u32 irq_tag; /* next irq tag */ 201 }; 202 203 /* PEAK-PCIe FD board object */ 204 struct pciefd_board { 205 void __iomem *reg_base; 206 struct pci_dev *pci_dev; 207 int can_count; 208 spinlock_t cmd_lock; /* 64-bits cmds must be atomic */ 209 struct pciefd_can *can[0]; /* array of network devices */ 210 }; 211 212 /* supported device ids. */ 213 static const struct pci_device_id peak_pciefd_tbl[] = { 214 {PEAK_PCI_VENDOR_ID, PEAK_PCIEFD_ID, PCI_ANY_ID, PCI_ANY_ID,}, 215 {PEAK_PCI_VENDOR_ID, PCAN_CPCIEFD_ID, PCI_ANY_ID, PCI_ANY_ID,}, 216 {PEAK_PCI_VENDOR_ID, PCAN_PCIE104FD_ID, PCI_ANY_ID, PCI_ANY_ID,}, 217 {PEAK_PCI_VENDOR_ID, PCAN_MINIPCIEFD_ID, PCI_ANY_ID, PCI_ANY_ID,}, 218 {PEAK_PCI_VENDOR_ID, PCAN_PCIEFD_OEM_ID, PCI_ANY_ID, PCI_ANY_ID,}, 219 {PEAK_PCI_VENDOR_ID, PCAN_M2_ID, PCI_ANY_ID, PCI_ANY_ID,}, 220 {0,} 221 }; 222 223 MODULE_DEVICE_TABLE(pci, peak_pciefd_tbl); 224 225 /* read a 32 bits value from a SYS block register */ 226 static inline u32 pciefd_sys_readreg(const struct pciefd_board *priv, u16 reg) 227 { 228 return readl(priv->reg_base + reg); 229 } 230 231 /* write a 32 bits value into a SYS block register */ 232 static inline void pciefd_sys_writereg(const struct pciefd_board *priv, 233 u32 val, u16 reg) 234 { 235 writel(val, priv->reg_base + reg); 236 } 237 238 /* read a 32 bits value from CAN-FD block register */ 239 static inline u32 pciefd_can_readreg(const struct pciefd_can *priv, u16 reg) 240 { 241 return readl(priv->reg_base + reg); 242 } 243 244 /* write a 32 bits value into a CAN-FD block register */ 245 static inline void pciefd_can_writereg(const struct pciefd_can *priv, 246 u32 val, u16 reg) 247 { 248 writel(val, priv->reg_base + reg); 249 } 250 251 /* give a channel logical Rx DMA address to the board */ 252 static void pciefd_can_setup_rx_dma(struct pciefd_can *priv) 253 { 254 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 255 const u32 dma_addr_h = (u32)(priv->rx_dma_laddr >> 32); 256 #else 257 const u32 dma_addr_h = 0; 258 #endif 259 260 /* (DMA must be reset for Rx) */ 261 pciefd_can_writereg(priv, CANFD_CTL_RST_BIT, PCIEFD_REG_CAN_RX_CTL_SET); 262 263 /* write the logical address of the Rx DMA area for this channel */ 264 pciefd_can_writereg(priv, (u32)priv->rx_dma_laddr, 265 PCIEFD_REG_CAN_RX_DMA_ADDR_L); 266 pciefd_can_writereg(priv, dma_addr_h, PCIEFD_REG_CAN_RX_DMA_ADDR_H); 267 268 /* also indicates that Rx DMA is cacheable */ 269 pciefd_can_writereg(priv, CANFD_CTL_UNC_BIT, PCIEFD_REG_CAN_RX_CTL_CLR); 270 } 271 272 /* clear channel logical Rx DMA address from the board */ 273 static void pciefd_can_clear_rx_dma(struct pciefd_can *priv) 274 { 275 /* DMA must be reset for Rx */ 276 pciefd_can_writereg(priv, CANFD_CTL_RST_BIT, PCIEFD_REG_CAN_RX_CTL_SET); 277 278 /* clear the logical address of the Rx DMA area for this channel */ 279 pciefd_can_writereg(priv, 0, PCIEFD_REG_CAN_RX_DMA_ADDR_L); 280 pciefd_can_writereg(priv, 0, PCIEFD_REG_CAN_RX_DMA_ADDR_H); 281 } 282 283 /* give a channel logical Tx DMA address to the board */ 284 static void pciefd_can_setup_tx_dma(struct pciefd_can *priv) 285 { 286 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 287 const u32 dma_addr_h = (u32)(priv->tx_dma_laddr >> 32); 288 #else 289 const u32 dma_addr_h = 0; 290 #endif 291 292 /* (DMA must be reset for Tx) */ 293 pciefd_can_writereg(priv, CANFD_CTL_RST_BIT, PCIEFD_REG_CAN_TX_CTL_SET); 294 295 /* write the logical address of the Tx DMA area for this channel */ 296 pciefd_can_writereg(priv, (u32)priv->tx_dma_laddr, 297 PCIEFD_REG_CAN_TX_DMA_ADDR_L); 298 pciefd_can_writereg(priv, dma_addr_h, PCIEFD_REG_CAN_TX_DMA_ADDR_H); 299 300 /* also indicates that Tx DMA is cacheable */ 301 pciefd_can_writereg(priv, CANFD_CTL_UNC_BIT, PCIEFD_REG_CAN_TX_CTL_CLR); 302 } 303 304 /* clear channel logical Tx DMA address from the board */ 305 static void pciefd_can_clear_tx_dma(struct pciefd_can *priv) 306 { 307 /* DMA must be reset for Tx */ 308 pciefd_can_writereg(priv, CANFD_CTL_RST_BIT, PCIEFD_REG_CAN_TX_CTL_SET); 309 310 /* clear the logical address of the Tx DMA area for this channel */ 311 pciefd_can_writereg(priv, 0, PCIEFD_REG_CAN_TX_DMA_ADDR_L); 312 pciefd_can_writereg(priv, 0, PCIEFD_REG_CAN_TX_DMA_ADDR_H); 313 } 314 315 static void pciefd_can_ack_rx_dma(struct pciefd_can *priv) 316 { 317 /* read value of current IRQ tag and inc it for next one */ 318 priv->irq_tag = le32_to_cpu(*(__le32 *)priv->rx_dma_vaddr); 319 priv->irq_tag++; 320 priv->irq_tag &= 0xf; 321 322 /* write the next IRQ tag for this CAN */ 323 pciefd_can_writereg(priv, priv->irq_tag, PCIEFD_REG_CAN_RX_CTL_ACK); 324 } 325 326 /* IRQ handler */ 327 static irqreturn_t pciefd_irq_handler(int irq, void *arg) 328 { 329 struct pciefd_can *priv = arg; 330 struct pciefd_rx_dma *rx_dma = priv->rx_dma_vaddr; 331 332 /* INTA mode only to sync with PCIe transaction */ 333 if (!pci_dev_msi_enabled(priv->board->pci_dev)) 334 (void)pciefd_sys_readreg(priv->board, PCIEFD_REG_SYS_VER1); 335 336 /* read IRQ status from the first 32-bits of the Rx DMA area */ 337 priv->irq_status = le32_to_cpu(rx_dma->irq_status); 338 339 /* check if this (shared) IRQ is for this CAN */ 340 if (pciefd_irq_tag(priv->irq_status) != priv->irq_tag) 341 return IRQ_NONE; 342 343 /* handle rx messages (if any) */ 344 peak_canfd_handle_msgs_list(&priv->ucan, 345 rx_dma->msg, 346 pciefd_irq_rx_cnt(priv->irq_status)); 347 348 /* handle tx link interrupt (if any) */ 349 if (pciefd_irq_is_lnk(priv->irq_status)) { 350 unsigned long flags; 351 352 spin_lock_irqsave(&priv->tx_lock, flags); 353 priv->tx_pages_free++; 354 spin_unlock_irqrestore(&priv->tx_lock, flags); 355 356 /* wake producer up (only if enough room in echo_skb array) */ 357 spin_lock_irqsave(&priv->ucan.echo_lock, flags); 358 if (!priv->ucan.can.echo_skb[priv->ucan.echo_idx]) 359 netif_wake_queue(priv->ucan.ndev); 360 361 spin_unlock_irqrestore(&priv->ucan.echo_lock, flags); 362 } 363 364 /* re-enable Rx DMA transfer for this CAN */ 365 pciefd_can_ack_rx_dma(priv); 366 367 return IRQ_HANDLED; 368 } 369 370 static int pciefd_enable_tx_path(struct peak_canfd_priv *ucan) 371 { 372 struct pciefd_can *priv = (struct pciefd_can *)ucan; 373 int i; 374 375 /* initialize the Tx pages descriptors */ 376 priv->tx_pages_free = PCIEFD_TX_PAGE_COUNT - 1; 377 priv->tx_page_index = 0; 378 379 priv->tx_pages[0].vbase = priv->tx_dma_vaddr; 380 priv->tx_pages[0].lbase = priv->tx_dma_laddr; 381 382 for (i = 0; i < PCIEFD_TX_PAGE_COUNT; i++) { 383 priv->tx_pages[i].offset = 0; 384 priv->tx_pages[i].size = PCIEFD_TX_PAGE_SIZE - 385 sizeof(struct pciefd_tx_link); 386 if (i) { 387 priv->tx_pages[i].vbase = 388 priv->tx_pages[i - 1].vbase + 389 PCIEFD_TX_PAGE_SIZE; 390 priv->tx_pages[i].lbase = 391 priv->tx_pages[i - 1].lbase + 392 PCIEFD_TX_PAGE_SIZE; 393 } 394 } 395 396 /* setup Tx DMA addresses into IP core */ 397 pciefd_can_setup_tx_dma(priv); 398 399 /* start (TX_RST=0) Tx Path */ 400 pciefd_can_writereg(priv, CANFD_CTL_RST_BIT, PCIEFD_REG_CAN_TX_CTL_CLR); 401 402 return 0; 403 } 404 405 /* board specific CANFD command pre-processing */ 406 static int pciefd_pre_cmd(struct peak_canfd_priv *ucan) 407 { 408 struct pciefd_can *priv = (struct pciefd_can *)ucan; 409 u16 cmd = pucan_cmd_get_opcode(&priv->pucan_cmd); 410 int err; 411 412 /* pre-process command */ 413 switch (cmd) { 414 case PUCAN_CMD_NORMAL_MODE: 415 case PUCAN_CMD_LISTEN_ONLY_MODE: 416 417 if (ucan->can.state == CAN_STATE_BUS_OFF) 418 break; 419 420 /* going into operational mode: setup IRQ handler */ 421 err = request_irq(priv->board->pci_dev->irq, 422 pciefd_irq_handler, 423 IRQF_SHARED, 424 PCIEFD_DRV_NAME, 425 priv); 426 if (err) 427 return err; 428 429 /* setup Rx DMA address */ 430 pciefd_can_setup_rx_dma(priv); 431 432 /* setup max count of msgs per IRQ */ 433 pciefd_can_writereg(priv, (CANFD_CTL_IRQ_TL_DEF) << 8 | 434 CANFD_CTL_IRQ_CL_DEF, 435 PCIEFD_REG_CAN_RX_CTL_WRT); 436 437 /* clear DMA RST for Rx (Rx start) */ 438 pciefd_can_writereg(priv, CANFD_CTL_RST_BIT, 439 PCIEFD_REG_CAN_RX_CTL_CLR); 440 441 /* reset timestamps */ 442 pciefd_can_writereg(priv, !CANFD_MISC_TS_RST, 443 PCIEFD_REG_CAN_MISC); 444 445 /* do an initial ACK */ 446 pciefd_can_ack_rx_dma(priv); 447 448 /* enable IRQ for this CAN after having set next irq_tag */ 449 pciefd_can_writereg(priv, CANFD_CTL_IEN_BIT, 450 PCIEFD_REG_CAN_RX_CTL_SET); 451 452 /* Tx path will be setup as soon as RX_BARRIER is received */ 453 break; 454 default: 455 break; 456 } 457 458 return 0; 459 } 460 461 /* write a command */ 462 static int pciefd_write_cmd(struct peak_canfd_priv *ucan) 463 { 464 struct pciefd_can *priv = (struct pciefd_can *)ucan; 465 unsigned long flags; 466 467 /* 64-bits command is atomic */ 468 spin_lock_irqsave(&priv->board->cmd_lock, flags); 469 470 pciefd_can_writereg(priv, *(u32 *)ucan->cmd_buffer, 471 PCIEFD_REG_CAN_CMD_PORT_L); 472 pciefd_can_writereg(priv, *(u32 *)(ucan->cmd_buffer + 4), 473 PCIEFD_REG_CAN_CMD_PORT_H); 474 475 spin_unlock_irqrestore(&priv->board->cmd_lock, flags); 476 477 return 0; 478 } 479 480 /* board specific CANFD command post-processing */ 481 static int pciefd_post_cmd(struct peak_canfd_priv *ucan) 482 { 483 struct pciefd_can *priv = (struct pciefd_can *)ucan; 484 u16 cmd = pucan_cmd_get_opcode(&priv->pucan_cmd); 485 486 switch (cmd) { 487 case PUCAN_CMD_RESET_MODE: 488 489 if (ucan->can.state == CAN_STATE_STOPPED) 490 break; 491 492 /* controller now in reset mode: */ 493 494 /* stop and reset DMA addresses in Tx/Rx engines */ 495 pciefd_can_clear_tx_dma(priv); 496 pciefd_can_clear_rx_dma(priv); 497 498 /* disable IRQ for this CAN */ 499 pciefd_can_writereg(priv, CANFD_CTL_IEN_BIT, 500 PCIEFD_REG_CAN_RX_CTL_CLR); 501 502 free_irq(priv->board->pci_dev->irq, priv); 503 504 ucan->can.state = CAN_STATE_STOPPED; 505 506 break; 507 } 508 509 return 0; 510 } 511 512 static void *pciefd_alloc_tx_msg(struct peak_canfd_priv *ucan, u16 msg_size, 513 int *room_left) 514 { 515 struct pciefd_can *priv = (struct pciefd_can *)ucan; 516 struct pciefd_page *page = priv->tx_pages + priv->tx_page_index; 517 unsigned long flags; 518 void *msg; 519 520 spin_lock_irqsave(&priv->tx_lock, flags); 521 522 if (page->offset + msg_size > page->size) { 523 struct pciefd_tx_link *lk; 524 525 /* not enough space in this page: try another one */ 526 if (!priv->tx_pages_free) { 527 spin_unlock_irqrestore(&priv->tx_lock, flags); 528 529 /* Tx overflow */ 530 return NULL; 531 } 532 533 priv->tx_pages_free--; 534 535 /* keep address of the very last free slot of current page */ 536 lk = page->vbase + page->offset; 537 538 /* next, move on a new free page */ 539 priv->tx_page_index = (priv->tx_page_index + 1) % 540 PCIEFD_TX_PAGE_COUNT; 541 page = priv->tx_pages + priv->tx_page_index; 542 543 /* put link record to this new page at the end of prev one */ 544 lk->size = cpu_to_le16(sizeof(*lk)); 545 lk->type = cpu_to_le16(CANFD_MSG_LNK_TX); 546 lk->laddr_lo = cpu_to_le32(page->lbase); 547 548 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 549 lk->laddr_hi = cpu_to_le32(page->lbase >> 32); 550 #else 551 lk->laddr_hi = 0; 552 #endif 553 /* next msgs will be put from the begininng of this new page */ 554 page->offset = 0; 555 } 556 557 *room_left = priv->tx_pages_free * page->size; 558 559 spin_unlock_irqrestore(&priv->tx_lock, flags); 560 561 msg = page->vbase + page->offset; 562 563 /* give back room left in the tx ring */ 564 *room_left += page->size - (page->offset + msg_size); 565 566 return msg; 567 } 568 569 static int pciefd_write_tx_msg(struct peak_canfd_priv *ucan, 570 struct pucan_tx_msg *msg) 571 { 572 struct pciefd_can *priv = (struct pciefd_can *)ucan; 573 struct pciefd_page *page = priv->tx_pages + priv->tx_page_index; 574 575 /* this slot is now reserved for writing the frame */ 576 page->offset += le16_to_cpu(msg->size); 577 578 /* tell the board a frame has been written in Tx DMA area */ 579 pciefd_can_writereg(priv, 1, PCIEFD_REG_CAN_TX_REQ_ACC); 580 581 return 0; 582 } 583 584 /* probe for CAN-FD channel #pciefd_board->can_count */ 585 static int pciefd_can_probe(struct pciefd_board *pciefd) 586 { 587 struct net_device *ndev; 588 struct pciefd_can *priv; 589 u32 clk; 590 int err; 591 592 /* allocate the candev object with default isize of echo skbs ring */ 593 ndev = alloc_peak_canfd_dev(sizeof(*priv), pciefd->can_count, 594 PCIEFD_ECHO_SKB_MAX); 595 if (!ndev) { 596 dev_err(&pciefd->pci_dev->dev, 597 "failed to alloc candev object\n"); 598 goto failure; 599 } 600 601 priv = netdev_priv(ndev); 602 603 /* fill-in candev private object: */ 604 605 /* setup PCIe-FD own callbacks */ 606 priv->ucan.pre_cmd = pciefd_pre_cmd; 607 priv->ucan.write_cmd = pciefd_write_cmd; 608 priv->ucan.post_cmd = pciefd_post_cmd; 609 priv->ucan.enable_tx_path = pciefd_enable_tx_path; 610 priv->ucan.alloc_tx_msg = pciefd_alloc_tx_msg; 611 priv->ucan.write_tx_msg = pciefd_write_tx_msg; 612 613 /* setup PCIe-FD own command buffer */ 614 priv->ucan.cmd_buffer = &priv->pucan_cmd; 615 priv->ucan.cmd_maxlen = sizeof(priv->pucan_cmd); 616 617 priv->board = pciefd; 618 619 /* CAN config regs block address */ 620 priv->reg_base = pciefd->reg_base + PCIEFD_CANX_OFF(priv->ucan.index); 621 622 /* allocate non-cacheable DMA'able 4KB memory area for Rx */ 623 priv->rx_dma_vaddr = dmam_alloc_coherent(&pciefd->pci_dev->dev, 624 PCIEFD_RX_DMA_SIZE, 625 &priv->rx_dma_laddr, 626 GFP_KERNEL); 627 if (!priv->rx_dma_vaddr) { 628 dev_err(&pciefd->pci_dev->dev, 629 "Rx dmam_alloc_coherent(%u) failure\n", 630 PCIEFD_RX_DMA_SIZE); 631 goto err_free_candev; 632 } 633 634 /* allocate non-cacheable DMA'able 4KB memory area for Tx */ 635 priv->tx_dma_vaddr = dmam_alloc_coherent(&pciefd->pci_dev->dev, 636 PCIEFD_TX_DMA_SIZE, 637 &priv->tx_dma_laddr, 638 GFP_KERNEL); 639 if (!priv->tx_dma_vaddr) { 640 dev_err(&pciefd->pci_dev->dev, 641 "Tx dmaim_alloc_coherent(%u) failure\n", 642 PCIEFD_TX_DMA_SIZE); 643 goto err_free_candev; 644 } 645 646 /* CAN clock in RST mode */ 647 pciefd_can_writereg(priv, CANFD_MISC_TS_RST, PCIEFD_REG_CAN_MISC); 648 649 /* read current clock value */ 650 clk = pciefd_can_readreg(priv, PCIEFD_REG_CAN_CLK_SEL); 651 switch (clk) { 652 case CANFD_CLK_SEL_20MHZ: 653 priv->ucan.can.clock.freq = 20 * 1000 * 1000; 654 break; 655 case CANFD_CLK_SEL_24MHZ: 656 priv->ucan.can.clock.freq = 24 * 1000 * 1000; 657 break; 658 case CANFD_CLK_SEL_30MHZ: 659 priv->ucan.can.clock.freq = 30 * 1000 * 1000; 660 break; 661 case CANFD_CLK_SEL_40MHZ: 662 priv->ucan.can.clock.freq = 40 * 1000 * 1000; 663 break; 664 case CANFD_CLK_SEL_60MHZ: 665 priv->ucan.can.clock.freq = 60 * 1000 * 1000; 666 break; 667 default: 668 pciefd_can_writereg(priv, CANFD_CLK_SEL_80MHZ, 669 PCIEFD_REG_CAN_CLK_SEL); 670 671 /* fallthough */ 672 case CANFD_CLK_SEL_80MHZ: 673 priv->ucan.can.clock.freq = 80 * 1000 * 1000; 674 break; 675 } 676 677 ndev->irq = pciefd->pci_dev->irq; 678 679 SET_NETDEV_DEV(ndev, &pciefd->pci_dev->dev); 680 681 err = register_candev(ndev); 682 if (err) { 683 dev_err(&pciefd->pci_dev->dev, 684 "couldn't register CAN device: %d\n", err); 685 goto err_free_candev; 686 } 687 688 spin_lock_init(&priv->tx_lock); 689 690 /* save the object address in the board structure */ 691 pciefd->can[pciefd->can_count] = priv; 692 693 dev_info(&pciefd->pci_dev->dev, "%s at reg_base=0x%p irq=%d\n", 694 ndev->name, priv->reg_base, pciefd->pci_dev->irq); 695 696 return 0; 697 698 err_free_candev: 699 free_candev(ndev); 700 701 failure: 702 return -ENOMEM; 703 } 704 705 /* remove a CAN-FD channel by releasing all of its resources */ 706 static void pciefd_can_remove(struct pciefd_can *priv) 707 { 708 /* unregister (close) the can device to go back to RST mode first */ 709 unregister_candev(priv->ucan.ndev); 710 711 /* finally, free the candev object */ 712 free_candev(priv->ucan.ndev); 713 } 714 715 /* remove all CAN-FD channels by releasing their own resources */ 716 static void pciefd_can_remove_all(struct pciefd_board *pciefd) 717 { 718 while (pciefd->can_count > 0) 719 pciefd_can_remove(pciefd->can[--pciefd->can_count]); 720 } 721 722 /* probe for the entire device */ 723 static int peak_pciefd_probe(struct pci_dev *pdev, 724 const struct pci_device_id *ent) 725 { 726 struct pciefd_board *pciefd; 727 int err, can_count; 728 u16 sub_sys_id; 729 u8 hw_ver_major; 730 u8 hw_ver_minor; 731 u8 hw_ver_sub; 732 u32 v2; 733 734 err = pci_enable_device(pdev); 735 if (err) 736 return err; 737 err = pci_request_regions(pdev, PCIEFD_DRV_NAME); 738 if (err) 739 goto err_disable_pci; 740 741 /* the number of channels depends on sub-system id */ 742 err = pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &sub_sys_id); 743 if (err) 744 goto err_release_regions; 745 746 dev_dbg(&pdev->dev, "probing device %04x:%04x:%04x\n", 747 pdev->vendor, pdev->device, sub_sys_id); 748 749 if (sub_sys_id >= 0x0012) 750 can_count = 4; 751 else if (sub_sys_id >= 0x0010) 752 can_count = 3; 753 else if (sub_sys_id >= 0x0004) 754 can_count = 2; 755 else 756 can_count = 1; 757 758 /* allocate board structure object */ 759 pciefd = devm_kzalloc(&pdev->dev, struct_size(pciefd, can, can_count), 760 GFP_KERNEL); 761 if (!pciefd) { 762 err = -ENOMEM; 763 goto err_release_regions; 764 } 765 766 /* initialize the board structure */ 767 pciefd->pci_dev = pdev; 768 spin_lock_init(&pciefd->cmd_lock); 769 770 /* save the PCI BAR0 virtual address for further system regs access */ 771 pciefd->reg_base = pci_iomap(pdev, 0, PCIEFD_BAR0_SIZE); 772 if (!pciefd->reg_base) { 773 dev_err(&pdev->dev, "failed to map PCI resource #0\n"); 774 err = -ENOMEM; 775 goto err_release_regions; 776 } 777 778 /* read the firmware version number */ 779 v2 = pciefd_sys_readreg(pciefd, PCIEFD_REG_SYS_VER2); 780 781 hw_ver_major = (v2 & 0x0000f000) >> 12; 782 hw_ver_minor = (v2 & 0x00000f00) >> 8; 783 hw_ver_sub = (v2 & 0x000000f0) >> 4; 784 785 dev_info(&pdev->dev, 786 "%ux CAN-FD PCAN-PCIe FPGA v%u.%u.%u:\n", can_count, 787 hw_ver_major, hw_ver_minor, hw_ver_sub); 788 789 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 790 /* FW < v3.3.0 DMA logic doesn't handle correctly the mix of 32-bit and 791 * 64-bit logical addresses: this workaround forces usage of 32-bit 792 * DMA addresses only when such a fw is detected. 793 */ 794 if (PCIEFD_FW_VERSION(hw_ver_major, hw_ver_minor, hw_ver_sub) < 795 PCIEFD_FW_VERSION(3, 3, 0)) { 796 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 797 if (err) 798 dev_warn(&pdev->dev, 799 "warning: can't set DMA mask %llxh (err %d)\n", 800 DMA_BIT_MASK(32), err); 801 } 802 #endif 803 804 /* stop system clock */ 805 pciefd_sys_writereg(pciefd, PCIEFD_SYS_CTL_CLK_EN, 806 PCIEFD_REG_SYS_CTL_CLR); 807 808 pci_set_master(pdev); 809 810 /* create now the corresponding channels objects */ 811 while (pciefd->can_count < can_count) { 812 err = pciefd_can_probe(pciefd); 813 if (err) 814 goto err_free_canfd; 815 816 pciefd->can_count++; 817 } 818 819 /* set system timestamps counter in RST mode */ 820 pciefd_sys_writereg(pciefd, PCIEFD_SYS_CTL_TS_RST, 821 PCIEFD_REG_SYS_CTL_SET); 822 823 /* wait a bit (read cycle) */ 824 (void)pciefd_sys_readreg(pciefd, PCIEFD_REG_SYS_VER1); 825 826 /* free all clocks */ 827 pciefd_sys_writereg(pciefd, PCIEFD_SYS_CTL_TS_RST, 828 PCIEFD_REG_SYS_CTL_CLR); 829 830 /* start system clock */ 831 pciefd_sys_writereg(pciefd, PCIEFD_SYS_CTL_CLK_EN, 832 PCIEFD_REG_SYS_CTL_SET); 833 834 /* remember the board structure address in the device user data */ 835 pci_set_drvdata(pdev, pciefd); 836 837 return 0; 838 839 err_free_canfd: 840 pciefd_can_remove_all(pciefd); 841 842 pci_iounmap(pdev, pciefd->reg_base); 843 844 err_release_regions: 845 pci_release_regions(pdev); 846 847 err_disable_pci: 848 pci_disable_device(pdev); 849 850 /* pci_xxx_config_word() return positive PCIBIOS_xxx error codes while 851 * the probe() function must return a negative errno in case of failure 852 * (err is unchanged if negative) */ 853 return pcibios_err_to_errno(err); 854 } 855 856 /* free the board structure object, as well as its resources: */ 857 static void peak_pciefd_remove(struct pci_dev *pdev) 858 { 859 struct pciefd_board *pciefd = pci_get_drvdata(pdev); 860 861 /* release CAN-FD channels resources */ 862 pciefd_can_remove_all(pciefd); 863 864 pci_iounmap(pdev, pciefd->reg_base); 865 866 pci_release_regions(pdev); 867 pci_disable_device(pdev); 868 } 869 870 static struct pci_driver peak_pciefd_driver = { 871 .name = PCIEFD_DRV_NAME, 872 .id_table = peak_pciefd_tbl, 873 .probe = peak_pciefd_probe, 874 .remove = peak_pciefd_remove, 875 }; 876 877 module_pci_driver(peak_pciefd_driver); 878