1 /* 2 * CAN bus driver for the Freescale MPC5xxx embedded CPU. 3 * 4 * Copyright (C) 2004-2005 Andrey Volkov <avolkov@varma-el.com>, 5 * Varma Electronics Oy 6 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com> 7 * Copyright (C) 2009 Wolfram Sang, Pengutronix <w.sang@pengutronix.de> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the version 2 of the GNU General Public License 11 * as published by the Free Software Foundation 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/interrupt.h> 26 #include <linux/platform_device.h> 27 #include <linux/netdevice.h> 28 #include <linux/can/dev.h> 29 #include <linux/of_platform.h> 30 #include <sysdev/fsl_soc.h> 31 #include <linux/clk.h> 32 #include <linux/io.h> 33 #include <asm/mpc52xx.h> 34 35 #include "mscan.h" 36 37 #define DRV_NAME "mpc5xxx_can" 38 39 struct mpc5xxx_can_data { 40 unsigned int type; 41 u32 (*get_clock)(struct platform_device *ofdev, const char *clock_name, 42 int *mscan_clksrc); 43 }; 44 45 #ifdef CONFIG_PPC_MPC52xx 46 static struct of_device_id mpc52xx_cdm_ids[] = { 47 { .compatible = "fsl,mpc5200-cdm", }, 48 {} 49 }; 50 51 static u32 mpc52xx_can_get_clock(struct platform_device *ofdev, 52 const char *clock_name, int *mscan_clksrc) 53 { 54 unsigned int pvr; 55 struct mpc52xx_cdm __iomem *cdm; 56 struct device_node *np_cdm; 57 unsigned int freq; 58 u32 val; 59 60 pvr = mfspr(SPRN_PVR); 61 62 /* 63 * Either the oscillator clock (SYS_XTAL_IN) or the IP bus clock 64 * (IP_CLK) can be selected as MSCAN clock source. According to 65 * the MPC5200 user's manual, the oscillator clock is the better 66 * choice as it has less jitter. For this reason, it is selected 67 * by default. Unfortunately, it can not be selected for the old 68 * MPC5200 Rev. A chips due to a hardware bug (check errata). 69 */ 70 if (clock_name && strcmp(clock_name, "ip") == 0) 71 *mscan_clksrc = MSCAN_CLKSRC_BUS; 72 else 73 *mscan_clksrc = MSCAN_CLKSRC_XTAL; 74 75 freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node); 76 if (!freq) 77 return 0; 78 79 if (*mscan_clksrc == MSCAN_CLKSRC_BUS || pvr == 0x80822011) 80 return freq; 81 82 /* Determine SYS_XTAL_IN frequency from the clock domain settings */ 83 np_cdm = of_find_matching_node(NULL, mpc52xx_cdm_ids); 84 if (!np_cdm) { 85 dev_err(&ofdev->dev, "can't get clock node!\n"); 86 return 0; 87 } 88 cdm = of_iomap(np_cdm, 0); 89 90 if (in_8(&cdm->ipb_clk_sel) & 0x1) 91 freq *= 2; 92 val = in_be32(&cdm->rstcfg); 93 94 freq *= (val & (1 << 5)) ? 8 : 4; 95 freq /= (val & (1 << 6)) ? 12 : 16; 96 97 of_node_put(np_cdm); 98 iounmap(cdm); 99 100 return freq; 101 } 102 #else /* !CONFIG_PPC_MPC52xx */ 103 static u32 mpc52xx_can_get_clock(struct platform_device *ofdev, 104 const char *clock_name, int *mscan_clksrc) 105 { 106 return 0; 107 } 108 #endif /* CONFIG_PPC_MPC52xx */ 109 110 #ifdef CONFIG_PPC_MPC512x 111 struct mpc512x_clockctl { 112 u32 spmr; /* System PLL Mode Reg */ 113 u32 sccr[2]; /* System Clk Ctrl Reg 1 & 2 */ 114 u32 scfr1; /* System Clk Freq Reg 1 */ 115 u32 scfr2; /* System Clk Freq Reg 2 */ 116 u32 reserved; 117 u32 bcr; /* Bread Crumb Reg */ 118 u32 pccr[12]; /* PSC Clk Ctrl Reg 0-11 */ 119 u32 spccr; /* SPDIF Clk Ctrl Reg */ 120 u32 cccr; /* CFM Clk Ctrl Reg */ 121 u32 dccr; /* DIU Clk Cnfg Reg */ 122 u32 mccr[4]; /* MSCAN Clk Ctrl Reg 1-3 */ 123 }; 124 125 static struct of_device_id mpc512x_clock_ids[] = { 126 { .compatible = "fsl,mpc5121-clock", }, 127 {} 128 }; 129 130 static u32 mpc512x_can_get_clock(struct platform_device *ofdev, 131 const char *clock_name, int *mscan_clksrc) 132 { 133 struct mpc512x_clockctl __iomem *clockctl; 134 struct device_node *np_clock; 135 struct clk *sys_clk, *ref_clk; 136 int plen, clockidx, clocksrc = -1; 137 u32 sys_freq, val, clockdiv = 1, freq = 0; 138 const u32 *pval; 139 140 np_clock = of_find_matching_node(NULL, mpc512x_clock_ids); 141 if (!np_clock) { 142 dev_err(&ofdev->dev, "couldn't find clock node\n"); 143 return 0; 144 } 145 clockctl = of_iomap(np_clock, 0); 146 if (!clockctl) { 147 dev_err(&ofdev->dev, "couldn't map clock registers\n"); 148 goto exit_put; 149 } 150 151 /* Determine the MSCAN device index from the physical address */ 152 pval = of_get_property(ofdev->dev.of_node, "reg", &plen); 153 BUG_ON(!pval || plen < sizeof(*pval)); 154 clockidx = (*pval & 0x80) ? 1 : 0; 155 if (*pval & 0x2000) 156 clockidx += 2; 157 158 /* 159 * Clock source and divider selection: 3 different clock sources 160 * can be selected: "ip", "ref" or "sys". For the latter two, a 161 * clock divider can be defined as well. If the clock source is 162 * not specified by the device tree, we first try to find an 163 * optimal CAN source clock based on the system clock. If that 164 * is not posslible, the reference clock will be used. 165 */ 166 if (clock_name && !strcmp(clock_name, "ip")) { 167 *mscan_clksrc = MSCAN_CLKSRC_IPS; 168 freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node); 169 } else { 170 *mscan_clksrc = MSCAN_CLKSRC_BUS; 171 172 pval = of_get_property(ofdev->dev.of_node, 173 "fsl,mscan-clock-divider", &plen); 174 if (pval && plen == sizeof(*pval)) 175 clockdiv = *pval; 176 if (!clockdiv) 177 clockdiv = 1; 178 179 if (!clock_name || !strcmp(clock_name, "sys")) { 180 sys_clk = clk_get(&ofdev->dev, "sys_clk"); 181 if (IS_ERR(sys_clk)) { 182 dev_err(&ofdev->dev, "couldn't get sys_clk\n"); 183 goto exit_unmap; 184 } 185 /* Get and round up/down sys clock rate */ 186 sys_freq = 1000000 * 187 ((clk_get_rate(sys_clk) + 499999) / 1000000); 188 189 if (!clock_name) { 190 /* A multiple of 16 MHz would be optimal */ 191 if ((sys_freq % 16000000) == 0) { 192 clocksrc = 0; 193 clockdiv = sys_freq / 16000000; 194 freq = sys_freq / clockdiv; 195 } 196 } else { 197 clocksrc = 0; 198 freq = sys_freq / clockdiv; 199 } 200 } 201 202 if (clocksrc < 0) { 203 ref_clk = clk_get(&ofdev->dev, "ref_clk"); 204 if (IS_ERR(ref_clk)) { 205 dev_err(&ofdev->dev, "couldn't get ref_clk\n"); 206 goto exit_unmap; 207 } 208 clocksrc = 1; 209 freq = clk_get_rate(ref_clk) / clockdiv; 210 } 211 } 212 213 /* Disable clock */ 214 out_be32(&clockctl->mccr[clockidx], 0x0); 215 if (clocksrc >= 0) { 216 /* Set source and divider */ 217 val = (clocksrc << 14) | ((clockdiv - 1) << 17); 218 out_be32(&clockctl->mccr[clockidx], val); 219 /* Enable clock */ 220 out_be32(&clockctl->mccr[clockidx], val | 0x10000); 221 } 222 223 /* Enable MSCAN clock domain */ 224 val = in_be32(&clockctl->sccr[1]); 225 if (!(val & (1 << 25))) 226 out_be32(&clockctl->sccr[1], val | (1 << 25)); 227 228 dev_dbg(&ofdev->dev, "using '%s' with frequency divider %d\n", 229 *mscan_clksrc == MSCAN_CLKSRC_IPS ? "ips_clk" : 230 clocksrc == 1 ? "ref_clk" : "sys_clk", clockdiv); 231 232 exit_unmap: 233 iounmap(clockctl); 234 exit_put: 235 of_node_put(np_clock); 236 return freq; 237 } 238 #else /* !CONFIG_PPC_MPC512x */ 239 static u32 mpc512x_can_get_clock(struct platform_device *ofdev, 240 const char *clock_name, int *mscan_clksrc) 241 { 242 return 0; 243 } 244 #endif /* CONFIG_PPC_MPC512x */ 245 246 static const struct of_device_id mpc5xxx_can_table[]; 247 static int mpc5xxx_can_probe(struct platform_device *ofdev) 248 { 249 const struct of_device_id *match; 250 const struct mpc5xxx_can_data *data; 251 struct device_node *np = ofdev->dev.of_node; 252 struct net_device *dev; 253 struct mscan_priv *priv; 254 void __iomem *base; 255 const char *clock_name = NULL; 256 int irq, mscan_clksrc = 0; 257 int err = -ENOMEM; 258 259 match = of_match_device(mpc5xxx_can_table, &ofdev->dev); 260 if (!match) 261 return -EINVAL; 262 data = match->data; 263 264 base = of_iomap(np, 0); 265 if (!base) { 266 dev_err(&ofdev->dev, "couldn't ioremap\n"); 267 return err; 268 } 269 270 irq = irq_of_parse_and_map(np, 0); 271 if (!irq) { 272 dev_err(&ofdev->dev, "no irq found\n"); 273 err = -ENODEV; 274 goto exit_unmap_mem; 275 } 276 277 dev = alloc_mscandev(); 278 if (!dev) 279 goto exit_dispose_irq; 280 281 priv = netdev_priv(dev); 282 priv->reg_base = base; 283 dev->irq = irq; 284 285 clock_name = of_get_property(np, "fsl,mscan-clock-source", NULL); 286 287 BUG_ON(!data); 288 priv->type = data->type; 289 priv->can.clock.freq = data->get_clock(ofdev, clock_name, 290 &mscan_clksrc); 291 if (!priv->can.clock.freq) { 292 dev_err(&ofdev->dev, "couldn't get MSCAN clock properties\n"); 293 goto exit_free_mscan; 294 } 295 296 SET_NETDEV_DEV(dev, &ofdev->dev); 297 298 err = register_mscandev(dev, mscan_clksrc); 299 if (err) { 300 dev_err(&ofdev->dev, "registering %s failed (err=%d)\n", 301 DRV_NAME, err); 302 goto exit_free_mscan; 303 } 304 305 dev_set_drvdata(&ofdev->dev, dev); 306 307 dev_info(&ofdev->dev, "MSCAN at 0x%p, irq %d, clock %d Hz\n", 308 priv->reg_base, dev->irq, priv->can.clock.freq); 309 310 return 0; 311 312 exit_free_mscan: 313 free_candev(dev); 314 exit_dispose_irq: 315 irq_dispose_mapping(irq); 316 exit_unmap_mem: 317 iounmap(base); 318 319 return err; 320 } 321 322 static int mpc5xxx_can_remove(struct platform_device *ofdev) 323 { 324 struct net_device *dev = dev_get_drvdata(&ofdev->dev); 325 struct mscan_priv *priv = netdev_priv(dev); 326 327 dev_set_drvdata(&ofdev->dev, NULL); 328 329 unregister_mscandev(dev); 330 iounmap(priv->reg_base); 331 irq_dispose_mapping(dev->irq); 332 free_candev(dev); 333 334 return 0; 335 } 336 337 #ifdef CONFIG_PM 338 static struct mscan_regs saved_regs; 339 static int mpc5xxx_can_suspend(struct platform_device *ofdev, pm_message_t state) 340 { 341 struct net_device *dev = dev_get_drvdata(&ofdev->dev); 342 struct mscan_priv *priv = netdev_priv(dev); 343 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 344 345 _memcpy_fromio(&saved_regs, regs, sizeof(*regs)); 346 347 return 0; 348 } 349 350 static int mpc5xxx_can_resume(struct platform_device *ofdev) 351 { 352 struct net_device *dev = dev_get_drvdata(&ofdev->dev); 353 struct mscan_priv *priv = netdev_priv(dev); 354 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 355 356 regs->canctl0 |= MSCAN_INITRQ; 357 while (!(regs->canctl1 & MSCAN_INITAK)) 358 udelay(10); 359 360 regs->canctl1 = saved_regs.canctl1; 361 regs->canbtr0 = saved_regs.canbtr0; 362 regs->canbtr1 = saved_regs.canbtr1; 363 regs->canidac = saved_regs.canidac; 364 365 /* restore masks, buffers etc. */ 366 _memcpy_toio(®s->canidar1_0, (void *)&saved_regs.canidar1_0, 367 sizeof(*regs) - offsetof(struct mscan_regs, canidar1_0)); 368 369 regs->canctl0 &= ~MSCAN_INITRQ; 370 regs->cantbsel = saved_regs.cantbsel; 371 regs->canrier = saved_regs.canrier; 372 regs->cantier = saved_regs.cantier; 373 regs->canctl0 = saved_regs.canctl0; 374 375 return 0; 376 } 377 #endif 378 379 static const struct mpc5xxx_can_data mpc5200_can_data = { 380 .type = MSCAN_TYPE_MPC5200, 381 .get_clock = mpc52xx_can_get_clock, 382 }; 383 384 static const struct mpc5xxx_can_data mpc5121_can_data = { 385 .type = MSCAN_TYPE_MPC5121, 386 .get_clock = mpc512x_can_get_clock, 387 }; 388 389 static const struct of_device_id mpc5xxx_can_table[] = { 390 { .compatible = "fsl,mpc5200-mscan", .data = &mpc5200_can_data, }, 391 /* Note that only MPC5121 Rev. 2 (and later) is supported */ 392 { .compatible = "fsl,mpc5121-mscan", .data = &mpc5121_can_data, }, 393 {}, 394 }; 395 MODULE_DEVICE_TABLE(of, mpc5xxx_can_table); 396 397 static struct platform_driver mpc5xxx_can_driver = { 398 .driver = { 399 .name = "mpc5xxx_can", 400 .owner = THIS_MODULE, 401 .of_match_table = mpc5xxx_can_table, 402 }, 403 .probe = mpc5xxx_can_probe, 404 .remove = mpc5xxx_can_remove, 405 #ifdef CONFIG_PM 406 .suspend = mpc5xxx_can_suspend, 407 .resume = mpc5xxx_can_resume, 408 #endif 409 }; 410 411 module_platform_driver(mpc5xxx_can_driver); 412 413 MODULE_AUTHOR("Wolfgang Grandegger <wg@grandegger.com>"); 414 MODULE_DESCRIPTION("Freescale MPC5xxx CAN driver"); 415 MODULE_LICENSE("GPL v2"); 416